From 2a321348f54c83f9814e2a32ab6faed6e2deb53c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Tue, 17 Jan 2012 00:11:33 +0100
Subject: [PATCH] modules/common: updated manifest and package with freshly
added modules
---
modules/common/Manifest.py | 16 +++++++++-------
modules/common/gencores_pkg.vhd | 26 +++++++++++++++++++++++++-
2 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/modules/common/Manifest.py b/modules/common/Manifest.py
index 0c196d90..75363ef2 100644
--- a/modules/common/Manifest.py
+++ b/modules/common/Manifest.py
@@ -1,8 +1,10 @@
files = [ "gencores_pkg.vhd",
- "gc_crc_gen.vhd",
- "gc_moving_average.vhd",
- "gc_extend_pulse.vhd",
- "gc_delay_gen.vhd",
- "gc_dual_pi_controller.vhd",
- "gc_serial_dac.vhd",
- "gc_sync_ffs.vhd"];
+ "gc_crc_gen.vhd",
+ "gc_moving_average.vhd",
+ "gc_extend_pulse.vhd",
+ "gc_delay_gen.vhd",
+ "gc_dual_pi_controller.vhd",
+ "gc_serial_dac.vhd",
+ "gc_sync_ffs.vhd",
+ "gc_pulse_synchronizer.vhd",
+ "gc_frequency_meter.vhd"];
diff --git a/modules/common/gencores_pkg.vhd b/modules/common/gencores_pkg.vhd
index 45311dd5..582b8565 100644
--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2009-09-01
--- Last update: 2011-05-27
+-- Last update: 2012-01-17
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
@@ -146,6 +146,30 @@ package gencores_pkg is
npulse_o : out std_logic;
ppulse_o : out std_logic);
end component;
+
+ component gc_pulse_synchronizer
+ port (
+ clk_in_i : in std_logic;
+ clk_out_i : in std_logic;
+ rst_n_i : in std_logic;
+ d_ready_o : out std_logic;
+ d_p_i : in std_logic;
+ q_p_o : out std_logic);
+ end component;
+
+ component gc_frequency_meter
+ generic (
+ g_with_internal_timebase : boolean;
+ g_clk_sys_freq : integer;
+ g_counter_bits : integer);
+ port (
+ clk_sys_i : in std_logic;
+ clk_in_i : in std_logic;
+ rst_n_i : in std_logic;
+ pps_p1_i : in std_logic;
+ freq_o : out std_logic_vector(g_counter_bits-1 downto 0);
+ freq_valid_o : out std_logic);
+ end component;
end package;
--
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