From 295fd91b053e08618fbd05ca84a9fb85b55f0062 Mon Sep 17 00:00:00 2001
From: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
Date: Thu, 2 Apr 2020 01:35:00 +0200
Subject: [PATCH] xwb_fine_pulse_gen: fix PLL instantiation on Kintex
Ultrascale
---
.../fine_pulse_gen_kintexultrascale_shared.vhd | 4 ++--
modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd b/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
index 8ba7ecae..5f1fa366 100644
--- a/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
+++ b/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
@@ -139,7 +139,7 @@ architecture rtl of fine_pulse_gen_kintexultrascale_shared is
begin
- gen_use_Ext_serdes_clock : if not g_use_external_serdes_clock generate
+ gen_use_Ext_serdes_clock : if g_use_external_serdes_clock generate
-- stub for the moment
clk_ser_o <= clk_ser_ext_i;
clk_par_o <= clk_ref_i;
@@ -147,7 +147,7 @@ begin
end generate gen_use_Ext_serdes_clock;
- gen_use_int_serdes_clock : if g_use_external_serdes_clock generate
+ gen_use_int_serdes_clock : if not g_use_external_serdes_clock generate
U_MMCM : MMCME3_ADV
generic map (
diff --git a/modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd b/modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
index 61c781db..fa8f3724 100644
--- a/modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
+++ b/modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
@@ -7,8 +7,8 @@ use work.wishbone_pkg.all;
use work.fpg_wbgen2_pkg.all;
-library unisim;
-use unisim.VCOMPONENTS.all;
+--library unisim;
+--use unisim.VCOMPONENTS.all;
entity xwb_fine_pulse_gen is
generic (
--
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