From 26a43bc3b88afcf17f003d4d5b931598e5c4efcd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Thu, 9 Feb 2012 15:55:46 +0100
Subject: [PATCH] wishbone/wb_lm32: fixed typo in (I/D)cache burst length
causing lockup if I-cache was enabled
---
modules/wishbone/wb_lm32/gen_lmcores.py | 2 +-
.../wb_lm32/generated/lm32_allprofiles.v | 11884 ++++++++--------
.../wishbone/wb_lm32/generated/xwb_lm32.vhd | 2 +-
3 files changed, 5944 insertions(+), 5944 deletions(-)
diff --git a/modules/wishbone/wb_lm32/gen_lmcores.py b/modules/wishbone/wb_lm32/gen_lmcores.py
index 60faf97a..fc524812 100755
--- a/modules/wishbone/wb_lm32/gen_lmcores.py
+++ b/modules/wishbone/wb_lm32/gen_lmcores.py
@@ -324,7 +324,7 @@ port map(
if I_CYC = '1' and inst_was_busy = '0' then
inst_addr := I_ADR;
if I_CTI = "010" then
- inst_length := dcache_burst_length;
+ inst_length := icache_burst_length;
else
inst_length := 1;
end if;
diff --git a/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v b/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
index 6465a385..e59b37b1 100644
--- a/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
+++ b/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
@@ -53,6 +53,8 @@
+
+
@@ -78,13 +80,20 @@
-
-
-
-
+
+
-
+
+
+
+
+
+
+
+
+
+
@@ -222,24 +231,25 @@
-
+
+
-
-
+
+
+
+
-
-
@@ -342,24 +352,34 @@
-
-
+
+
+
+
+
+
+
+
+
+
-
+
-
+
+
+
@@ -371,6 +391,8 @@
+
+
@@ -378,28 +400,29 @@
-
-
+
-
-
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
+
@@ -557,7 +580,7 @@
-module lm32_top_full (
+module lm32_top_full_debug (
clk_i,
rst_i,
@@ -714,14 +737,15 @@ wire [ (2-1):0] D_BTE_O;
-
-
-
-
-
-
-
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+
@@ -800,7 +824,7 @@ endfunction
-lm32_cpu_full cpu (
+lm32_cpu_full_debug cpu (
.clk_i (clk_i),
@@ -821,12 +845,13 @@ lm32_cpu_full cpu (
-
-
-
-
-
+
+ .jtag_clk (jtck),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+
@@ -855,9 +880,10 @@ lm32_cpu_full cpu (
-
-
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d),
+
@@ -892,20 +918,21 @@ lm32_cpu_full cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
+
+jtag_cores jtag_cores (
-
-
-
-
-
-
-
-
+ .reg_d (jtag_reg_d),
+ .reg_addr_d (jtag_reg_addr_d),
-
+ .reg_update (jtag_update),
+ .reg_q (jtag_reg_q),
+ .reg_addr_q (jtag_reg_addr_q),
+ .jtck (jtck),
+ .jrstn (jrstn)
+ );
+
endmodule
@@ -1277,7 +1304,7 @@ endmodule
-module lm32_mc_arithmetic_full (
+module lm32_mc_arithmetic_full_debug (
clk_i,
rst_i,
@@ -1943,7 +1970,7 @@ endmodule
-module lm32_cpu_full (
+module lm32_cpu_full_debug (
clk_i,
@@ -1964,12 +1991,13 @@ module lm32_cpu_full (
-
-
-
-
-
+
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+
@@ -1998,9 +2026,10 @@ module lm32_cpu_full (
-
-
+ jtag_reg_d,
+ jtag_reg_addr_d,
+
@@ -2041,8 +2070,9 @@ module lm32_cpu_full (
parameter eba_reset = 32'h00000000;
-
+parameter deba_reset = 32'h10000000;
+
@@ -2078,11 +2108,11 @@ parameter dcache_limit = 32'h7fffffff;
-
-
-parameter watchpoints = 0;
+parameter watchpoints = 32'h4;
+
+
@@ -2124,11 +2154,12 @@ input [ (32-1):0] interrupt;
-
-
-
-
+input jtag_clk;
+input jtag_update;
+input [ 7:0] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+
@@ -2168,11 +2199,12 @@ input D_RTY_I;
-
-
-
-
+output [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
+
@@ -2352,14 +2384,15 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
+wire [ (5-1):0] csr_d;
+reg [ (5-1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
-
-
+wire break_d;
+reg break_x;
+
wire scall_d;
reg scall_x;
@@ -2372,14 +2405,16 @@ reg eret_m;
-
-
-
-
-
+
+wire bret_d;
+reg bret_x;
+wire bret_q_x;
+reg bret_m;
+
+
wire csr_write_enable_d;
reg csr_write_enable_x;
@@ -2585,25 +2620,32 @@ wire stall_wb_load;
-
-
-
-
-
-
-
-
+
+wire [ (32-1):0] jtx_csr_read_data;
+wire [ (32-1):0] jrx_csr_read_data;
+
-
-
+wire jtag_csr_write_enable;
+wire [ (32-1):0] jtag_csr_write_data;
+wire [ (5-1):0] jtag_csr;
+wire jtag_read_enable;
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
-
+
+wire jtag_break;
+
+
+
@@ -2636,8 +2678,9 @@ wire kill_w;
reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
-
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
+
reg [ (3-1):0] eid_x;
@@ -2647,34 +2690,39 @@ reg [ (3-1):0] eid_x;
-
-
-
-
-
-
-
+
+
+wire dc_ss;
+
+wire dc_re;
+wire exception_x;
+reg exception_m;
+wire debug_exception_x;
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
-
+
-wire exception_x;
-reg exception_m;
-reg exception_w;
-wire exception_q_w;
-
+
-
-
+wire reset_exception;
+
+
@@ -2682,9 +2730,10 @@ wire interrupt_exception;
-
-
+wire breakpoint_exception;
+wire watchpoint_exception;
+
@@ -2768,7 +2817,7 @@ endfunction
-lm32_instruction_unit_full #(
+lm32_instruction_unit_full_debug #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -2827,11 +2876,12 @@ lm32_instruction_unit_full #(
-
-
-
-
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
+
@@ -2867,9 +2917,10 @@ lm32_instruction_unit_full #(
-
-
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
+
@@ -2885,7 +2936,7 @@ lm32_instruction_unit_full #(
);
-lm32_decoder_full decoder (
+lm32_decoder_full_debug decoder (
.instruction (instruction_d),
@@ -2966,14 +3017,16 @@ lm32_decoder_full decoder (
.branch_reg (branch_reg_d),
.condition (condition_d),
-
+ .break_opcode (break_d),
+
.scall (scall_d),
.eret (eret_d),
-
+ .bret (bret_d),
+
@@ -2983,7 +3036,7 @@ lm32_decoder_full decoder (
);
-lm32_load_store_unit_full #(
+lm32_load_store_unit_full_debug #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -3119,7 +3172,7 @@ lm32_multiplier multiplier (
-lm32_mc_arithmetic_full mc_arithmetic (
+lm32_mc_arithmetic_full_debug mc_arithmetic (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -3158,7 +3211,7 @@ lm32_mc_arithmetic_full mc_arithmetic (
-lm32_interrupt_full interrupt_unit (
+lm32_interrupt_full_debug interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -3167,17 +3220,18 @@ lm32_interrupt_full interrupt_unit (
.stall_x (stall_x),
-
-
-
- .exception (exception_q_w),
+ .non_debug_exception (non_debug_exception_q_w),
+ .debug_exception (debug_exception_q_w),
+
+
.eret_q_x (eret_q_x),
-
+ .bret_q_x (bret_q_x),
+
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -3192,95 +3246,117 @@ lm32_interrupt_full interrupt_unit (
-
+
+lm32_jtag_full_debug jtag (
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
-
-
-
-
+ .jtag_clk (jtag_clk),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+
+
+ .csr (csr_x),
+ .csr_write_data (operand_1_x),
+ .csr_write_enable (csr_write_enable_q_x),
+ .stall_x (stall_x),
-
-
-
-
+
+
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
-
-
+
+
+ .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
-
+
+
+ .jtx_csr_read_data (jtx_csr_read_data),
+ .jrx_csr_read_data (jrx_csr_read_data),
-
-
+
+
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
-
-
-
-
-
-
-
+
+
+ .jtag_break (jtag_break),
+ .jtag_reset (reset_exception),
-
-
-
-
-
-
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d)
+ );
+
-
-
-
-
+
+lm32_debug_full_debug #(
+ .breakpoints (breakpoints),
+ .watchpoints (watchpoints)
+ ) hw_debug (
-
-
-
-
-
-
-
-
-
-
-
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .pc_x (pc_x),
+ .load_x (load_x),
+ .store_x (store_x),
+ .load_store_address_x (adder_result_x),
+ .csr_write_enable_x (csr_write_enable_q_x),
+ .csr_write_data (operand_1_x),
+ .csr_x (csr_x),
+
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
-
-
-
-
-
-
-
+
+
+ .eret_q_x (eret_q_x),
+ .bret_q_x (bret_q_x),
+ .stall_x (stall_x),
+ .exception_x (exception_x),
+ .q_x (q_x),
+
+
+ .dcache_refill_request (dcache_refill_request),
+
-
-
-
-
-
+
+ .dc_ss (dc_ss),
+
+
+ .dc_re (dc_re),
+ .bp_match (bp_match),
+ .wp_match (wp_match)
+ );
+
@@ -3780,21 +3856,25 @@ assign kill_w = 1'b0
-
-
-
-
-
-
-
-
+assign breakpoint_exception = ( ( (break_x == 1'b1)
+ || (bp_match == 1'b1)
+ )
+ && (valid_x == 1'b1)
+ )
+
+ || (jtag_break == 1'b1)
+
+
+ ;
+
-
+assign watchpoint_exception = wp_match == 1'b1;
+
@@ -3821,38 +3901,17 @@ assign system_call_exception = ( (scall_x == 1'b1)
);
-
-
-
-
-
-
-
-
-
-
+assign debug_exception_x = (breakpoint_exception == 1'b1)
+ || (watchpoint_exception == 1'b1)
+ ;
-
-
+assign non_debug_exception_x = (system_call_exception == 1'b1)
+
+ || (reset_exception == 1'b1)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-assign exception_x = (system_call_exception == 1'b1)
|| (instruction_bus_error_exception == 1'b1)
@@ -3868,8 +3927,9 @@ assign exception_x = (system_call_exception == 1'b1)
|| ( (interrupt_exception == 1'b1)
-
+ && (dc_ss == 1'b0)
+
@@ -3881,27 +3941,55 @@ assign exception_x = (system_call_exception == 1'b1)
;
+
+assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
always @(*)
begin
+
+
+
+ if (reset_exception == 1'b1)
+ eid_x = 3'h0;
+ else
-
-
-
-
-
-
-
+
-
-
-
+ if (data_bus_error_exception == 1'b1)
+ eid_x = 3'h4;
+ else
+
+ if (breakpoint_exception == 1'b1)
+ eid_x = 3'd1;
+ else
+
@@ -3914,10 +4002,11 @@ begin
-
-
-
+ if (watchpoint_exception == 1'b1)
+ eid_x = 3'd3;
+ else
+
@@ -3930,8 +4019,9 @@ begin
if ( (interrupt_exception == 1'b1)
-
+ && (dc_ss == 1'b0)
+
)
eid_x = 3'h6;
@@ -3968,18 +4058,19 @@ assign stall_d = (stall_x == 1'b1)
&& (kill_d == 1'b0)
)
-
-
-
-
-
-
-
-
-
-
-
+ || ( ( (break_d == 1'b1)
+ || (bret_d == 1'b1)
+ )
+ && ( (load_q_x == 1'b1)
+ || (store_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
+ )
+ && (kill_d == 1'b0)
+ )
+
|| ( (csr_write_enable_d == 1'b1)
&& (load_q_x == 1'b1)
@@ -4085,21 +4176,24 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
+assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
+
assign load_q_x = (load_x == 1'b1)
&& (q_x == 1'b1)
-
+ && (bp_match == 1'b0)
+
;
assign store_q_x = (store_x == 1'b1)
&& (q_x == 1'b1)
-
+ && (bp_match == 1'b0)
+
;
@@ -4110,12 +4204,12 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-
-
-assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
+assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+
+
assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
@@ -4131,19 +4225,12 @@ assign cfg = {
breakpoints[3:0],
interrupts[5:0],
-
-
- 1'b0,
+ 1'b1,
-
-
- 1'b0,
-
-
@@ -4152,11 +4239,18 @@ assign cfg = {
+
+ 1'b1,
+
- 1'b0,
+
+
+ 1'b1,
+
+
@@ -4238,16 +4332,17 @@ assign cfg2 = {
assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 3'h3)
+ && (csr_d == 5'h3)
&& (stall_d == 1'b0)
&& (kill_d == 1'b0)
&& (valid_d == 1'b1))
-
-
-
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h3))
+
;
@@ -4255,20 +4350,21 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
assign dflush_x = ( (csr_write_enable_q_x == 1'b1)
- && (csr_x == 3'h4))
+ && (csr_x == 5'h4))
-
-
-
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h4))
+
;
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[ (5-1):0];
always @(*)
@@ -4276,27 +4372,29 @@ begin
case (csr_x)
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 5'h0,
+ 5'h1,
+ 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
+ 5'h6: csr_read_data_x = cfg;
+ 5'h7: csr_read_data_x = {eba, 8'h00};
-
+ 5'h9: csr_read_data_x = {deba, 8'h00};
+
-
-
+ 5'he: csr_read_data_x = jtx_csr_read_data;
+ 5'hf: csr_read_data_x = jrx_csr_read_data;
+
- 3'ha: csr_read_data_x = cfg2;
+ 5'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -4313,33 +4411,37 @@ begin
eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
+ eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
end
end
-
-
-
-
-
-
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ else
+ begin
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
+ deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
+ deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+ end
+end
+
@@ -4521,7 +4623,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
+ csr_x <= { 5{1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -4544,14 +4646,16 @@ begin
branch_predict_taken_x <= 1'b0;
condition_x <= 3'b000;
-
+ break_x <= 1'b0;
+
scall_x <= 1'b0;
eret_x <= 1'b0;
-
+ bret_x <= 1'b0;
+
@@ -4595,9 +4699,10 @@ begin
-
-
+ debug_exception_m <= 1'b0;
+ non_debug_exception_m <= 1'b0;
+
operand_w <= { 32{1'b0}};
w_result_sel_load_w <= 1'b0;
@@ -4609,12 +4714,12 @@ begin
write_idx_w <= { 5{1'b0}};
write_enable_w <= 1'b0;
-
-
-
- exception_w <= 1'b0;
+ debug_exception_w <= 1'b0;
+ non_debug_exception_w <= 1'b0;
+
+
@@ -4695,8 +4800,9 @@ begin
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
+ break_x <= break_d;
+
scall_x <= scall_d;
@@ -4706,8 +4812,9 @@ begin
eret_x <= eret_d;
-
+ bret_x <= bret_d;
+
write_enable_x <= write_enable_d;
end
@@ -4759,40 +4866,40 @@ begin
+
-
-
-
-
-
-
-
-
- if (exception_x == 1'b1)
+ if (non_debug_exception_x == 1'b1)
write_idx_m <= 5'd30;
+ else if (debug_exception_x == 1'b1)
+ write_idx_m <= 5'd31;
else
write_idx_m <= write_idx_x;
+
+
+
+
+
condition_met_m <= condition_met_x;
-
-
-
-
-
-
-
-
-
-
- branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ if (exception_x == 1'b1)
+ if ((dc_re == 1'b1)
+ || ((debug_exception_x == 1'b1)
+ && (non_debug_exception_x == 1'b0)))
+ branch_target_m <= {deba, eid_x, {3{1'b0}}};
+ else
+ branch_target_m <= {eba, eid_x, {3{1'b0}}};
+ else
+ branch_target_m <= branch_target_x;
+
+
@@ -4805,14 +4912,16 @@ begin
eret_m <= eret_q_x;
-
+ bret_m <= bret_q_x;
+
write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
-
+ debug_exception_m <= debug_exception_x;
+ non_debug_exception_m <= non_debug_exception_x;
+
end
@@ -4827,8 +4936,9 @@ begin
data_bus_error_exception_m <= (data_bus_error_exception == 1'b1)
-
+ && (reset_exception == 1'b0)
+
;
@@ -4860,12 +4970,12 @@ begin
write_enable_w <= write_enable_m;
-
-
-
- exception_w <= exception_m;
+ debug_exception_w <= debug_exception_m;
+ non_debug_exception_w <= non_debug_exception_m;
+
+
@@ -5411,7 +5521,7 @@ endmodule
-module lm32_load_store_unit_full (
+module lm32_load_store_unit_full_debug (
clk_i,
rst_i,
@@ -5789,7 +5899,7 @@ endfunction
-lm32_dcache_full #(
+lm32_dcache_full_debug #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -6741,7 +6851,7 @@ endmodule
-module lm32_decoder_full (
+module lm32_decoder_full_debug (
instruction,
@@ -6822,14 +6932,16 @@ module lm32_decoder_full (
bi_conditional,
bi_unconditional,
-
+ break_opcode,
+
scall,
eret,
-
+ bret,
+
@@ -6965,18 +7077,20 @@ wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-
+output break_opcode;
+wire break_opcode;
+
output scall;
wire scall;
output eret;
wire eret;
-
-
+output bret;
+wire bret;
+
@@ -7340,14 +7454,16 @@ assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
+assign break_opcode = op_raise & ~instruction[2];
+
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
+assign bret = op_b & (instruction[25:21] == 5'd31);
+
@@ -7779,7 +7895,7 @@ endmodule
-module lm32_icache_full (
+module lm32_icache_full_debug (
clk_i,
rst_i,
@@ -8625,7 +8741,7 @@ endmodule
-module lm32_dcache_full (
+module lm32_dcache_full_debug (
clk_i,
rst_i,
@@ -9481,135 +9597,162 @@ endmodule
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+module lm32_debug_full_debug (
-
-
-
-
-
-
-
-
-
-
-
-
-
+ clk_i,
+ rst_i,
+ pc_x,
+ load_x,
+ store_x,
+ load_store_address_x,
+ csr_write_enable_x,
+ csr_write_data,
+ csr_x,
+
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
-
-
-
-
-
+
+
+
+ eret_q_x,
+ bret_q_x,
+ stall_x,
+ exception_x,
+ q_x,
+
+
+ dcache_refill_request,
-
+
+
+
+ dc_ss,
-
-
-
-
-
+ dc_re,
+ bp_match,
+ wp_match
+ );
-
-
+parameter breakpoints = 0;
+parameter watchpoints = 0;
-
-
+input clk_i;
+input rst_i;
-
-
-
-
-
-
-
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+input load_x;
+input store_x;
+input [ (32-1):0] load_store_address_x;
+input csr_write_enable_x;
+input [ (32-1):0] csr_write_data;
+input [ (5-1):0] csr_x;
+
+
+input jtag_csr_write_enable;
+input [ (32-1):0] jtag_csr_write_data;
+input [ (5-1):0] jtag_csr;
-
-
-
+
+
+input eret_q_x;
+input bret_q_x;
+input stall_x;
+input exception_x;
+input q_x;
+
+
+input dcache_refill_request;
-
-
-
-
-
+
-
+
+output dc_ss;
+reg dc_ss;
-
-
-
-
-
-
-
-
+output dc_re;
+reg dc_re;
+output bp_match;
+wire bp_match;
+output wp_match;
+wire wp_match;
-
+genvar i;
-
-
-
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
+reg bp_e[0:breakpoints-1];
+wire [0:breakpoints-1]bp_match_n;
-
-
-
+reg [ 1:0] wpc_c[0:watchpoints-1];
+reg [ (32-1):0] wp[0:watchpoints-1];
+wire [0:watchpoints]wp_match_n;
+
+wire debug_csr_write_enable;
+wire [ (32-1):0] debug_csr_write_data;
+wire [ (5-1):0] debug_csr;
+
+
-
-
-
+
+reg [ 2:0] state;
-
+
-
@@ -9617,48 +9760,15 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
@@ -9667,132 +9777,225 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+function integer clogb2;
+input [31:0] value;
+begin
+ for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+ value = value >> 1;
+end
+endfunction
+function integer clogb2_v1;
+input [31:0] value;
+reg [31:0] i;
+reg [31:0] temp;
+begin
+ temp = 0;
+ i = 0;
+ for (i = 0; temp < value; i = i + 1)
+ temp = 1<<i;
+ clogb2_v1 = i-1;
+end
+endfunction
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
+ end
+endgenerate
+generate
+
+ if (breakpoints > 0)
+assign bp_match = (|bp_match_n) || (state == 3'b011);
+ else
+assign bp_match = state == 3'b011;
+
+
-
-
-
-
-
-
-
+
+
+
+endgenerate
-
-
+
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+ end
+endgenerate
+generate
+ if (watchpoints > 0)
+assign wp_match = |wp_match_n;
+ else
+assign wp_match = 1'b0;
+endgenerate
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
-
-
+
+
+
-
+
+
+
+
+
+
+
+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_seq
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ bp_e[i] <= 1'b0;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
+ begin
+ bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+ bp_e[i] <= debug_csr_write_data[0];
+ end
+ end
+end
+ end
+endgenerate
+
+
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_seq
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ wp[i] <= { 32{1'bx}};
+ wpc_c[i] <= 2'b00;
+ end
+ else
+ begin
+ if (debug_csr_write_enable == 1'b1)
+ begin
+ if (debug_csr == 5'h8)
+ wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+ if (debug_csr == 5'h18 + i)
+ wp[i] <= debug_csr_write_data;
+ end
+ end
+end
+ end
+endgenerate
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ dc_re <= 1'b0;
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ dc_re <= debug_csr_write_data[1];
+ end
+end
+
+
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 3'b000;
+ dc_ss <= 1'b0;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ begin
+ dc_ss <= debug_csr_write_data[0];
+ if (debug_csr_write_data[0] == 1'b0)
+ state <= 3'b000;
+ else
+ state <= 3'b001;
+ end
+ case (state)
+ 3'b001:
+ begin
-
-
+ if ( ( (eret_q_x == 1'b1)
+ || (bret_q_x == 1'b1)
+ )
+ && (stall_x == 1'b0)
+ )
+ state <= 3'b010;
+ end
+ 3'b010:
+ begin
-
-
-
+ if ((q_x == 1'b1) && (stall_x == 1'b0))
+ state <= 3'b011;
+ end
+ 3'b011:
+ begin
-
-
-
-
+
-
-
-
-
+ if (dcache_refill_request == 1'b1)
+ state <= 3'b010;
+ else
+
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ begin
+ dc_ss <= 1'b0;
+ state <= 3'b100;
+ end
+ end
+ 3'b100:
+ begin
+
+
+ if (dcache_refill_request == 1'b1)
+ state <= 3'b010;
+ else
+
+ state <= 3'b000;
+ end
+ endcase
+ end
+end
+
+endmodule
+
@@ -10165,7 +10368,7 @@ endmodule
-module lm32_instruction_unit_full (
+module lm32_instruction_unit_full_debug (
clk_i,
rst_i,
@@ -10218,11 +10421,12 @@ module lm32_instruction_unit_full (
-
-
-
-
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
+
@@ -10258,9 +10462,10 @@ module lm32_instruction_unit_full (
-
-
+ jtag_read_data,
+ jtag_access_complete,
+
@@ -10350,11 +10555,12 @@ input i_rty_i;
-
-
-
-
+input jtag_read_enable;
+input jtag_write_enable;
+input [ 7:0] jtag_write_data;
+input [ (32-1):0] jtag_address;
+
@@ -10395,11 +10601,11 @@ wire icache_refilling;
output [ (32-1):0] i_dat_o;
-
-
-wire [ (32-1):0] i_dat_o;
+reg [ (32-1):0] i_dat_o;
+
+
output [ (32-1):0] i_adr_o;
reg [ (32-1):0] i_adr_o;
@@ -10407,21 +10613,21 @@ output i_cyc_o;
reg i_cyc_o;
output [ (4-1):0] i_sel_o;
-
-
-wire [ (4-1):0] i_sel_o;
+reg [ (4-1):0] i_sel_o;
+
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
-
-wire i_we_o;
+reg i_we_o;
+
+
output [ (3-1):0] i_cti_o;
reg [ (3-1):0] i_cti_o;
@@ -10433,11 +10639,12 @@ wire [ (2-1):0] i_bte_o;
-
-
-
-
+output [ 7:0] jtag_read_data;
+reg [ 7:0] jtag_read_data;
+output jtag_access_complete;
+wire jtag_access_complete;
+
@@ -10503,8 +10710,9 @@ reg bus_error_f;
-
+reg jtag_access;
+
@@ -10622,7 +10830,7 @@ endfunction
-lm32_icache_full #(
+lm32_icache_full_debug #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -10745,11 +10953,11 @@ assign instruction_f = icache_data_f;
-
-assign i_dat_o = 32'd0;
-assign i_we_o = 1'b0;
-assign i_sel_o = 4'b1111;
+
+
+
+
assign i_bte_o = 2'b00;
@@ -10866,17 +11074,18 @@ end
-
-
-
-
-
-
-
-
-
-
+assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
+always @(*)
+begin
+ case (jtag_address[1:0])
+ 2'b00: jtag_read_data = i_dat_i[ 31:24];
+ 2'b01: jtag_read_data = i_dat_i[ 23:16];
+ 2'b10: jtag_read_data = i_dat_i[ 15:8];
+ 2'b11: jtag_read_data = i_dat_i[ 7:0];
+ endcase
+end
+
@@ -10901,10 +11110,11 @@ begin
-
-
-
+ i_we_o <= 1'b0;
+ i_sel_o <= 4'b1111;
+ jtag_access <= 1'b0;
+
end
else
@@ -10917,15 +11127,16 @@ begin
if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
-
-
-
-
-
-
-
-
+ if (jtag_access == 1'b1)
+ begin
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_we_o <= 1'b0;
+ jtag_access <= 1'b0;
+ end
+ else
+
begin
if (last_word == 1'b1)
@@ -10958,9 +11169,10 @@ begin
if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
begin
-
-
-
+
+
+ i_sel_o <= 4'b1111;
+
i_adr_o <= {first_address, 2'b00};
i_cyc_o <= 1'b1;
@@ -10974,26 +11186,27 @@ begin
end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ else
+ begin
+ if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
+ begin
+ case (jtag_address[1:0])
+ 2'b00: i_sel_o <= 4'b1000;
+ 2'b01: i_sel_o <= 4'b0100;
+ 2'b10: i_sel_o <= 4'b0010;
+ 2'b11: i_sel_o <= 4'b0001;
+ endcase
+ i_adr_o <= jtag_address;
+ i_dat_o <= {4{jtag_write_data}};
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+ i_we_o <= jtag_write_enable;
+ i_cti_o <= 3'b111;
+ jtag_access <= 1'b1;
+ end
+ end
+
@@ -11468,443 +11681,523 @@ endmodule
-
-
-
+
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+module lm32_jtag_full_debug (
-
-
-
-
-
-
+ clk_i,
+ rst_i,
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+
+
+ csr,
+ csr_write_enable,
+ csr_write_data,
+ stall_x,
-
-
-
-
+
+
+ jtag_read_data,
+ jtag_access_complete,
-
-
+
+
+ exception_q_w,
-
+
+
+ jtx_csr_read_data,
+ jrx_csr_read_data,
-
-
+
+
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
-
-
-
-
-
-
-
+
+
+ jtag_break,
+ jtag_reset,
-
-
-
-
-
+ jtag_reg_d,
+ jtag_reg_addr_d
+ );
-
-
+input clk_i;
+input rst_i;
-
-
-
-
+input jtag_clk;
+input jtag_update;
+input [ 7:0] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+
+
+input [ (5-1):0] csr;
+input csr_write_enable;
+input [ (32-1):0] csr_write_data;
+input stall_x;
-
-
-
-
+
+
+input [ 7:0] jtag_read_data;
+input jtag_access_complete;
-
-
+
+
+input exception_q_w;
-
-
-
-
-
-
+
+output [ (32-1):0] jtx_csr_read_data;
+wire [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;
+wire [ (32-1):0] jrx_csr_read_data;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+output jtag_csr_write_enable;
+reg jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;
+wire [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;
+wire [ (5-1):0] jtag_csr;
+output jtag_read_enable;
+reg jtag_read_enable;
+output jtag_write_enable;
+reg jtag_write_enable;
+output [ 7:0] jtag_write_data;
+wire [ 7:0] jtag_write_data;
+output [ (32-1):0] jtag_address;
+wire [ (32-1):0] jtag_address;
-
-
-
-
-
-
-
+
+output jtag_break;
+reg jtag_break;
+output jtag_reset;
+reg jtag_reset;
+
+
+output [ 7:0] jtag_reg_d;
+reg [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
-
-
-
-
+reg rx_update;
+reg rx_update_r;
+reg rx_update_r_r;
+reg rx_update_r_r_r;
-
+wire [ 7:0] rx_byte;
+wire [2:0] rx_addr;
+
+
+reg [ 7:0] uart_tx_byte;
+reg uart_tx_valid;
+reg [ 7:0] uart_rx_byte;
+reg uart_rx_valid;
+
-
-
-
-
-
+reg [ 3:0] command;
+
-
+reg [ 7:0] jtag_byte_0;
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;
-
-
-
-
-
-
-
+reg [ 3:0] state;
+
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
-
-
-
-
-
-
-
+
+
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
+
+
+
+
+assign jtag_reg_addr_d[2] = processing;
-
-
-
-
+
+
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+
-
-
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ rx_update <= 1'b0;
+ rx_update_r <= 1'b0;
+ rx_update_r_r <= 1'b0;
+ rx_update_r_r_r <= 1'b0;
+ end
+ else
+ begin
+ rx_update <= jtag_update;
+ rx_update_r <= rx_update;
+ rx_update_r_r <= rx_update_r;
+ rx_update_r_r_r <= rx_update_r_r;
+ end
+end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 4'h0;
+ command <= 4'b0000;
+ jtag_reg_d <= 8'h00;
+
+ processing <= 1'b0;
+ jtag_csr_write_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
+ jtag_write_enable <= 1'b0;
+
-
+
-
-
-
-
-
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
-
-
-
-
+
+
+ uart_tx_byte <= 8'h00;
+ uart_tx_valid <= 1'b0;
+ uart_rx_byte <= 8'h00;
+ uart_rx_valid <= 1'b0;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ end
+ else
+ begin
+
+
+ if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
+ begin
+ case (csr)
+ 5'he:
+ begin
-
-
-
-
-
+ uart_tx_byte <= csr_write_data[ 7:0];
+ uart_tx_valid <= 1'b1;
+ end
+ 5'hf:
+ begin
-
-
-
-
-
+ uart_rx_valid <= 1'b0;
+ end
+ endcase
+ end
+
+
+
-
-
-
-
-
+ if (exception_q_w == 1'b1)
+ begin
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
+ end
+
-
-
-
-
-
+ case (state)
+ 4'h0:
+ begin
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ command <= rx_byte[7:4];
+ case (rx_addr)
+
-
-
-
-
-
-
-
+ 3'b000:
+ begin
+ case (rx_byte[7:4])
+
-
+ 4'b0001:
+ state <= 4'h1;
+ 4'b0011:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= 4'h6;
+ end
+ 4'b0010:
+ state <= 4'h1;
+ 4'b0100:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= 5;
+ end
+ 4'b0101:
+ state <= 4'h1;
+
-
-
+ 4'b0110:
+ begin
+
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
+
-
-
-
-
-
-
-
-
-
-
-
+ jtag_break <= 1'b1;
+ end
+ 4'b0111:
+ begin
+
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
+
-
-
-
-
-
+ jtag_reset <= 1'b1;
+ end
+ endcase
+ end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+ 3'b001:
+ begin
+ uart_rx_byte <= rx_byte;
+ uart_rx_valid <= 1'b1;
+ end
+ 3'b010:
+ begin
+ jtag_reg_d <= uart_tx_byte;
+ uart_tx_valid <= 1'b0;
+ end
+
+ default:
+ ;
+ endcase
+ end
+ end
+ 4'h1:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_0 <= rx_byte;
+ state <= 4'h2;
+ end
+ end
+ 4'h2:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_1 <= rx_byte;
+ state <= 4'h3;
+ end
+ end
+ 4'h3:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_2 <= rx_byte;
+ state <= 4'h4;
+ end
+ end
+ 4'h4:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_3 <= rx_byte;
+ if (command == 4'b0001)
+ state <= 4'h6;
+ else
+ state <= 4'h5;
+ end
+ end
+ 4'h5:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_4 <= rx_byte;
+ state <= 4'h6;
+ end
+ end
+ 4'h6:
+ begin
+ case (command)
+ 4'b0001,
+ 4'b0011:
+ begin
+ jtag_read_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
+ end
+ 4'b0010,
+ 4'b0100:
+ begin
+ jtag_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
+ end
+ 4'b0101:
+ begin
+ jtag_csr_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h8;
+ end
+ endcase
+ end
+ 4'h7:
+ begin
+ if (jtag_access_complete == 1'b1)
+ begin
+ jtag_read_enable <= 1'b0;
+ jtag_reg_d <= jtag_read_data;
+ jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
+ end
+ end
+ 4'h8:
+ begin
+ jtag_csr_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
+ end
+
+ endcase
+ end
+end
+
+endmodule
+
@@ -12259,7 +12552,7 @@ endmodule
-module lm32_interrupt_full (
+module lm32_interrupt_full_debug (
clk_i,
rst_i,
@@ -12268,17 +12561,18 @@ module lm32_interrupt_full (
stall_x,
-
-
-
- exception,
+ non_debug_exception,
+ debug_exception,
+
+
eret_q_x,
-
+ bret_q_x,
+
csr,
csr_write_data,
@@ -12307,20 +12601,21 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
-
-
-input exception;
+input non_debug_exception;
+input debug_exception;
+
+
input eret_q_x;
-
+input bret_q_x;
+
-input [ (3-1):0] csr;
+input [ (5-1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -12347,8 +12642,9 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
-
+reg bie;
+
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -12368,11 +12664,11 @@ assign asserted = ip | interrupt;
assign ie_csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
@@ -12386,19 +12682,19 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
+ 5'h2: csr_read_data = ip;
+ 5'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -12409,18 +12705,18 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
};
- 3'h2: csr_read_data = ip;
+ 5'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -12449,8 +12745,9 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
-
+ bie <= 1'b0;
+
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -12462,13 +12759,21 @@ always @(posedge clk_i )
ip <= asserted;
-
-
+
+ if (non_debug_exception == 1'b1)
+ begin
-
-
-
+ eie <= ie;
+ ie <= 1'b0;
+ end
+ else if (debug_exception == 1'b1)
+ begin
+ bie <= ie;
+ ie <= 1'b0;
+ end
+
+
@@ -12476,14 +12781,6 @@ always @(posedge clk_i )
- if (exception == 1'b1)
- begin
-
- eie <= ie;
- ie <= 1'b0;
- end
-
-
else if (stall_x == 1'b0)
begin
@@ -12501,26 +12798,28 @@ always @(posedge clk_i )
-
-
-
+ else if (bret_q_x == 1'b1)
+
+ ie <= bie;
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+ bie <= csr_write_data[2];
+
end
- if (csr == 3'h1)
+ if (csr == 5'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -12537,8 +12836,9 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
-
+ bie <= 1'b0;
+
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -12548,13 +12848,21 @@ always @(posedge clk_i )
ip <= asserted;
-
-
+
+ if (non_debug_exception == 1'b1)
+ begin
-
-
-
+ eie <= ie;
+ ie <= 1'b0;
+ end
+ else if (debug_exception == 1'b1)
+ begin
+ bie <= ie;
+ ie <= 1'b0;
+ end
+
+
@@ -12562,14 +12870,6 @@ always @(posedge clk_i )
- if (exception == 1'b1)
- begin
-
- eie <= ie;
- ie <= 1'b0;
- end
-
-
else if (stall_x == 1'b0)
begin
@@ -12585,24 +12885,26 @@ always @(posedge clk_i )
end
-
-
-
+ else if (bret_q_x == 1'b1)
+
+ ie <= bie;
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+ bie <= csr_write_data[2];
+
end
- if (csr == 3'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -12669,16 +12971,6 @@ endmodule
-
-
-
-
-
-
-
-
-
-
@@ -12704,12 +12996,13 @@ endmodule
-
+
+
+
+
-
-
-
+
@@ -12847,25 +13140,24 @@ endmodule
-
-
-
+
+
-
-
-
+
+
+
@@ -12968,47 +13260,27 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
+
-
+
-
-
-
-
@@ -13017,8 +13289,6 @@ endmodule
-
-
@@ -13026,19 +13296,28 @@ endmodule
+
+
-
+
+
-
+
+
+
+
+
+
+
+
-
@@ -13196,7 +13475,7 @@ endmodule
-module lm32_top_full_debug (
+module lm32_top_full (
clk_i,
rst_i,
@@ -13353,18 +13632,17 @@ wire [ (2-1):0] D_BTE_O;
-
-wire [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_q;
-wire jtag_update;
-wire [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_q;
-wire jtck;
-wire jrstn;
+
+
+
+
+
+
+
@@ -13440,7 +13718,7 @@ endfunction
-lm32_cpu_full_debug cpu (
+lm32_cpu_full cpu (
.clk_i (clk_i),
@@ -13461,13 +13739,12 @@ lm32_cpu_full_debug cpu (
-
- .jtag_clk (jtck),
- .jtag_update (jtag_update),
- .jtag_reg_q (jtag_reg_q),
- .jtag_reg_addr_q (jtag_reg_addr_q),
-
+
+
+
+
+
@@ -13496,10 +13773,9 @@ lm32_cpu_full_debug cpu (
+
+
- .jtag_reg_d (jtag_reg_d),
- .jtag_reg_addr_d (jtag_reg_addr_d),
-
@@ -13534,21 +13810,20 @@ lm32_cpu_full_debug cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
-jtag_cores jtag_cores (
+
- .reg_d (jtag_reg_d),
- .reg_addr_d (jtag_reg_addr_d),
+
+
- .reg_update (jtag_update),
- .reg_q (jtag_reg_q),
- .reg_addr_q (jtag_reg_addr_q),
- .jtck (jtck),
- .jrstn (jrstn)
- );
-
+
+
+
+
+
+
+
endmodule
@@ -13920,7 +14195,7 @@ endmodule
-module lm32_mc_arithmetic_full_debug (
+module lm32_mc_arithmetic_full (
clk_i,
rst_i,
@@ -14586,7 +14861,7 @@ endmodule
-module lm32_cpu_full_debug (
+module lm32_cpu_full (
clk_i,
@@ -14607,13 +14882,12 @@ module lm32_cpu_full_debug (
-
- jtag_clk,
- jtag_update,
- jtag_reg_q,
- jtag_reg_addr_q,
-
+
+
+
+
+
@@ -14642,10 +14916,9 @@ module lm32_cpu_full_debug (
+
+
- jtag_reg_d,
- jtag_reg_addr_d,
-
@@ -14686,9 +14959,8 @@ module lm32_cpu_full_debug (
parameter eba_reset = 32'h00000000;
+
-parameter deba_reset = 32'h10000000;
-
@@ -14724,11 +14996,11 @@ parameter dcache_limit = 32'h7fffffff;
+
-parameter watchpoints = 32'h4;
-
-
+parameter watchpoints = 0;
+
@@ -14770,12 +15042,11 @@ input [ (32-1):0] interrupt;
+
+
+
+
-input jtag_clk;
-input jtag_update;
-input [ 7:0] jtag_reg_q;
-input [2:0] jtag_reg_addr_q;
-
@@ -14815,12 +15086,11 @@ input D_RTY_I;
+
+
+
+
-output [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_d;
-output [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_d;
-
@@ -15000,15 +15270,14 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (5-1):0] csr_d;
-reg [ (5-1):0] csr_x;
+wire [ (3-1):0] csr_d;
+reg [ (3-1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
+
+
-wire break_d;
-reg break_x;
-
wire scall_d;
reg scall_x;
@@ -15021,16 +15290,14 @@ reg eret_m;
-
-wire bret_d;
-reg bret_x;
-wire bret_q_x;
-reg bret_m;
-
+
+
+
+
+
-
wire csr_write_enable_d;
reg csr_write_enable_x;
@@ -15236,32 +15503,25 @@ wire stall_wb_load;
-
-
-
-wire [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+
+
+
+
+
+
-
-wire jtag_csr_write_enable;
-wire [ (32-1):0] jtag_csr_write_data;
-wire [ (5-1):0] jtag_csr;
-wire jtag_read_enable;
-wire [ 7:0] jtag_read_data;
-wire jtag_write_enable;
-wire [ 7:0] jtag_write_data;
-wire [ (32-1):0] jtag_address;
-wire jtag_access_complete;
-
-
-wire jtag_break;
+
+
+
+
@@ -15294,9 +15554,8 @@ wire kill_w;
reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
+
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
-
reg [ (3-1):0] eid_x;
@@ -15306,39 +15565,34 @@ reg [ (3-1):0] eid_x;
-
-
-
-wire dc_ss;
+
-wire dc_re;
-wire exception_x;
-reg exception_m;
-wire debug_exception_x;
-reg debug_exception_m;
-reg debug_exception_w;
-wire debug_exception_q_w;
-wire non_debug_exception_x;
-reg non_debug_exception_m;
-reg non_debug_exception_w;
-wire non_debug_exception_q_w;
-
+
+
+
+
+
+
+
+wire exception_x;
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+
-
-
-wire reset_exception;
+
+
-
@@ -15346,10 +15600,9 @@ wire interrupt_exception;
+
+
-wire breakpoint_exception;
-wire watchpoint_exception;
-
@@ -15433,7 +15686,7 @@ endfunction
-lm32_instruction_unit_full_debug #(
+lm32_instruction_unit_full #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -15492,12 +15745,11 @@ lm32_instruction_unit_full_debug #(
+
+
+
+
- .jtag_read_enable (jtag_read_enable),
- .jtag_write_enable (jtag_write_enable),
- .jtag_write_data (jtag_write_data),
- .jtag_address (jtag_address),
-
@@ -15533,10 +15785,9 @@ lm32_instruction_unit_full_debug #(
+
+
- .jtag_read_data (jtag_read_data),
- .jtag_access_complete (jtag_access_complete),
-
@@ -15552,7 +15803,7 @@ lm32_instruction_unit_full_debug #(
);
-lm32_decoder_full_debug decoder (
+lm32_decoder_full decoder (
.instruction (instruction_d),
@@ -15633,16 +15884,14 @@ lm32_decoder_full_debug decoder (
.branch_reg (branch_reg_d),
.condition (condition_d),
+
- .break_opcode (break_d),
-
.scall (scall_d),
.eret (eret_d),
+
- .bret (bret_d),
-
@@ -15652,7 +15901,7 @@ lm32_decoder_full_debug decoder (
);
-lm32_load_store_unit_full_debug #(
+lm32_load_store_unit_full #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -15788,7 +16037,7 @@ lm32_multiplier multiplier (
-lm32_mc_arithmetic_full_debug mc_arithmetic (
+lm32_mc_arithmetic_full mc_arithmetic (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -15827,7 +16076,7 @@ lm32_mc_arithmetic_full_debug mc_arithmetic (
-lm32_interrupt_full_debug interrupt_unit (
+lm32_interrupt_full interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -15836,18 +16085,17 @@ lm32_interrupt_full_debug interrupt_unit (
.stall_x (stall_x),
+
+
- .non_debug_exception (non_debug_exception_q_w),
- .debug_exception (debug_exception_q_w),
-
-
+ .exception (exception_q_w),
+
.eret_q_x (eret_q_x),
+
- .bret_q_x (bret_q_x),
-
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -15862,117 +16110,95 @@ lm32_interrupt_full_debug interrupt_unit (
-
-lm32_jtag_full_debug jtag (
+
- .clk_i (clk_i),
- .rst_i (rst_i),
+
+
- .jtag_clk (jtag_clk),
- .jtag_update (jtag_update),
- .jtag_reg_q (jtag_reg_q),
- .jtag_reg_addr_q (jtag_reg_addr_q),
+
+
+
+
-
-
- .csr (csr_x),
- .csr_write_data (operand_1_x),
- .csr_write_enable (csr_write_enable_q_x),
- .stall_x (stall_x),
+
+
+
+
-
-
- .jtag_read_data (jtag_read_data),
- .jtag_access_complete (jtag_access_complete),
+
+
-
-
- .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
+
-
-
- .jtx_csr_read_data (jtx_csr_read_data),
- .jrx_csr_read_data (jrx_csr_read_data),
+
+
-
-
- .jtag_csr_write_enable (jtag_csr_write_enable),
- .jtag_csr_write_data (jtag_csr_write_data),
- .jtag_csr (jtag_csr),
- .jtag_read_enable (jtag_read_enable),
- .jtag_write_enable (jtag_write_enable),
- .jtag_write_data (jtag_write_data),
- .jtag_address (jtag_address),
+
+
+
+
+
+
+
-
-
- .jtag_break (jtag_break),
- .jtag_reset (reset_exception),
+
+
- .jtag_reg_d (jtag_reg_d),
- .jtag_reg_addr_d (jtag_reg_addr_d)
- );
-
-
-
-
-
-
-lm32_debug_full_debug #(
- .breakpoints (breakpoints),
- .watchpoints (watchpoints)
- ) hw_debug (
+
+
- .clk_i (clk_i),
- .rst_i (rst_i),
- .pc_x (pc_x),
- .load_x (load_x),
- .store_x (store_x),
- .load_store_address_x (adder_result_x),
- .csr_write_enable_x (csr_write_enable_q_x),
- .csr_write_data (operand_1_x),
- .csr_x (csr_x),
-
- .jtag_csr_write_enable (jtag_csr_write_enable),
- .jtag_csr_write_data (jtag_csr_write_data),
- .jtag_csr (jtag_csr),
-
-
- .eret_q_x (eret_q_x),
- .bret_q_x (bret_q_x),
- .stall_x (stall_x),
- .exception_x (exception_x),
- .q_x (q_x),
- .dcache_refill_request (dcache_refill_request),
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
- .dc_ss (dc_ss),
+
+
+
+
+
+
+
- .dc_re (dc_re),
- .bp_match (bp_match),
- .wp_match (wp_match)
- );
-
@@ -16472,25 +16698,21 @@ assign kill_w = 1'b0
-
-assign breakpoint_exception = ( ( (break_x == 1'b1)
- || (bp_match == 1'b1)
- )
- && (valid_x == 1'b1)
- )
-
-
- || (jtag_break == 1'b1)
+
+
+
+
+
+
+
+
- ;
-
+
-assign watchpoint_exception = wp_match == 1'b1;
-
@@ -16517,17 +16739,38 @@ assign system_call_exception = ( (scall_x == 1'b1)
);
+
+
+
-assign debug_exception_x = (breakpoint_exception == 1'b1)
- || (watchpoint_exception == 1'b1)
- ;
+
+
+
-assign non_debug_exception_x = (system_call_exception == 1'b1)
-
+
+
+
- || (reset_exception == 1'b1)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+assign exception_x = (system_call_exception == 1'b1)
|| (instruction_bus_error_exception == 1'b1)
@@ -16543,9 +16786,8 @@ assign non_debug_exception_x = (system_call_exception == 1'b1)
|| ( (interrupt_exception == 1'b1)
+
- && (dc_ss == 1'b0)
-
@@ -16557,55 +16799,27 @@ assign non_debug_exception_x = (system_call_exception == 1'b1)
;
-
-assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
always @(*)
begin
-
-
-
- if (reset_exception == 1'b1)
- eid_x = 3'h0;
- else
+
+
+
-
-
- if (data_bus_error_exception == 1'b1)
- eid_x = 3'h4;
- else
+
+
+
+
+
+
+
- if (breakpoint_exception == 1'b1)
- eid_x = 3'd1;
- else
-
@@ -16618,11 +16832,10 @@ begin
+
+
+
- if (watchpoint_exception == 1'b1)
- eid_x = 3'd3;
- else
-
@@ -16635,9 +16848,8 @@ begin
if ( (interrupt_exception == 1'b1)
+
- && (dc_ss == 1'b0)
-
)
eid_x = 3'h6;
@@ -16674,19 +16886,18 @@ assign stall_d = (stall_x == 1'b1)
&& (kill_d == 1'b0)
)
+
+
+
+
+
+
+
+
+
+
+
- || ( ( (break_d == 1'b1)
- || (bret_d == 1'b1)
- )
- && ( (load_q_x == 1'b1)
- || (store_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
- )
- && (kill_d == 1'b0)
- )
-
|| ( (csr_write_enable_d == 1'b1)
&& (load_q_x == 1'b1)
@@ -16792,24 +17003,21 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+
-assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
-
assign load_q_x = (load_x == 1'b1)
&& (q_x == 1'b1)
+
- && (bp_match == 1'b0)
-
;
assign store_q_x = (store_x == 1'b1)
&& (q_x == 1'b1)
+
- && (bp_match == 1'b0)
-
;
@@ -16820,13 +17028,13 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
-assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
-
+
+assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
+
+
assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
@@ -16841,12 +17049,12 @@ assign cfg = {
breakpoints[3:0],
interrupts[5:0],
-
- 1'b1,
-
+ 1'b0,
+
+
@@ -16855,19 +17063,19 @@ assign cfg = {
-
- 1'b1,
-
-
-
- 1'b1,
+ 1'b0,
+
+
+ 1'b0,
+
+
1'b1,
@@ -16948,17 +17156,16 @@ assign cfg2 = {
assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 5'h3)
+ && (csr_d == 3'h3)
&& (stall_d == 1'b0)
&& (kill_d == 1'b0)
&& (valid_d == 1'b1))
+
+
+
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h3))
-
;
@@ -16966,21 +17173,20 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
assign dflush_x = ( (csr_write_enable_q_x == 1'b1)
- && (csr_x == 5'h4))
+ && (csr_x == 3'h4))
+
+
+
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h4))
-
;
-assign csr_d = read_idx_0_d[ (5-1):0];
+assign csr_d = read_idx_0_d[ (3-1):0];
always @(*)
@@ -16988,29 +17194,27 @@ begin
case (csr_x)
- 5'h0,
- 5'h1,
- 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 3'h0,
+ 3'h1,
+ 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 5'h6: csr_read_data_x = cfg;
- 5'h7: csr_read_data_x = {eba, 8'h00};
+ 3'h6: csr_read_data_x = cfg;
+ 3'h7: csr_read_data_x = {eba, 8'h00};
+
- 5'h9: csr_read_data_x = {deba, 8'h00};
-
+
+
- 5'he: csr_read_data_x = jtx_csr_read_data;
- 5'hf: csr_read_data_x = jrx_csr_read_data;
-
- 5'ha: csr_read_data_x = cfg2;
+ 3'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -17027,37 +17231,33 @@ begin
eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
- eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
end
end
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
- else
- begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
- deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
- deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+
+
+
+
+
+
+
+
+
+
- end
-end
-
@@ -17239,7 +17439,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 5{1'b0}};
+ csr_x <= { 3{1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -17262,16 +17462,14 @@ begin
branch_predict_taken_x <= 1'b0;
condition_x <= 3'b000;
+
- break_x <= 1'b0;
-
scall_x <= 1'b0;
eret_x <= 1'b0;
+
- bret_x <= 1'b0;
-
@@ -17315,10 +17513,9 @@ begin
+
+
- debug_exception_m <= 1'b0;
- non_debug_exception_m <= 1'b0;
-
operand_w <= { 32{1'b0}};
w_result_sel_load_w <= 1'b0;
@@ -17330,13 +17527,13 @@ begin
write_idx_w <= { 5{1'b0}};
write_enable_w <= 1'b0;
-
- debug_exception_w <= 1'b0;
- non_debug_exception_w <= 1'b0;
-
+
+ exception_w <= 1'b0;
+
+
memop_pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
@@ -17416,9 +17613,8 @@ begin
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
+
- break_x <= break_d;
-
scall_x <= scall_d;
@@ -17428,9 +17624,8 @@ begin
eret_x <= eret_d;
+
- bret_x <= bret_d;
-
write_enable_x <= write_enable_d;
end
@@ -17482,40 +17677,40 @@ begin
-
- if (non_debug_exception_x == 1'b1)
- write_idx_m <= 5'd30;
- else if (debug_exception_x == 1'b1)
- write_idx_m <= 5'd31;
- else
- write_idx_m <= write_idx_x;
-
-
+
+
+
+ if (exception_x == 1'b1)
+ write_idx_m <= 5'd30;
+ else
+ write_idx_m <= write_idx_x;
+
+
condition_met_m <= condition_met_x;
+
+
+
+
+
+
+
+
+
- if (exception_x == 1'b1)
- if ((dc_re == 1'b1)
- || ((debug_exception_x == 1'b1)
- && (non_debug_exception_x == 1'b0)))
- branch_target_m <= {deba, eid_x, {3{1'b0}}};
- else
- branch_target_m <= {eba, eid_x, {3{1'b0}}};
- else
- branch_target_m <= branch_target_x;
-
-
+ branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+
@@ -17528,16 +17723,14 @@ begin
eret_m <= eret_q_x;
+
- bret_m <= bret_q_x;
-
write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
+
- debug_exception_m <= debug_exception_x;
- non_debug_exception_m <= non_debug_exception_x;
-
end
@@ -17552,9 +17745,8 @@ begin
data_bus_error_exception_m <= (data_bus_error_exception == 1'b1)
+
- && (reset_exception == 1'b0)
-
;
@@ -17586,12 +17778,12 @@ begin
write_enable_w <= write_enable_m;
-
- debug_exception_w <= debug_exception_m;
- non_debug_exception_w <= non_debug_exception_m;
-
+
+
+ exception_w <= exception_m;
+
@@ -18137,7 +18329,7 @@ endmodule
-module lm32_load_store_unit_full_debug (
+module lm32_load_store_unit_full (
clk_i,
rst_i,
@@ -18515,7 +18707,7 @@ endfunction
-lm32_dcache_full_debug #(
+lm32_dcache_full #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -19467,7 +19659,7 @@ endmodule
-module lm32_decoder_full_debug (
+module lm32_decoder_full (
instruction,
@@ -19548,16 +19740,14 @@ module lm32_decoder_full_debug (
bi_conditional,
bi_unconditional,
+
- break_opcode,
-
scall,
eret,
+
- bret,
-
@@ -19693,20 +19883,18 @@ wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-output break_opcode;
-wire break_opcode;
+
+
output scall;
wire scall;
output eret;
wire eret;
-
-output bret;
-wire bret;
+
+
@@ -20070,16 +20258,14 @@ assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
+
-assign break_opcode = op_raise & ~instruction[2];
-
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
+
-assign bret = op_b & (instruction[25:21] == 5'd31);
-
@@ -20511,7 +20697,7 @@ endmodule
-module lm32_icache_full_debug (
+module lm32_icache_full (
clk_i,
rst_i,
@@ -21357,7 +21543,7 @@ endmodule
-module lm32_dcache_full_debug (
+module lm32_dcache_full (
clk_i,
rst_i,
@@ -22213,163 +22399,135 @@ endmodule
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-module lm32_debug_full_debug (
- clk_i,
- rst_i,
- pc_x,
- load_x,
- store_x,
- load_store_address_x,
- csr_write_enable_x,
- csr_write_data,
- csr_x,
-
-
- jtag_csr_write_enable,
- jtag_csr_write_data,
- jtag_csr,
+
+
+
+
+
+
+
+
+
+
+
+
-
-
- eret_q_x,
- bret_q_x,
- stall_x,
- exception_x,
- q_x,
-
-
- dcache_refill_request,
-
+
+
+
+
+
-
-
- dc_ss,
-
- dc_re,
- bp_match,
- wp_match
- );
+
+
+
+
+
+
+
-parameter breakpoints = 0;
-parameter watchpoints = 0;
+
+
-input clk_i;
-input rst_i;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-input load_x;
-input store_x;
-input [ (32-1):0] load_store_address_x;
-input csr_write_enable_x;
-input [ (32-1):0] csr_write_data;
-input [ (5-1):0] csr_x;
-
+
+
-input jtag_csr_write_enable;
-input [ (32-1):0] jtag_csr_write_data;
-input [ (5-1):0] jtag_csr;
+
+
+
+
+
+
+
+
+
+
-
-
-input eret_q_x;
-input bret_q_x;
-input stall_x;
-input exception_x;
-input q_x;
-
-
-input dcache_refill_request;
-
+
+
+
+
+
+
-
-output dc_ss;
-reg dc_ss;
+
+
-output dc_re;
-reg dc_re;
-output bp_match;
-wire bp_match;
-output wp_match;
-wire wp_match;
-
-
-
+
+
+
+
+
+
-genvar i;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
-reg bp_e[0:breakpoints-1];
-wire [0:breakpoints-1]bp_match_n;
+
-reg [ 1:0] wpc_c[0:watchpoints-1];
-reg [ (32-1):0] wp[0:watchpoints-1];
-wire [0:watchpoints]wp_match_n;
-wire debug_csr_write_enable;
-wire [ (32-1):0] debug_csr_write_data;
-wire [ (5-1):0] debug_csr;
-
+
+
+
+
+
+
-reg [ 2:0] state;
+
+
+
+
-
-
+
@@ -22377,15 +22535,48 @@ reg [ 2:0] state;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -22394,224 +22585,132 @@ reg [ 2:0] state;
+
+
+
-
-function integer clogb2;
-input [31:0] value;
-begin
- for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
- value = value >> 1;
-end
-endfunction
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-function integer clogb2_v1;
-input [31:0] value;
-reg [31:0] i;
-reg [31:0] temp;
-begin
- temp = 0;
- i = 0;
- for (i = 0; temp < value; i = i + 1)
- temp = 1<<i;
- clogb2_v1 = i-1;
-end
-endfunction
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-generate
- for (i = 0; i < breakpoints; i = i + 1)
- begin : bp_comb
-assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
- end
-endgenerate
-generate
-
+
+
+
+
+
+
+
+
- if (breakpoints > 0)
-assign bp_match = (|bp_match_n) || (state == 3'b011);
- else
-assign bp_match = state == 3'b011;
-
-
-
-
+
-endgenerate
+
+
+
+
+
+
+
-
-generate
- for (i = 0; i < watchpoints; i = i + 1)
- begin : wp_comb
-assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
- end
-endgenerate
-generate
- if (watchpoints > 0)
-assign wp_match = |wp_match_n;
- else
-assign wp_match = 1'b0;
-endgenerate
-
-
+
+
-
-assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
-assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
-assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-generate
- for (i = 0; i < breakpoints; i = i + 1)
- begin : bp_seq
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- bp_e[i] <= 1'b0;
- end
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
- begin
- bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
- bp_e[i] <= debug_csr_write_data[0];
- end
- end
-end
- end
-endgenerate
-
-
-generate
- for (i = 0; i < watchpoints; i = i + 1)
- begin : wp_seq
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- wp[i] <= { 32{1'bx}};
- wpc_c[i] <= 2'b00;
- end
- else
- begin
- if (debug_csr_write_enable == 1'b1)
- begin
- if (debug_csr == 5'h8)
- wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
- if (debug_csr == 5'h18 + i)
- wp[i] <= debug_csr_write_data;
- end
- end
-end
- end
-endgenerate
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- dc_re <= 1'b0;
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
- dc_re <= debug_csr_write_data[1];
- end
-end
-
-
-
+
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 3'b000;
- dc_ss <= 1'b0;
- end
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
- begin
- dc_ss <= debug_csr_write_data[0];
- if (debug_csr_write_data[0] == 1'b0)
- state <= 3'b000;
- else
- state <= 3'b001;
- end
- case (state)
- 3'b001:
- begin
+
- if ( ( (eret_q_x == 1'b1)
- || (bret_q_x == 1'b1)
- )
- && (stall_x == 1'b0)
- )
- state <= 3'b010;
- end
- 3'b010:
- begin
+
+
- if ((q_x == 1'b1) && (stall_x == 1'b0))
- state <= 3'b011;
- end
- 3'b011:
- begin
+
+
+
-
-
- if (dcache_refill_request == 1'b1)
- state <= 3'b010;
- else
+
+
+
+
+
+
+
+
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- begin
- dc_ss <= 1'b0;
- state <= 3'b100;
- end
- end
- 3'b100:
- begin
-
-
- if (dcache_refill_request == 1'b1)
- state <= 3'b010;
- else
-
- state <= 3'b000;
- end
- endcase
- end
-end
-
-endmodule
-
@@ -22984,7 +23083,7 @@ endmodule
-module lm32_instruction_unit_full_debug (
+module lm32_instruction_unit_full (
clk_i,
rst_i,
@@ -23037,12 +23136,11 @@ module lm32_instruction_unit_full_debug (
+
+
+
+
- jtag_read_enable,
- jtag_write_enable,
- jtag_write_data,
- jtag_address,
-
@@ -23078,10 +23176,9 @@ module lm32_instruction_unit_full_debug (
+
+
- jtag_read_data,
- jtag_access_complete,
-
@@ -23171,12 +23268,11 @@ input i_rty_i;
+
+
+
+
-input jtag_read_enable;
-input jtag_write_enable;
-input [ 7:0] jtag_write_data;
-input [ (32-1):0] jtag_address;
-
@@ -23217,11 +23313,11 @@ wire icache_refilling;
output [ (32-1):0] i_dat_o;
+
-reg [ (32-1):0] i_dat_o;
-
-
+wire [ (32-1):0] i_dat_o;
+
output [ (32-1):0] i_adr_o;
reg [ (32-1):0] i_adr_o;
@@ -23229,21 +23325,21 @@ output i_cyc_o;
reg i_cyc_o;
output [ (4-1):0] i_sel_o;
+
-reg [ (4-1):0] i_sel_o;
-
-
+wire [ (4-1):0] i_sel_o;
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
+
-reg i_we_o;
-
-
+wire i_we_o;
+
output [ (3-1):0] i_cti_o;
reg [ (3-1):0] i_cti_o;
@@ -23255,12 +23351,11 @@ wire [ (2-1):0] i_bte_o;
+
+
+
+
-output [ 7:0] jtag_read_data;
-reg [ 7:0] jtag_read_data;
-output jtag_access_complete;
-wire jtag_access_complete;
-
@@ -23326,9 +23421,8 @@ reg bus_error_f;
+
-reg jtag_access;
-
@@ -23446,7 +23540,7 @@ endfunction
-lm32_icache_full_debug #(
+lm32_icache_full #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -23569,11 +23663,11 @@ assign instruction_f = icache_data_f;
-
-
-
-
+assign i_dat_o = 32'd0;
+assign i_we_o = 1'b0;
+assign i_sel_o = 4'b1111;
+
assign i_bte_o = 2'b00;
@@ -23690,18 +23784,17 @@ end
-
-assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
-always @(*)
-begin
- case (jtag_address[1:0])
- 2'b00: jtag_read_data = i_dat_i[ 31:24];
- 2'b01: jtag_read_data = i_dat_i[ 23:16];
- 2'b10: jtag_read_data = i_dat_i[ 15:8];
- 2'b11: jtag_read_data = i_dat_i[ 7:0];
- endcase
-end
+
+
+
+
+
+
+
+
+
+
@@ -23726,11 +23819,10 @@ begin
+
+
+
- i_we_o <= 1'b0;
- i_sel_o <= 4'b1111;
- jtag_access <= 1'b0;
-
end
else
@@ -23743,16 +23835,15 @@ begin
if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
+
+
+
+
+
+
+
+
- if (jtag_access == 1'b1)
- begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_we_o <= 1'b0;
- jtag_access <= 1'b0;
- end
- else
-
begin
if (last_word == 1'b1)
@@ -23785,10 +23876,9 @@ begin
if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
begin
-
-
- i_sel_o <= 4'b1111;
-
+
+
+
i_adr_o <= {first_address, 2'b00};
i_cyc_o <= 1'b1;
@@ -23802,27 +23892,26 @@ begin
end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- else
- begin
- if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
- begin
- case (jtag_address[1:0])
- 2'b00: i_sel_o <= 4'b1000;
- 2'b01: i_sel_o <= 4'b0100;
- 2'b10: i_sel_o <= 4'b0010;
- 2'b11: i_sel_o <= 4'b0001;
- endcase
- i_adr_o <= jtag_address;
- i_dat_o <= {4{jtag_write_data}};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
- i_we_o <= jtag_write_enable;
- i_cti_o <= 3'b111;
- jtag_access <= 1'b1;
- end
- end
-
@@ -24297,523 +24386,443 @@ endmodule
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-
-
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-module lm32_jtag_full_debug (
- clk_i,
- rst_i,
- jtag_clk,
- jtag_update,
- jtag_reg_q,
- jtag_reg_addr_q,
-
-
- csr,
- csr_write_enable,
- csr_write_data,
- stall_x,
+
+
+
+
+
+
+
+
+
+
-
-
- jtag_read_data,
- jtag_access_complete,
+
+
-
-
- exception_q_w,
-
-
- jtx_csr_read_data,
- jrx_csr_read_data,
+
+
+
-
-
- jtag_csr_write_enable,
- jtag_csr_write_data,
- jtag_csr,
- jtag_read_enable,
- jtag_write_enable,
- jtag_write_data,
- jtag_address,
+
+
+
+
+
+
+
-
-
- jtag_break,
- jtag_reset,
+
+
- jtag_reg_d,
- jtag_reg_addr_d
- );
-
+
+
+
-input clk_i;
-input rst_i;
-input jtag_clk;
-input jtag_update;
-input [ 7:0] jtag_reg_q;
-input [2:0] jtag_reg_addr_q;
+
+
-
+
+
+
+
-input [ (5-1):0] csr;
-input csr_write_enable;
-input [ (32-1):0] csr_write_data;
-input stall_x;
+
+
+
+
-
-
-input [ 7:0] jtag_read_data;
-input jtag_access_complete;
+
+
-
-
-input exception_q_w;
+
-
-
-output [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jtx_csr_read_data;
-output [ (32-1):0] jrx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+
+
+
-
-
-output jtag_csr_write_enable;
-reg jtag_csr_write_enable;
-output [ (32-1):0] jtag_csr_write_data;
-wire [ (32-1):0] jtag_csr_write_data;
-output [ (5-1):0] jtag_csr;
-wire [ (5-1):0] jtag_csr;
-output jtag_read_enable;
-reg jtag_read_enable;
-output jtag_write_enable;
-reg jtag_write_enable;
-output [ 7:0] jtag_write_data;
-wire [ 7:0] jtag_write_data;
-output [ (32-1):0] jtag_address;
-wire [ (32-1):0] jtag_address;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-output jtag_break;
-reg jtag_break;
-output jtag_reset;
-reg jtag_reset;
+
+
+
+
-output [ 7:0] jtag_reg_d;
-reg [ 7:0] jtag_reg_d;
-output [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_d;
+
+
+
+
-reg rx_update;
-reg rx_update_r;
-reg rx_update_r_r;
-reg rx_update_r_r_r;
-
+
+
+
+
-wire [ 7:0] rx_byte;
-wire [2:0] rx_addr;
+
-
-reg [ 7:0] uart_tx_byte;
-reg uart_tx_valid;
-reg [ 7:0] uart_rx_byte;
-reg uart_rx_valid;
-
+
+
+
+
+
-reg [ 3:0] command;
-
-reg [ 7:0] jtag_byte_0;
-reg [ 7:0] jtag_byte_1;
-reg [ 7:0] jtag_byte_2;
-reg [ 7:0] jtag_byte_3;
-reg [ 7:0] jtag_byte_4;
-reg processing;
+
+
+
+
+
+
+
-reg [ 3:0] state;
-
+
-
-assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_csr = jtag_byte_4[ (5-1):0];
-assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_write_data = jtag_byte_4;
+
+
+
+
-
-
-assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
-
-
-
+
+
-
+
-assign jtag_reg_addr_d[2] = processing;
+
-
-
-assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
-assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
-
+
+
+
-assign rx_byte = jtag_reg_q;
-assign rx_addr = jtag_reg_addr_q;
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- rx_update <= 1'b0;
- rx_update_r <= 1'b0;
- rx_update_r_r <= 1'b0;
- rx_update_r_r_r <= 1'b0;
- end
- else
- begin
- rx_update <= jtag_update;
- rx_update_r <= rx_update;
- rx_update_r_r <= rx_update_r;
- rx_update_r_r_r <= rx_update_r_r;
- end
-end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 4'h0;
- command <= 4'b0000;
- jtag_reg_d <= 8'h00;
-
- processing <= 1'b0;
- jtag_csr_write_enable <= 1'b0;
- jtag_read_enable <= 1'b0;
- jtag_write_enable <= 1'b0;
-
-
+
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
+
+
+
+
+
+
+
+
+
-
-
- uart_tx_byte <= 8'h00;
- uart_tx_valid <= 1'b0;
- uart_rx_byte <= 8'h00;
- uart_rx_valid <= 1'b0;
+
+
- end
- else
- begin
-
-
- if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
- begin
- case (csr)
- 5'he:
- begin
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- uart_tx_byte <= csr_write_data[ 7:0];
- uart_tx_valid <= 1'b1;
- end
- 5'hf:
- begin
+
+
+
+
+
- uart_rx_valid <= 1'b0;
- end
- endcase
- end
-
-
-
+
+
+
+
+
+
+
+
+
+
- if (exception_q_w == 1'b1)
- begin
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
- end
-
- case (state)
- 4'h0:
- begin
+
+
+
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- command <= rx_byte[7:4];
- case (rx_addr)
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- 3'b000:
- begin
- case (rx_byte[7:4])
-
+
+
+
+
+
+
+
- 4'b0001:
- state <= 4'h1;
- 4'b0011:
- begin
- {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 4'h6;
- end
- 4'b0010:
- state <= 4'h1;
- 4'b0100:
- begin
- {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 5;
- end
- 4'b0101:
- state <= 4'h1;
-
+
- 4'b0110:
- begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+
- jtag_break <= 1'b1;
- end
- 4'b0111:
- begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+
+
+
+
+
+
+
+
+
+
- jtag_reset <= 1'b1;
- end
- endcase
- end
+
+
+
+
+
-
-
+
+
- 3'b001:
- begin
- uart_rx_byte <= rx_byte;
- uart_rx_valid <= 1'b1;
- end
- 3'b010:
- begin
- jtag_reg_d <= uart_tx_byte;
- uart_tx_valid <= 1'b0;
- end
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- default:
- ;
- endcase
- end
- end
- 4'h1:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_0 <= rx_byte;
- state <= 4'h2;
- end
- end
- 4'h2:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_1 <= rx_byte;
- state <= 4'h3;
- end
- end
- 4'h3:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_2 <= rx_byte;
- state <= 4'h4;
- end
- end
- 4'h4:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_3 <= rx_byte;
- if (command == 4'b0001)
- state <= 4'h6;
- else
- state <= 4'h5;
- end
- end
- 4'h5:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_4 <= rx_byte;
- state <= 4'h6;
- end
- end
- 4'h6:
- begin
- case (command)
- 4'b0001,
- 4'b0011:
- begin
- jtag_read_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
- end
- 4'b0010,
- 4'b0100:
- begin
- jtag_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
- end
- 4'b0101:
- begin
- jtag_csr_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h8;
- end
- endcase
- end
- 4'h7:
- begin
- if (jtag_access_complete == 1'b1)
- begin
- jtag_read_enable <= 1'b0;
- jtag_reg_d <= jtag_read_data;
- jtag_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
- end
- end
- 4'h8:
- begin
- jtag_csr_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
- end
-
- endcase
- end
-end
-
-endmodule
-
@@ -25168,7 +25177,7 @@ endmodule
-module lm32_interrupt_full_debug (
+module lm32_interrupt_full (
clk_i,
rst_i,
@@ -25177,18 +25186,17 @@ module lm32_interrupt_full_debug (
stall_x,
-
- non_debug_exception,
- debug_exception,
-
+
+
+ exception,
+
eret_q_x,
+
- bret_q_x,
-
csr,
csr_write_data,
@@ -25217,21 +25225,20 @@ input [interrupts-1:0] interrupt;
input stall_x;
+
+
-input non_debug_exception;
-input debug_exception;
-
-
+input exception;
+
input eret_q_x;
+
-input bret_q_x;
-
-input [ (5-1):0] csr;
+input [ (3-1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -25258,9 +25265,8 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
+
-reg bie;
-
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -25280,11 +25286,11 @@ assign asserted = ip | interrupt;
assign ie_csr_read_data = {{ 32-3{1'b0}},
-
- bie,
-
+
+ 1'b0,
+
eie,
ie
@@ -25298,19 +25304,19 @@ generate
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
+ 3'h0: csr_read_data = {{ 32-3{1'b0}},
+
- bie,
-
-
+ 1'b0,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- 5'h1: csr_read_data = im;
+ 3'h2: csr_read_data = ip;
+ 3'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -25321,18 +25327,18 @@ end
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
+ 3'h0: csr_read_data = {{ 32-3{1'b0}},
+
- bie,
-
-
+ 1'b0,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
+ 3'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -25361,9 +25367,8 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
+
- bie <= 1'b0;
-
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -25375,21 +25380,13 @@ always @(posedge clk_i )
ip <= asserted;
-
- if (non_debug_exception == 1'b1)
- begin
+
+
- eie <= ie;
- ie <= 1'b0;
- end
- else if (debug_exception == 1'b1)
- begin
+
+
+
- bie <= ie;
- ie <= 1'b0;
- end
-
-
@@ -25397,6 +25394,14 @@ always @(posedge clk_i )
+ if (exception == 1'b1)
+ begin
+
+ eie <= ie;
+ ie <= 1'b0;
+ end
+
+
else if (stall_x == 1'b0)
begin
@@ -25414,28 +25419,26 @@ always @(posedge clk_i )
-
- else if (bret_q_x == 1'b1)
- ie <= bie;
-
+
+
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
+
- bie <= csr_write_data[2];
-
end
- if (csr == 5'h1)
+ if (csr == 3'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 5'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -25452,9 +25455,8 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
+
- bie <= 1'b0;
-
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -25464,21 +25466,13 @@ always @(posedge clk_i )
ip <= asserted;
-
- if (non_debug_exception == 1'b1)
- begin
+
+
- eie <= ie;
- ie <= 1'b0;
- end
- else if (debug_exception == 1'b1)
- begin
+
+
+
- bie <= ie;
- ie <= 1'b0;
- end
-
-
@@ -25486,6 +25480,14 @@ always @(posedge clk_i )
+ if (exception == 1'b1)
+ begin
+
+ eie <= ie;
+ ie <= 1'b0;
+ end
+
+
else if (stall_x == 1'b0)
begin
@@ -25501,26 +25503,24 @@ always @(posedge clk_i )
end
-
- else if (bret_q_x == 1'b1)
- ie <= bie;
-
+
+
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
+
- bie <= csr_write_data[2];
-
end
- if (csr == 5'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -25577,6 +25577,10 @@ endmodule
+
+
+
+
@@ -25602,13 +25606,20 @@ endmodule
-
-
-
-
+
+
-
+
+
+
+
+
+
+
+
+
+
@@ -25708,18 +25719,16 @@ endmodule
-
-
-
-
+
+
+
-
@@ -25748,24 +25757,25 @@ endmodule
-
+
+
-
-
+
+
+
+
-
-
@@ -25866,24 +25876,34 @@ endmodule
-
-
+
+
+
+
+
+
+
+
+
+
-
+
-
+
+
+
@@ -25895,6 +25915,8 @@ endmodule
+
+
@@ -25902,27 +25924,28 @@ endmodule
-
-
+
-
-
+
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
@@ -25984,14 +26007,14 @@ endmodule
-
-
+
+
+
-
@@ -26081,7 +26104,7 @@ endmodule
-module lm32_top_medium (
+module lm32_top_medium_debug (
clk_i,
rst_i,
@@ -26238,14 +26261,15 @@ wire [ (2-1):0] D_BTE_O;
-
-
-
-
-
-
-
+wire [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
+
@@ -26324,7 +26348,7 @@ endfunction
-lm32_cpu_medium cpu (
+lm32_cpu_medium_debug cpu (
.clk_i (clk_i),
@@ -26345,12 +26369,13 @@ lm32_cpu_medium cpu (
-
-
-
-
-
+
+ .jtag_clk (jtck),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+
@@ -26379,9 +26404,10 @@ lm32_cpu_medium cpu (
-
-
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d),
+
@@ -26416,20 +26442,21 @@ lm32_cpu_medium cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
+
+jtag_cores jtag_cores (
-
-
-
-
-
-
-
-
+ .reg_d (jtag_reg_d),
+ .reg_addr_d (jtag_reg_addr_d),
-
+ .reg_update (jtag_update),
+ .reg_q (jtag_reg_q),
+ .reg_addr_q (jtag_reg_addr_q),
+ .jtck (jtck),
+ .jrstn (jrstn)
+ );
+
endmodule
@@ -26801,7 +26828,7 @@ endmodule
-module lm32_mc_arithmetic_medium (
+module lm32_mc_arithmetic_medium_debug (
clk_i,
rst_i,
@@ -27457,7 +27484,7 @@ endmodule
-module lm32_cpu_medium (
+module lm32_cpu_medium_debug (
clk_i,
@@ -27478,12 +27505,13 @@ module lm32_cpu_medium (
-
-
-
-
-
+
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+
@@ -27512,9 +27540,10 @@ module lm32_cpu_medium (
-
-
+ jtag_reg_d,
+ jtag_reg_addr_d,
+
@@ -27555,24 +27584,25 @@ module lm32_cpu_medium (
parameter eba_reset = 32'h00000000;
-
+parameter deba_reset = 32'h10000000;
+
-
-
-
-
-
-
-parameter icache_associativity = 1;
-parameter icache_sets = 512;
-parameter icache_bytes_per_line = 16;
-parameter icache_base_address = 0;
-parameter icache_limit = 0;
+parameter icache_associativity = 1;
+parameter icache_sets = 256;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 32'h0;
+parameter icache_limit = 32'h7fffffff;
+
+
+
+
+
+
@@ -27592,11 +27622,11 @@ parameter dcache_limit = 0;
-
-
-parameter watchpoints = 0;
+parameter watchpoints = 32'h4;
+
+
@@ -27638,11 +27668,12 @@ input [ (32-1):0] interrupt;
-
-
-
-
+input jtag_clk;
+input jtag_update;
+input [ 7:0] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+
@@ -27682,11 +27713,12 @@ input D_RTY_I;
-
-
-
-
+output [ 7:0] jtag_reg_d;
+wire [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
+
@@ -27750,8 +27782,9 @@ wire [ (2-1):0] D_BTE_O;
-
+reg valid_a;
+
reg valid_f;
reg valid_d;
@@ -27774,8 +27807,8 @@ reg [ 1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((32-2)+2-1):2] branch_predict_address_d;
-wire [ ((32-2)+2-1):2] branch_target_d;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -27787,9 +27820,9 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((32-2)+2-1):2] branch_offset_d;
-reg [ ((32-2)+2-1):2] branch_target_x;
-reg [ ((32-2)+2-1):2] branch_target_m;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
wire [ 0:0] d_result_sel_0_d;
wire [ 1:0] d_result_sel_1_d;
@@ -27864,14 +27897,15 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
+wire [ (5-1):0] csr_d;
+reg [ (5-1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
-
-
+wire break_d;
+reg break_x;
+
wire scall_d;
reg scall_x;
@@ -27884,14 +27918,16 @@ reg eret_m;
-
-
-
-
-
+
+wire bret_d;
+reg bret_x;
+wire bret_q_x;
+reg bret_m;
+
+
wire csr_write_enable_d;
reg csr_write_enable_x;
@@ -28043,11 +28079,11 @@ wire [ (32-1):0] cfg2;
reg [ (32-1):0] csr_read_data_x;
-wire [ ((32-2)+2-1):2] pc_f;
-wire [ ((32-2)+2-1):2] pc_d;
-wire [ ((32-2)+2-1):2] pc_x;
-wire [ ((32-2)+2-1):2] pc_m;
-wire [ ((32-2)+2-1):2] pc_w;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
@@ -28061,12 +28097,13 @@ wire [ (32-1):0] instruction_f;
wire [ (32-1):0] instruction_d;
-
-
-
-
-
+wire iflush;
+wire icache_stall_request;
+wire icache_restart_request;
+wire icache_refill_request;
+wire icache_refilling;
+
@@ -28092,25 +28129,32 @@ wire stall_wb_load;
-
-
-
-
-
-
-
-
+
+wire [ (32-1):0] jtx_csr_read_data;
+wire [ (32-1):0] jrx_csr_read_data;
+
-
-
+wire jtag_csr_write_enable;
+wire [ (32-1):0] jtag_csr_write_data;
+wire [ (5-1):0] jtag_csr;
+wire jtag_read_enable;
+wire [ 7:0] jtag_read_data;
+wire jtag_write_enable;
+wire [ 7:0] jtag_write_data;
+wire [ (32-1):0] jtag_address;
+wire jtag_access_complete;
-
+
+
+wire jtag_break;
+
+
@@ -28140,10 +28184,11 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (32-2)+2-1:8] eba;
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
-
+reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
+
reg [ (3-1):0] eid_x;
@@ -28153,34 +28198,39 @@ reg [ (3-1):0] eid_x;
-
-
-
-
-
-
-
+
+
+wire dc_ss;
+
+wire dc_re;
+wire exception_x;
+reg exception_m;
+wire debug_exception_x;
+reg debug_exception_m;
+reg debug_exception_w;
+wire debug_exception_q_w;
+wire non_debug_exception_x;
+reg non_debug_exception_m;
+reg non_debug_exception_w;
+wire non_debug_exception_q_w;
-
+
-wire exception_x;
-reg exception_m;
-reg exception_w;
-wire exception_q_w;
-
+
-
-
+wire reset_exception;
+
+
@@ -28188,9 +28238,10 @@ wire interrupt_exception;
-
-
+wire breakpoint_exception;
+wire watchpoint_exception;
+
@@ -28271,7 +28322,7 @@ endfunction
-lm32_instruction_unit_medium #(
+lm32_instruction_unit_medium_debug #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -28302,8 +28353,9 @@ lm32_instruction_unit_medium #(
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
-
+ .iflush (iflush),
+
@@ -28327,11 +28379,12 @@ lm32_instruction_unit_medium #(
-
-
-
-
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
+
@@ -28341,11 +28394,12 @@ lm32_instruction_unit_medium #(
.pc_m (pc_m),
.pc_w (pc_w),
-
-
-
-
+ .icache_stall_request (icache_stall_request),
+ .icache_restart_request (icache_restart_request),
+ .icache_refill_request (icache_refill_request),
+ .icache_refilling (icache_refilling),
+
@@ -28366,9 +28420,10 @@ lm32_instruction_unit_medium #(
-
-
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
+
@@ -28383,7 +28438,7 @@ lm32_instruction_unit_medium #(
);
-lm32_decoder_medium decoder (
+lm32_decoder_medium_debug decoder (
.instruction (instruction_d),
@@ -28462,14 +28517,16 @@ lm32_decoder_medium decoder (
.branch_reg (branch_reg_d),
.condition (condition_d),
-
+ .break_opcode (break_d),
+
.scall (scall_d),
.eret (eret_d),
-
+ .bret (bret_d),
+
@@ -28479,7 +28536,7 @@ lm32_decoder_medium decoder (
);
-lm32_load_store_unit_medium #(
+lm32_load_store_unit_medium_debug #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -28645,7 +28702,7 @@ lm32_multiplier multiplier (
-lm32_interrupt_medium interrupt_unit (
+lm32_interrupt_medium_debug interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -28654,17 +28711,18 @@ lm32_interrupt_medium interrupt_unit (
.stall_x (stall_x),
-
-
-
- .exception (exception_q_w),
+ .non_debug_exception (non_debug_exception_q_w),
+ .debug_exception (debug_exception_q_w),
+
+
.eret_q_x (eret_q_x),
-
+ .bret_q_x (bret_q_x),
+
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -28679,95 +28737,116 @@ lm32_interrupt_medium interrupt_unit (
-
+
+lm32_jtag_medium_debug jtag (
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
-
-
-
-
+ .jtag_clk (jtag_clk),
+ .jtag_update (jtag_update),
+ .jtag_reg_q (jtag_reg_q),
+ .jtag_reg_addr_q (jtag_reg_addr_q),
+
+
+ .csr (csr_x),
+ .csr_write_data (operand_1_x),
+ .csr_write_enable (csr_write_enable_q_x),
+ .stall_x (stall_x),
-
-
-
-
+
+
+ .jtag_read_data (jtag_read_data),
+ .jtag_access_complete (jtag_access_complete),
-
-
+
+
+ .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
-
+
+
+ .jtx_csr_read_data (jtx_csr_read_data),
+ .jrx_csr_read_data (jrx_csr_read_data),
-
-
+
+
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
+ .jtag_read_enable (jtag_read_enable),
+ .jtag_write_enable (jtag_write_enable),
+ .jtag_write_data (jtag_write_data),
+ .jtag_address (jtag_address),
-
-
-
-
-
-
-
+
+
+ .jtag_break (jtag_break),
+ .jtag_reset (reset_exception),
-
-
-
-
-
-
+ .jtag_reg_d (jtag_reg_d),
+ .jtag_reg_addr_d (jtag_reg_addr_d)
+ );
+
-
-
-
-
+
+lm32_debug_medium_debug #(
+ .breakpoints (breakpoints),
+ .watchpoints (watchpoints)
+ ) hw_debug (
-
-
-
-
-
-
-
-
-
-
-
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .pc_x (pc_x),
+ .load_x (load_x),
+ .store_x (store_x),
+ .load_store_address_x (adder_result_x),
+ .csr_write_enable_x (csr_write_enable_q_x),
+ .csr_write_data (operand_1_x),
+ .csr_x (csr_x),
+
+ .jtag_csr_write_enable (jtag_csr_write_enable),
+ .jtag_csr_write_data (jtag_csr_write_data),
+ .jtag_csr (jtag_csr),
-
-
-
-
-
-
+
+
+
+ .eret_q_x (eret_q_x),
+ .bret_q_x (bret_q_x),
+ .stall_x (stall_x),
+ .exception_x (exception_x),
+ .q_x (q_x),
+
-
-
-
-
-
+
+ .dc_ss (dc_ss),
+
+
+ .dc_re (dc_re),
+ .bp_match (bp_match),
+ .wp_match (wp_match)
+ );
+
@@ -29212,8 +29291,9 @@ assign kill_f = ( (valid_d == 1'b1)
-
+ || (icache_refill_request == 1'b1)
+
@@ -29226,8 +29306,9 @@ assign kill_d = (branch_taken_m == 1'b1)
-
+ || (icache_refill_request == 1'b1)
+
@@ -29256,21 +29337,25 @@ assign kill_w = 1'b0
-
-
-
-
-
-
-
-
+assign breakpoint_exception = ( ( (break_x == 1'b1)
+ || (bp_match == 1'b1)
+ )
+ && (valid_x == 1'b1)
+ )
+
+ || (jtag_break == 1'b1)
+
+
+ ;
+
-
+assign watchpoint_exception = wp_match == 1'b1;
+
@@ -29294,38 +29379,17 @@ assign system_call_exception = ( (scall_x == 1'b1)
);
-
-
-
-
-
-
-
-
-
-
+assign debug_exception_x = (breakpoint_exception == 1'b1)
+ || (watchpoint_exception == 1'b1)
+ ;
-
-
+assign non_debug_exception_x = (system_call_exception == 1'b1)
+
+ || (reset_exception == 1'b1)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-assign exception_x = (system_call_exception == 1'b1)
@@ -29339,8 +29403,9 @@ assign exception_x = (system_call_exception == 1'b1)
|| ( (interrupt_exception == 1'b1)
-
+ && (dc_ss == 1'b0)
+
@@ -29351,27 +29416,54 @@ assign exception_x = (system_call_exception == 1'b1)
;
+
+assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
always @(*)
begin
+
+
+
+ if (reset_exception == 1'b1)
+ eid_x = 3'h0;
+ else
-
-
-
-
+
-
-
-
+ if (breakpoint_exception == 1'b1)
+ eid_x = 3'd1;
+ else
+
@@ -29383,10 +29475,11 @@ begin
-
-
-
+ if (watchpoint_exception == 1'b1)
+ eid_x = 3'd3;
+ else
+
@@ -29398,8 +29491,9 @@ begin
if ( (interrupt_exception == 1'b1)
-
+ && (dc_ss == 1'b0)
+
)
eid_x = 3'h6;
@@ -29435,18 +29529,19 @@ assign stall_d = (stall_x == 1'b1)
&& (kill_d == 1'b0)
)
-
-
-
-
-
-
-
-
-
-
-
+ || ( ( (break_d == 1'b1)
+ || (bret_d == 1'b1)
+ )
+ && ( (load_q_x == 1'b1)
+ || (store_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
+ )
+ && (kill_d == 1'b0)
+ )
+
|| ( (csr_write_enable_d == 1'b1)
&& (load_q_x == 1'b1)
@@ -29508,16 +29603,14 @@ assign stall_m = (stall_wb_load == 1'b1)
-
-
-
-
-
- || (I_CYC_O == 1'b1)
+ || (icache_stall_request == 1'b1)
+ || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
-
+
+
+
@@ -29550,21 +29643,24 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
+assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
+
assign load_q_x = (load_x == 1'b1)
&& (q_x == 1'b1)
-
+ && (bp_match == 1'b0)
+
;
assign store_q_x = (store_x == 1'b1)
&& (q_x == 1'b1)
-
+ && (bp_match == 1'b0)
+
;
@@ -29575,12 +29671,12 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-
-
-assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
+assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+
+
assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
@@ -29596,19 +29692,12 @@ assign cfg = {
breakpoints[3:0],
interrupts[5:0],
-
-
- 1'b0,
+ 1'b1,
-
-
- 1'b0,
-
-
@@ -29617,18 +29706,25 @@ assign cfg = {
-
-
- 1'b0,
+ 1'b1,
+
+
+
+ 1'b1,
+
- 1'b0,
+
+
+ 1'b1,
+
+
@@ -29701,19 +29797,22 @@ assign cfg2 = {
-
-
-
-
-
-
-
-
-
+assign iflush = ( (csr_write_enable_d == 1'b1)
+ && (csr_d == 5'h3)
+ && (stall_d == 1'b0)
+ && (kill_d == 1'b0)
+ && (valid_d == 1'b1))
-
+
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h3))
+
+
+ ;
+
@@ -29729,7 +29828,7 @@ assign cfg2 = {
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[ (5-1):0];
always @(*)
@@ -29737,27 +29836,29 @@ begin
case (csr_x)
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 5'h0,
+ 5'h1,
+ 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
+ 5'h6: csr_read_data_x = cfg;
+ 5'h7: csr_read_data_x = {eba, 8'h00};
-
+ 5'h9: csr_read_data_x = {deba, 8'h00};
+
-
-
+ 5'he: csr_read_data_x = jtx_csr_read_data;
+ 5'hf: csr_read_data_x = jrx_csr_read_data;
+
- 3'ha: csr_read_data_x = cfg2;
+ 5'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -29771,36 +29872,40 @@ end
always @(posedge clk_i )
begin
if (rst_i == 1'b1)
- eba <= eba_reset[ (32-2)+2-1:8];
+ eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (32-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
+ eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
end
end
-
-
-
-
-
-
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ else
+ begin
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
+ deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
+ deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+ end
+end
+
@@ -29837,7 +29942,8 @@ end
-
+
+
@@ -29852,19 +29958,20 @@ end
-
-
-
-
-
-
-
+always @(*)
+begin
+ if (icache_refill_request == 1'b1)
+ valid_a = 1'b0;
+ else if (icache_restart_request == 1'b1)
+ valid_a = 1'b1;
+ else
+ valid_a = !icache_refilling;
+end
-
-
-
+
+
@@ -29876,7 +29983,6 @@ end
-
always @(posedge clk_i )
@@ -29893,11 +29999,11 @@ begin
begin
if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
-
- valid_f <= 1'b1;
+ valid_f <= valid_a;
+
+
else if (stall_f == 1'b0)
valid_f <= 1'b0;
@@ -29942,7 +30048,7 @@ begin
operand_0_x <= { 32{1'b0}};
operand_1_x <= { 32{1'b0}};
store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (32-2){1'b0}};
+ branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
x_result_sel_csr_x <= 1'b0;
@@ -29979,7 +30085,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
+ csr_x <= { 5{1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -30002,14 +30108,16 @@ begin
branch_predict_taken_x <= 1'b0;
condition_x <= 3'b000;
-
+ break_x <= 1'b0;
+
scall_x <= 1'b0;
eret_x <= 1'b0;
-
+ bret_x <= 1'b0;
+
@@ -30018,7 +30126,7 @@ begin
csr_write_enable_x <= 1'b0;
operand_m <= { 32{1'b0}};
- branch_target_m <= { (32-2){1'b0}};
+ branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
m_result_sel_compare_m <= 1'b0;
@@ -30051,9 +30159,10 @@ begin
-
-
+ debug_exception_m <= 1'b0;
+ non_debug_exception_m <= 1'b0;
+
operand_w <= { 32{1'b0}};
w_result_sel_load_w <= 1'b0;
@@ -30065,12 +30174,12 @@ begin
write_idx_w <= { 5{1'b0}};
write_enable_w <= 1'b0;
-
-
-
- exception_w <= 1'b0;
+ debug_exception_w <= 1'b0;
+ non_debug_exception_w <= 1'b0;
+
+
@@ -30090,7 +30199,7 @@ begin
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
@@ -30149,8 +30258,9 @@ begin
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
+ break_x <= break_d;
+
scall_x <= scall_d;
@@ -30159,8 +30269,9 @@ begin
eret_x <= eret_d;
-
+ bret_x <= bret_d;
+
write_enable_x <= write_enable_d;
end
@@ -30212,40 +30323,40 @@ begin
+
-
-
-
-
-
-
-
-
- if (exception_x == 1'b1)
+ if (non_debug_exception_x == 1'b1)
write_idx_m <= 5'd30;
+ else if (debug_exception_x == 1'b1)
+ write_idx_m <= 5'd31;
else
write_idx_m <= write_idx_x;
+
+
+
+
+
condition_met_m <= condition_met_x;
-
-
-
-
-
-
-
-
-
-
- branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+ if (exception_x == 1'b1)
+ if ((dc_re == 1'b1)
+ || ((debug_exception_x == 1'b1)
+ && (non_debug_exception_x == 1'b0)))
+ branch_target_m <= {deba, eid_x, {3{1'b0}}};
+ else
+ branch_target_m <= {eba, eid_x, {3{1'b0}}};
+ else
+ branch_target_m <= branch_target_x;
+
+
@@ -30257,14 +30368,16 @@ begin
eret_m <= eret_q_x;
-
+ bret_m <= bret_q_x;
+
write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
-
+ debug_exception_m <= debug_exception_x;
+ non_debug_exception_m <= non_debug_exception_x;
+
end
@@ -30310,12 +30423,12 @@ begin
write_enable_w <= write_enable_m;
-
-
-
- exception_w <= exception_m;
+ debug_exception_w <= debug_exception_m;
+ non_debug_exception_w <= non_debug_exception_m;
+
+
@@ -30860,7 +30973,7 @@ endmodule
-module lm32_load_store_unit_medium (
+module lm32_load_store_unit_medium_debug (
clk_i,
rst_i,
@@ -32172,7 +32285,7 @@ endmodule
-module lm32_decoder_medium (
+module lm32_decoder_medium_debug (
instruction,
@@ -32251,14 +32364,16 @@ module lm32_decoder_medium (
bi_conditional,
bi_unconditional,
-
+ break_opcode,
+
scall,
eret,
-
+ bret,
+
@@ -32342,8 +32457,8 @@ output [ (5-1):0] write_idx;
wire [ (5-1):0] write_idx;
output [ (32-1):0] immediate;
wire [ (32-1):0] immediate;
-output [ ((32-2)+2-1):2] branch_offset;
-wire [ ((32-2)+2-1):2] branch_offset;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
@@ -32392,18 +32507,20 @@ wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-
+output break_opcode;
+wire break_opcode;
+
output scall;
wire scall;
output eret;
wire eret;
-
-
+output bret;
+wire bret;
+
@@ -32757,14 +32874,16 @@ assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
+assign break_opcode = op_raise & ~instruction[2];
+
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
+assign bret = op_b & (instruction[25:21] == 5'd31);
+
@@ -33153,426 +33272,499 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
+
+
+
+
-
-
+
-
-
+
-
-
-
-
-
-
+
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
+module lm32_icache_medium_debug (
-
+ clk_i,
+ rst_i,
+ stall_a,
+ stall_f,
+ address_a,
+ address_f,
+ read_enable_f,
+ refill_ready,
+ refill_data,
+ iflush,
+
+ valid_d,
+ branch_predict_taken_d,
+
+ stall_request,
+ restart_request,
+ refill_request,
+ refill_address,
+ refilling,
+ inst
+ );
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+parameter associativity = 1;
+parameter sets = 512;
+parameter bytes_per_line = 16;
+parameter base_address = 0;
+parameter limit = 0;
-
-
-
-
+localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
+localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_lsb = 2;
+localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
+localparam addr_set_lsb = (addr_offset_msb+1);
+localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
+localparam addr_tag_lsb = (addr_set_msb+1);
+localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
-
+input clk_i;
+input rst_i;
-
+input stall_a;
+input stall_f;
+input valid_d;
+input branch_predict_taken_d;
+
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
+input read_enable_f;
+input refill_ready;
+input [ (32-1):0] refill_data;
+input iflush;
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+output stall_request;
+wire stall_request;
+output restart_request;
+reg restart_request;
+output refill_request;
+wire refill_request;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+output refilling;
+reg refilling;
+output [ (32-1):0] inst;
+wire [ (32-1):0] inst;
+wire enable;
+wire [0:associativity-1] way_mem_we;
+wire [ (32-1):0] way_data[0:associativity-1];
+wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [0:associativity-1] way_valid;
+wire [0:associativity-1] way_match;
+wire miss;
-
-
-
-
+wire [ (addr_set_width-1):0] tmem_read_address;
+wire [ (addr_set_width-1):0] tmem_write_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+reg [ 3:0] state;
+wire flushing;
+wire check;
+wire refill;
+reg [associativity-1:0] refill_way_select;
+reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+wire last_refill;
+reg [ (addr_set_width-1):0] flush_set;
+genvar i;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+function integer clogb2;
+input [31:0] value;
+begin
+ for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+ value = value >> 1;
+end
+endfunction
+function integer clogb2_v1;
+input [31:0] value;
+reg [31:0] i;
+reg [31:0] temp;
+begin
+ temp = 0;
+ i = 0;
+ for (i = 0; temp < value; i = i + 1)
+ temp = 1<<i;
+ clogb2_v1 = i-1;
+end
+endfunction
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+ generate
+ for (i = 0; i < associativity; i = i + 1)
+ begin : memories
+
+ lm32_ram
+ #(
-
+ .data_width (32),
+ .address_width ( (addr_offset_width+addr_set_width))
+
+)
+ way_0_data_ram
+ (
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (dmem_read_address),
+ .enable_read (enable),
+ .write_address (dmem_write_address),
+ .enable_write ( 1'b1),
+ .write_enable (way_mem_we[i]),
+ .write_data (refill_data),
+
+ .read_data (way_data[i])
+ );
+
+ lm32_ram
+ #(
+
+ .data_width ( (addr_tag_width+1)),
+ .address_width ( addr_set_width)
-
+ )
+ way_0_tag_ram
+ (
+
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (tmem_read_address),
+ .enable_read (enable),
+ .write_address (tmem_write_address),
+ .enable_write ( 1'b1),
+ .write_enable (way_mem_we[i] | flushing),
+ .write_data (tmem_write_data),
+
+ .read_data ({way_tag[i], way_valid[i]})
+ );
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ end
+endgenerate
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+generate
+ for (i = 0; i < associativity; i = i + 1)
+ begin : match
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb], 1'b1});
+ end
+endgenerate
+
+
+generate
+ if (associativity == 1)
+ begin : inst_1
+assign inst = way_match[0] ? way_data[0] : 32'b0;
+ end
+ else if (associativity == 2)
+ begin : inst_2
+assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
+ end
+endgenerate
+
+
+generate
+ if (bytes_per_line > 4)
+assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+ else
+assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+endgenerate
-
-
+assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_write_address = flushing
+ ? flush_set
+ : refill_address[ addr_set_msb:addr_set_lsb];
+
+
+generate
+ if (bytes_per_line > 4)
+assign last_refill = refill_offset == {addr_offset_width{1'b1}};
+ else
+assign last_refill = 1'b1;
+endgenerate
+
+
+assign enable = (stall_a == 1'b0);
+
+
+generate
+ if (associativity == 1)
+ begin : we_1
+assign way_mem_we[0] = (refill_ready == 1'b1);
+ end
+ else
+ begin : we_2
+assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
+assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
+ end
+endgenerate
+
+
+assign tmem_write_data[ 0] = last_refill & !flushing;
+assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+
+
+assign flushing = |state[1:0];
+assign check = state[2];
+assign refill = state[3];
+
+assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check == 1'b0);
+assign refill_request = (refill == 1'b1);
+
+
+
+
+
+
+generate
+ if (associativity >= 2)
+ begin : way_select
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
+ else
+ begin
+ if (miss == 1'b1)
+ refill_way_select <= {refill_way_select[0], refill_way_select[1]};
+ end
+end
+ end
+endgenerate
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ refilling <= 1'b0;
+ else
+ refilling <= refill;
+end
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 4'b0001;
+ flush_set <= { addr_set_width{1'b1}};
+ refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ restart_request <= 1'b0;
+ end
+ else
+ begin
+ case (state)
+
+ 4'b0001:
+ begin
+ if (flush_set == { addr_set_width{1'b0}})
+ state <= 4'b0100;
+ flush_set <= flush_set - 1'b1;
+ end
+
-
-
-
-
+ 4'b0010:
+ begin
+ if (flush_set == { addr_set_width{1'b0}})
+
+
-
+
+
+ state <= 4'b0100;
+
+ flush_set <= flush_set - 1'b1;
+ end
-
-
-
+ 4'b0100:
+ begin
+ if (stall_a == 1'b0)
+ restart_request <= 1'b0;
+ if (iflush == 1'b1)
+ begin
+ refill_address <= address_f;
+ state <= 4'b0010;
+ end
+ else if (miss == 1'b1)
+ begin
+ refill_address <= address_f;
+ state <= 4'b1000;
+ end
+ end
+
+ 4'b1000:
+ begin
+ if (refill_ready == 1'b1)
+ begin
+ if (last_refill == 1'b1)
+ begin
+ restart_request <= 1'b1;
+ state <= 4'b0100;
+ end
+ end
+ end
-
-
+ endcase
+ end
+end
-
+generate
+ if (bytes_per_line > 4)
+ begin
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else
+ begin
+ case (state)
+
+
+ 4'b0100:
+ begin
+ if (iflush == 1'b1)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else if (miss == 1'b1)
+ refill_offset <= {addr_offset_width{1'b0}};
+ end
+
+ 4'b1000:
+ begin
+ if (refill_ready == 1'b1)
+ refill_offset <= refill_offset + 1'b1;
+ end
+ endcase
+ end
+end
+ end
+endgenerate
+
+endmodule
+
@@ -34756,135 +34948,160 @@ endmodule
-
-
-
-
-
-
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+module lm32_debug_medium_debug (
+ clk_i,
+ rst_i,
+ pc_x,
+ load_x,
+ store_x,
+ load_store_address_x,
+ csr_write_enable_x,
+ csr_write_data,
+ csr_x,
+
+
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
-
+
+ eret_q_x,
+ bret_q_x,
+ stall_x,
+ exception_x,
+ q_x,
+
+
+
-
-
-
-
+
+
+ dc_ss,
+
+
+ dc_re,
+ bp_match,
+ wp_match
+ );
-
-
+parameter breakpoints = 0;
+parameter watchpoints = 0;
-
-
+input clk_i;
+input rst_i;
-
-
-
-
-
-
-
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+input load_x;
+input store_x;
+input [ (32-1):0] load_store_address_x;
+input csr_write_enable_x;
+input [ (32-1):0] csr_write_data;
+input [ (5-1):0] csr_x;
+
+
+input jtag_csr_write_enable;
+input [ (32-1):0] jtag_csr_write_data;
+input [ (5-1):0] jtag_csr;
+
+
+
+input eret_q_x;
+input bret_q_x;
+input stall_x;
+input exception_x;
+input q_x;
+
-
-
+
-
-
-
-
-
-
-
+
+output dc_ss;
+reg dc_ss;
-
-
-
-
-
-
-
-
+output dc_re;
+reg dc_re;
+output bp_match;
+wire bp_match;
+output wp_match;
+wire wp_match;
-
+genvar i;
-
-
-
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
+reg bp_e[0:breakpoints-1];
+wire [0:breakpoints-1]bp_match_n;
-
-
-
+reg [ 1:0] wpc_c[0:watchpoints-1];
+reg [ (32-1):0] wp[0:watchpoints-1];
+wire [0:watchpoints]wp_match_n;
+
+wire debug_csr_write_enable;
+wire [ (32-1):0] debug_csr_write_data;
+wire [ (5-1):0] debug_csr;
+
+
-
-
-
+
+reg [ 2:0] state;
-
+
-
@@ -34892,48 +35109,15 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
@@ -34942,132 +35126,223 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+function integer clogb2;
+input [31:0] value;
+begin
+ for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+ value = value >> 1;
+end
+endfunction
+function integer clogb2_v1;
+input [31:0] value;
+reg [31:0] i;
+reg [31:0] temp;
+begin
+ temp = 0;
+ i = 0;
+ for (i = 0; temp < value; i = i + 1)
+ temp = 1<<i;
+ clogb2_v1 = i-1;
+end
+endfunction
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_comb
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
+ end
+endgenerate
+generate
+
+ if (breakpoints > 0)
+assign bp_match = (|bp_match_n) || (state == 3'b011);
+ else
+assign bp_match = state == 3'b011;
+
+
-
-
-
-
-
-
-
+
+
+
+endgenerate
-
-
+
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_comb
+assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
+ end
+endgenerate
+generate
+ if (watchpoints > 0)
+assign wp_match = |wp_match_n;
+ else
+assign wp_match = 1'b0;
+endgenerate
-
-
-
-
-
-
-
+
+
+
+assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
+
+
+
+
+
+
+
+
+
+
+
+
+generate
+ for (i = 0; i < breakpoints; i = i + 1)
+ begin : bp_seq
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ bp_e[i] <= 1'b0;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
+ begin
+ bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+ bp_e[i] <= debug_csr_write_data[0];
+ end
+ end
+end
+ end
+endgenerate
+
+
+generate
+ for (i = 0; i < watchpoints; i = i + 1)
+ begin : wp_seq
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ wp[i] <= { 32{1'bx}};
+ wpc_c[i] <= 2'b00;
+ end
+ else
+ begin
+ if (debug_csr_write_enable == 1'b1)
+ begin
+ if (debug_csr == 5'h8)
+ wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
+ if (debug_csr == 5'h18 + i)
+ wp[i] <= debug_csr_write_data;
+ end
+ end
+end
+ end
+endgenerate
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ dc_re <= 1'b0;
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ dc_re <= debug_csr_write_data[1];
+ end
+end
+
+
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 3'b000;
+ dc_ss <= 1'b0;
+ end
+ else
+ begin
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ begin
+ dc_ss <= debug_csr_write_data[0];
+ if (debug_csr_write_data[0] == 1'b0)
+ state <= 3'b000;
+ else
+ state <= 3'b001;
+ end
+ case (state)
+ 3'b001:
+ begin
-
-
-
-
-
-
-
-
-
+ if ( ( (eret_q_x == 1'b1)
+ || (bret_q_x == 1'b1)
+ )
+ && (stall_x == 1'b0)
+ )
+ state <= 3'b010;
+ end
+ 3'b010:
+ begin
-
-
-
-
-
+ if ((q_x == 1'b1) && (stall_x == 1'b0))
+ state <= 3'b011;
+ end
+ 3'b011:
+ begin
-
+
-
-
-
-
-
-
-
-
+
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ begin
+ dc_ss <= 1'b0;
+ state <= 3'b100;
+ end
+ end
+ 3'b100:
+ begin
-
+
-
-
-
-
-
-
+ state <= 3'b000;
+ end
+ endcase
+ end
+end
+
+endmodule
+
@@ -35440,7 +35715,7 @@ endmodule
-module lm32_instruction_unit_medium (
+module lm32_instruction_unit_medium_debug (
clk_i,
rst_i,
@@ -35465,8 +35740,9 @@ module lm32_instruction_unit_medium (
branch_mispredict_taken_m,
branch_target_m,
-
+ iflush,
+
@@ -35490,11 +35766,12 @@ module lm32_instruction_unit_medium (
-
-
-
-
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
+
@@ -35504,11 +35781,12 @@ module lm32_instruction_unit_medium (
pc_m,
pc_w,
-
-
-
-
+ icache_stall_request,
+ icache_restart_request,
+ icache_refill_request,
+ icache_refilling,
+
@@ -35529,9 +35807,10 @@ module lm32_instruction_unit_medium (
-
-
+ jtag_read_data,
+ jtag_access_complete,
+
@@ -35577,7 +35856,7 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((32-2)+2-1):2] branch_predict_address_d;
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
@@ -35587,11 +35866,12 @@ input [ ((32-2)+2-1):2] branch_predict_address_d;
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((32-2)+2-1):2] branch_target_m;
+input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-
+input iflush;
+
@@ -35617,38 +35897,40 @@ input i_rty_i;
-
-
-
-
+input jtag_read_enable;
+input jtag_write_enable;
+input [ 7:0] jtag_write_data;
+input [ (32-1):0] jtag_address;
+
-output [ ((32-2)+2-1):2] pc_f;
-reg [ ((32-2)+2-1):2] pc_f;
-output [ ((32-2)+2-1):2] pc_d;
-reg [ ((32-2)+2-1):2] pc_d;
-output [ ((32-2)+2-1):2] pc_x;
-reg [ ((32-2)+2-1):2] pc_x;
-output [ ((32-2)+2-1):2] pc_m;
-reg [ ((32-2)+2-1):2] pc_m;
-output [ ((32-2)+2-1):2] pc_w;
-reg [ ((32-2)+2-1):2] pc_w;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
-
-
-
-
-
-
-
+output icache_stall_request;
+wire icache_stall_request;
+output icache_restart_request;
+wire icache_restart_request;
+output icache_refill_request;
+wire icache_refill_request;
+output icache_refilling;
+wire icache_refilling;
+
@@ -35661,11 +35943,11 @@ reg [ ((32-2)+2-1):2] pc_w;
output [ (32-1):0] i_dat_o;
-
-
-wire [ (32-1):0] i_dat_o;
+reg [ (32-1):0] i_dat_o;
+
+
output [ (32-1):0] i_adr_o;
reg [ (32-1):0] i_adr_o;
@@ -35673,21 +35955,21 @@ output i_cyc_o;
reg i_cyc_o;
output [ (4-1):0] i_sel_o;
-
-
-wire [ (4-1):0] i_sel_o;
+reg [ (4-1):0] i_sel_o;
+
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
-
-wire i_we_o;
+reg i_we_o;
+
+
output [ (3-1):0] i_cti_o;
reg [ (3-1):0] i_cti_o;
@@ -35699,11 +35981,12 @@ wire [ (2-1):0] i_bte_o;
-
-
-
-
+output [ 7:0] jtag_read_data;
+reg [ 7:0] jtag_read_data;
+output jtag_access_complete;
+wire jtag_access_complete;
+
@@ -35724,31 +36007,30 @@ reg [ (32-1):0] instruction_d;
-reg [ ((32-2)+2-1):2] pc_a;
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
-
-
-
-
-
-
-
-
-
-
-
-
-
+reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
+
-reg [ (32-1):0] wb_data_f;
+wire icache_read_enable_f;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
+reg icache_refill_ready;
+reg [ (32-1):0] icache_refill_data;
+wire [ (32-1):0] icache_data_f;
+wire [ (3-1):0] first_cycle_type;
+wire [ (3-1):0] next_cycle_type;
+wire last_word;
+wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
-
+
+
+
@@ -35768,8 +36050,9 @@ reg [ (32-1):0] wb_data_f;
-
+reg jtag_access;
+
@@ -35886,35 +36169,36 @@ endfunction
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+lm32_icache_medium_debug #(
+ .associativity (associativity),
+ .sets (sets),
+ .bytes_per_line (bytes_per_line),
+ .base_address (base_address),
+ .limit (limit)
+ ) icache (
-
-
-
-
-
-
+ .clk_i (clk_i),
+ .rst_i (rst_i),
+ .stall_a (stall_a),
+ .stall_f (stall_f),
+ .branch_predict_taken_d (branch_predict_taken_d),
+ .valid_d (valid_d),
+ .address_a (pc_a),
+ .address_f (pc_f),
+ .read_enable_f (icache_read_enable_f),
+ .refill_ready (icache_refill_ready),
+ .refill_data (icache_refill_data),
+ .iflush (iflush),
-
+ .stall_request (icache_stall_request),
+ .restart_request (icache_restart_request),
+ .refill_request (icache_refill_request),
+ .refill_address (icache_refill_address),
+ .refilling (icache_refilling),
+ .inst (icache_data_f)
+ );
+
@@ -35923,16 +36207,19 @@ endfunction
-
-
-
+
+assign icache_read_enable_f = (valid_f == 1'b1)
+ && (kill_f == 1'b0)
+
+
-
+
-
-
+
+ ;
+
@@ -35960,10 +36247,11 @@ begin
pc_a = branch_predict_address_d;
else
-
-
-
+ if (icache_restart_request == 1'b1)
+ pc_a = restart_address;
+ else
+
pc_a = pc_f + 1'b1;
end
@@ -35976,25 +36264,25 @@ end
-
-
-
+
+
+assign instruction_f = icache_data_f;
+
-
+
+
+
-assign instruction_f = wb_data_f;
-
-
@@ -36002,11 +36290,11 @@ assign instruction_f = wb_data_f;
-
-assign i_dat_o = 32'd0;
-assign i_we_o = 1'b0;
-assign i_sel_o = 4'b1111;
+
+
+
+
assign i_bte_o = 2'b00;
@@ -36015,31 +36303,32 @@ assign i_bte_o = 2'b00;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+generate
+ case (bytes_per_line)
+ 4:
+ begin
+assign first_cycle_type = 3'b111;
+assign next_cycle_type = 3'b111;
+assign last_word = 1'b1;
+assign first_address = icache_refill_address;
+ end
+ 8:
+ begin
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = 3'b111;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+ end
+ 16:
+ begin
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
+assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+ end
+ endcase
+endgenerate
+
@@ -36052,10 +36341,10 @@ begin
if (rst_i == 1'b1)
begin
pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (32-2){1'b0}};
- pc_x <= { (32-2){1'b0}};
- pc_m <= { (32-2){1'b0}};
- pc_w <= { (32-2){1'b0}};
+ pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
end
else
begin
@@ -36073,13 +36362,14 @@ end
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ else
+ begin
+
@@ -36091,14 +36381,18 @@ end
-
-
-
-
-
+
+
+ if (icache_refill_request == 1'b1)
+ restart_address <= icache_refill_address;
+
+
+ end
+end
+
@@ -36117,23 +36411,152 @@ end
-
+
+assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
+always @(*)
+begin
+ case (jtag_address[1:0])
+ 2'b00: jtag_read_data = i_dat_i[ 31:24];
+ 2'b01: jtag_read_data = i_dat_i[ 23:16];
+ 2'b10: jtag_read_data = i_dat_i[ 15:8];
+ 2'b11: jtag_read_data = i_dat_i[ 7:0];
+ endcase
+end
-
-
-
-
-
-
+
+
+
+
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= { 32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ icache_refill_data <= { 32{1'b0}};
+ icache_refill_ready <= 1'b0;
+
+
+
+
+
+
+ i_we_o <= 1'b0;
+ i_sel_o <= 4'b1111;
+ jtag_access <= 1'b0;
+
+
+ end
+ else
+ begin
+ icache_refill_ready <= 1'b0;
+
+ if (i_cyc_o == 1'b1)
+ begin
+
+ if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ begin
+
+
+ if (jtag_access == 1'b1)
+ begin
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_we_o <= 1'b0;
+ jtag_access <= 1'b0;
+ end
+ else
+
+
+ begin
+ if (last_word == 1'b1)
+ begin
+
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_lock_o <= 1'b0;
+ end
+
+ i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
+ i_cti_o <= next_cycle_type;
+
+ icache_refill_ready <= 1'b1;
+ icache_refill_data <= i_dat_i;
+ end
+ end
+
+
+
+
+
+
+
+
+ end
+ else
+ begin
+ if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
+ begin
+
+
+
+ i_sel_o <= 4'b1111;
+
+ i_adr_o <= {first_address, 2'b00};
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+ i_cti_o <= first_cycle_type;
+
+
+
+ end
+ else
+ begin
+ if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
+ begin
+ case (jtag_address[1:0])
+ 2'b00: i_sel_o <= 4'b1000;
+ 2'b01: i_sel_o <= 4'b0100;
+ 2'b10: i_sel_o <= 4'b0010;
+ 2'b11: i_sel_o <= 4'b0001;
+ endcase
+ i_adr_o <= jtag_address;
+ i_dat_o <= {4{jtag_write_data}};
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+ i_we_o <= jtag_write_enable;
+ i_cti_o <= 3'b111;
+ jtag_access <= 1'b1;
+ end
+ end
+
+
+
+
+
+
+
+
+
+
+
+ end
+ end
+end
+
@@ -36144,50 +36567,23 @@ end
-
-
-
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
@@ -36199,7 +36595,12 @@ end
+
+
+
+
+
@@ -36207,129 +36608,28 @@ end
-
-
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- wb_data_f <= { 32{1'b0}};
-
-
-
-
- end
- else
- begin
-
- if (i_cyc_o == 1'b1)
- begin
-
- if((i_ack_i == 1'b1) || (i_err_i == 1'b1))
- begin
-
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
-
- wb_data_f <= i_dat_i;
- end
-
-
-
-
-
-
-
-
- end
- else
- begin
-
- if ( (stall_a == 1'b0)
-
-
-
-
- )
- begin
-
-
-
-
-
- i_adr_o <= {pc_a, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
-
-
-
-
- end
- else
- begin
- if ( (stall_a == 1'b0)
-
-
-
-
- )
- begin
-
-
-
-
- end
- end
- end
- end
-end
-
@@ -36710,443 +37010,523 @@ endmodule
-
-
-
+
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+module lm32_jtag_medium_debug (
-
-
-
-
-
-
+ clk_i,
+ rst_i,
+ jtag_clk,
+ jtag_update,
+ jtag_reg_q,
+ jtag_reg_addr_q,
+
+
+ csr,
+ csr_write_enable,
+ csr_write_data,
+ stall_x,
-
-
-
-
+
+
+ jtag_read_data,
+ jtag_access_complete,
-
-
+
+
+ exception_q_w,
-
+
+
+ jtx_csr_read_data,
+ jrx_csr_read_data,
-
-
+
+
+ jtag_csr_write_enable,
+ jtag_csr_write_data,
+ jtag_csr,
+ jtag_read_enable,
+ jtag_write_enable,
+ jtag_write_data,
+ jtag_address,
-
-
-
-
-
-
-
+
+
+ jtag_break,
+ jtag_reset,
-
-
-
-
-
+ jtag_reg_d,
+ jtag_reg_addr_d
+ );
-
-
+input clk_i;
+input rst_i;
-
-
-
-
+input jtag_clk;
+input jtag_update;
+input [ 7:0] jtag_reg_q;
+input [2:0] jtag_reg_addr_q;
+
+
+input [ (5-1):0] csr;
+input csr_write_enable;
+input [ (32-1):0] csr_write_data;
+input stall_x;
-
-
-
-
+
+
+input [ 7:0] jtag_read_data;
+input jtag_access_complete;
-
-
+
+
+input exception_q_w;
-
-
-
-
-
-
+
+output [ (32-1):0] jtx_csr_read_data;
+wire [ (32-1):0] jtx_csr_read_data;
+output [ (32-1):0] jrx_csr_read_data;
+wire [ (32-1):0] jrx_csr_read_data;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+output jtag_csr_write_enable;
+reg jtag_csr_write_enable;
+output [ (32-1):0] jtag_csr_write_data;
+wire [ (32-1):0] jtag_csr_write_data;
+output [ (5-1):0] jtag_csr;
+wire [ (5-1):0] jtag_csr;
+output jtag_read_enable;
+reg jtag_read_enable;
+output jtag_write_enable;
+reg jtag_write_enable;
+output [ 7:0] jtag_write_data;
+wire [ 7:0] jtag_write_data;
+output [ (32-1):0] jtag_address;
+wire [ (32-1):0] jtag_address;
-
-
-
-
-
-
-
+
+output jtag_break;
+reg jtag_break;
+output jtag_reset;
+reg jtag_reset;
+
+
+output [ 7:0] jtag_reg_d;
+reg [ 7:0] jtag_reg_d;
+output [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_d;
-
-
-
-
+reg rx_update;
+reg rx_update_r;
+reg rx_update_r_r;
+reg rx_update_r_r_r;
-
+wire [ 7:0] rx_byte;
+wire [2:0] rx_addr;
+
+
+reg [ 7:0] uart_tx_byte;
+reg uart_tx_valid;
+reg [ 7:0] uart_rx_byte;
+reg uart_rx_valid;
+
-
-
-
-
-
+reg [ 3:0] command;
+
-
+reg [ 7:0] jtag_byte_0;
+reg [ 7:0] jtag_byte_1;
+reg [ 7:0] jtag_byte_2;
+reg [ 7:0] jtag_byte_3;
+reg [ 7:0] jtag_byte_4;
+reg processing;
-
-
-
-
-
-
-
+reg [ 3:0] state;
+
+
+assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
+assign jtag_write_data = jtag_byte_4;
-
-
-
-
-
-
-
+
+
+assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
+
+
+
+
+assign jtag_reg_addr_d[2] = processing;
-
-
-
-
+
+
+assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
+
-
-
+assign rx_byte = jtag_reg_q;
+assign rx_addr = jtag_reg_addr_q;
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ rx_update <= 1'b0;
+ rx_update_r <= 1'b0;
+ rx_update_r_r <= 1'b0;
+ rx_update_r_r_r <= 1'b0;
+ end
+ else
+ begin
+ rx_update <= jtag_update;
+ rx_update_r <= rx_update;
+ rx_update_r_r <= rx_update_r;
+ rx_update_r_r_r <= rx_update_r_r;
+ end
+end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ state <= 4'h0;
+ command <= 4'b0000;
+ jtag_reg_d <= 8'h00;
+
+ processing <= 1'b0;
+ jtag_csr_write_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
+ jtag_write_enable <= 1'b0;
+
-
+
-
-
-
-
-
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
-
-
-
-
+
+
+ uart_tx_byte <= 8'h00;
+ uart_tx_valid <= 1'b0;
+ uart_rx_byte <= 8'h00;
+ uart_rx_valid <= 1'b0;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ end
+ else
+ begin
+
+
+ if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
+ begin
+ case (csr)
+ 5'he:
+ begin
-
-
-
-
-
+ uart_tx_byte <= csr_write_data[ 7:0];
+ uart_tx_valid <= 1'b1;
+ end
+ 5'hf:
+ begin
-
-
-
-
-
+ uart_rx_valid <= 1'b0;
+ end
+ endcase
+ end
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
-
-
-
+ if (exception_q_w == 1'b1)
+ begin
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
+ end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+ case (state)
+ 4'h0:
+ begin
+
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ command <= rx_byte[7:4];
+ case (rx_addr)
+
-
+ 3'b000:
+ begin
+ case (rx_byte[7:4])
+
+
+ 4'b0001:
+ state <= 4'h1;
+ 4'b0011:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= 4'h6;
+ end
+ 4'b0010:
+ state <= 4'h1;
+ 4'b0100:
+ begin
+ {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
+ state <= 5;
+ end
+ 4'b0101:
+ state <= 4'h1;
+
-
-
+ 4'b0110:
+ begin
+
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
+
-
-
-
-
-
-
-
-
-
-
-
+ jtag_break <= 1'b1;
+ end
+ 4'b0111:
+ begin
+
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
+
-
-
-
-
-
+ jtag_reset <= 1'b1;
+ end
+ endcase
+ end
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+ 3'b001:
+ begin
+ uart_rx_byte <= rx_byte;
+ uart_rx_valid <= 1'b1;
+ end
+ 3'b010:
+ begin
+ jtag_reg_d <= uart_tx_byte;
+ uart_tx_valid <= 1'b0;
+ end
+
+ default:
+ ;
+ endcase
+ end
+ end
+ 4'h1:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_0 <= rx_byte;
+ state <= 4'h2;
+ end
+ end
+ 4'h2:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_1 <= rx_byte;
+ state <= 4'h3;
+ end
+ end
+ 4'h3:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_2 <= rx_byte;
+ state <= 4'h4;
+ end
+ end
+ 4'h4:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_3 <= rx_byte;
+ if (command == 4'b0001)
+ state <= 4'h6;
+ else
+ state <= 4'h5;
+ end
+ end
+ 4'h5:
+ begin
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ begin
+ jtag_byte_4 <= rx_byte;
+ state <= 4'h6;
+ end
+ end
+ 4'h6:
+ begin
+ case (command)
+ 4'b0001,
+ 4'b0011:
+ begin
+ jtag_read_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
+ end
+ 4'b0010,
+ 4'b0100:
+ begin
+ jtag_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
+ end
+ 4'b0101:
+ begin
+ jtag_csr_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h8;
+ end
+ endcase
+ end
+ 4'h7:
+ begin
+ if (jtag_access_complete == 1'b1)
+ begin
+ jtag_read_enable <= 1'b0;
+ jtag_reg_d <= jtag_read_data;
+ jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
+ end
+ end
+ 4'h8:
+ begin
+ jtag_csr_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
+ end
+
+ endcase
+ end
+end
+
+endmodule
+
@@ -37501,7 +37881,7 @@ endmodule
-module lm32_interrupt_medium (
+module lm32_interrupt_medium_debug (
clk_i,
rst_i,
@@ -37510,17 +37890,18 @@ module lm32_interrupt_medium (
stall_x,
-
-
-
- exception,
+ non_debug_exception,
+ debug_exception,
+
+
eret_q_x,
-
+ bret_q_x,
+
csr,
csr_write_data,
@@ -37549,20 +37930,21 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
-
-
-input exception;
+input non_debug_exception;
+input debug_exception;
+
+
input eret_q_x;
-
+input bret_q_x;
+
-input [ (3-1):0] csr;
+input [ (5-1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -37589,8 +37971,9 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
-
+reg bie;
+
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -37610,11 +37993,11 @@ assign asserted = ip | interrupt;
assign ie_csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
@@ -37628,19 +38011,19 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
+ 5'h2: csr_read_data = ip;
+ 5'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -37651,18 +38034,18 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
+ 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- 1'b0,
+ bie,
+
+
eie,
ie
};
- 3'h2: csr_read_data = ip;
+ 5'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -37691,8 +38074,9 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
-
+ bie <= 1'b0;
+
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -37704,13 +38088,21 @@ always @(posedge clk_i )
ip <= asserted;
-
-
+
+ if (non_debug_exception == 1'b1)
+ begin
-
-
-
+ eie <= ie;
+ ie <= 1'b0;
+ end
+ else if (debug_exception == 1'b1)
+ begin
+ bie <= ie;
+ ie <= 1'b0;
+ end
+
+
@@ -37718,14 +38110,6 @@ always @(posedge clk_i )
- if (exception == 1'b1)
- begin
-
- eie <= ie;
- ie <= 1'b0;
- end
-
-
else if (stall_x == 1'b0)
begin
@@ -37743,26 +38127,28 @@ always @(posedge clk_i )
-
-
-
+ else if (bret_q_x == 1'b1)
+
+ ie <= bie;
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+ bie <= csr_write_data[2];
+
end
- if (csr == 3'h1)
+ if (csr == 5'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -37779,8 +38165,9 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
-
+ bie <= 1'b0;
+
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -37790,13 +38177,21 @@ always @(posedge clk_i )
ip <= asserted;
-
-
+
+ if (non_debug_exception == 1'b1)
+ begin
-
-
-
+ eie <= ie;
+ ie <= 1'b0;
+ end
+ else if (debug_exception == 1'b1)
+ begin
+ bie <= ie;
+ ie <= 1'b0;
+ end
+
+
@@ -37804,14 +38199,6 @@ always @(posedge clk_i )
- if (exception == 1'b1)
- begin
-
- eie <= ie;
- ie <= 1'b0;
- end
-
-
else if (stall_x == 1'b0)
begin
@@ -37827,24 +38214,26 @@ always @(posedge clk_i )
end
-
-
-
+ else if (bret_q_x == 1'b1)
+
+ ie <= bie;
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+ bie <= csr_write_data[2];
+
end
- if (csr == 3'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -38428,7 +38817,7 @@ endmodule
-module lm32_top_medium_debug (
+module lm32_top_medium_icache_debug (
clk_i,
rst_i,
@@ -38672,7 +39061,7 @@ endfunction
-lm32_cpu_medium_debug cpu (
+lm32_cpu_medium_icache_debug cpu (
.clk_i (clk_i),
@@ -39152,7 +39541,7 @@ endmodule
-module lm32_mc_arithmetic_medium_debug (
+module lm32_mc_arithmetic_medium_icache_debug (
clk_i,
rst_i,
@@ -39808,7 +40197,7 @@ endmodule
-module lm32_cpu_medium_debug (
+module lm32_cpu_medium_icache_debug (
clk_i,
@@ -40646,7 +41035,7 @@ endfunction
-lm32_instruction_unit_medium_debug #(
+lm32_instruction_unit_medium_icache_debug #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -40762,7 +41151,7 @@ lm32_instruction_unit_medium_debug #(
);
-lm32_decoder_medium_debug decoder (
+lm32_decoder_medium_icache_debug decoder (
.instruction (instruction_d),
@@ -40860,7 +41249,7 @@ lm32_decoder_medium_debug decoder (
);
-lm32_load_store_unit_medium_debug #(
+lm32_load_store_unit_medium_icache_debug #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -41026,7 +41415,7 @@ lm32_multiplier multiplier (
-lm32_interrupt_medium_debug interrupt_unit (
+lm32_interrupt_medium_icache_debug interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -41062,7 +41451,7 @@ lm32_interrupt_medium_debug interrupt_unit (
-lm32_jtag_medium_debug jtag (
+lm32_jtag_medium_icache_debug jtag (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -41126,7 +41515,7 @@ lm32_jtag_medium_debug jtag (
-lm32_debug_medium_debug #(
+lm32_debug_medium_icache_debug #(
.breakpoints (breakpoints),
.watchpoints (watchpoints)
) hw_debug (
@@ -43297,7 +43686,7 @@ endmodule
-module lm32_load_store_unit_medium_debug (
+module lm32_load_store_unit_medium_icache_debug (
clk_i,
rst_i,
@@ -44609,7 +44998,7 @@ endmodule
-module lm32_decoder_medium_debug (
+module lm32_decoder_medium_icache_debug (
instruction,
@@ -45639,7 +46028,7 @@ endmodule
-module lm32_icache_medium_debug (
+module lm32_icache_medium_icache_debug (
clk_i,
rst_i,
@@ -47290,7 +47679,7 @@ endmodule
-module lm32_debug_medium_debug (
+module lm32_debug_medium_icache_debug (
clk_i,
rst_i,
@@ -48039,7 +48428,7 @@ endmodule
-module lm32_instruction_unit_medium_debug (
+module lm32_instruction_unit_medium_icache_debug (
clk_i,
rst_i,
@@ -48494,7 +48883,7 @@ endfunction
-lm32_icache_medium_debug #(
+lm32_icache_medium_icache_debug #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
@@ -49386,7 +49775,7 @@ endmodule
-module lm32_jtag_medium_debug (
+module lm32_jtag_medium_icache_debug (
clk_i,
rst_i,
@@ -50205,7 +50594,7 @@ endmodule
-module lm32_interrupt_medium_debug (
+module lm32_interrupt_medium_icache_debug (
clk_i,
rst_i,
@@ -63033,18 +63422,6 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
@@ -63070,12 +63447,13 @@ endmodule
-
+
+
+
+
-
-
-
+
@@ -63175,16 +63553,18 @@ endmodule
+
+
-
-
-
+
+
+
@@ -63213,25 +63593,24 @@ endmodule
-
-
-
+
+
-
-
-
+
+
+
@@ -63332,47 +63711,27 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
+
-
+
-
-
-
-
@@ -63381,8 +63740,6 @@ endmodule
-
-
@@ -63390,19 +63747,28 @@ endmodule
+
+
-
+
+
-
+
+
+
+
+
+
+
+
-
@@ -63463,14 +63829,14 @@ endmodule
+
-
-
-
+
+
@@ -63560,7 +63926,7 @@ endmodule
-module lm32_top_medium_icache_debug (
+module lm32_top_medium (
clk_i,
rst_i,
@@ -63717,18 +64083,17 @@ wire [ (2-1):0] D_BTE_O;
-
-wire [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_q;
-wire jtag_update;
-wire [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_q;
-wire jtck;
-wire jrstn;
+
+
+
+
+
+
+
@@ -63804,7 +64169,7 @@ endfunction
-lm32_cpu_medium_icache_debug cpu (
+lm32_cpu_medium cpu (
.clk_i (clk_i),
@@ -63825,13 +64190,12 @@ lm32_cpu_medium_icache_debug cpu (
-
- .jtag_clk (jtck),
- .jtag_update (jtag_update),
- .jtag_reg_q (jtag_reg_q),
- .jtag_reg_addr_q (jtag_reg_addr_q),
-
+
+
+
+
+
@@ -63860,10 +64224,9 @@ lm32_cpu_medium_icache_debug cpu (
+
+
- .jtag_reg_d (jtag_reg_d),
- .jtag_reg_addr_d (jtag_reg_addr_d),
-
@@ -63898,21 +64261,20 @@ lm32_cpu_medium_icache_debug cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
-jtag_cores jtag_cores (
+
- .reg_d (jtag_reg_d),
- .reg_addr_d (jtag_reg_addr_d),
+
+
- .reg_update (jtag_update),
- .reg_q (jtag_reg_q),
- .reg_addr_q (jtag_reg_addr_q),
- .jtck (jtck),
- .jrstn (jrstn)
- );
-
+
+
+
+
+
+
+
endmodule
@@ -64284,7 +64646,7 @@ endmodule
-module lm32_mc_arithmetic_medium_icache_debug (
+module lm32_mc_arithmetic_medium (
clk_i,
rst_i,
@@ -64940,7 +65302,7 @@ endmodule
-module lm32_cpu_medium_icache_debug (
+module lm32_cpu_medium (
clk_i,
@@ -64961,13 +65323,12 @@ module lm32_cpu_medium_icache_debug (
-
- jtag_clk,
- jtag_update,
- jtag_reg_q,
- jtag_reg_addr_q,
-
+
+
+
+
+
@@ -64996,10 +65357,9 @@ module lm32_cpu_medium_icache_debug (
+
+
- jtag_reg_d,
- jtag_reg_addr_d,
-
@@ -65040,25 +65400,24 @@ module lm32_cpu_medium_icache_debug (
parameter eba_reset = 32'h00000000;
+
-parameter deba_reset = 32'h10000000;
-
+
+
+
+
+
-parameter icache_associativity = 1;
-parameter icache_sets = 256;
-parameter icache_bytes_per_line = 16;
-parameter icache_base_address = 32'h0;
-parameter icache_limit = 32'h7fffffff;
-
-
-
-
-
-
+parameter icache_associativity = 1;
+parameter icache_sets = 512;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 0;
+parameter icache_limit = 0;
+
@@ -65078,11 +65437,11 @@ parameter dcache_limit = 0;
+
-parameter watchpoints = 32'h4;
-
-
+parameter watchpoints = 0;
+
@@ -65124,12 +65483,11 @@ input [ (32-1):0] interrupt;
+
+
+
+
-input jtag_clk;
-input jtag_update;
-input [ 7:0] jtag_reg_q;
-input [2:0] jtag_reg_addr_q;
-
@@ -65169,12 +65527,11 @@ input D_RTY_I;
+
+
+
+
-output [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_d;
-output [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_d;
-
@@ -65238,9 +65595,8 @@ wire [ (2-1):0] D_BTE_O;
+
-reg valid_a;
-
reg valid_f;
reg valid_d;
@@ -65263,8 +65619,8 @@ reg [ 1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire [ ((32-2)+2-1):2] branch_predict_address_d;
+wire [ ((32-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -65276,9 +65632,9 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [ ((32-2)+2-1):2] branch_offset_d;
+reg [ ((32-2)+2-1):2] branch_target_x;
+reg [ ((32-2)+2-1):2] branch_target_m;
wire [ 0:0] d_result_sel_0_d;
wire [ 1:0] d_result_sel_1_d;
@@ -65353,15 +65709,14 @@ wire [ (5-1):0] write_idx_d;
reg [ (5-1):0] write_idx_x;
reg [ (5-1):0] write_idx_m;
reg [ (5-1):0] write_idx_w;
-wire [ (5-1):0] csr_d;
-reg [ (5-1):0] csr_x;
+wire [ (3-1):0] csr_d;
+reg [ (3-1):0] csr_x;
wire [ (3-1):0] condition_d;
reg [ (3-1):0] condition_x;
+
+
-wire break_d;
-reg break_x;
-
wire scall_d;
reg scall_x;
@@ -65374,16 +65729,14 @@ reg eret_m;
-
-wire bret_d;
-reg bret_x;
-wire bret_q_x;
-reg bret_m;
-
+
+
+
+
+
-
wire csr_write_enable_d;
reg csr_write_enable_x;
@@ -65535,11 +65888,11 @@ wire [ (32-1):0] cfg2;
reg [ (32-1):0] csr_read_data_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+wire [ ((32-2)+2-1):2] pc_f;
+wire [ ((32-2)+2-1):2] pc_d;
+wire [ ((32-2)+2-1):2] pc_x;
+wire [ ((32-2)+2-1):2] pc_m;
+wire [ ((32-2)+2-1):2] pc_w;
@@ -65553,13 +65906,12 @@ wire [ (32-1):0] instruction_f;
wire [ (32-1):0] instruction_d;
+
+
+
+
+
-wire iflush;
-wire icache_stall_request;
-wire icache_restart_request;
-wire icache_refill_request;
-wire icache_refilling;
-
@@ -65585,32 +65937,25 @@ wire stall_wb_load;
-
-
-
-wire [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+
+
+
+
+
+
-
-wire jtag_csr_write_enable;
-wire [ (32-1):0] jtag_csr_write_data;
-wire [ (5-1):0] jtag_csr;
-wire jtag_read_enable;
-wire [ 7:0] jtag_read_data;
-wire jtag_write_enable;
-wire [ 7:0] jtag_write_data;
-wire [ (32-1):0] jtag_address;
-wire jtag_access_complete;
-
-
-wire jtag_break;
+
+
+
+
@@ -65640,11 +65985,10 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
+reg [ (32-2)+2-1:8] eba;
+
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
-
reg [ (3-1):0] eid_x;
@@ -65654,39 +65998,34 @@ reg [ (3-1):0] eid_x;
-
-
-
-wire dc_ss;
+
-wire dc_re;
-wire exception_x;
-reg exception_m;
-wire debug_exception_x;
-reg debug_exception_m;
-reg debug_exception_w;
-wire debug_exception_q_w;
-wire non_debug_exception_x;
-reg non_debug_exception_m;
-reg non_debug_exception_w;
-wire non_debug_exception_q_w;
-
+
+
+
+
+
+
+
+wire exception_x;
+reg exception_m;
+reg exception_w;
+wire exception_q_w;
+
-
-
-wire reset_exception;
+
+
-
@@ -65694,10 +66033,9 @@ wire interrupt_exception;
+
+
-wire breakpoint_exception;
-wire watchpoint_exception;
-
@@ -65778,7 +66116,7 @@ endfunction
-lm32_instruction_unit_medium_icache_debug #(
+lm32_instruction_unit_medium #(
.associativity (icache_associativity),
.sets (icache_sets),
.bytes_per_line (icache_bytes_per_line),
@@ -65809,9 +66147,8 @@ lm32_instruction_unit_medium_icache_debug #(
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
+
- .iflush (iflush),
-
@@ -65835,12 +66172,11 @@ lm32_instruction_unit_medium_icache_debug #(
+
+
+
+
- .jtag_read_enable (jtag_read_enable),
- .jtag_write_enable (jtag_write_enable),
- .jtag_write_data (jtag_write_data),
- .jtag_address (jtag_address),
-
@@ -65850,12 +66186,11 @@ lm32_instruction_unit_medium_icache_debug #(
.pc_m (pc_m),
.pc_w (pc_w),
+
+
+
+
- .icache_stall_request (icache_stall_request),
- .icache_restart_request (icache_restart_request),
- .icache_refill_request (icache_refill_request),
- .icache_refilling (icache_refilling),
-
@@ -65876,10 +66211,9 @@ lm32_instruction_unit_medium_icache_debug #(
+
+
- .jtag_read_data (jtag_read_data),
- .jtag_access_complete (jtag_access_complete),
-
@@ -65894,7 +66228,7 @@ lm32_instruction_unit_medium_icache_debug #(
);
-lm32_decoder_medium_icache_debug decoder (
+lm32_decoder_medium decoder (
.instruction (instruction_d),
@@ -65973,16 +66307,14 @@ lm32_decoder_medium_icache_debug decoder (
.branch_reg (branch_reg_d),
.condition (condition_d),
+
- .break_opcode (break_d),
-
.scall (scall_d),
.eret (eret_d),
+
- .bret (bret_d),
-
@@ -65992,7 +66324,7 @@ lm32_decoder_medium_icache_debug decoder (
);
-lm32_load_store_unit_medium_icache_debug #(
+lm32_load_store_unit_medium #(
.associativity (dcache_associativity),
.sets (dcache_sets),
.bytes_per_line (dcache_bytes_per_line),
@@ -66158,7 +66490,7 @@ lm32_multiplier multiplier (
-lm32_interrupt_medium_icache_debug interrupt_unit (
+lm32_interrupt_medium interrupt_unit (
.clk_i (clk_i),
.rst_i (rst_i),
@@ -66167,18 +66499,17 @@ lm32_interrupt_medium_icache_debug interrupt_unit (
.stall_x (stall_x),
+
+
- .non_debug_exception (non_debug_exception_q_w),
- .debug_exception (debug_exception_q_w),
-
-
+ .exception (exception_q_w),
+
.eret_q_x (eret_q_x),
+
- .bret_q_x (bret_q_x),
-
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -66193,116 +66524,95 @@ lm32_interrupt_medium_icache_debug interrupt_unit (
-
-lm32_jtag_medium_icache_debug jtag (
+
- .clk_i (clk_i),
- .rst_i (rst_i),
+
+
- .jtag_clk (jtag_clk),
- .jtag_update (jtag_update),
- .jtag_reg_q (jtag_reg_q),
- .jtag_reg_addr_q (jtag_reg_addr_q),
+
+
+
+
-
-
- .csr (csr_x),
- .csr_write_data (operand_1_x),
- .csr_write_enable (csr_write_enable_q_x),
- .stall_x (stall_x),
+
+
+
+
-
-
- .jtag_read_data (jtag_read_data),
- .jtag_access_complete (jtag_access_complete),
+
+
-
-
- .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
+
-
-
- .jtx_csr_read_data (jtx_csr_read_data),
- .jrx_csr_read_data (jrx_csr_read_data),
+
+
-
-
- .jtag_csr_write_enable (jtag_csr_write_enable),
- .jtag_csr_write_data (jtag_csr_write_data),
- .jtag_csr (jtag_csr),
- .jtag_read_enable (jtag_read_enable),
- .jtag_write_enable (jtag_write_enable),
- .jtag_write_data (jtag_write_data),
- .jtag_address (jtag_address),
+
+
+
+
+
+
+
-
-
- .jtag_break (jtag_break),
- .jtag_reset (reset_exception),
+
+
- .jtag_reg_d (jtag_reg_d),
- .jtag_reg_addr_d (jtag_reg_addr_d)
- );
-
-
+
+
+
-
-lm32_debug_medium_icache_debug #(
- .breakpoints (breakpoints),
- .watchpoints (watchpoints)
- ) hw_debug (
-
- .clk_i (clk_i),
- .rst_i (rst_i),
- .pc_x (pc_x),
- .load_x (load_x),
- .store_x (store_x),
- .load_store_address_x (adder_result_x),
- .csr_write_enable_x (csr_write_enable_q_x),
- .csr_write_data (operand_1_x),
- .csr_x (csr_x),
- .jtag_csr_write_enable (jtag_csr_write_enable),
- .jtag_csr_write_data (jtag_csr_write_data),
- .jtag_csr (jtag_csr),
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
- .eret_q_x (eret_q_x),
- .bret_q_x (bret_q_x),
- .stall_x (stall_x),
- .exception_x (exception_x),
- .q_x (q_x),
-
+
+
+
+
+
+
+
+
+
+
+
+
-
- .dc_ss (dc_ss),
-
-
- .dc_re (dc_re),
- .bp_match (bp_match),
- .wp_match (wp_match)
- );
-
@@ -66747,9 +67057,8 @@ assign kill_f = ( (valid_d == 1'b1)
+
- || (icache_refill_request == 1'b1)
-
@@ -66762,9 +67071,8 @@ assign kill_d = (branch_taken_m == 1'b1)
+
- || (icache_refill_request == 1'b1)
-
@@ -66793,25 +67101,21 @@ assign kill_w = 1'b0
-
-assign breakpoint_exception = ( ( (break_x == 1'b1)
- || (bp_match == 1'b1)
- )
- && (valid_x == 1'b1)
- )
-
-
- || (jtag_break == 1'b1)
+
+
+
+
+
+
+
+
- ;
-
+
-assign watchpoint_exception = wp_match == 1'b1;
-
@@ -66835,17 +67139,38 @@ assign system_call_exception = ( (scall_x == 1'b1)
);
+
+
+
-assign debug_exception_x = (breakpoint_exception == 1'b1)
- || (watchpoint_exception == 1'b1)
- ;
+
+
+
-assign non_debug_exception_x = (system_call_exception == 1'b1)
-
+
+
+
- || (reset_exception == 1'b1)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+assign exception_x = (system_call_exception == 1'b1)
@@ -66859,9 +67184,8 @@ assign non_debug_exception_x = (system_call_exception == 1'b1)
|| ( (interrupt_exception == 1'b1)
+
- && (dc_ss == 1'b0)
-
@@ -66872,54 +67196,27 @@ assign non_debug_exception_x = (system_call_exception == 1'b1)
;
-
-assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
always @(*)
begin
-
-
-
- if (reset_exception == 1'b1)
- eid_x = 3'h0;
- else
+
+
+
-
+
+
+
+
- if (breakpoint_exception == 1'b1)
- eid_x = 3'd1;
- else
-
@@ -66931,11 +67228,10 @@ begin
+
+
+
- if (watchpoint_exception == 1'b1)
- eid_x = 3'd3;
- else
-
@@ -66947,9 +67243,8 @@ begin
if ( (interrupt_exception == 1'b1)
+
- && (dc_ss == 1'b0)
-
)
eid_x = 3'h6;
@@ -66985,19 +67280,18 @@ assign stall_d = (stall_x == 1'b1)
&& (kill_d == 1'b0)
)
+
+
+
+
+
+
+
+
+
+
+
- || ( ( (break_d == 1'b1)
- || (bret_d == 1'b1)
- )
- && ( (load_q_x == 1'b1)
- || (store_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
- )
- && (kill_d == 1'b0)
- )
-
|| ( (csr_write_enable_d == 1'b1)
&& (load_q_x == 1'b1)
@@ -67059,14 +67353,16 @@ assign stall_m = (stall_wb_load == 1'b1)
+
+
- || (icache_stall_request == 1'b1)
- || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
-
-
-
+
+
+ || (I_CYC_O == 1'b1)
+
+
@@ -67099,24 +67395,21 @@ assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+
-assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
-
assign load_q_x = (load_x == 1'b1)
&& (q_x == 1'b1)
+
- && (bp_match == 1'b0)
-
;
assign store_q_x = (store_x == 1'b1)
&& (q_x == 1'b1)
+
- && (bp_match == 1'b0)
-
;
@@ -67127,13 +67420,13 @@ assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
-assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
-
+
+assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
+
+
assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
@@ -67148,12 +67441,12 @@ assign cfg = {
breakpoints[3:0],
interrupts[5:0],
-
- 1'b1,
-
+ 1'b0,
+
+
@@ -67162,26 +67455,26 @@ assign cfg = {
-
- 1'b1,
-
-
-
- 1'b1,
+ 1'b0,
-
-
+
- 1'b1,
+
+ 1'b0,
+
+
+ 1'b0,
+
+
@@ -67253,22 +67546,19 @@ assign cfg2 = {
+
+
+
+
+
-assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 5'h3)
- && (stall_d == 1'b0)
- && (kill_d == 1'b0)
- && (valid_d == 1'b1))
-
-
-
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h3))
+
+
+
+
+
- ;
-
@@ -67284,7 +67574,7 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
-assign csr_d = read_idx_0_d[ (5-1):0];
+assign csr_d = read_idx_0_d[ (3-1):0];
always @(*)
@@ -67292,29 +67582,27 @@ begin
case (csr_x)
- 5'h0,
- 5'h1,
- 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 3'h0,
+ 3'h1,
+ 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
- 5'h6: csr_read_data_x = cfg;
- 5'h7: csr_read_data_x = {eba, 8'h00};
+ 3'h6: csr_read_data_x = cfg;
+ 3'h7: csr_read_data_x = {eba, 8'h00};
+
- 5'h9: csr_read_data_x = {deba, 8'h00};
-
+
+
- 5'he: csr_read_data_x = jtx_csr_read_data;
- 5'hf: csr_read_data_x = jrx_csr_read_data;
-
- 5'ha: csr_read_data_x = cfg2;
+ 3'ha: csr_read_data_x = cfg2;
default: csr_read_data_x = { 32{1'bx}};
endcase
@@ -67328,40 +67616,36 @@ end
always @(posedge clk_i )
begin
if (rst_i == 1'b1)
- eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ eba <= eba_reset[ (32-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[ (32-2)+2-1:8];
+
+
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
- eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
end
end
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
- else
- begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
- deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
- deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
+
+
+
+
+
+
+
+
+
+
- end
-end
-
@@ -67396,11 +67680,10 @@ end
-
-
+
@@ -67414,20 +67697,19 @@ end
-
-always @(*)
-begin
- if (icache_refill_request == 1'b1)
- valid_a = 1'b0;
- else if (icache_restart_request == 1'b1)
- valid_a = 1'b1;
- else
- valid_a = !icache_refilling;
-end
+
+
+
+
+
+
-
+
+
+
+
@@ -67439,6 +67721,7 @@ end
+
always @(posedge clk_i )
@@ -67455,11 +67738,11 @@ begin
begin
if ((kill_f == 1'b1) || (stall_a == 1'b0))
+
- valid_f <= valid_a;
-
-
+ valid_f <= 1'b1;
+
else if (stall_f == 1'b0)
valid_f <= 1'b0;
@@ -67504,7 +67787,7 @@ begin
operand_0_x <= { 32{1'b0}};
operand_1_x <= { 32{1'b0}};
store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ branch_target_x <= { (32-2){1'b0}};
x_result_sel_csr_x <= 1'b0;
@@ -67541,7 +67824,7 @@ begin
m_bypass_enable_x <= 1'b0;
write_enable_x <= 1'b0;
write_idx_x <= { 5{1'b0}};
- csr_x <= { 5{1'b0}};
+ csr_x <= { 3{1'b0}};
load_x <= 1'b0;
store_x <= 1'b0;
size_x <= { 2{1'b0}};
@@ -67564,16 +67847,14 @@ begin
branch_predict_taken_x <= 1'b0;
condition_x <= 3'b000;
+
- break_x <= 1'b0;
-
scall_x <= 1'b0;
eret_x <= 1'b0;
+
- bret_x <= 1'b0;
-
@@ -67582,7 +67863,7 @@ begin
csr_write_enable_x <= 1'b0;
operand_m <= { 32{1'b0}};
- branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ branch_target_m <= { (32-2){1'b0}};
m_result_sel_compare_m <= 1'b0;
@@ -67615,10 +67896,9 @@ begin
+
+
- debug_exception_m <= 1'b0;
- non_debug_exception_m <= 1'b0;
-
operand_w <= { 32{1'b0}};
w_result_sel_load_w <= 1'b0;
@@ -67630,13 +67910,13 @@ begin
write_idx_w <= { 5{1'b0}};
write_enable_w <= 1'b0;
-
- debug_exception_w <= 1'b0;
- non_debug_exception_w <= 1'b0;
-
+
+ exception_w <= 1'b0;
+
+
@@ -67655,7 +67935,7 @@ begin
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
@@ -67714,9 +67994,8 @@ begin
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
+
- break_x <= break_d;
-
scall_x <= scall_d;
@@ -67725,9 +68004,8 @@ begin
eret_x <= eret_d;
+
- bret_x <= bret_d;
-
write_enable_x <= write_enable_d;
end
@@ -67779,40 +68057,40 @@ begin
-
- if (non_debug_exception_x == 1'b1)
- write_idx_m <= 5'd30;
- else if (debug_exception_x == 1'b1)
- write_idx_m <= 5'd31;
- else
- write_idx_m <= write_idx_x;
-
-
+
+
+
+ if (exception_x == 1'b1)
+ write_idx_m <= 5'd30;
+ else
+ write_idx_m <= write_idx_x;
+
+
condition_met_m <= condition_met_x;
+
+
+
+
+
+
+
+
+
- if (exception_x == 1'b1)
- if ((dc_re == 1'b1)
- || ((debug_exception_x == 1'b1)
- && (non_debug_exception_x == 1'b0)))
- branch_target_m <= {deba, eid_x, {3{1'b0}}};
- else
- branch_target_m <= {eba, eid_x, {3{1'b0}}};
- else
- branch_target_m <= branch_target_x;
-
-
+ branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+
@@ -67824,16 +68102,14 @@ begin
eret_m <= eret_q_x;
+
- bret_m <= bret_q_x;
-
write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
+
- debug_exception_m <= debug_exception_x;
- non_debug_exception_m <= non_debug_exception_x;
-
end
@@ -67879,13 +68155,13 @@ begin
write_enable_w <= write_enable_m;
-
- debug_exception_w <= debug_exception_m;
- non_debug_exception_w <= non_debug_exception_m;
-
+
+ exception_w <= exception_m;
+
+
@@ -68429,7 +68705,7 @@ endmodule
-module lm32_load_store_unit_medium_icache_debug (
+module lm32_load_store_unit_medium (
clk_i,
rst_i,
@@ -69741,7 +70017,7 @@ endmodule
-module lm32_decoder_medium_icache_debug (
+module lm32_decoder_medium (
instruction,
@@ -69820,16 +70096,14 @@ module lm32_decoder_medium_icache_debug (
bi_conditional,
bi_unconditional,
+
- break_opcode,
-
scall,
eret,
+
- bret,
-
@@ -69913,8 +70187,8 @@ output [ (5-1):0] write_idx;
wire [ (5-1):0] write_idx;
output [ (32-1):0] immediate;
wire [ (32-1):0] immediate;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output [ ((32-2)+2-1):2] branch_offset;
+wire [ ((32-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
@@ -69963,20 +70237,18 @@ wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-output break_opcode;
-wire break_opcode;
+
+
output scall;
wire scall;
output eret;
wire eret;
-
-output bret;
-wire bret;
+
+
@@ -70330,16 +70602,14 @@ assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
+
-assign break_opcode = op_raise & ~instruction[2];
-
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
+
-assign bret = op_b & (instruction[25:21] == 5'd31);
-
@@ -70728,190 +70998,210 @@ endmodule
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
+
+
+
+
+
+
+
+
+
-module lm32_icache_medium_icache_debug (
+
- clk_i,
- rst_i,
- stall_a,
- stall_f,
- address_a,
- address_f,
- read_enable_f,
- refill_ready,
- refill_data,
- iflush,
-
+
+
+
+
+
+
+
+
+
+
+
-
- valid_d,
- branch_predict_taken_d,
- stall_request,
- restart_request,
- refill_request,
- refill_address,
- refilling,
- inst
- );
+
+
+
+
+
+
+
+
+
-parameter associativity = 1;
-parameter sets = 512;
-parameter bytes_per_line = 16;
-parameter base_address = 0;
-parameter limit = 0;
+
+
+
+
+
-localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
-localparam addr_set_width = clogb2(sets)-1;
-localparam addr_offset_lsb = 2;
-localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
-localparam addr_set_lsb = (addr_offset_msb+1);
-localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
-localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
-localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
+
+
+
+
+
+
+
+
+
-input clk_i;
-input rst_i;
+
+
-input stall_a;
-input stall_f;
+
+
-input valid_d;
-input branch_predict_taken_d;
+
+
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
-input read_enable_f;
+
+
+
-input refill_ready;
-input [ (32-1):0] refill_data;
+
+
-input iflush;
-
+
+
-
-output stall_request;
-wire stall_request;
-output restart_request;
-reg restart_request;
-output refill_request;
-wire refill_request;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
-output refilling;
-reg refilling;
-output [ (32-1):0] inst;
-wire [ (32-1):0] inst;
-
-
-
-
-
-wire enable;
-wire [0:associativity-1] way_mem_we;
-wire [ (32-1):0] way_data[0:associativity-1];
-wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
-wire [0:associativity-1] way_valid;
-wire [0:associativity-1] way_match;
-wire miss;
-
-wire [ (addr_set_width-1):0] tmem_read_address;
-wire [ (addr_set_width-1):0] tmem_write_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
-
-reg [ 3:0] state;
-wire flushing;
-wire check;
-wire refill;
-
-reg [associativity-1:0] refill_way_select;
-reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
-wire last_refill;
-reg [ (addr_set_width-1):0] flush_set;
-
-genvar i;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -70920,307 +71210,214 @@ genvar i;
+
+
+
+
-
-function integer clogb2;
-input [31:0] value;
-begin
- for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
- value = value >> 1;
-end
-endfunction
-
-function integer clogb2_v1;
-input [31:0] value;
-reg [31:0] i;
-reg [31:0] temp;
-begin
- temp = 0;
- i = 0;
- for (i = 0; temp < value; i = i + 1)
- temp = 1<<i;
- clogb2_v1 = i-1;
-end
-endfunction
-
-
-
-
-
-
+
+
+
+
+
+
+
+
- generate
- for (i = 0; i < associativity; i = i + 1)
- begin : memories
-
- lm32_ram
- #(
-
- .data_width (32),
- .address_width ( (addr_offset_width+addr_set_width))
-)
- way_0_data_ram
- (
-
- .read_clk (clk_i),
- .write_clk (clk_i),
- .reset (rst_i),
- .read_address (dmem_read_address),
- .enable_read (enable),
- .write_address (dmem_write_address),
- .enable_write ( 1'b1),
- .write_enable (way_mem_we[i]),
- .write_data (refill_data),
-
- .read_data (way_data[i])
- );
-
- lm32_ram
- #(
-
- .data_width ( (addr_tag_width+1)),
- .address_width ( addr_set_width)
+
+
+
+
+
- )
- way_0_tag_ram
- (
-
- .read_clk (clk_i),
- .write_clk (clk_i),
- .reset (rst_i),
- .read_address (tmem_read_address),
- .enable_read (enable),
- .write_address (tmem_write_address),
- .enable_write ( 1'b1),
- .write_enable (way_mem_we[i] | flushing),
- .write_data (tmem_write_data),
-
- .read_data ({way_tag[i], way_valid[i]})
- );
-
- end
-endgenerate
+
+
+
+
+
+
+
+
+
+
+
-generate
- for (i = 0; i < associativity; i = i + 1)
- begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb], 1'b1});
- end
-endgenerate
+
-generate
- if (associativity == 1)
- begin : inst_1
-assign inst = way_match[0] ? way_data[0] : 32'b0;
- end
- else if (associativity == 2)
- begin : inst_2
-assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
- end
-endgenerate
-generate
- if (bytes_per_line > 4)
-assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
- else
-assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
-endgenerate
+
+
+
-assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+
+
+
+
+
+
-assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
-assign tmem_write_address = flushing
- ? flush_set
- : refill_address[ addr_set_msb:addr_set_lsb];
+
+
-generate
- if (bytes_per_line > 4)
-assign last_refill = refill_offset == {addr_offset_width{1'b1}};
- else
-assign last_refill = 1'b1;
-endgenerate
-
+
+
+
-assign enable = (stall_a == 1'b0);
+
+
+
+
-generate
- if (associativity == 1)
- begin : we_1
-assign way_mem_we[0] = (refill_ready == 1'b1);
- end
- else
- begin : we_2
-assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
-assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
- end
-endgenerate
-assign tmem_write_data[ 0] = last_refill & !flushing;
-assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
-assign flushing = |state[1:0];
-assign check = state[2];
-assign refill = state[3];
+
+
+
-assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
-assign stall_request = (check == 1'b0);
-assign refill_request = (refill == 1'b1);
-
+
+
+
+
+
+
+
+
+
-generate
- if (associativity >= 2)
- begin : way_select
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
- else
- begin
- if (miss == 1'b1)
- refill_way_select <= {refill_way_select[0], refill_way_select[1]};
- end
-end
- end
-endgenerate
+
+
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- refilling <= 1'b0;
- else
- refilling <= refill;
-end
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 4'b0001;
- flush_set <= { addr_set_width{1'b1}};
- refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- restart_request <= 1'b0;
- end
- else
- begin
- case (state)
+
+
+
+
+
+
+
+
+
+
- 4'b0001:
- begin
- if (flush_set == { addr_set_width{1'b0}})
- state <= 4'b0100;
- flush_set <= flush_set - 1'b1;
- end
+
+
+
+
+
+
- 4'b0010:
- begin
- if (flush_set == { addr_set_width{1'b0}})
-
+
+
+
+
-
- state <= 4'b0100;
+
- flush_set <= flush_set - 1'b1;
- end
+
- 4'b0100:
- begin
- if (stall_a == 1'b0)
- restart_request <= 1'b0;
- if (iflush == 1'b1)
- begin
- refill_address <= address_f;
- state <= 4'b0010;
- end
- else if (miss == 1'b1)
- begin
- refill_address <= address_f;
- state <= 4'b1000;
- end
- end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- 4'b1000:
- begin
- if (refill_ready == 1'b1)
- begin
- if (last_refill == 1'b1)
- begin
- restart_request <= 1'b1;
- state <= 4'b0100;
- end
- end
- end
+
+
+
+
+
+
+
+
+
+
+
- endcase
- end
-end
+
+
-generate
- if (bytes_per_line > 4)
- begin
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- refill_offset <= {addr_offset_width{1'b0}};
- else
- begin
- case (state)
+
+
+
+
+
+
+
+
+
+
+
- 4'b0100:
- begin
- if (iflush == 1'b1)
- refill_offset <= {addr_offset_width{1'b0}};
- else if (miss == 1'b1)
- refill_offset <= {addr_offset_width{1'b0}};
- end
+
+
+
+
+
+
+
- 4'b1000:
- begin
- if (refill_ready == 1'b1)
- refill_offset <= refill_offset + 1'b1;
- end
+
+
+
+
+
+
+
+
+
+
- endcase
- end
-end
- end
-endgenerate
-endmodule
-
+
+
@@ -72404,165 +72601,127 @@ endmodule
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-module lm32_debug_medium_icache_debug (
- clk_i,
- rst_i,
- pc_x,
- load_x,
- store_x,
- load_store_address_x,
- csr_write_enable_x,
- csr_write_data,
- csr_x,
-
-
- jtag_csr_write_enable,
- jtag_csr_write_data,
- jtag_csr,
+
+
+
+
+
+
+
+
+
-
-
-
- eret_q_x,
- bret_q_x,
- stall_x,
- exception_x,
- q_x,
-
-
+
+
-
-
-
- dc_ss,
+
+
+
+
-
- dc_re,
- bp_match,
- wp_match
- );
+
+
+
+
+
+
+
+
-parameter breakpoints = 0;
-parameter watchpoints = 0;
+
+
-input clk_i;
-input rst_i;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-input load_x;
-input store_x;
-input [ (32-1):0] load_store_address_x;
-input csr_write_enable_x;
-input [ (32-1):0] csr_write_data;
-input [ (5-1):0] csr_x;
-
-input jtag_csr_write_enable;
-input [ (32-1):0] jtag_csr_write_data;
-input [ (5-1):0] jtag_csr;
-
-
+
+
-input eret_q_x;
-input bret_q_x;
-input stall_x;
-input exception_x;
-input q_x;
-
+
+
+
+
+
+
+
+
-
+
+
-
-
-
-
-
-
-
-
-output dc_ss;
-reg dc_ss;
+
+
+
+
+
-
-output dc_re;
-reg dc_re;
-output bp_match;
-wire bp_match;
-output wp_match;
-wire wp_match;
-
-
-
-
-
-genvar i;
-
+
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
-reg bp_e[0:breakpoints-1];
-wire [0:breakpoints-1]bp_match_n;
-
-reg [ 1:0] wpc_c[0:watchpoints-1];
-reg [ (32-1):0] wp[0:watchpoints-1];
-wire [0:watchpoints]wp_match_n;
-wire debug_csr_write_enable;
-wire [ (32-1):0] debug_csr_write_data;
-wire [ (5-1):0] debug_csr;
-
-reg [ 2:0] state;
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
+
+
@@ -72570,6 +72729,7 @@ reg [ 2:0] state;
+
@@ -72577,35 +72737,48 @@ reg [ 2:0] state;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-function integer clogb2;
-input [31:0] value;
-begin
- for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
- value = value >> 1;
-end
-endfunction
+
+
-function integer clogb2_v1;
-input [31:0] value;
-reg [31:0] i;
-reg [31:0] temp;
-begin
- temp = 0;
- i = 0;
- for (i = 0; temp < value; i = i + 1)
- temp = 1<<i;
- clogb2_v1 = i-1;
-end
-endfunction
+
+
+
+
+
+
@@ -72614,191 +72787,132 @@ endfunction
-generate
- for (i = 0; i < breakpoints; i = i + 1)
- begin : bp_comb
-assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
- end
-endgenerate
-generate
-
+
+
+
- if (breakpoints > 0)
-assign bp_match = (|bp_match_n) || (state == 3'b011);
- else
-assign bp_match = state == 3'b011;
-
+
+
+
+
+
+
+
+
+
+
+
-
-
+
+
-endgenerate
-
-generate
- for (i = 0; i < watchpoints; i = i + 1)
- begin : wp_comb
-assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
- end
-endgenerate
-generate
- if (watchpoints > 0)
-assign wp_match = |wp_match_n;
- else
-assign wp_match = 1'b0;
-endgenerate
-
-
-
-assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
-assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
-assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-generate
- for (i = 0; i < breakpoints; i = i + 1)
- begin : bp_seq
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- bp_e[i] <= 1'b0;
- end
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
- begin
- bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
- bp_e[i] <= debug_csr_write_data[0];
- end
- end
-end
- end
-endgenerate
-
-
-generate
- for (i = 0; i < watchpoints; i = i + 1)
- begin : wp_seq
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- wp[i] <= { 32{1'bx}};
- wpc_c[i] <= 2'b00;
- end
- else
- begin
- if (debug_csr_write_enable == 1'b1)
- begin
- if (debug_csr == 5'h8)
- wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
- if (debug_csr == 5'h18 + i)
- wp[i] <= debug_csr_write_data;
- end
- end
-end
- end
-endgenerate
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- dc_re <= 1'b0;
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
- dc_re <= debug_csr_write_data[1];
- end
-end
-
-
-
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 3'b000;
- dc_ss <= 1'b0;
- end
- else
- begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
- begin
- dc_ss <= debug_csr_write_data[0];
- if (debug_csr_write_data[0] == 1'b0)
- state <= 3'b000;
- else
- state <= 3'b001;
- end
- case (state)
- 3'b001:
- begin
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- if ( ( (eret_q_x == 1'b1)
- || (bret_q_x == 1'b1)
- )
- && (stall_x == 1'b0)
- )
- state <= 3'b010;
- end
- 3'b010:
- begin
+
+
+
+
+
+
+
+
+
- if ((q_x == 1'b1) && (stall_x == 1'b0))
- state <= 3'b011;
- end
- 3'b011:
- begin
+
+
+
+
+
-
+
-
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- begin
- dc_ss <= 1'b0;
- state <= 3'b100;
- end
- end
- 3'b100:
- begin
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- state <= 3'b000;
- end
- endcase
- end
-end
-
-endmodule
-
@@ -73171,7 +73285,7 @@ endmodule
-module lm32_instruction_unit_medium_icache_debug (
+module lm32_instruction_unit_medium (
clk_i,
rst_i,
@@ -73196,9 +73310,8 @@ module lm32_instruction_unit_medium_icache_debug (
branch_mispredict_taken_m,
branch_target_m,
+
- iflush,
-
@@ -73222,12 +73335,11 @@ module lm32_instruction_unit_medium_icache_debug (
+
+
+
+
- jtag_read_enable,
- jtag_write_enable,
- jtag_write_data,
- jtag_address,
-
@@ -73237,12 +73349,11 @@ module lm32_instruction_unit_medium_icache_debug (
pc_m,
pc_w,
+
+
+
+
- icache_stall_request,
- icache_restart_request,
- icache_refill_request,
- icache_refilling,
-
@@ -73263,10 +73374,9 @@ module lm32_instruction_unit_medium_icache_debug (
+
+
- jtag_read_data,
- jtag_access_complete,
-
@@ -73312,7 +73422,7 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+input [ ((32-2)+2-1):2] branch_predict_address_d;
@@ -73322,12 +73432,11 @@ input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+input [ ((32-2)+2-1):2] branch_target_m;
+
-input iflush;
-
@@ -73353,40 +73462,38 @@ input i_rty_i;
+
+
+
+
-input jtag_read_enable;
-input jtag_write_enable;
-input [ 7:0] jtag_write_data;
-input [ (32-1):0] jtag_address;
-
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+output [ ((32-2)+2-1):2] pc_f;
+reg [ ((32-2)+2-1):2] pc_f;
+output [ ((32-2)+2-1):2] pc_d;
+reg [ ((32-2)+2-1):2] pc_d;
+output [ ((32-2)+2-1):2] pc_x;
+reg [ ((32-2)+2-1):2] pc_x;
+output [ ((32-2)+2-1):2] pc_m;
+reg [ ((32-2)+2-1):2] pc_m;
+output [ ((32-2)+2-1):2] pc_w;
+reg [ ((32-2)+2-1):2] pc_w;
+
+
+
+
+
+
+
+
-output icache_stall_request;
-wire icache_stall_request;
-output icache_restart_request;
-wire icache_restart_request;
-output icache_refill_request;
-wire icache_refill_request;
-output icache_refilling;
-wire icache_refilling;
-
@@ -73399,11 +73506,11 @@ wire icache_refilling;
output [ (32-1):0] i_dat_o;
+
-reg [ (32-1):0] i_dat_o;
-
-
+wire [ (32-1):0] i_dat_o;
+
output [ (32-1):0] i_adr_o;
reg [ (32-1):0] i_adr_o;
@@ -73411,21 +73518,21 @@ output i_cyc_o;
reg i_cyc_o;
output [ (4-1):0] i_sel_o;
+
-reg [ (4-1):0] i_sel_o;
-
-
+wire [ (4-1):0] i_sel_o;
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
+
-reg i_we_o;
-
-
+wire i_we_o;
+
output [ (3-1):0] i_cti_o;
reg [ (3-1):0] i_cti_o;
@@ -73437,12 +73544,11 @@ wire [ (2-1):0] i_bte_o;
+
+
+
+
-output [ 7:0] jtag_read_data;
-reg [ 7:0] jtag_read_data;
-output jtag_access_complete;
-wire jtag_access_complete;
-
@@ -73463,30 +73569,31 @@ reg [ (32-1):0] instruction_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
+reg [ ((32-2)+2-1):2] pc_a;
+
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
-
+
+
+
+
+
+
+
+
+
-wire icache_read_enable_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
-reg icache_refill_ready;
-reg [ (32-1):0] icache_refill_data;
-wire [ (32-1):0] icache_data_f;
-wire [ (3-1):0] first_cycle_type;
-wire [ (3-1):0] next_cycle_type;
-wire last_word;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
-
-
-
+
+
+reg [ (32-1):0] wb_data_f;
+
+
@@ -73506,9 +73613,8 @@ wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
+
-reg jtag_access;
-
@@ -73625,57 +73731,53 @@ endfunction
-
-lm32_icache_medium_icache_debug #(
- .associativity (associativity),
- .sets (sets),
- .bytes_per_line (bytes_per_line),
- .base_address (base_address),
- .limit (limit)
- ) icache (
+
+
+
+
+
+
+
- .clk_i (clk_i),
- .rst_i (rst_i),
- .stall_a (stall_a),
- .stall_f (stall_f),
- .branch_predict_taken_d (branch_predict_taken_d),
- .valid_d (valid_d),
- .address_a (pc_a),
- .address_f (pc_f),
- .read_enable_f (icache_read_enable_f),
- .refill_ready (icache_refill_ready),
- .refill_data (icache_refill_data),
- .iflush (iflush),
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- .stall_request (icache_stall_request),
- .restart_request (icache_restart_request),
- .refill_request (icache_refill_request),
- .refill_address (icache_refill_address),
- .refilling (icache_refilling),
- .inst (icache_data_f)
- );
-
-
-
-assign icache_read_enable_f = (valid_f == 1'b1)
- && (kill_f == 1'b0)
-
+
+
+
+
-
+
-
- ;
-
+
+
@@ -73703,11 +73805,10 @@ begin
pc_a = branch_predict_address_d;
else
+
+
+
- if (icache_restart_request == 1'b1)
- pc_a = restart_address;
- else
-
pc_a = pc_f + 1'b1;
end
@@ -73720,25 +73821,25 @@ end
-
-
+
+
-assign instruction_f = icache_data_f;
-
-
-
+
+
-
+assign instruction_f = wb_data_f;
+
+
@@ -73746,11 +73847,11 @@ assign instruction_f = icache_data_f;
-
-
-
-
+assign i_dat_o = 32'd0;
+assign i_we_o = 1'b0;
+assign i_sel_o = 4'b1111;
+
assign i_bte_o = 2'b00;
@@ -73759,32 +73860,31 @@ assign i_bte_o = 2'b00;
-generate
- case (bytes_per_line)
- 4:
- begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
-assign first_address = icache_refill_address;
- end
- 8:
- begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
-assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
- end
- 16:
- begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
-assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
- end
- endcase
-endgenerate
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -73797,10 +73897,10 @@ begin
if (rst_i == 1'b1)
begin
pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_d <= { (32-2){1'b0}};
+ pc_x <= { (32-2){1'b0}};
+ pc_m <= { (32-2){1'b0}};
+ pc_w <= { (32-2){1'b0}};
end
else
begin
@@ -73818,14 +73918,13 @@ end
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- else
- begin
-
+
+
+
+
+
@@ -73837,18 +73936,14 @@ begin
+
+
+
-
-
- if (icache_refill_request == 1'b1)
- restart_address <= icache_refill_address;
-
-
+
+
- end
-end
-
@@ -73867,138 +73962,125 @@ end
-
-assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
-always @(*)
-begin
- case (jtag_address[1:0])
- 2'b00: jtag_read_data = i_dat_i[ 31:24];
- 2'b01: jtag_read_data = i_dat_i[ 23:16];
- 2'b10: jtag_read_data = i_dat_i[ 15:8];
- 2'b11: jtag_read_data = i_dat_i[ 7:0];
- endcase
-end
+
+
+
+
+
+
+
+
-
-
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- icache_refill_data <= { 32{1'b0}};
- icache_refill_ready <= 1'b0;
-
-
-
+
+
- i_we_o <= 1'b0;
- i_sel_o <= 4'b1111;
- jtag_access <= 1'b0;
+
+
+
+
+
+
+
+
+
+
- end
- else
- begin
- icache_refill_ready <= 1'b0;
+
+
+
+
+
+
+
+
+
+
+
- if (i_cyc_o == 1'b1)
- begin
- if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
- begin
-
-
- if (jtag_access == 1'b1)
- begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_we_o <= 1'b0;
- jtag_access <= 1'b0;
- end
- else
+
+
+
+
+
+
+
+
+
+
- begin
- if (last_word == 1'b1)
- begin
+
+
+
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_lock_o <= 1'b0;
- end
+
+
+
- i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
- i_cti_o <= next_cycle_type;
- icache_refill_ready <= 1'b1;
- icache_refill_data <= i_dat_i;
- end
- end
-
+
+
+
+
+
+
+
+
-
- end
- else
- begin
- if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
- begin
-
-
-
- i_sel_o <= 4'b1111;
-
-
- i_adr_o <= {first_address, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
- i_cti_o <= first_cycle_type;
+
+
+
+
+
-
+
+
+
+
+
+
+
+
- end
-
-
- else
- begin
- if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
- begin
- case (jtag_address[1:0])
- 2'b00: i_sel_o <= 4'b1000;
- 2'b01: i_sel_o <= 4'b0100;
- 2'b10: i_sel_o <= 4'b0010;
- 2'b11: i_sel_o <= 4'b0001;
- endcase
- i_adr_o <= jtag_address;
- i_dat_o <= {4{jtag_write_data}};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
- i_we_o <= jtag_write_enable;
- i_cti_o <= 3'b111;
- jtag_access <= 1'b1;
- end
- end
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
+
@@ -74008,84 +74090,91 @@ begin
+
+
- end
- end
-end
-
-
-
-
-
-
-
-
-
-
-
+
+always @(posedge clk_i )
+begin
+ if (rst_i == 1'b1)
+ begin
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= { 32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ wb_data_f <= { 32{1'b0}};
+
-
-
-
-
-
+
+ end
+ else
+ begin
+ if (i_cyc_o == 1'b1)
+ begin
-
-
+ if((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ begin
-
-
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
-
-
-
+ wb_data_f <= i_dat_i;
+ end
+
-
-
-
+
+ end
+ else
+ begin
+ if ( (stall_a == 1'b0)
+
-
-
+
-
-
+ )
+ begin
-
+
-
-
-
-
-
-
-
-
-
+ i_adr_o <= {pc_a, 2'b00};
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+
+
+
+ end
+ else
+ begin
+ if ( (stall_a == 1'b0)
+
+
-
-
-
+ )
+ begin
+
-
-
-
-
-
+ end
+ end
+ end
+ end
+end
+
@@ -74466,523 +74555,443 @@ endmodule
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-
-
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-module lm32_jtag_medium_icache_debug (
- clk_i,
- rst_i,
- jtag_clk,
- jtag_update,
- jtag_reg_q,
- jtag_reg_addr_q,
-
-
- csr,
- csr_write_enable,
- csr_write_data,
- stall_x,
+
+
+
+
+
+
+
+
+
+
-
-
- jtag_read_data,
- jtag_access_complete,
+
+
-
-
- exception_q_w,
-
-
- jtx_csr_read_data,
- jrx_csr_read_data,
+
+
+
-
-
- jtag_csr_write_enable,
- jtag_csr_write_data,
- jtag_csr,
- jtag_read_enable,
- jtag_write_enable,
- jtag_write_data,
- jtag_address,
+
+
+
+
+
+
+
-
-
- jtag_break,
- jtag_reset,
+
+
- jtag_reg_d,
- jtag_reg_addr_d
- );
-
+
+
+
-input clk_i;
-input rst_i;
-input jtag_clk;
-input jtag_update;
-input [ 7:0] jtag_reg_q;
-input [2:0] jtag_reg_addr_q;
+
+
-
+
+
+
+
-input [ (5-1):0] csr;
-input csr_write_enable;
-input [ (32-1):0] csr_write_data;
-input stall_x;
+
+
+
+
-
-
-input [ 7:0] jtag_read_data;
-input jtag_access_complete;
+
+
-
-
-input exception_q_w;
+
-
-
-output [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jtx_csr_read_data;
-output [ (32-1):0] jrx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+
+
+
-
-
-output jtag_csr_write_enable;
-reg jtag_csr_write_enable;
-output [ (32-1):0] jtag_csr_write_data;
-wire [ (32-1):0] jtag_csr_write_data;
-output [ (5-1):0] jtag_csr;
-wire [ (5-1):0] jtag_csr;
-output jtag_read_enable;
-reg jtag_read_enable;
-output jtag_write_enable;
-reg jtag_write_enable;
-output [ 7:0] jtag_write_data;
-wire [ 7:0] jtag_write_data;
-output [ (32-1):0] jtag_address;
-wire [ (32-1):0] jtag_address;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-output jtag_break;
-reg jtag_break;
-output jtag_reset;
-reg jtag_reset;
+
+
+
+
-output [ 7:0] jtag_reg_d;
-reg [ 7:0] jtag_reg_d;
-output [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_d;
+
+
+
+
-reg rx_update;
-reg rx_update_r;
-reg rx_update_r_r;
-reg rx_update_r_r_r;
-
+
+
+
+
-wire [ 7:0] rx_byte;
-wire [2:0] rx_addr;
+
-
-reg [ 7:0] uart_tx_byte;
-reg uart_tx_valid;
-reg [ 7:0] uart_rx_byte;
-reg uart_rx_valid;
-
+
+
+
+
+
-reg [ 3:0] command;
-
-reg [ 7:0] jtag_byte_0;
-reg [ 7:0] jtag_byte_1;
-reg [ 7:0] jtag_byte_2;
-reg [ 7:0] jtag_byte_3;
-reg [ 7:0] jtag_byte_4;
-reg processing;
+
+
+
+
+
+
+
-reg [ 3:0] state;
-
+
-
-assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_csr = jtag_byte_4[ (5-1):0];
-assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_write_data = jtag_byte_4;
+
+
+
+
-
-
-assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
-
-
-
+
+
-
+
-assign jtag_reg_addr_d[2] = processing;
+
-
-
-assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
-assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
-
+
+
+
-assign rx_byte = jtag_reg_q;
-assign rx_addr = jtag_reg_addr_q;
-
+
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- rx_update <= 1'b0;
- rx_update_r <= 1'b0;
- rx_update_r_r <= 1'b0;
- rx_update_r_r_r <= 1'b0;
- end
- else
- begin
- rx_update <= jtag_update;
- rx_update_r <= rx_update;
- rx_update_r_r <= rx_update_r;
- rx_update_r_r_r <= rx_update_r_r;
- end
-end
+
-always @(posedge clk_i )
-begin
- if (rst_i == 1'b1)
- begin
- state <= 4'h0;
- command <= 4'b0000;
- jtag_reg_d <= 8'h00;
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- processing <= 1'b0;
- jtag_csr_write_enable <= 1'b0;
- jtag_read_enable <= 1'b0;
- jtag_write_enable <= 1'b0;
-
-
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
-
+
-
-
- uart_tx_byte <= 8'h00;
- uart_tx_valid <= 1'b0;
- uart_rx_byte <= 8'h00;
- uart_rx_valid <= 1'b0;
+
+
+
+
+
+
+
+
+
- end
- else
- begin
-
-
- if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
- begin
- case (csr)
- 5'he:
- begin
-
- uart_tx_byte <= csr_write_data[ 7:0];
- uart_tx_valid <= 1'b1;
- end
- 5'hf:
- begin
-
- uart_rx_valid <= 1'b0;
- end
- endcase
- end
+
+
-
+
+
+
+
+
+
+
+
+
+
- if (exception_q_w == 1'b1)
- begin
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
- end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- case (state)
- 4'h0:
- begin
+
+
+
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- command <= rx_byte[7:4];
- case (rx_addr)
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- 3'b000:
- begin
- case (rx_byte[7:4])
-
+
+
+
+
+
+
+
- 4'b0001:
- state <= 4'h1;
- 4'b0011:
- begin
- {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 4'h6;
- end
- 4'b0010:
- state <= 4'h1;
- 4'b0100:
- begin
- {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 5;
- end
- 4'b0101:
- state <= 4'h1;
-
+
- 4'b0110:
- begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+
- jtag_break <= 1'b1;
- end
- 4'b0111:
- begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+
+
+
+
+
+
+
+
+
+
- jtag_reset <= 1'b1;
- end
- endcase
- end
+
+
+
+
+
-
-
+
+
- 3'b001:
- begin
- uart_rx_byte <= rx_byte;
- uart_rx_valid <= 1'b1;
- end
- 3'b010:
- begin
- jtag_reg_d <= uart_tx_byte;
- uart_tx_valid <= 1'b0;
- end
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- default:
- ;
- endcase
- end
- end
- 4'h1:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_0 <= rx_byte;
- state <= 4'h2;
- end
- end
- 4'h2:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_1 <= rx_byte;
- state <= 4'h3;
- end
- end
- 4'h3:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_2 <= rx_byte;
- state <= 4'h4;
- end
- end
- 4'h4:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_3 <= rx_byte;
- if (command == 4'b0001)
- state <= 4'h6;
- else
- state <= 4'h5;
- end
- end
- 4'h5:
- begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
- begin
- jtag_byte_4 <= rx_byte;
- state <= 4'h6;
- end
- end
- 4'h6:
- begin
- case (command)
- 4'b0001,
- 4'b0011:
- begin
- jtag_read_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
- end
- 4'b0010,
- 4'b0100:
- begin
- jtag_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
- end
- 4'b0101:
- begin
- jtag_csr_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h8;
- end
- endcase
- end
- 4'h7:
- begin
- if (jtag_access_complete == 1'b1)
- begin
- jtag_read_enable <= 1'b0;
- jtag_reg_d <= jtag_read_data;
- jtag_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
- end
- end
- 4'h8:
- begin
- jtag_csr_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
- end
-
- endcase
- end
-end
-
-endmodule
-
@@ -75337,7 +75346,7 @@ endmodule
-module lm32_interrupt_medium_icache_debug (
+module lm32_interrupt_medium (
clk_i,
rst_i,
@@ -75346,18 +75355,17 @@ module lm32_interrupt_medium_icache_debug (
stall_x,
-
- non_debug_exception,
- debug_exception,
-
+
+ exception,
+
+
eret_q_x,
+
- bret_q_x,
-
csr,
csr_write_data,
@@ -75386,21 +75394,20 @@ input [interrupts-1:0] interrupt;
input stall_x;
+
+
-input non_debug_exception;
-input debug_exception;
-
-
+input exception;
+
input eret_q_x;
+
-input bret_q_x;
-
-input [ (5-1):0] csr;
+input [ (3-1):0] csr;
input [ (32-1):0] csr_write_data;
input csr_write_enable;
@@ -75427,9 +75434,8 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
+
-reg bie;
-
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -75449,11 +75455,11 @@ assign asserted = ip | interrupt;
assign ie_csr_read_data = {{ 32-3{1'b0}},
-
- bie,
-
+
+ 1'b0,
+
eie,
ie
@@ -75467,19 +75473,19 @@ generate
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
+ 3'h0: csr_read_data = {{ 32-3{1'b0}},
+
- bie,
-
-
+ 1'b0,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- 5'h1: csr_read_data = im;
+ 3'h2: csr_read_data = ip;
+ 3'h1: csr_read_data = im;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -75490,18 +75496,18 @@ end
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
+ 3'h0: csr_read_data = {{ 32-3{1'b0}},
+
- bie,
-
-
+ 1'b0,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
+ 3'h2: csr_read_data = ip;
default: csr_read_data = { 32{1'bx}};
endcase
end
@@ -75530,9 +75536,8 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
+
- bie <= 1'b0;
-
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -75544,21 +75549,13 @@ always @(posedge clk_i )
ip <= asserted;
-
- if (non_debug_exception == 1'b1)
- begin
+
+
- eie <= ie;
- ie <= 1'b0;
- end
- else if (debug_exception == 1'b1)
- begin
+
+
+
- bie <= ie;
- ie <= 1'b0;
- end
-
-
@@ -75566,6 +75563,14 @@ always @(posedge clk_i )
+ if (exception == 1'b1)
+ begin
+
+ eie <= ie;
+ ie <= 1'b0;
+ end
+
+
else if (stall_x == 1'b0)
begin
@@ -75583,28 +75588,26 @@ always @(posedge clk_i )
-
- else if (bret_q_x == 1'b1)
- ie <= bie;
-
+
+
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
+
- bie <= csr_write_data[2];
-
end
- if (csr == 5'h1)
+ if (csr == 3'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 5'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -75621,9 +75624,8 @@ always @(posedge clk_i )
ie <= 1'b0;
eie <= 1'b0;
+
- bie <= 1'b0;
-
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -75633,21 +75635,13 @@ always @(posedge clk_i )
ip <= asserted;
-
- if (non_debug_exception == 1'b1)
- begin
+
+
- eie <= ie;
- ie <= 1'b0;
- end
- else if (debug_exception == 1'b1)
- begin
+
+
+
- bie <= ie;
- ie <= 1'b0;
- end
-
-
@@ -75655,6 +75649,14 @@ always @(posedge clk_i )
+ if (exception == 1'b1)
+ begin
+
+ eie <= ie;
+ ie <= 1'b0;
+ end
+
+
else if (stall_x == 1'b0)
begin
@@ -75670,26 +75672,24 @@ always @(posedge clk_i )
end
-
- else if (bret_q_x == 1'b1)
- ie <= bie;
-
+
+
+
else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
+
- bie <= csr_write_data[2];
-
end
- if (csr == 5'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
diff --git a/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd b/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
index e5fc68a3..73b87ee9 100644
--- a/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
+++ b/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
@@ -635,7 +635,7 @@ end generate gen_profile_full_debug;
if I_CYC = '1' and inst_was_busy = '0' then
inst_addr := I_ADR;
if I_CTI = "010" then
- inst_length := dcache_burst_length;
+ inst_length := icache_burst_length;
else
inst_length := 1;
end if;
--
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