From 206ccd26e257150e17b99be80b55d33e1d8c5d24 Mon Sep 17 00:00:00 2001
From: Dimitris Lampridis <dimitris.lampridis@cern.ch>
Date: Wed, 21 Nov 2018 16:07:41 +0100
Subject: [PATCH] wb_crossbar: introfuce generic to control WB mode (classic,
pipelined) for SDB ROM WB interface
---
modules/wishbone/wb_crossbar/sdb_rom.vhd | 49 +++++++++++++------
.../wishbone/wb_crossbar/xwb_sdb_crossbar.vhd | 3 ++
modules/wishbone/wishbone_pkg.vhd | 11 +++--
3 files changed, 45 insertions(+), 18 deletions(-)
diff --git a/modules/wishbone/wb_crossbar/sdb_rom.vhd b/modules/wishbone/wb_crossbar/sdb_rom.vhd
index 383381ca..57cffb08 100644
--- a/modules/wishbone/wb_crossbar/sdb_rom.vhd
+++ b/modules/wishbone/wb_crossbar/sdb_rom.vhd
@@ -34,12 +34,14 @@ entity sdb_rom is
g_layout : t_sdb_record_array;
g_masters : natural;
g_bus_end : unsigned(63 downto 0);
- g_sdb_name : string := "WB4-Crossbar-GSI ");
+ g_wb_mode : t_wishbone_interface_mode := CLASSIC;
+ g_sdb_name : string := "WB4-Crossbar-GSI ");
port(
- clk_sys_i : in std_logic;
- master_i : in std_logic_vector(g_masters-1 downto 0);
- slave_i : in t_wishbone_slave_in;
- slave_o : out t_wishbone_slave_out);
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic := '1';
+ master_i : in std_logic_vector(g_masters-1 downto 0);
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out);
end sdb_rom;
architecture rtl of sdb_rom is
@@ -159,21 +161,40 @@ architecture rtl of sdb_rom is
signal r_flag : t_wishbone_data;
signal r_ack : std_logic;
+ signal slave_in : t_wishbone_slave_in;
+ signal slave_out : t_wishbone_slave_out;
+
begin
- slave_o.dat <= r_rom or r_flag;
- slave_o.ack <= r_ack;
- slave_o.err <= '0';
- slave_o.rty <= '0';
- slave_o.stall <= '0';
+ cmp_sdb_wb_adapter : wb_slave_adapter
+ generic map (
+ g_master_use_struct => TRUE,
+ g_master_mode => CLASSIC,
+ g_master_granularity => BYTE,
+ g_slave_use_struct => TRUE,
+ g_slave_mode => g_wb_mode,
+ g_slave_granularity => BYTE)
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ slave_i => slave_i,
+ slave_o => slave_o,
+ master_i => slave_out,
+ master_o => slave_in);
+
+ slave_out.dat <= r_rom or r_flag;
+ slave_out.ack <= r_ack;
+ slave_out.err <= '0';
+ slave_out.rty <= '0';
+ slave_out.stall <= '0';
- s_adr <= unsigned(slave_i.adr(c_rom_depth+c_rom_lowbits-1 downto c_rom_lowbits));
+ s_adr <= unsigned(slave_in.adr(c_rom_depth+c_rom_lowbits-1 downto c_rom_lowbits));
s_sel <= unsigned(f_msi_flag_index(master_i));
-
+
slave_clk : process(clk_sys_i)
begin
if (rising_edge(clk_sys_i)) then
- r_ack <= slave_i.cyc and slave_i.stb;
+ r_ack <= slave_in.cyc and slave_in.stb;
r_rom <= rom(to_integer(s_adr));
r_flag <= (others => '0');
if s_adr = s_sel and c_msi then
@@ -181,5 +202,5 @@ begin
end if;
end if;
end process;
-
+
end rtl;
diff --git a/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd b/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
index f35badc6..9c3b26bf 100644
--- a/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
+++ b/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
@@ -37,6 +37,7 @@ entity xwb_sdb_crossbar is
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address;
+ g_sdb_wb_mode : t_wishbone_interface_mode := CLASSIC;
g_sdb_name : string := "WB4-Crossbar-GSI ");
port(
clk_sys_i : in std_logic;
@@ -216,9 +217,11 @@ begin
g_layout => c_layout,
g_masters => g_num_masters,
g_bus_end => c_bus_last,
+ g_wb_mode => g_sdb_wb_mode,
g_sdb_name => g_sdb_name)
port map(
clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
master_i => sdb_sel,
slave_i => master_o_1(g_num_slaves),
slave_o => master_i_1(g_num_slaves));
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 094228ad..14cdb2aa 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -425,6 +425,7 @@ package wishbone_pkg is
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address;
+ g_sdb_wb_mode : t_wishbone_interface_mode := CLASSIC;
g_sdb_name : string := "WB4-Crossbar-GSI ");
port (
clk_sys_i : in std_logic;
@@ -482,12 +483,14 @@ package wishbone_pkg is
component sdb_rom is
generic(
- g_layout : t_sdb_record_array;
- g_masters : natural;
- g_bus_end : unsigned(63 downto 0);
- g_sdb_name : string := "WB4-Crossbar-GSI ");
+ g_layout : t_sdb_record_array;
+ g_masters : natural;
+ g_bus_end : unsigned(63 downto 0);
+ g_wb_mode : t_wishbone_interface_mode := CLASSIC;
+ g_sdb_name : string := "WB4-Crossbar-GSI ");
port(
clk_sys_i : in std_logic;
+ rst_n_i : in std_logic := '1';
master_i : in std_logic_vector(g_masters-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
--
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