From 1aa83ee26d451ad208c8f050fd6f3da7a366ddde Mon Sep 17 00:00:00 2001
From: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
Date: Wed, 2 Nov 2011 19:59:16 +0100
Subject: [PATCH] xwb_simple_uart: must tie ERR, RTY & INT lines to zero when
not used
---
modules/wishbone/wb_uart/xwb_simple_uart.vhd | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/modules/wishbone/wb_uart/xwb_simple_uart.vhd b/modules/wishbone/wb_uart/xwb_simple_uart.vhd
index 0c4da820..c66701fd 100644
--- a/modules/wishbone/wb_uart/xwb_simple_uart.vhd
+++ b/modules/wishbone/wb_uart/xwb_simple_uart.vhd
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
--- Last update: 2011-10-04
+-- Last update: 2011-11-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -101,4 +101,8 @@ begin -- rtl
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o);
+ slave_o.err <= '0';
+ slave_o.rty <= '0';
+ slave_o.int <='0';
+
end rtl;
--
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