diff --git a/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd b/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
index 1b7707b833a8ec9857361674e8c87d3d880201af..b0d93764ef2472460a11f624f0526ce4d7e8cd57 100644
--- a/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
+++ b/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
@@ -59,6 +59,12 @@ use ieee.numeric_std.all;
 use work.gencores_pkg.all;
 
 entity wb_i2c_bridge is
+  generic
+  (
+    -- FSM watchdog timeout, see Appendix A in the component documentation for
+    -- an example of setting this generic
+    g_fsm_wdt : positive
+  );
   port
   (
     -- Clock, reset
@@ -391,20 +397,10 @@ begin
   --============================================================================
   -- FSM watchdog timer
   --============================================================================
-  -- * in the case of writemregs command, a maximum of 35 bytes can be written
-  --     - 1 I2C address byte
-  --     - 2 register (Wishbone) address bytes
-  --     - 8*4 Wishbone register values
-  -- * we will therefore set the watchdog max. value to allow for 36 bytes to
-  -- be sent, considering a maximum clk_i frequency of 20 MHz (period = 50 ns)
-  -- and an SCL frequency of 100 kHz
-  -- * 100 us / 50 ns = 2000 clock cycles to send one byte
-  -- * 2000 * 36 bytes = 72000 clock cycles to send 36 bytes
-  -- * g_wdt_max = 72000
   cmp_watchdog : gc_fsm_watchdog
     generic map
     (
-      g_wdt_max => 72000
+      g_wdt_max => g_fsm_wdt
     )
     port map
     (
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index e919fce1075c66262cbb3dfd756ac8ad86b2e319..e8ed69ae2eb6472d88bbba6ba403bcbb0aac2c16 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -903,6 +903,12 @@ package wishbone_pkg is
   -- I2C to Wishbone bridge, following protocol defined with ELMA
   -----------------------------------------------------------------------------
   component wb_i2c_bridge is
+    generic
+    (
+      -- FSM watchdog timeout, see Appendix A in the component documentation for
+      -- an example of setting this generic
+      g_fsm_wdt : positive
+    );
     port
     (
       -- Clock, reset