From 10e213b5b915726d357fb6fc73ea9fb98b7bcc77 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Tue, 17 Jan 2012 00:17:15 +0100
Subject: [PATCH] modules/wb_vic: fixed port names to match the coding style
---
modules/wishbone/wb_vic/Manifest.py | 5 +-
modules/wishbone/wb_vic/wb_slave_vic.vhd | 441 +++++++++++++++++++++++
modules/wishbone/wb_vic/wb_vic.vhd | 93 +++--
modules/wishbone/wb_vic/xwb_vic.vhd | 89 +++++
4 files changed, 598 insertions(+), 30 deletions(-)
create mode 100644 modules/wishbone/wb_vic/wb_slave_vic.vhd
create mode 100644 modules/wishbone/wb_vic/xwb_vic.vhd
diff --git a/modules/wishbone/wb_vic/Manifest.py b/modules/wishbone/wb_vic/Manifest.py
index bc01174c..e28ab748 100644
--- a/modules/wishbone/wb_vic/Manifest.py
+++ b/modules/wishbone/wb_vic/Manifest.py
@@ -1,3 +1,4 @@
files = ["vic_prio_enc.vhd",
- "wb_slave_vic.wb",
- "wb_vic.vhd"]
\ No newline at end of file
+ "wb_slave_vic.vhd",
+ "wb_vic.vhd",
+ "xwb_vic.vhd"]
diff --git a/modules/wishbone/wb_vic/wb_slave_vic.vhd b/modules/wishbone/wb_vic/wb_slave_vic.vhd
new file mode 100644
index 00000000..7be5f796
--- /dev/null
+++ b/modules/wishbone/wb_vic/wb_slave_vic.vhd
@@ -0,0 +1,441 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for Vectored Interrupt Controller (VIC)
+---------------------------------------------------------------------------------------
+-- File : wb_slave_vic.vhd
+-- Author : auto-generated by wbgen2 from wb_slave_vic.wb
+-- Created : Fri Jan 13 11:31:39 2012
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_slave_vic.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+entity wb_slave_vic is
+ port (
+ rst_n_i : in std_logic;
+ wb_clk_i : in std_logic;
+ wb_addr_i : in std_logic_vector(5 downto 0);
+ wb_data_i : in std_logic_vector(31 downto 0);
+ wb_data_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+-- Port for BIT field: 'VIC Enable' in reg: 'VIC Control Register'
+ vic_ctl_enable_o : out std_logic;
+-- Port for BIT field: 'VIC output polarity' in reg: 'VIC Control Register'
+ vic_ctl_pol_o : out std_logic;
+-- Port for std_logic_vector field: 'Raw interrupt status' in reg: 'Raw Interrupt Status Register'
+ vic_risr_i : in std_logic_vector(31 downto 0);
+-- Ports for PASS_THROUGH field: 'Enable IRQ' in reg: 'Interrupt Enable Register'
+ vic_ier_o : out std_logic_vector(31 downto 0);
+ vic_ier_wr_o : out std_logic;
+-- Ports for PASS_THROUGH field: 'Disable IRQ' in reg: 'Interrupt Disable Register'
+ vic_idr_o : out std_logic_vector(31 downto 0);
+ vic_idr_wr_o : out std_logic;
+-- Port for std_logic_vector field: 'IRQ disabled/enabled' in reg: 'Interrupt Mask Register'
+ vic_imr_i : in std_logic_vector(31 downto 0);
+-- Port for std_logic_vector field: 'Vector Address' in reg: 'Vector Address Register'
+ vic_var_i : in std_logic_vector(31 downto 0);
+-- Ports for PASS_THROUGH field: 'SWI interrupt mask' in reg: 'Software Interrupt Register'
+ vic_swir_o : out std_logic_vector(31 downto 0);
+ vic_swir_wr_o : out std_logic;
+-- Ports for PASS_THROUGH field: 'End of Interrupt' in reg: 'End Of Interrupt Acknowledge Register'
+ vic_eoir_o : out std_logic_vector(31 downto 0);
+ vic_eoir_wr_o : out std_logic;
+-- Ports for RAM: Interrupt Vector Table
+ vic_ivt_ram_addr_i : in std_logic_vector(4 downto 0);
+-- Read data output
+ vic_ivt_ram_data_o : out std_logic_vector(31 downto 0);
+-- Read strobe input (active high)
+ vic_ivt_ram_rd_i : in std_logic
+ );
+end wb_slave_vic;
+
+architecture syn of wb_slave_vic is
+
+signal vic_ctl_enable_int : std_logic ;
+signal vic_ctl_pol_int : std_logic ;
+signal vic_ivt_ram_rddata_int : std_logic_vector(31 downto 0);
+signal vic_ivt_ram_rd_int : std_logic ;
+signal vic_ivt_ram_wr_int : std_logic ;
+signal ack_sreg : std_logic_vector(9 downto 0);
+signal rddata_reg : std_logic_vector(31 downto 0);
+signal wrdata_reg : std_logic_vector(31 downto 0);
+signal bwsel_reg : std_logic_vector(3 downto 0);
+signal rwaddr_reg : std_logic_vector(5 downto 0);
+signal ack_in_progress : std_logic ;
+signal wr_int : std_logic ;
+signal rd_int : std_logic ;
+signal bus_clock_int : std_logic ;
+signal allones : std_logic_vector(31 downto 0);
+signal allzeros : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+ wrdata_reg <= wb_data_i;
+ bwsel_reg <= wb_sel_i;
+ bus_clock_int <= wb_clk_i;
+ rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+ wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+ allones <= (others => '1');
+ allzeros <= (others => '0');
+--
+-- Main register bank access process.
+ process (bus_clock_int, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ ack_sreg <= "0000000000";
+ ack_in_progress <= '0';
+ rddata_reg <= "00000000000000000000000000000000";
+ vic_ctl_enable_int <= '0';
+ vic_ctl_pol_int <= '0';
+ vic_ier_wr_o <= '0';
+ vic_idr_wr_o <= '0';
+ vic_swir_wr_o <= '0';
+ vic_eoir_wr_o <= '0';
+ elsif rising_edge(bus_clock_int) then
+-- advance the ACK generator shift register
+ ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+ ack_sreg(9) <= '0';
+ if (ack_in_progress = '1') then
+ if (ack_sreg(0) = '1') then
+ vic_ier_wr_o <= '0';
+ vic_idr_wr_o <= '0';
+ vic_swir_wr_o <= '0';
+ vic_eoir_wr_o <= '0';
+ ack_in_progress <= '0';
+ else
+ vic_ier_wr_o <= '0';
+ vic_idr_wr_o <= '0';
+ vic_swir_wr_o <= '0';
+ vic_eoir_wr_o <= '0';
+ end if;
+ else
+ if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+ case rwaddr_reg(5) is
+ when '0' =>
+ case rwaddr_reg(2 downto 0) is
+ when "000" =>
+ if (wb_we_i = '1') then
+ rddata_reg(0) <= 'X';
+ vic_ctl_enable_int <= wrdata_reg(0);
+ rddata_reg(1) <= 'X';
+ vic_ctl_pol_int <= wrdata_reg(1);
+ else
+ rddata_reg(0) <= vic_ctl_enable_int;
+ rddata_reg(1) <= vic_ctl_pol_int;
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "001" =>
+ if (wb_we_i = '1') then
+ else
+ rddata_reg(31 downto 0) <= vic_risr_i;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "010" =>
+ if (wb_we_i = '1') then
+ vic_ier_wr_o <= '1';
+ else
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "011" =>
+ if (wb_we_i = '1') then
+ vic_idr_wr_o <= '1';
+ else
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "100" =>
+ if (wb_we_i = '1') then
+ else
+ rddata_reg(31 downto 0) <= vic_imr_i;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "101" =>
+ if (wb_we_i = '1') then
+ else
+ rddata_reg(31 downto 0) <= vic_var_i;
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "110" =>
+ if (wb_we_i = '1') then
+ vic_swir_wr_o <= '1';
+ else
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "111" =>
+ if (wb_we_i = '1') then
+ vic_eoir_wr_o <= '1';
+ else
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ end if;
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when others =>
+-- prevent the slave from hanging the bus on invalid address
+ ack_in_progress <= '1';
+ ack_sreg(0) <= '1';
+ end case;
+ when '1' =>
+ if (rd_int = '1') then
+ ack_sreg(0) <= '1';
+ else
+ ack_sreg(0) <= '1';
+ end if;
+ ack_in_progress <= '1';
+ when others =>
+-- prevent the slave from hanging the bus on invalid address
+ ack_in_progress <= '1';
+ ack_sreg(0) <= '1';
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+-- Data output multiplexer process
+ process (rddata_reg, rwaddr_reg, vic_ivt_ram_rddata_int, wb_addr_i )
+ begin
+ case rwaddr_reg(5) is
+ when '1' =>
+ wb_data_o(31 downto 0) <= vic_ivt_ram_rddata_int;
+ when others =>
+ wb_data_o <= rddata_reg;
+ end case;
+ end process;
+
+
+-- Read & write lines decoder for RAMs
+ process (wb_addr_i, rd_int, wr_int )
+ begin
+ if (wb_addr_i(5) = '1') then
+ vic_ivt_ram_rd_int <= rd_int;
+ vic_ivt_ram_wr_int <= wr_int;
+ else
+ vic_ivt_ram_wr_int <= '0';
+ vic_ivt_ram_rd_int <= '0';
+ end if;
+ end process;
+
+
+-- VIC Enable
+ vic_ctl_enable_o <= vic_ctl_enable_int;
+-- VIC output polarity
+ vic_ctl_pol_o <= vic_ctl_pol_int;
+-- Raw interrupt status
+-- Enable IRQ
+-- pass-through field: Enable IRQ in register: Interrupt Enable Register
+ vic_ier_o <= wrdata_reg(31 downto 0);
+-- Disable IRQ
+-- pass-through field: Disable IRQ in register: Interrupt Disable Register
+ vic_idr_o <= wrdata_reg(31 downto 0);
+-- IRQ disabled/enabled
+-- Vector Address
+-- SWI interrupt mask
+-- pass-through field: SWI interrupt mask in register: Software Interrupt Register
+ vic_swir_o <= wrdata_reg(31 downto 0);
+-- End of Interrupt
+-- pass-through field: End of Interrupt in register: End Of Interrupt Acknowledge Register
+ vic_eoir_o <= wrdata_reg(31 downto 0);
+-- extra code for reg/fifo/mem: Interrupt Vector Table
+-- RAM block instantiation for memory: Interrupt Vector Table
+ vic_ivt_ram_raminst : wbgen2_dpssram
+ generic map (
+ g_data_width => 32,
+ g_size => 32,
+ g_addr_width => 5,
+ g_dual_clock => false,
+ g_use_bwsel => false
+ )
+ port map (
+ clk_a_i => bus_clock_int,
+ clk_b_i => bus_clock_int,
+ addr_b_i => vic_ivt_ram_addr_i,
+ addr_a_i => rwaddr_reg(4 downto 0),
+ data_b_o => vic_ivt_ram_data_o,
+ rd_b_i => vic_ivt_ram_rd_i,
+ bwsel_b_i => allones(3 downto 0),
+ data_b_i => allzeros(31 downto 0),
+ wr_b_i => allzeros(0),
+ data_a_o => vic_ivt_ram_rddata_int(31 downto 0),
+ rd_a_i => vic_ivt_ram_rd_int,
+ data_a_i => wrdata_reg(31 downto 0),
+ wr_a_i => vic_ivt_ram_wr_int,
+ bwsel_a_i => allones(3 downto 0)
+ );
+
+ rwaddr_reg <= wb_addr_i;
+-- ACK signal generation. Just pass the LSB of ACK counter.
+ wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/modules/wishbone/wb_vic/wb_vic.vhd b/modules/wishbone/wb_vic/wb_vic.vhd
index 8cd51963..ec02c3ed 100644
--- a/modules/wishbone/wb_vic/wb_vic.vhd
+++ b/modules/wishbone/wb_vic/wb_vic.vhd
@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
--- Last update: 2010-07-29
+-- Last update: 2012-01-13
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -38,25 +38,29 @@ use work.wishbone_pkg.all;
entity wb_vic is
generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+
g_num_interrupts : natural := 32 -- number of IRQ inputs.
);
port (
+ clk_sys_i : in std_logic; -- wishbone clock
rst_n_i : in std_logic; -- reset
- wb_clk_i : in std_logic; -- wishbone clock
- wb_addr_i : in std_logic_vector(5 downto 0);
- wb_data_i : in std_logic_vector(31 downto 0);
- wb_data_o : out std_logic_vector(31 downto 0);
- wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
- wb_stb_i : in std_logic;
- wb_we_i : in std_logic;
- wb_ack_o : out std_logic;
+ wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
+ wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0); -- IRQ inputs
- irq_master_o : out std_logic -- master IRQ output (multiplexed line,
- -- to the CPU)
+ irq_master_o : out std_logic -- master IRQ output (multiplexed line, to the CPU)
+
);
end wb_vic;
@@ -128,6 +132,10 @@ architecture syn of wb_vic is
signal current_irq : std_logic_vector(4 downto 0);
signal irq_id_encoded : std_logic_vector(4 downto 0);
signal state : t_state;
+
+ signal wb_in : t_wishbone_slave_in;
+ signal wb_out : t_wishbone_slave_out;
+
begin -- syn
@@ -136,9 +144,9 @@ begin -- syn
end generate check1;
- register_irq_lines : process(wb_clk_i, rst_n_i)
+ register_irq_lines : process(clk_sys_i, rst_n_i)
begin
- if rising_edge(wb_clk_i) then
+ if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
irqs_i_reg <= (others => '0');
else
@@ -160,18 +168,47 @@ begin -- syn
vic_ivt_ram_addr <= current_irq;
- wb_controller : wb_slave_vic
+ U_Slave_adapter: wb_slave_adapter
+ generic map (
+ g_master_use_struct => true,
+ g_master_mode => CLASSIC,
+ g_master_granularity => WORD,
+ g_slave_use_struct => false,
+ g_slave_mode => g_interface_mode,
+ g_slave_granularity => g_address_granularity)
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ sl_adr_i => wb_adr_i,
+ sl_dat_i => wb_dat_i,
+ sl_sel_i => wb_sel_i,
+ sl_cyc_i => wb_cyc_i,
+ sl_stb_i => wb_stb_i,
+ sl_we_i => wb_we_i,
+ sl_dat_o => wb_dat_o,
+ sl_ack_o => wb_ack_o,
+ sl_stall_o => wb_stall_o,
+ master_i => wb_out,
+ master_o => wb_in);
+
+ wb_out.stall <= '0';
+ wb_out.rty <= '0';
+ wb_out.err <= '0';
+ wb_out.int <= '0';
+
+
+ U_wb_controller : wb_slave_vic
port map (
rst_n_i => rst_n_i,
- wb_clk_i => wb_clk_i,
- wb_addr_i => wb_addr_i,
- wb_data_i => wb_data_i,
- wb_data_o => wb_data_o,
- wb_cyc_i => wb_cyc_i,
- wb_sel_i => wb_sel_i,
- wb_stb_i => wb_stb_i,
- wb_we_i => wb_we_i,
- wb_ack_o => wb_ack_o,
+ wb_clk_i => clk_sys_i,
+ wb_addr_i => wb_in.adr(5 downto 0),
+ wb_data_i => wb_in.dat,
+ wb_data_o => wb_out.dat,
+ wb_cyc_i => wb_in.cyc,
+ wb_sel_i => wb_in.sel,
+ wb_stb_i => wb_in.stb,
+ wb_we_i => wb_in.we,
+ wb_ack_o => wb_out.ack,
vic_ctl_enable_o => vic_ctl_enable,
vic_ctl_pol_o => vic_ctl_pol,
@@ -190,9 +227,9 @@ begin -- syn
vic_ivt_ram_data_o => vic_ivt_ram_data,
vic_ivt_ram_rd_i => vic_ivt_ram_rd);
- process (wb_clk_i, rst_n_i)
+ process (clk_sys_i, rst_n_i)
begin -- process enable_disable_irqs
- if rising_edge(wb_clk_i) then
+ if rising_edge(clk_sys_i) then
if rst_n_i = '0' then -- asynchronous reset (active low)
vic_imr <= (others => '0');
@@ -218,9 +255,9 @@ begin -- syn
end if;
end process;
- vic_fsm : process (wb_clk_i, rst_n_i)
+ vic_fsm : process (clk_sys_i, rst_n_i)
begin -- process vic_fsm
- if rising_edge(wb_clk_i) then
+ if rising_edge(clk_sys_i) then
if rst_n_i = '0' then -- asynchronous reset (active low)
state <= WAIT_IRQ;
diff --git a/modules/wishbone/wb_vic/xwb_vic.vhd b/modules/wishbone/wb_vic/xwb_vic.vhd
new file mode 100644
index 00000000..7a451ba9
--- /dev/null
+++ b/modules/wishbone/wb_vic/xwb_vic.vhd
@@ -0,0 +1,89 @@
+------------------------------------------------------------------------------
+-- Title : Wishbone Vectored Interrupt Controller
+-- Project : White Rabbit Switch
+------------------------------------------------------------------------------
+-- Author : Tomasz Wlostowski
+-- Company : CERN BE-Co-HT
+-- Created : 2010-05-18
+-- Last update: 2012-01-13
+-- Platform : FPGA-generic
+-- Standard : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: Simple interrupt controller/multiplexer:
+-- - designed to cooperate with wbgen2 peripherals Embedded Interrupt
+-- Controllers (EICs)
+-- - accepts 2 to 32 inputs (configurable using g_num_interrupts)
+-- - inputs are high-level sensitive
+-- - inputs have fixed priorities. Input 0 has the highest priority, Input
+-- g_num_interrupts-1 has the lowest priority.
+-- - output interrupt line (to the CPU) is active low or high depending on
+-- a configuration bit.
+-- - interrupt is acknowledged by writing to EIC_EOIR register.
+-- - register layout: see wb_vic.wb for details.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Tomasz Wlostowski
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-05-18 1.0 twlostow Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+
+entity xwb_vic is
+
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+
+ g_num_interrupts : natural := 32 -- number of IRQ inputs.
+ );
+
+ port (
+ clk_sys_i : in std_logic; -- wishbone clock
+ rst_n_i : in std_logic; -- reset
+
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+
+ irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0); -- IRQ inputs
+ irq_master_o : out std_logic -- master IRQ output (multiplexed line, to the CPU)
+
+ );
+
+end xwb_vic;
+
+architecture wrapper of xwb_vic is
+
+begin -- wrapper
+
+ U_Wrapped_VIC : wb_vic
+ generic map (
+ g_interface_mode => g_interface_mode,
+ g_address_granularity => g_address_granularity,
+ g_num_interrupts => g_num_interrupts)
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ wb_adr_i => slave_i.adr,
+ wb_dat_i => slave_i.dat,
+ wb_dat_o => slave_o.dat,
+ wb_cyc_i => slave_i.Cyc,
+ wb_sel_i => slave_i.sel,
+ wb_stb_i => slave_i.stb,
+ wb_we_i => slave_i.we,
+ wb_ack_o => slave_o.ack,
+ wb_stall_o => slave_o.stall,
+ irqs_i => irqs_i,
+ irq_master_o => irq_master_o);
+
+ slave_o.err <= '0';
+ slave_o.rty <= '0';
+ slave_o.int <= '0';
+
+end wrapper;
--
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