From 0383f5fcfdad50efabb464dd5d51b3a6e03351c3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Thu, 14 Aug 2014 10:29:39 +0200
Subject: [PATCH] common/gc_sync_ffs: prevent synthesizer from optimizing sync
 chain flip-flops

---
 modules/common/gc_sync_ffs.vhd | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/modules/common/gc_sync_ffs.vhd b/modules/common/gc_sync_ffs.vhd
index 2dfa447c..2816586d 100644
--- a/modules/common/gc_sync_ffs.vhd
+++ b/modules/common/gc_sync_ffs.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-06-14
--- Last update: 2011-04-29
+-- Last update: 2014-07-31
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
@@ -63,6 +63,11 @@ architecture behavioral of gc_sync_ffs is
   attribute shreg_extract of sync0  : signal is "no";
   attribute shreg_extract of sync1  : signal is "no";
   attribute shreg_extract of sync2  : signal is "no";
+
+  attribute keep : string;
+  attribute keep of sync0  : signal is "true";
+  attribute keep of sync1  : signal is "true";
+
 begin
 
 
-- 
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