From 0245f2b713d9121acdceb55353812e65f07fde7e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Fri, 14 Dec 2018 00:40:44 +0100
Subject: [PATCH] xwb_axi4_bridge: conform (hopefully more) to the AXI4
specification
---
.../wishbone/wb_axi4lite_bridge/axi4_pkg.vhd | 7 ++++--
.../wb_axi4lite_bridge/wb_axi4lite_bridge.vhd | 1 +
.../xwb_axi4lite_bridge.vhd | 24 ++++++++++++-------
3 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
index 31b8d358..024edd1c 100644
--- a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
@@ -46,10 +46,10 @@ package axi4_pkg is
AWID : std_logic_vector (11 downto 0);
WID : std_logic_vector (11 downto 0);
ARBURST : std_logic_vector (1 downto 0);
- ARLOCK : std_logic_vector (1 downto 0);
+ ARLOCK : std_logic;
ARSIZE : std_logic_vector (2 downto 0);
AWBURST : std_logic_vector (1 downto 0);
- AWLOCK : std_logic_vector (1 downto 0);
+ AWLOCK : std_logic;
AWSIZE : std_logic_vector (2 downto 0);
ARPROT : std_logic_vector (2 downto 0);
AWPROT : std_logic_vector (2 downto 0);
@@ -145,6 +145,9 @@ package axi4_pkg is
constant c_AXI4_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
constant c_AXI4_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
+ constant c_AXI4_LOCK_NORMAL : std_logic := '0';
+ constant c_AXI4_LOCK_EXCLUSIVE : std_logic:= '1';
+
function f_axi4_full_to_lite (
f : t_axi4_full_master_out_32
) return t_axi4_lite_master_out_32;
diff --git a/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
index adfe1b4b..43b685f8 100644
--- a/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
@@ -94,6 +94,7 @@ begin
axi_in.AWADDR <= AWADDR;
axi_in.WDATA <= WDATA;
axi_in.WSTRB <= WSTRB;
+
ARREADY <= axi_out.ARREADY;
AWREADY <= axi_out.AWREADY;
BVALID <= axi_out.BVALID;
diff --git a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
index 4f94d8ac..95e456e0 100644
--- a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -118,7 +118,7 @@ begin
wb_master_o.stb <= '0';
if(wb_master_i.ack = '1') then
state <= IDLE;
- axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+ axi4_slave_o.RRESP <= c_AXI4_RESP_OKAY;
axi4_slave_o.RDATA <= wb_master_i.dat;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
@@ -135,7 +135,8 @@ begin
wb_master_o.stb <= '0';
if(wb_master_i.ack = '1') then
state <= RESPONSE_WRITE;
- axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+ axi4_slave_o.BVALID <= '1';
+ axi4_slave_o.BRESP <= c_AXI4_RESP_OKAY;
wb_master_o.cyc <= '0';
else
state <= WAIT_ACK_WRITE;
@@ -147,25 +148,27 @@ begin
when WAIT_ACK_WRITE =>
if(wb_master_i.ack = '1') then
state <= RESPONSE_WRITE;
- axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+ axi4_slave_o.BRESP <= c_AXI4_RESP_OKAY;
+ axi4_slave_o.BVALID <= '1';
wb_master_o.cyc <= '0';
elsif count = c_timeout then
state <= RESPONSE_WRITE;
axi4_slave_o.BRESP <= c_AXI4_RESP_SLVERR;
+ axi4_slave_o.BVALID <= '1';
wb_master_o.cyc <= '0';
end if;
count <= count + 1;
when WAIT_ACK_READ =>
if(wb_master_i.ack = '1') then
- state <= IDLE;
- axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+ state <= RESPONSE_READ;
+ axi4_slave_o.RRESP <= c_AXI4_RESP_OKAY;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
axi4_slave_o.RDATA <= wb_master_i.dat;
wb_master_o.cyc <= '0';
elsif count = c_timeout then
- state <= IDLE;
+ state <= RESPONSE_READ;
axi4_slave_o.RRESP <= c_AXI4_RESP_SLVERR;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
@@ -177,11 +180,16 @@ begin
when RESPONSE_WRITE =>
if (axi4_slave_i.BREADY = '1') then
- axi4_slave_o.BVALID <= '1';
+ axi4_slave_o.BVALID <= '0';
state <= IDLE;
end if;
- when RESPONSE_READ => null;
+ when RESPONSE_READ =>
+ if (axi4_slave_I.RREADY = '1') then
+ axi4_slave_o.RVALID <= '0';
+ state <= IDLE;
+ end if;
+
end case;
--
GitLab