From 0053bd47157f56a3715bcde6b3d05ba8e99d1ef3 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tristan.gingold@cern.ch>
Date: Thu, 26 Mar 2020 15:09:21 +0100
Subject: [PATCH] modules/genrams: more cleanup (for unused signals).
---
modules/genrams/common/inferred_sync_fifo.vhd | 14 +++++++-------
modules/genrams/xilinx/generic_dpram_dualclock.vhd | 11 +++--------
2 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/modules/genrams/common/inferred_sync_fifo.vhd b/modules/genrams/common/inferred_sync_fifo.vhd
index 45c59f70..b4bcf4c1 100644
--- a/modules/genrams/common/inferred_sync_fifo.vhd
+++ b/modules/genrams/common/inferred_sync_fifo.vhd
@@ -72,13 +72,13 @@ end inferred_sync_fifo;
architecture syn of inferred_sync_fifo is
- constant c_pointer_width : integer := f_log2_size(g_size);
- signal rd_ptr, wr_ptr, wr_ptr_d0, rd_ptr_muxed : unsigned(c_pointer_width-1 downto 0);
- signal usedw : unsigned(c_pointer_width downto 0);
- signal full, empty : std_logic;
- signal q_int : std_logic_vector(g_data_width-1 downto 0);
- signal we_int, rd_int : std_logic;
- signal guard_bit : std_logic;
+ constant c_pointer_width : integer := f_log2_size(g_size);
+ signal rd_ptr, wr_ptr, rd_ptr_muxed : unsigned(c_pointer_width-1 downto 0);
+ signal usedw : unsigned(c_pointer_width downto 0);
+ signal full, empty : std_logic;
+
+ signal we_int, rd_int : std_logic;
+ signal guard_bit : std_logic;
signal q_comb : std_logic_vector(g_data_width-1 downto 0);
diff --git a/modules/genrams/xilinx/generic_dpram_dualclock.vhd b/modules/genrams/xilinx/generic_dpram_dualclock.vhd
index c7e7d40a..3cf18370 100644
--- a/modules/genrams/xilinx/generic_dpram_dualclock.vhd
+++ b/modules/genrams/xilinx/generic_dpram_dualclock.vhd
@@ -118,17 +118,12 @@ architecture syn of generic_dpram_dualclock is
return false;
-- synthesis translate_on
return true;
- end f_is_synthesis;
+ end f_is_synthesis;
shared variable ram : t_ram_type := f_file_to_ramtype;
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
- signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
- signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
-
- signal clka_int : std_logic;
- signal clkb_int : std_logic;
signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
@@ -177,7 +172,7 @@ begin
end loop;
end if;
end process;
-
+
@@ -266,6 +261,6 @@ begin
end if;
end process;
end generate gen_without_byte_enable_nochange;
-
+
end syn;
--
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