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-- Title          : Wishbone slave core for Simple Wishbone UART
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-- File           : simple_uart_wb.vhd
-- Author         : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created        : Tue Aug 25 17:17:50 2020
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.uart_wbgen2_pkg.all;


entity simple_uart_wb is
port (
  rst_n_i                                  : in     std_logic;
  clk_sys_i                                : in     std_logic;
  wb_adr_i                                 : in     std_logic_vector(2 downto 0);
  wb_dat_i                                 : in     std_logic_vector(31 downto 0);
  wb_dat_o                                 : out    std_logic_vector(31 downto 0);
  wb_cyc_i                                 : in     std_logic;
  wb_sel_i                                 : in     std_logic_vector(3 downto 0);
  wb_stb_i                                 : in     std_logic;
  wb_we_i                                  : in     std_logic;
  wb_ack_o                                 : out    std_logic;
  wb_err_o                                 : out    std_logic;
  wb_rty_o                                 : out    std_logic;
  wb_stall_o                               : out    std_logic;
  rdr_rack_o                               : out    std_logic;
  host_rack_o                              : out    std_logic;
  regs_i                                   : in     t_uart_in_registers;
  regs_o                                   : out    t_uart_out_registers
);
end simple_uart_wb;

architecture syn of simple_uart_wb is

signal uart_cr_rx_fifo_purge_dly0               : std_logic      ;
signal uart_cr_rx_fifo_purge_int                : std_logic      ;
signal uart_cr_tx_fifo_purge_dly0               : std_logic      ;
signal uart_cr_tx_fifo_purge_int                : std_logic      ;
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(2 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
-- 
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
  if (rst_n_i = '0') then 
    ack_sreg <= "0000000000";
    ack_in_progress <= '0';
    rddata_reg <= "00000000000000000000000000000000";
    regs_o.sr_rx_fifo_overflow_load_o <= '0';
    regs_o.bcr_wr_o <= '0';
    regs_o.tdr_tx_data_wr_o <= '0';
    rdr_rack_o <= '0';
    regs_o.host_tdr_data_wr_o <= '0';
    host_rack_o <= '0';
    uart_cr_rx_fifo_purge_int <= '0';
    uart_cr_tx_fifo_purge_int <= '0';
  elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
    ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
    ack_sreg(9) <= '0';
    if (ack_in_progress = '1') then
      if (ack_sreg(0) = '1') then
        regs_o.sr_rx_fifo_overflow_load_o <= '0';
        regs_o.bcr_wr_o <= '0';
        regs_o.tdr_tx_data_wr_o <= '0';
        rdr_rack_o <= '0';
        regs_o.host_tdr_data_wr_o <= '0';
        host_rack_o <= '0';
        uart_cr_rx_fifo_purge_int <= '0';
        uart_cr_tx_fifo_purge_int <= '0';
        ack_in_progress <= '0';
      else
        regs_o.sr_rx_fifo_overflow_load_o <= '0';
        regs_o.bcr_wr_o <= '0';
        regs_o.tdr_tx_data_wr_o <= '0';
        regs_o.host_tdr_data_wr_o <= '0';
      end if;
    else
      if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
        case rwaddr_reg(2 downto 0) is
        when "000" => 
          if (wb_we_i = '1') then
            regs_o.sr_rx_fifo_overflow_load_o <= '1';
          end if;
          rddata_reg(0) <= regs_i.sr_tx_busy_i;
          rddata_reg(1) <= regs_i.sr_rx_rdy_i;
          rddata_reg(2) <= regs_i.sr_rx_fifo_supported_i;
          rddata_reg(3) <= regs_i.sr_tx_fifo_supported_i;
          rddata_reg(4) <= regs_i.sr_rx_fifo_valid_i;
          rddata_reg(5) <= regs_i.sr_tx_fifo_empty_i;
          rddata_reg(6) <= regs_i.sr_tx_fifo_full_i;
          rddata_reg(7) <= regs_i.sr_rx_fifo_overflow_i;
          rddata_reg(15 downto 8) <= regs_i.sr_rx_fifo_bytes_i;
          rddata_reg(16) <= 'X';
          rddata_reg(17) <= 'X';
          rddata_reg(18) <= 'X';
          rddata_reg(19) <= 'X';
          rddata_reg(20) <= 'X';
          rddata_reg(21) <= 'X';
          rddata_reg(22) <= 'X';
          rddata_reg(23) <= 'X';
          rddata_reg(24) <= 'X';
          rddata_reg(25) <= 'X';
          rddata_reg(26) <= 'X';
          rddata_reg(27) <= 'X';
          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "001" => 
          if (wb_we_i = '1') then
            regs_o.bcr_wr_o <= '1';
          end if;
          rddata_reg(0) <= 'X';
          rddata_reg(1) <= 'X';
          rddata_reg(2) <= 'X';
          rddata_reg(3) <= 'X';
          rddata_reg(4) <= 'X';
          rddata_reg(5) <= 'X';
          rddata_reg(6) <= 'X';
          rddata_reg(7) <= 'X';
          rddata_reg(8) <= 'X';
          rddata_reg(9) <= 'X';
          rddata_reg(10) <= 'X';
          rddata_reg(11) <= 'X';
          rddata_reg(12) <= 'X';
          rddata_reg(13) <= 'X';
          rddata_reg(14) <= 'X';
          rddata_reg(15) <= 'X';
          rddata_reg(16) <= 'X';
          rddata_reg(17) <= 'X';
          rddata_reg(18) <= 'X';
          rddata_reg(19) <= 'X';
          rddata_reg(20) <= 'X';
          rddata_reg(21) <= 'X';
          rddata_reg(22) <= 'X';
          rddata_reg(23) <= 'X';
          rddata_reg(24) <= 'X';
          rddata_reg(25) <= 'X';
          rddata_reg(26) <= 'X';
          rddata_reg(27) <= 'X';
          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "010" => 
          if (wb_we_i = '1') then
            regs_o.tdr_tx_data_wr_o <= '1';
          end if;
          rddata_reg(0) <= 'X';
          rddata_reg(1) <= 'X';
          rddata_reg(2) <= 'X';
          rddata_reg(3) <= 'X';
          rddata_reg(4) <= 'X';
          rddata_reg(5) <= 'X';
          rddata_reg(6) <= 'X';
          rddata_reg(7) <= 'X';
          rddata_reg(8) <= 'X';
          rddata_reg(9) <= 'X';
          rddata_reg(10) <= 'X';
          rddata_reg(11) <= 'X';
          rddata_reg(12) <= 'X';
          rddata_reg(13) <= 'X';
          rddata_reg(14) <= 'X';
          rddata_reg(15) <= 'X';
          rddata_reg(16) <= 'X';
          rddata_reg(17) <= 'X';
          rddata_reg(18) <= 'X';
          rddata_reg(19) <= 'X';
          rddata_reg(20) <= 'X';
          rddata_reg(21) <= 'X';
          rddata_reg(22) <= 'X';
          rddata_reg(23) <= 'X';
          rddata_reg(24) <= 'X';
          rddata_reg(25) <= 'X';
          rddata_reg(26) <= 'X';
          rddata_reg(27) <= 'X';
          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "011" => 
          if (wb_we_i = '1') then
          end if;
          rddata_reg(7 downto 0) <= regs_i.rdr_rx_data_i;
          rdr_rack_o <= '1';
          rddata_reg(8) <= 'X';
          rddata_reg(9) <= 'X';
          rddata_reg(10) <= 'X';
          rddata_reg(11) <= 'X';
          rddata_reg(12) <= 'X';
          rddata_reg(13) <= 'X';
          rddata_reg(14) <= 'X';
          rddata_reg(15) <= 'X';
          rddata_reg(16) <= 'X';
          rddata_reg(17) <= 'X';
          rddata_reg(18) <= 'X';
          rddata_reg(19) <= 'X';
          rddata_reg(20) <= 'X';
          rddata_reg(21) <= 'X';
          rddata_reg(22) <= 'X';
          rddata_reg(23) <= 'X';
          rddata_reg(24) <= 'X';
          rddata_reg(25) <= 'X';
          rddata_reg(26) <= 'X';
          rddata_reg(27) <= 'X';
          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "100" => 
          if (wb_we_i = '1') then
            regs_o.host_tdr_data_wr_o <= '1';
          end if;
          rddata_reg(8) <= regs_i.host_tdr_rdy_i;
          rddata_reg(0) <= 'X';
          rddata_reg(1) <= 'X';
          rddata_reg(2) <= 'X';
          rddata_reg(3) <= 'X';
          rddata_reg(4) <= 'X';
          rddata_reg(5) <= 'X';
          rddata_reg(6) <= 'X';
          rddata_reg(7) <= 'X';
          rddata_reg(9) <= 'X';
          rddata_reg(10) <= 'X';
          rddata_reg(11) <= 'X';
          rddata_reg(12) <= 'X';
          rddata_reg(13) <= 'X';
          rddata_reg(14) <= 'X';
          rddata_reg(15) <= 'X';
          rddata_reg(16) <= 'X';
          rddata_reg(17) <= 'X';
          rddata_reg(18) <= 'X';
          rddata_reg(19) <= 'X';
          rddata_reg(20) <= 'X';
          rddata_reg(21) <= 'X';
          rddata_reg(22) <= 'X';
          rddata_reg(23) <= 'X';
          rddata_reg(24) <= 'X';
          rddata_reg(25) <= 'X';
          rddata_reg(26) <= 'X';
          rddata_reg(27) <= 'X';
          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "101" => 
          if (wb_we_i = '1') then
          end if;
          rddata_reg(7 downto 0) <= regs_i.host_rdr_data_i;
          host_rack_o <= '1';
          rddata_reg(8) <= regs_i.host_rdr_rdy_i;
          rddata_reg(24 downto 9) <= regs_i.host_rdr_count_i;
          rddata_reg(25) <= 'X';
          rddata_reg(26) <= 'X';
          rddata_reg(27) <= 'X';
          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "110" => 
          if (wb_we_i = '1') then
            uart_cr_rx_fifo_purge_int <= wrdata_reg(0);
            uart_cr_tx_fifo_purge_int <= wrdata_reg(1);
          end if;
          rddata_reg(0) <= '0';
          rddata_reg(1) <= '0';
          rddata_reg(0) <= 'X';
          rddata_reg(1) <= 'X';
          rddata_reg(2) <= 'X';
          rddata_reg(3) <= 'X';
          rddata_reg(4) <= 'X';
          rddata_reg(5) <= 'X';
          rddata_reg(6) <= 'X';
          rddata_reg(7) <= 'X';
          rddata_reg(8) <= 'X';
          rddata_reg(9) <= 'X';
          rddata_reg(10) <= 'X';
          rddata_reg(11) <= 'X';
          rddata_reg(12) <= 'X';
          rddata_reg(13) <= 'X';
          rddata_reg(14) <= 'X';
          rddata_reg(15) <= 'X';
          rddata_reg(16) <= 'X';
          rddata_reg(17) <= 'X';
          rddata_reg(18) <= 'X';
          rddata_reg(19) <= 'X';
          rddata_reg(20) <= 'X';
          rddata_reg(21) <= 'X';
          rddata_reg(22) <= 'X';
          rddata_reg(23) <= 'X';
          rddata_reg(24) <= 'X';
          rddata_reg(25) <= 'X';
          rddata_reg(26) <= 'X';
          rddata_reg(27) <= 'X';
          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
          ack_sreg(2) <= '1';
          ack_in_progress <= '1';
        when others =>
-- prevent the slave from hanging the bus on invalid address
          ack_in_progress <= '1';
          ack_sreg(0) <= '1';
        end case;
      end if;
    end if;
  end if;
end process;


-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- TX busy
-- RX ready
-- RX FIFO supported
-- TX FIFO supported
-- RX FIFO data valid
-- TX FIFO empty
-- TX FIFO full
-- RX FIFO overflow
regs_o.sr_rx_fifo_overflow_o <= wrdata_reg(7);
-- RX FIFO data count
-- Baudrate divider setting
-- pass-through field: Baudrate divider setting in register: Baudrate control register
regs_o.bcr_o <= wrdata_reg(31 downto 0);
-- Transmit data
-- pass-through field: Transmit data in register: Transmit data regsiter
regs_o.tdr_tx_data_o <= wrdata_reg(7 downto 0);
-- Received data
-- TX Data
-- pass-through field: TX Data in register: Host VUART Tx register
regs_o.host_tdr_data_o <= wrdata_reg(7 downto 0);
-- TX Ready
-- RX Data
-- RX Ready
-- RX FIFO Count
-- RX FIFO purge
process (clk_sys_i, rst_n_i)
begin
  if (rst_n_i = '0') then 
    uart_cr_rx_fifo_purge_dly0 <= '0';
    regs_o.cr_rx_fifo_purge_o <= '0';
  elsif rising_edge(clk_sys_i) then
    uart_cr_rx_fifo_purge_dly0 <= uart_cr_rx_fifo_purge_int;
    regs_o.cr_rx_fifo_purge_o <= uart_cr_rx_fifo_purge_int and (not uart_cr_rx_fifo_purge_dly0);
  end if;
end process;


-- TX FIFO purge
process (clk_sys_i, rst_n_i)
begin
  if (rst_n_i = '0') then 
    uart_cr_tx_fifo_purge_dly0 <= '0';
    regs_o.cr_tx_fifo_purge_o <= '0';
  elsif rising_edge(clk_sys_i) then
    uart_cr_tx_fifo_purge_dly0 <= uart_cr_tx_fifo_purge_int;
    regs_o.cr_tx_fifo_purge_o <= uart_cr_tx_fifo_purge_int and (not uart_cr_tx_fifo_purge_dly0);
  end if;
end process;


rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
