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FSI Data Acquisition Path Gateware and Software
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FSI Data Acquisition Path Gateware and Software
Commits
18693fd1
Commit
18693fd1
authored
Jan 26, 2023
by
Maciej Lipinski
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periph_adc_v2: fix few minor bugs in the new AC/DC control
parent
87af1439
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3 changed files
with
6 additions
and
5 deletions
+6
-5
fsi_adc_pkg.vhd
hdl/rtl/fsi/fsi_adc_pkg.vhd
+2
-1
fsi_control.vhd
hdl/rtl/fsi/fsi_control.vhd
+2
-2
periph_adc_top.xdc
hdl/syn/periph_adc_top/periph_adc_top.xdc
+2
-2
No files found.
hdl/rtl/fsi/fsi_adc_pkg.vhd
View file @
18693fd1
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
package
fsi_adc_pkg
is
type
t_slv_8x12
is
array
(
7
downto
0
)
of
std_logic_vector
(
11
downto
0
);
...
...
@@ -58,7 +59,7 @@ package fsi_adc_pkg is
constant
c_acdc_none
:
std_logic_vector
(
3
downto
0
)
:
=
x"0"
;
constant
c_acdc_ac
:
std_logic_vector
(
3
downto
0
)
:
=
x"1"
;
constant
c_acdc_dc
:
std_logic_vector
(
3
downto
0
)
:
=
x"2"
;
constant
c_acdc_pulse_width
:
unsigned
(
31
downto
0
)
:
=
d
"150000
0"
;
--x[10ns]=15ms
constant
c_acdc_pulse_width
:
unsigned
(
31
downto
0
)
:
=
x"0016E36
0"
;
--x[10ns]=15ms
-- Flash update: (TODO)
-- Control CS, tx+rx x1, tx 2x4, tx 8x4, rx 2x4, rx 8x4
...
...
hdl/rtl/fsi/fsi_control.vhd
View file @
18693fd1
...
...
@@ -90,7 +90,7 @@ architecture arch of fsi_control is
signal
acdc_set_cmd
:
std_logic_vector
(
3
downto
0
);
signal
acdc_pulse_cnt
:
unsigned
(
31
downto
0
);
type
t_acdc_state
is
(
ACDC_STATE_IDLE
,
ACDC_STATE_SET
);
signal
acdc_state
:
t_
send
;
signal
acdc_state
:
t_
acdc_state
;
begin
-- Data for the backplane
status
(
11
)
<=
trigger_i
;
...
...
@@ -416,7 +416,7 @@ begin
-- onec puse generated, set LOW the output and come back to waiting
if
(
acdc_pulse_cnt
=
d
"0000000"
)
then
if
(
acdc_pulse_cnt
=
x"00000000"
)
then
acdc_state
<=
ACDC_STATE_IDLE
;
afe_dc_o
<=
'0'
;
afe_ac_o
<=
'0'
;
...
...
hdl/syn/periph_adc_top/periph_adc_top.xdc
View file @
18693fd1
...
...
@@ -25,9 +25,9 @@ set_property IOSTANDARD LVCMOS33 [get_ports afe_tia_ctrl_o[2]]
set_property IOSTANDARD LVCMOS33 [get_ports afe_tia_ctrl_o[1]]
set_property PACKAGE_PIN M6 [get_ports afe_dc_o]
set_property PACKAGE_PIN N6 [get_ports afe_dc_o]
set_property IOSTANDARD LVCMOS33 [get_ports afe_dc_o]
set_property PACKAGE_PIN N6 [get_ports afe_ac_o]
set_property IOSTANDARD LVCMOS33 [get_ports afe_dc_o]
set_property IOSTANDARD LVCMOS33 [get_ports afe_ac_o]
set_property PACKAGE_PIN R12 [get_ports bp_sda_b]
set_property PACKAGE_PIN T12 [get_ports bp_scl_i]
...
...
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