diff --git a/hdl/pcie_altera.vhd b/hdl/pcie_altera.vhd
index ca92087e67ec171746c7c9e65e766dc47657dd72..cf1e92f1a3bbd89801fb203e0aece2f3ad33ef8f 100644
--- a/hdl/pcie_altera.vhd
+++ b/hdl/pcie_altera.vhd
@@ -20,6 +20,7 @@ entity pcie_altera is
     wb_clk_o      : out std_logic;
     
     rx_wb_stb_o   : out std_logic;
+    rx_wb_bar_o   : out std_logic_vector(2 downto 0);
     rx_wb_dat_o   : out std_logic_vector(31 downto 0);
     rx_wb_stall_i : in  std_logic;
     
@@ -221,9 +222,13 @@ architecture rtl of pcie_altera is
   
   -- RX registers and signals
   
-  signal rx_st_ready0, rx_st_valid0 : std_logic;
+  signal rx_st_ready0, rx_st_valid0, rx_st_sop0 : std_logic;
   signal rx_st_be0 : std_logic_vector(7 downto 0);
   signal rx_st_data0 : std_logic_vector(63 downto 0);
+  signal rx_st_bardec0 : std_logic_vector(7 downto 0);
+  
+  signal r_rx_sop : std_logic;
+  signal r_bar : std_logic_vector(2 downto 0);
   
   signal r64_ready : std_logic_vector(1 downto 0); -- length must equal the latency of the Avalon RX bus
   signal r64_dat, s64_dat : std_logic_vector(63 downto 0);
@@ -242,7 +247,7 @@ architecture rtl of pcie_altera is
   signal tx_st_sop0, tx_st_eop0, tx_st_ready0, tx_st_valid0 : std_logic;
   signal tx_st_data0 : std_logic_vector(63 downto 0);
   signal s_eop, tx_queue_stall : std_logic;
-  signal r_sop : std_logic := '1';
+  signal r_tx_sop : std_logic := '1';
   
   signal queue : queue_t;
   
@@ -302,12 +307,12 @@ begin
       -- Avalon RX
       rx_st_mask0          => '0',
       rx_st_ready0         => rx_st_ready0,
-      rx_st_bardec0        => open, --  7 downto 0
+      rx_st_bardec0        => rx_st_bardec0, --  7 downto 0
       rx_st_be0            => rx_st_be0, --  7 downto 0
       rx_st_data0          => rx_st_data0, -- 63 downto 0
       rx_st_eop0           => open,
       rx_st_err0           => open,
-      rx_st_sop0           => open,
+      rx_st_sop0           => rx_st_sop0,
       rx_st_valid0         => rx_st_valid0,
       rx_fifo_empty0       => open, -- informative/debug only (ignore in real design)
       rx_fifo_full0        => open, -- informative/debug only (ignore in real design)
@@ -479,6 +484,23 @@ begin
     end if;
   end process;
   
+  -- Record bar
+  rx_wb_bar_o <= r_bar;
+  bardec : process(core_clk_out)
+  begin
+    if rising_edge(core_clk_out) then
+      if rx_st_valid0 = '1' then
+        if r_rx_sop = '1' then
+          -- Decode one-hot
+          r_bar(0) <= (rx_st_bardec0(1) or rx_st_bardec0(3) or rx_st_bardec0(5) or rx_st_bardec0(7));
+          r_bar(1) <= (rx_st_bardec0(2) or rx_st_bardec0(3) or rx_st_bardec0(6) or rx_st_bardec0(7));
+          r_bar(2) <= (rx_st_bardec0(4) or rx_st_bardec0(5) or rx_st_bardec0(6) or rx_st_bardec0(7));
+        end if;
+        r_rx_sop <= rx_st_sop0;
+      end if;
+    end if;
+  end process;
+  
   -- Stream rx data out as wishbone
   rx_wb_stb_o <= r32_full;
   rx_wb_dat_o <= r32_dat0;
@@ -551,7 +573,7 @@ begin
   tx_st_data0 <= queue(to_integer(r_idxr(buf_bits-1 downto 0)))(63 downto 0);
   s_eop       <= queue(to_integer(r_idxr(buf_bits-1 downto 0)))(64);
   tx_st_eop0  <= s_eop;
-  tx_st_sop0  <= r_sop;
+  tx_st_sop0  <= r_tx_sop;
   
   tx_st_valid0 <= active_high(r_idxr /= r_idxe) and r_delay_ready(r_delay_ready'length-1);
   
@@ -561,12 +583,12 @@ begin
       if rstn = '0' then
         r_delay_ready <= (others => '0');
         r_idxr <= (others => '0');
-        r_sop <= '1';
+        r_tx_sop <= '1';
       else
         r_delay_ready <= r_delay_ready(r_delay_ready'length-2 downto 0) & tx_st_ready0;
         if tx_st_valid0 = '1' then
           r_idxr <= r_idxr + 1;
-          r_sop <= s_eop;
+          r_tx_sop <= s_eop;
         end if;
       end if;
     end if;
diff --git a/hdl/pcie_tlp.vhd b/hdl/pcie_tlp.vhd
index d2503531c7603e08a8b53d8e2d4f82ed5f8dc1a9..9c18236bb88c1f60f4c7528335015e6c7515642e 100644
--- a/hdl/pcie_tlp.vhd
+++ b/hdl/pcie_tlp.vhd
@@ -8,7 +8,7 @@ entity pcie_tlp is
     rstn_i        : in std_logic;
     
     rx_wb_stb_i   : in  std_logic;
-    rx_wb_bar_i   : in  std_logic;
+    rx_wb_bar_i   : in  std_logic_vector(2 downto 0);
     rx_wb_dat_i   : in  std_logic_vector(31 downto 0);
     rx_wb_stall_o : out std_logic;
     
@@ -22,6 +22,7 @@ entity pcie_tlp is
     
     wb_stb_o      : out std_logic;
     wb_adr_o      : out std_logic_vector(63 downto 0);
+    wb_bar_o      : out std_logic_vector(2 downto 0);
     wb_we_o       : out std_logic;
     wb_dat_o      : out std_logic_vector(31 downto 0);
     wb_sel_o      : out std_logic_vector(3 downto 0);
@@ -65,6 +66,7 @@ architecture rtl of pcie_tlp is
   signal r_last_be     : std_logic_vector(3 downto 0);
   signal r_first_be    : std_logic_vector(3 downto 0);
   signal r_address     : std_logic_vector(63 downto 0);
+  signal r_bar         : std_logic_vector(2 downto 0);
   
   -- Common subexpressions:
   signal s_length_m1 : unsigned(9 downto 0);
@@ -86,6 +88,7 @@ begin
   wb_stb <= r_always_stb or (not r_never_stb and rx_wb_stb_i);
   wb_stb_o <= wb_stb;
   wb_adr_o <= r_address;
+  wb_bar_o <= r_bar;
   wb_dat_o <= rx_wb_dat_i;
   
   -- Fields in the rx_data
@@ -132,6 +135,7 @@ begin
           when h_low_addr =>
             -- address also stores busnum/devnum/ext/reg for IO ops
             r_address(31 downto 2) <= rx_wb_dat_i(31 downto 2);
+            r_bar <= rx_wb_bar_i;
           when p_w0 => null;
           when p_wx => null;
           when p_we => null;
diff --git a/hdl/pcie_wb.vhd b/hdl/pcie_wb.vhd
index b41930b8767c32f083e972939c59e550e0441176..6e01b2db4583cbf0ec1e2c86d85d37b8d68b0f27 100644
--- a/hdl/pcie_wb.vhd
+++ b/hdl/pcie_wb.vhd
@@ -46,12 +46,14 @@ architecture rtl of pcie_wb is
   
   signal rx_wb_stb, rx_wb_stall : std_logic;
   signal rx_wb_dat : std_logic_vector(31 downto 0);
+  signal rx_wb_bar : std_logic_vector(2 downto 0);
   
   signal tx_rdy, tx_alloc, tx_en, tx_eop : std_logic;
   signal tx_dat : std_logic_vector(31 downto 0);
   
   signal wb_stb_o, wb_we_o, wb_ack_i : std_logic;
   signal wb_dat_o, wb_dat_i, demo_reg : std_logic_vector(31 downto 0);
+  signal wb_bar : std_logic_vector(2 downto 0);
   
   signal cfg_busdev : std_logic_vector(12 downto 0);
   
@@ -88,6 +90,7 @@ begin
     
     rx_wb_stb_o   => rx_wb_stb,
     rx_wb_dat_o   => rx_wb_dat,
+    rx_wb_bar_o   => rx_wb_bar,
     rx_wb_stall_i => rx_wb_stall,
     
     tx_rdy_o      => tx_rdy,
@@ -101,8 +104,8 @@ begin
     rstn_i        => rstn,
     
     rx_wb_stb_i   => rx_wb_stb,
-    rx_wb_bar_i   => '0',
     rx_wb_dat_i   => rx_wb_dat,
+    rx_wb_bar_i   => rx_wb_bar,
     rx_wb_stall_o => rx_wb_stall,
     
     tx_rdy_i      => tx_rdy,
@@ -115,6 +118,7 @@ begin
       
     wb_stb_o      => wb_stb_o,
     wb_adr_o      => open,
+    wb_bar_o      => wb_bar,
     wb_we_o       => wb_we_o,
     wb_dat_o      => wb_dat_o,
     wb_sel_o      => open,
diff --git a/hdl/pcie_wb_pkg.vhd b/hdl/pcie_wb_pkg.vhd
index 161c234004ddd2abe4caddc0b5a626c34bd31613..45fe9ab6f3a393c3a703cd4415ee05246a69e183 100644
--- a/hdl/pcie_wb_pkg.vhd
+++ b/hdl/pcie_wb_pkg.vhd
@@ -21,6 +21,7 @@ package pcie_wb_pkg is
       wb_clk_o      : out std_logic;
       
       rx_wb_stb_o   : out std_logic;
+      rx_wb_bar_o   : out std_logic_vector(2 downto 0);
       rx_wb_dat_o   : out std_logic_vector(31 downto 0);
       rx_wb_stall_i : in  std_logic;
       
@@ -40,7 +41,7 @@ package pcie_wb_pkg is
       rstn_i        : in std_logic;
       
       rx_wb_stb_i   : in  std_logic;
-      rx_wb_bar_i   : in  std_logic;
+      rx_wb_bar_i   : in  std_logic_vector(2 downto 0);
       rx_wb_dat_i   : in  std_logic_vector(31 downto 0);
       rx_wb_stall_o : out std_logic;
       
@@ -54,6 +55,7 @@ package pcie_wb_pkg is
       
       wb_stb_o      : out std_logic;
       wb_adr_o      : out std_logic_vector(63 downto 0);
+      wb_bar_o      : out std_logic_vector(2 downto 0);
       wb_we_o       : out std_logic;
       wb_dat_o      : out std_logic_vector(31 downto 0);
       wb_sel_o      : out std_logic_vector(3 downto 0);