diff --git a/altera_pcie.qip b/altera_pcie.qip
index 99064b352fc63e25d2bb3bee41e6cad1fa821c84..fc19ec9ebb874f9ecf88860fbceddde3d006ddbd 100644
--- a/altera_pcie.qip
+++ b/altera_pcie.qip
@@ -4,62 +4,62 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pc
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie_core.vhd"]
 set_global_assignment -name SEARCH_PATH  [file join $::quartus(qip_path) "." ]
 set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) ip_compiler_for_pci_express-library ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_250_100.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp_dcram.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_pll.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.ocp ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_align.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_rs_serdes.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_125.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_125_250.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_250.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy0.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy2.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_rs_serdes.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_trans.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_125.v ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_250_100.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_trans.v ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_phasefifo.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_250.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_pll.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp_dcram.v ]
 set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_align.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_125_250.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy2.v ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_phasefifo.v ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.vhd ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.cmp ]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.vhd ]
diff --git a/altera_pcie.sdc b/altera_pcie.sdc
index 65a16675f70eb58f5673ccf3964a73d5ee2d4360..5a1ac5fd7157531ca42028d64cee069b4ef97af9 100644
--- a/altera_pcie.sdc
+++ b/altera_pcie.sdc
@@ -1,11 +1,7 @@
-create_clock -period "100 MHz" -name {refclk} {pcie_refclk_i}
-derive_pll_clocks -create_base_clocks
-derive_clock_uncertainty
-
 # The refclk assignment may need to be renamed to match design top level port name.
 # May be desireable to move refclk assignment to a top level SDC file.
-#create_clock -period "100 MHz" -name {refclk} {pcie_refclk_i}
-#create_clock -period "125 MHz" -name {fixedclk_serdes} {pcie_clk125_i}
+#create_clock -period "100 MHz" -name {refclk} {refclk}
+#create_clock -period "100 MHz" -name {fixedclk_serdes} {fixedclk_serdes}
 # testin bits are either static or treated asynchronously, cut the paths.
 #set_false_path -to [get_pins -hierarchical {*hssi_pcie_hip|testin[*]} ]
 # SERDES Digital Reset inputs are asynchronous
diff --git a/altera_pcie.vhd b/altera_pcie.vhd
index 9d492240b1510b7d3f3cfebb24c8e53d850de7a4..917019a3a63563c7564ac3ecfdc8ed46ce1eb7ee 100644
--- a/altera_pcie.vhd
+++ b/altera_pcie.vhd
@@ -1131,7 +1131,7 @@ end europa;
 -- Warning: If you modify this section, IP Compiler for PCI Express Wizard may not be able to reproduce your chosen configuration.
 -- 
 -- Retrieval info: <?xml version="1.0"?>
--- Retrieval info: <MEGACORE title="IP Compiler for PCI Express"  version="11.1"  build="216"  iptb_version="1.3.0 Build 216"  format_version="120" >
+-- Retrieval info: <MEGACORE title="IP Compiler for PCI Express"  version="11.1"  build="173"  iptb_version="1.3.0 Build 173"  format_version="120" >
 -- Retrieval info:  <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.MVCModel"  active_core="altpcie_hip_pipen1b" >
 -- Retrieval info:   <STATIC_SECTION>
 -- Retrieval info:    <PRIVATES>
@@ -1264,10 +1264,10 @@ end europa;
 -- Retrieval info:      <PRIVATE name = "p_pci_master" value="true"  type="STRING"  enable="1" />
 -- Retrieval info:      <PRIVATE name = "p_pci_master_bursts" value="true"  type="STRING"  enable="1" />
 -- Retrieval info:      <PRIVATE name = "p_pci_master_concurrent_reads" value="false"  type="STRING"  enable="1" />
--- Retrieval info:      <PRIVATE name = "p_pci_master_data_width" value="32"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "p_pci_master_data_width" value="64"  type="STRING"  enable="1" />
 -- Retrieval info:      <PRIVATE name = "p_pci_maximum_burst_size" value="128"  type="STRING"  enable="1" />
 -- Retrieval info:      <PRIVATE name = "p_pci_maximum_burst_size_a2p" value="128"  type="STRING"  enable="1" />
--- Retrieval info:      <PRIVATE name = "p_pci_maximum_pending_read_transactions_a2p" value="2"  type="STRING"  enable="1" />
+-- Retrieval info:      <PRIVATE name = "p_pci_maximum_pending_read_transactions_a2p" value="8"  type="STRING"  enable="1" />
 -- Retrieval info:      <PRIVATE name = "p_pci_non_pref_av_master_port" value="true"  type="STRING"  enable="1" />
 -- Retrieval info:      <PRIVATE name = "p_pci_not_target_only_port" value="true"  type="STRING"  enable="1" />
 -- Retrieval info:      <PRIVATE name = "p_pci_pref_av_master_port" value="true"  type="STRING"  enable="1" />
diff --git a/altera_pcie_core.vhd b/altera_pcie_core.vhd
index acfd6ffebaf3361a4b34c480822df586451dcc30..71f5c24c3447421454b637fcef2bd9f98ca49513 100644
--- a/altera_pcie_core.vhd
+++ b/altera_pcie_core.vhd
@@ -1,4 +1,4 @@
--- Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 216]
+-- Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 173]
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 -- ************************************************************
diff --git a/altera_pcie_pll.vhd b/altera_pcie_pll.vhd
index 423caca9d765888f85d0a9564df91cec60c2fcb9..ef9759ef838550d65f63021e9d2a6b820fd11cce 100644
--- a/altera_pcie_pll.vhd
+++ b/altera_pcie_pll.vhd
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
+-- 11.1 Build 173 11/01/2011 SJ Full Version
 -- ************************************************************
 
 
@@ -45,6 +45,7 @@ ENTITY altera_pcie_pll IS
 		areset		: IN STD_LOGIC  := '0';
 		inclk0		: IN STD_LOGIC  := '0';
 		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
 		locked		: OUT STD_LOGIC 
 	);
 END altera_pcie_pll;
@@ -52,13 +53,14 @@ END altera_pcie_pll;
 
 ARCHITECTURE SYN OF altera_pcie_pll IS
 
-	SIGNAL sub_wire0	: STD_LOGIC ;
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
 	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire6_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -69,6 +71,10 @@ ARCHITECTURE SYN OF altera_pcie_pll IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
 		compensate_clock		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
@@ -131,13 +137,15 @@ ARCHITECTURE SYN OF altera_pcie_pll IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire5_bv(0 DOWNTO 0) <= "0";
-	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
-	locked    <= sub_wire0;
-	sub_wire2    <= sub_wire1(0);
-	c0    <= sub_wire2;
-	sub_wire3    <= inclk0;
-	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+	sub_wire6_bv(0 DOWNTO 0) <= "0";
+	sub_wire6    <= To_stdlogicvector(sub_wire6_bv);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	sub_wire4    <= inclk0;
+	sub_wire5    <= sub_wire6(0 DOWNTO 0) & sub_wire4;
 
 	altpll_component : altpll
 	GENERIC MAP (
@@ -146,6 +154,10 @@ BEGIN
 		clk0_duty_cycle => 50,
 		clk0_multiply_by => 8,
 		clk0_phase_shift => "0",
+		clk1_divide_by => 5,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 2,
+		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 8000,
 		intended_device_family => "Arria II GX",
@@ -180,7 +192,7 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_UNUSED",
+		port_clk1 => "PORT_USED",
 		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
@@ -201,9 +213,9 @@ BEGIN
 	)
 	PORT MAP (
 		areset => areset,
-		inclk => sub_wire4,
-		locked => sub_wire0,
-		clk => sub_wire1
+		inclk => sub_wire5,
+		clk => sub_wire0,
+		locked => sub_wire2
 	);
 
 
@@ -230,8 +242,11 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "5"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -252,17 +267,24 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -285,10 +307,12 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -297,6 +321,10 @@ END SYN;
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
@@ -330,7 +358,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -352,12 +380,14 @@ END SYN;
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll.ppf TRUE
diff --git a/altera_pcie_serdes.vhd b/altera_pcie_serdes.vhd
index 37de03763eb7986000d650fa85fb93829890887f..5bb5d381a6534751b70e50c291bbf51960a4e2fc 100644
--- a/altera_pcie_serdes.vhd
+++ b/altera_pcie_serdes.vhd
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
+-- 11.1 Build 173 11/01/2011 SJ Full Version
 -- ************************************************************
 
 
@@ -34,7 +34,7 @@
 
 
 --alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Arria II GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=1 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 hip_enable="true" input_clock_frequency="100.0 MHz" intended_device_speed_grade="4" intended_device_variant="ANY" loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=10000 rx_cru_m_divider=0 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x4" tx_channel_width=8 tx_clkout_width=4 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=0 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=2 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout fixedclk gxb_powerdown hip_tx_clkout pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked pll_powerdown powerdn rateswitch rateswitchbaseclock reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_elecidleinfersel rx_freqlocked rx_patterndetect rx_pll_locked rx_signaldetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
---VERSION_BEGIN 11.1SP1 cbx_alt4gxb 2011:11:23:21:11:17:SJ cbx_mgl 2011:11:23:21:12:03:SJ cbx_tgx 2011:11:23:21:11:17:SJ  VERSION_END
+--VERSION_BEGIN 11.1 cbx_alt4gxb 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_tgx 2011:10:31:21:09:45:SJ  VERSION_END
 
  LIBRARY arriaii_hssi;
  USE arriaii_hssi.all;
diff --git a/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v b/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v
index 088541e1707070c56bfdb33a77e948072292fb1d..0a75b83604e9962903d95fc86dfab6b465150169 100644
Binary files a/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v and b/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v differ
diff --git a/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v b/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v
index cbd2d4aaf538d07bf9429636c6f16bfc35b72024..7fc92fc50aea7adc150aa5910871faffc50101be 100644
Binary files a/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v and b/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v differ
diff --git a/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v b/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v
index 3073473a52d11cb99379cfa8b6a40be0e3837359..22ec7fe4d6ba6749f580ef9c3aa3cdcde61100b2 100644
Binary files a/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v and b/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v differ
diff --git a/ip_compiler_for_pci_express-library/pciexp64_dlink.v b/ip_compiler_for_pci_express-library/pciexp64_dlink.v
index 5d1e77af915715f55ea7867861389714564cc17f..2cf35064c0bff0943d36ede96ae16a960ea12275 100644
Binary files a/ip_compiler_for_pci_express-library/pciexp64_dlink.v and b/ip_compiler_for_pci_express-library/pciexp64_dlink.v differ
diff --git a/ip_compiler_for_pci_express-library/pciexp64_trans.v b/ip_compiler_for_pci_express-library/pciexp64_trans.v
index c9f3e76da208e882db14c7219a7c87410418aa2d..98c5a074ec65dcd6c3ea5e25b4f7a37498534185 100644
Binary files a/ip_compiler_for_pci_express-library/pciexp64_trans.v and b/ip_compiler_for_pci_express-library/pciexp64_trans.v differ
diff --git a/ip_compiler_for_pci_express-library/pciexp_dcram.v b/ip_compiler_for_pci_express-library/pciexp_dcram.v
index def0ff4d5b1ffb2c403c47d76aff988ab422fa10..1dd3693552f6239ec60e7417cfc3b12cb1321f8f 100644
Binary files a/ip_compiler_for_pci_express-library/pciexp_dcram.v and b/ip_compiler_for_pci_express-library/pciexp_dcram.v differ
diff --git a/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v b/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v
index 8cb8cdd8d6bde6919c634f332f3044afa3f38a3e..c6bef3e50033745a83f07fbbf706a04e46f0649d 100644
Binary files a/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v and b/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v differ
diff --git a/pcie_wb.qsf b/pcie_wb.qsf
index 73e6575a08ba17e7fcc6fedc8291e8e6386eae28..ec70bfd9f319e95960c6c851db57aff5870e179b 100644
--- a/pcie_wb.qsf
+++ b/pcie_wb.qsf
@@ -41,20 +41,17 @@ set_global_assignment -name DEVICE EP2AGX125DF25C6ES
 set_global_assignment -name TOP_LEVEL_ENTITY pcie_wb
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:17:02  MARCH 30, 2012"
-set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION 11.1
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
-set_global_assignment -name QIP_FILE altera_pcie.qip
-set_global_assignment -name VHDL_FILE pcie_wb.vhd
-set_global_assignment -name QIP_FILE altera_reconfig.qip
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
 set_location_assignment PIN_D11 -to pcie_clk125_i
 set_location_assignment PIN_U23 -to pcie_refclk_i
-set_location_assignment PIN_A11 -to pcie_rstn_i
+set_location_assignment PIN_W1 -to pcie_rstn_i
 set_location_assignment PIN_N23 -to pcie_rx_i[3]
 set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[3]
 set_location_assignment PIN_N24 -to "pcie_rx_i[3](n)"
@@ -83,6 +80,287 @@ set_instance_assignment -name IO_STANDARD LVDS -to pcie_clk125_i
 set_location_assignment PIN_C11 -to "pcie_clk125_i(n)"
 set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_i
 set_location_assignment PIN_U24 -to "pcie_refclk_i(n)"
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pcie_rstn_i
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "altera_pcie:pcie|core_clk_out" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=M9K" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_location_assignment PIN_AB10 -to led_o[0]
+set_location_assignment PIN_AA10 -to led_o[1]
+set_location_assignment PIN_W10 -to led_o[2]
+set_location_assignment PIN_W9 -to led_o[3]
+set_location_assignment PIN_AB7 -to led_o[4]
+set_location_assignment PIN_AA7 -to led_o[5]
+set_location_assignment PIN_V9 -to led_o[6]
+set_location_assignment PIN_U9 -to led_o[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[7]
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
+set_global_assignment -name VHDL_FILE pow_reset.vhd
+set_global_assignment -name QIP_FILE altera_pcie.qip
+set_global_assignment -name VHDL_FILE pcie_wb.vhd
+set_global_assignment -name QIP_FILE altera_reconfig.qip
 set_global_assignment -name QIP_FILE altera_pcie_pll.qip
-set_location_assignment PIN_AB10 -to led_o
+set_global_assignment -name SDC_FILE pcie_wb.sdc
+set_global_assignment -name SIGNALTAP_FILE stp2.stp
+set_global_assignment -name QIP_FILE flash_loader.qip
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CHECK_ADDR_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CLEAR_WAITREQ_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CTRL_RD_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CTRL_WR_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.ERR_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.IDLE_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_CLR_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_FRAME_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_PRE_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_START_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_ADDR" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_END" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_READ" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_WRITE" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.IDLE_ST_CNT" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.STABLE_TX_PLL_ST_CNT" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.STROBE_TXPLL_LOCKED_SD_CNT" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.WAIT_STATE_ST_CNT" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "altera_pcie:pcie|dlup_exit" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "altera_pcie:pcie|hotrst_exit" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "altera_pcie:pcie|l2_exit" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "altera_pcie:pcie|rx_fifo_empty0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "altera_pcie:pcie|rx_fifo_full0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "altera_pcie:pcie|rx_st_bardec0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "altera_pcie:pcie|rx_st_bardec0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "altera_pcie:pcie|rx_st_bardec0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "altera_pcie:pcie|rx_st_bardec0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "altera_pcie:pcie|rx_st_bardec0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "altera_pcie:pcie|rx_st_bardec0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "altera_pcie:pcie|rx_st_bardec0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "altera_pcie:pcie|rx_st_bardec0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "altera_pcie:pcie|rx_st_data0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "altera_pcie:pcie|rx_st_data0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "altera_pcie:pcie|rx_st_data0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "altera_pcie:pcie|rx_st_data0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "altera_pcie:pcie|rx_st_data0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "altera_pcie:pcie|rx_st_data0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "altera_pcie:pcie|rx_st_data0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "altera_pcie:pcie|rx_st_data0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "altera_pcie:pcie|rx_st_data0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "altera_pcie:pcie|rx_st_data0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "altera_pcie:pcie|rx_st_data0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "altera_pcie:pcie|rx_st_data0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "altera_pcie:pcie|rx_st_data0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "altera_pcie:pcie|rx_st_data0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "altera_pcie:pcie|rx_st_data0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "altera_pcie:pcie|rx_st_data0[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "altera_pcie:pcie|rx_st_data0[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "altera_pcie:pcie|rx_st_data0[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "altera_pcie:pcie|rx_st_data0[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "altera_pcie:pcie|rx_st_data0[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "altera_pcie:pcie|rx_st_data0[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "altera_pcie:pcie|rx_st_data0[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "altera_pcie:pcie|rx_st_data0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "altera_pcie:pcie|rx_st_data0[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "altera_pcie:pcie|rx_st_data0[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "altera_pcie:pcie|rx_st_data0[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "altera_pcie:pcie|rx_st_data0[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "altera_pcie:pcie|rx_st_data0[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "altera_pcie:pcie|rx_st_data0[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "altera_pcie:pcie|rx_st_data0[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "altera_pcie:pcie|rx_st_data0[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "altera_pcie:pcie|rx_st_data0[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "altera_pcie:pcie|rx_st_data0[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "altera_pcie:pcie|rx_st_data0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "altera_pcie:pcie|rx_st_data0[40]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "altera_pcie:pcie|rx_st_data0[41]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "altera_pcie:pcie|rx_st_data0[42]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "altera_pcie:pcie|rx_st_data0[43]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "altera_pcie:pcie|rx_st_data0[44]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "altera_pcie:pcie|rx_st_data0[45]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "altera_pcie:pcie|rx_st_data0[46]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "altera_pcie:pcie|rx_st_data0[47]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "altera_pcie:pcie|rx_st_data0[48]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "altera_pcie:pcie|rx_st_data0[49]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "altera_pcie:pcie|rx_st_data0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "altera_pcie:pcie|rx_st_data0[50]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "altera_pcie:pcie|rx_st_data0[51]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "altera_pcie:pcie|rx_st_data0[52]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "altera_pcie:pcie|rx_st_data0[53]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "altera_pcie:pcie|rx_st_data0[54]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "altera_pcie:pcie|rx_st_data0[55]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "altera_pcie:pcie|rx_st_data0[56]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "altera_pcie:pcie|rx_st_data0[57]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "altera_pcie:pcie|rx_st_data0[58]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "altera_pcie:pcie|rx_st_data0[59]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "altera_pcie:pcie|rx_st_data0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "altera_pcie:pcie|rx_st_data0[60]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "altera_pcie:pcie|rx_st_data0[61]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "altera_pcie:pcie|rx_st_data0[62]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "altera_pcie:pcie|rx_st_data0[63]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "altera_pcie:pcie|rx_st_data0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "altera_pcie:pcie|rx_st_data0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "altera_pcie:pcie|rx_st_data0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "altera_pcie:pcie|rx_st_data0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "altera_pcie:pcie|rx_st_eop0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "altera_pcie:pcie|rx_st_err0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "altera_pcie:pcie|rx_st_ready0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "altera_pcie:pcie|rx_st_sop0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "altera_pcie:pcie|rx_st_valid0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to crst -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to npor -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to pcie_rstn_i -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to pme_shift[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to pme_shift[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to pme_shift[2] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to pme_shift[3] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to pme_shift[4] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to rst_reg -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to srst -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CHECK_ADDR_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CLEAR_WAITREQ_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CTRL_RD_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CTRL_WR_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.ERR_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.IDLE_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_CLR_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_FRAME_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_PRE_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_START_ST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_ADDR" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_END" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_READ" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_WRITE" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.IDLE_ST_CNT" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.STABLE_TX_PLL_ST_CNT" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.STROBE_TXPLL_LOCKED_SD_CNT" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.WAIT_STATE_ST_CNT" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "altera_pcie:pcie|dlup_exit" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "altera_pcie:pcie|hotrst_exit" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "altera_pcie:pcie|l2_exit" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "altera_pcie:pcie|rx_fifo_empty0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "altera_pcie:pcie|rx_fifo_full0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "altera_pcie:pcie|rx_st_bardec0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "altera_pcie:pcie|rx_st_bardec0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "altera_pcie:pcie|rx_st_bardec0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "altera_pcie:pcie|rx_st_bardec0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "altera_pcie:pcie|rx_st_bardec0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "altera_pcie:pcie|rx_st_bardec0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "altera_pcie:pcie|rx_st_bardec0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "altera_pcie:pcie|rx_st_bardec0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "altera_pcie:pcie|rx_st_data0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "altera_pcie:pcie|rx_st_data0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "altera_pcie:pcie|rx_st_data0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "altera_pcie:pcie|rx_st_data0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "altera_pcie:pcie|rx_st_data0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "altera_pcie:pcie|rx_st_data0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "altera_pcie:pcie|rx_st_data0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "altera_pcie:pcie|rx_st_data0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "altera_pcie:pcie|rx_st_data0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "altera_pcie:pcie|rx_st_data0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "altera_pcie:pcie|rx_st_data0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "altera_pcie:pcie|rx_st_data0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "altera_pcie:pcie|rx_st_data0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "altera_pcie:pcie|rx_st_data0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "altera_pcie:pcie|rx_st_data0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "altera_pcie:pcie|rx_st_data0[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "altera_pcie:pcie|rx_st_data0[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "altera_pcie:pcie|rx_st_data0[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "altera_pcie:pcie|rx_st_data0[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "altera_pcie:pcie|rx_st_data0[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "altera_pcie:pcie|rx_st_data0[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "altera_pcie:pcie|rx_st_data0[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "altera_pcie:pcie|rx_st_data0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "altera_pcie:pcie|rx_st_data0[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "altera_pcie:pcie|rx_st_data0[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "altera_pcie:pcie|rx_st_data0[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "altera_pcie:pcie|rx_st_data0[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "altera_pcie:pcie|rx_st_data0[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "altera_pcie:pcie|rx_st_data0[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "altera_pcie:pcie|rx_st_data0[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "altera_pcie:pcie|rx_st_data0[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "altera_pcie:pcie|rx_st_data0[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "altera_pcie:pcie|rx_st_data0[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "altera_pcie:pcie|rx_st_data0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "altera_pcie:pcie|rx_st_data0[40]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "altera_pcie:pcie|rx_st_data0[41]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "altera_pcie:pcie|rx_st_data0[42]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "altera_pcie:pcie|rx_st_data0[43]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "altera_pcie:pcie|rx_st_data0[44]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "altera_pcie:pcie|rx_st_data0[45]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "altera_pcie:pcie|rx_st_data0[46]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "altera_pcie:pcie|rx_st_data0[47]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "altera_pcie:pcie|rx_st_data0[48]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "altera_pcie:pcie|rx_st_data0[49]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "altera_pcie:pcie|rx_st_data0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "altera_pcie:pcie|rx_st_data0[50]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "altera_pcie:pcie|rx_st_data0[51]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "altera_pcie:pcie|rx_st_data0[52]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "altera_pcie:pcie|rx_st_data0[53]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "altera_pcie:pcie|rx_st_data0[54]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "altera_pcie:pcie|rx_st_data0[55]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "altera_pcie:pcie|rx_st_data0[56]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "altera_pcie:pcie|rx_st_data0[57]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "altera_pcie:pcie|rx_st_data0[58]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "altera_pcie:pcie|rx_st_data0[59]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "altera_pcie:pcie|rx_st_data0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "altera_pcie:pcie|rx_st_data0[60]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "altera_pcie:pcie|rx_st_data0[61]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "altera_pcie:pcie|rx_st_data0[62]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "altera_pcie:pcie|rx_st_data0[63]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "altera_pcie:pcie|rx_st_data0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "altera_pcie:pcie|rx_st_data0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "altera_pcie:pcie|rx_st_data0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "altera_pcie:pcie|rx_st_data0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "altera_pcie:pcie|rx_st_eop0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "altera_pcie:pcie|rx_st_err0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "altera_pcie:pcie|rx_st_ready0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "altera_pcie:pcie|rx_st_sop0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "altera_pcie:pcie|rx_st_valid0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to crst -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to npor -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to pcie_rstn_i -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to pme_shift[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to pme_shift[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to pme_shift[2] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to pme_shift[3] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to pme_shift[4] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to rst_reg -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to srst -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=110" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=110" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=353" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=5814" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=2632" -section_id auto_signaltap_0
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/pow_reset.vhd b/pow_reset.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..83af6df7e54056bf76d2c8bcd801b236e4e84e48
--- /dev/null
+++ b/pow_reset.vhd
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity pow_reset is
+	port (
+		clk:	in std_logic;		-- 125Mhz
+		nreset:	buffer std_logic
+		);
+end entity;
+
+architecture pow_reset_arch of pow_reset is
+
+signal powerOn:	unsigned(6 downto 0) := "0000000";		-- 7Bit for 1ms nrst
+
+begin
+
+nres: process(Clk)
+begin
+if Clk'event and Clk = '1' then
+	if nreset = '0' then
+		powerOn <= powerOn + 1;
+	end if;
+	nReset <= std_logic(powerOn(powerON'high));
+	end if;
+end process;
+
+end architecture;
\ No newline at end of file