diff --git a/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v b/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v
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diff --git a/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v b/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v
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diff --git a/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v b/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v
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diff --git a/ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v b/ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v
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+++ b/ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v
@@ -0,0 +1,4402 @@
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors. Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings
+// altera message_level Level1
+// altera message_off 10034 10035 10036 10037 10230 10240 10030
+module sim_rxpipe_8bit_to_32_bit (
+ // Input PIPE simulation _ext for simulation only
+ input sim_pipe8_pclk,
+ input aclr,
+
+ input phystatus0_ext,
+ input phystatus1_ext,
+ input phystatus2_ext,
+ input phystatus3_ext,
+ input phystatus4_ext,
+ input phystatus5_ext,
+ input phystatus6_ext,
+ input phystatus7_ext,
+ input [7 : 0] rxdata0_ext,
+ input [7 : 0] rxdata1_ext,
+ input [7 : 0] rxdata2_ext,
+ input [7 : 0] rxdata3_ext,
+ input [7 : 0] rxdata4_ext,
+ input [7 : 0] rxdata5_ext,
+ input [7 : 0] rxdata6_ext,
+ input [7 : 0] rxdata7_ext,
+ input rxdatak0_ext,
+ input rxdatak1_ext,
+ input rxdatak2_ext,
+ input rxdatak3_ext,
+ input rxdatak4_ext,
+ input rxdatak5_ext,
+ input rxdatak6_ext,
+ input rxdatak7_ext,
+ input rxelecidle0_ext,
+ input rxelecidle1_ext,
+ input rxelecidle2_ext,
+ input rxelecidle3_ext,
+ input rxelecidle4_ext,
+ input rxelecidle5_ext,
+ input rxelecidle6_ext,
+ input rxelecidle7_ext,
+ input rxfreqlocked0_ext,
+ input rxfreqlocked1_ext,
+ input rxfreqlocked2_ext,
+ input rxfreqlocked3_ext,
+ input rxfreqlocked4_ext,
+ input rxfreqlocked5_ext,
+ input rxfreqlocked6_ext,
+ input rxfreqlocked7_ext,
+ input [2 : 0] rxstatus0_ext,
+ input [2 : 0] rxstatus1_ext,
+ input [2 : 0] rxstatus2_ext,
+ input [2 : 0] rxstatus3_ext,
+ input [2 : 0] rxstatus4_ext,
+ input [2 : 0] rxstatus5_ext,
+ input [2 : 0] rxstatus6_ext,
+ input [2 : 0] rxstatus7_ext,
+ input rxdataskip0_ext,
+ input rxdataskip1_ext,
+ input rxdataskip2_ext,
+ input rxdataskip3_ext,
+ input rxdataskip4_ext,
+ input rxdataskip5_ext,
+ input rxdataskip6_ext,
+ input rxdataskip7_ext,
+ input rxblkst0_ext,
+ input rxblkst1_ext,
+ input rxblkst2_ext,
+ input rxblkst3_ext,
+ input rxblkst4_ext,
+ input rxblkst5_ext,
+ input rxblkst6_ext,
+ input rxblkst7_ext,
+ input [1 : 0] rxsynchd0_ext,
+ input [1 : 0] rxsynchd1_ext,
+ input [1 : 0] rxsynchd2_ext,
+ input [1 : 0] rxsynchd3_ext,
+ input [1 : 0] rxsynchd4_ext,
+ input [1 : 0] rxsynchd5_ext,
+ input [1 : 0] rxsynchd6_ext,
+ input [1 : 0] rxsynchd7_ext,
+ input rxvalid0_ext,
+ input rxvalid1_ext,
+ input rxvalid2_ext,
+ input rxvalid3_ext,
+ input rxvalid4_ext,
+ input rxvalid5_ext,
+ input rxvalid6_ext,
+ input rxvalid7_ext,
+
+ output sim_pipe32_pclk,
+ output reg phystatus0_ext32b,
+ output reg phystatus1_ext32b,
+ output reg phystatus2_ext32b,
+ output reg phystatus3_ext32b,
+ output reg phystatus4_ext32b,
+ output reg phystatus5_ext32b,
+ output reg phystatus6_ext32b,
+ output reg phystatus7_ext32b,
+ output reg [31 : 0] rxdata0_ext32b,
+ output reg [31 : 0] rxdata1_ext32b,
+ output reg [31 : 0] rxdata2_ext32b,
+ output reg [31 : 0] rxdata3_ext32b,
+ output reg [31 : 0] rxdata4_ext32b,
+ output reg [31 : 0] rxdata5_ext32b,
+ output reg [31 : 0] rxdata6_ext32b,
+ output reg [31 : 0] rxdata7_ext32b,
+ output reg [3 : 0] rxdatak0_ext32b,
+ output reg [3 : 0] rxdatak1_ext32b,
+ output reg [3 : 0] rxdatak2_ext32b,
+ output reg [3 : 0] rxdatak3_ext32b,
+ output reg [3 : 0] rxdatak4_ext32b,
+ output reg [3 : 0] rxdatak5_ext32b,
+ output reg [3 : 0] rxdatak6_ext32b,
+ output reg [3 : 0] rxdatak7_ext32b,
+ output reg rxelecidle0_ext32b,
+ output reg rxelecidle1_ext32b,
+ output reg rxelecidle2_ext32b,
+ output reg rxelecidle3_ext32b,
+ output reg rxelecidle4_ext32b,
+ output reg rxelecidle5_ext32b,
+ output reg rxelecidle6_ext32b,
+ output reg rxelecidle7_ext32b,
+ output reg rxfreqlocked0_ext32b,
+ output reg rxfreqlocked1_ext32b,
+ output reg rxfreqlocked2_ext32b,
+ output reg rxfreqlocked3_ext32b,
+ output reg rxfreqlocked4_ext32b,
+ output reg rxfreqlocked5_ext32b,
+ output reg rxfreqlocked6_ext32b,
+ output reg rxfreqlocked7_ext32b,
+ output reg [2 : 0] rxstatus0_ext32b,
+ output reg [2 : 0] rxstatus1_ext32b,
+ output reg [2 : 0] rxstatus2_ext32b,
+ output reg [2 : 0] rxstatus3_ext32b,
+ output reg [2 : 0] rxstatus4_ext32b,
+ output reg [2 : 0] rxstatus5_ext32b,
+ output reg [2 : 0] rxstatus6_ext32b,
+ output reg [2 : 0] rxstatus7_ext32b,
+ output reg rxdataskip0_ext32b,
+ output reg rxdataskip1_ext32b,
+ output reg rxdataskip2_ext32b,
+ output reg rxdataskip3_ext32b,
+ output reg rxdataskip4_ext32b,
+ output reg rxdataskip5_ext32b,
+ output reg rxdataskip6_ext32b,
+ output reg rxdataskip7_ext32b,
+ output reg rxblkst0_ext32b,
+ output reg rxblkst1_ext32b,
+ output reg rxblkst2_ext32b,
+ output reg rxblkst3_ext32b,
+ output reg rxblkst4_ext32b,
+ output reg rxblkst5_ext32b,
+ output reg rxblkst6_ext32b,
+ output reg rxblkst7_ext32b,
+ output reg [1 : 0] rxsynchd0_ext32b,
+ output reg [1 : 0] rxsynchd1_ext32b,
+ output reg [1 : 0] rxsynchd2_ext32b,
+ output reg [1 : 0] rxsynchd3_ext32b,
+ output reg [1 : 0] rxsynchd4_ext32b,
+ output reg [1 : 0] rxsynchd5_ext32b,
+ output reg [1 : 0] rxsynchd6_ext32b,
+ output reg [1 : 0] rxsynchd7_ext32b,
+ output reg rxvalid0_ext32b,
+ output reg rxvalid1_ext32b,
+ output reg rxvalid2_ext32b,
+ output reg rxvalid3_ext32b,
+ output reg rxvalid4_ext32b,
+ output reg rxvalid5_ext32b,
+ output reg rxvalid6_ext32b,
+ output reg rxvalid7_ext32b
+ );
+
+ reg [1:0] cnt;
+ reg [1:0] cnt_rx;
+ genvar i;
+
+ reg [23 : 0] rxdata0_ext_i_32b;
+ reg [23 : 0] rxdata1_ext_i_32b;
+ reg [23 : 0] rxdata2_ext_i_32b;
+ reg [23 : 0] rxdata3_ext_i_32b;
+ reg [23 : 0] rxdata4_ext_i_32b;
+ reg [23 : 0] rxdata5_ext_i_32b;
+ reg [23 : 0] rxdata6_ext_i_32b;
+ reg [23 : 0] rxdata7_ext_i_32b;
+ reg [2 : 0] rxdatak0_ext_i_32b;
+ reg [2 : 0] rxdatak1_ext_i_32b;
+ reg [2 : 0] rxdatak2_ext_i_32b;
+ reg [2 : 0] rxdatak3_ext_i_32b;
+ reg [2 : 0] rxdatak4_ext_i_32b;
+ reg [2 : 0] rxdatak5_ext_i_32b;
+ reg [2 : 0] rxdatak6_ext_i_32b;
+ reg [2 : 0] rxdatak7_ext_i_32b;
+
+ reg phystatus0_ext_r_32b;
+ reg phystatus1_ext_r_32b;
+ reg phystatus2_ext_r_32b;
+ reg phystatus3_ext_r_32b;
+ reg phystatus4_ext_r_32b;
+ reg phystatus5_ext_r_32b;
+ reg phystatus6_ext_r_32b;
+ reg phystatus7_ext_r_32b;
+ reg [31 : 0] rxdata0_ext_r_32b;
+ reg [31 : 0] rxdata1_ext_r_32b;
+ reg [31 : 0] rxdata2_ext_r_32b;
+ reg [31 : 0] rxdata3_ext_r_32b;
+ reg [31 : 0] rxdata4_ext_r_32b;
+ reg [31 : 0] rxdata5_ext_r_32b;
+ reg [31 : 0] rxdata6_ext_r_32b;
+ reg [31 : 0] rxdata7_ext_r_32b;
+ reg [3 : 0] rxdatak0_ext_r_32b;
+ reg [3 : 0] rxdatak1_ext_r_32b;
+ reg [3 : 0] rxdatak2_ext_r_32b;
+ reg [3 : 0] rxdatak3_ext_r_32b;
+ reg [3 : 0] rxdatak4_ext_r_32b;
+ reg [3 : 0] rxdatak5_ext_r_32b;
+ reg [3 : 0] rxdatak6_ext_r_32b;
+ reg [3 : 0] rxdatak7_ext_r_32b;
+ reg rxelecidle0_ext_r_32b;
+ reg rxelecidle1_ext_r_32b;
+ reg rxelecidle2_ext_r_32b;
+ reg rxelecidle3_ext_r_32b;
+ reg rxelecidle4_ext_r_32b;
+ reg rxelecidle5_ext_r_32b;
+ reg rxelecidle6_ext_r_32b;
+ reg rxelecidle7_ext_r_32b;
+ reg rxfreqlocked0_ext_r_32b;
+ reg rxfreqlocked1_ext_r_32b;
+ reg rxfreqlocked2_ext_r_32b;
+ reg rxfreqlocked3_ext_r_32b;
+ reg rxfreqlocked4_ext_r_32b;
+ reg rxfreqlocked5_ext_r_32b;
+ reg rxfreqlocked6_ext_r_32b;
+ reg rxfreqlocked7_ext_r_32b;
+ reg [2 : 0] rxstatus0_ext_r_32b;
+ reg [2 : 0] rxstatus1_ext_r_32b;
+ reg [2 : 0] rxstatus2_ext_r_32b;
+ reg [2 : 0] rxstatus3_ext_r_32b;
+ reg [2 : 0] rxstatus4_ext_r_32b;
+ reg [2 : 0] rxstatus5_ext_r_32b;
+ reg [2 : 0] rxstatus6_ext_r_32b;
+ reg [2 : 0] rxstatus7_ext_r_32b;
+ reg rxdataskip0_ext_r_32b;
+ reg rxdataskip1_ext_r_32b;
+ reg rxdataskip2_ext_r_32b;
+ reg rxdataskip3_ext_r_32b;
+ reg rxdataskip4_ext_r_32b;
+ reg rxdataskip5_ext_r_32b;
+ reg rxdataskip6_ext_r_32b;
+ reg rxdataskip7_ext_r_32b;
+ reg rxblkst0_ext_r_32b;
+ reg rxblkst1_ext_r_32b;
+ reg rxblkst2_ext_r_32b;
+ reg rxblkst3_ext_r_32b;
+ reg rxblkst4_ext_r_32b;
+ reg rxblkst5_ext_r_32b;
+ reg rxblkst6_ext_r_32b;
+ reg rxblkst7_ext_r_32b;
+ reg [1 : 0] rxsynchd0_ext_r_32b;
+ reg [1 : 0] rxsynchd1_ext_r_32b;
+ reg [1 : 0] rxsynchd2_ext_r_32b;
+ reg [1 : 0] rxsynchd3_ext_r_32b;
+ reg [1 : 0] rxsynchd4_ext_r_32b;
+ reg [1 : 0] rxsynchd5_ext_r_32b;
+ reg [1 : 0] rxsynchd6_ext_r_32b;
+ reg [1 : 0] rxsynchd7_ext_r_32b;
+ reg rxvalid0_ext_r_32b;
+ reg rxvalid1_ext_r_32b;
+ reg rxvalid2_ext_r_32b;
+ reg rxvalid3_ext_r_32b;
+ reg rxvalid4_ext_r_32b;
+ reg rxvalid5_ext_r_32b;
+ reg rxvalid6_ext_r_32b;
+ reg rxvalid7_ext_r_32b;
+
+ assign sim_pipe32_pclk = cnt[1];
+
+ assign rxvalid_ext = rxvalid0_ext;
+
+ always @(posedge sim_pipe32_pclk or negedge aclr) begin
+ if (aclr == 1'b0) begin
+ phystatus0_ext32b<= 0;
+ phystatus1_ext32b<= 0;
+ phystatus2_ext32b<= 0;
+ phystatus3_ext32b<= 0;
+ phystatus4_ext32b<= 0;
+ phystatus5_ext32b<= 0;
+ phystatus6_ext32b<= 0;
+ phystatus7_ext32b<= 0;
+ rxdata0_ext32b<= 0;
+ rxdata1_ext32b<= 0;
+ rxdata2_ext32b<= 0;
+ rxdata3_ext32b<= 0;
+ rxdata4_ext32b<= 0;
+ rxdata5_ext32b<= 0;
+ rxdata6_ext32b<= 0;
+ rxdata7_ext32b<= 0;
+ rxdatak0_ext32b<= 0;
+ rxdatak1_ext32b<= 0;
+ rxdatak2_ext32b<= 0;
+ rxdatak3_ext32b<= 0;
+ rxdatak4_ext32b<= 0;
+ rxdatak5_ext32b<= 0;
+ rxdatak6_ext32b<= 0;
+ rxdatak7_ext32b<= 0;
+ rxelecidle0_ext32b<= 0;
+ rxelecidle1_ext32b<= 0;
+ rxelecidle2_ext32b<= 0;
+ rxelecidle3_ext32b<= 0;
+ rxelecidle4_ext32b<= 0;
+ rxelecidle5_ext32b<= 0;
+ rxelecidle6_ext32b<= 0;
+ rxelecidle7_ext32b<= 0;
+ rxfreqlocked0_ext32b<= 0;
+ rxfreqlocked1_ext32b<= 0;
+ rxfreqlocked2_ext32b<= 0;
+ rxfreqlocked3_ext32b<= 0;
+ rxfreqlocked4_ext32b<= 0;
+ rxfreqlocked5_ext32b<= 0;
+ rxfreqlocked6_ext32b<= 0;
+ rxfreqlocked7_ext32b<= 0;
+ rxstatus0_ext32b<= 0;
+ rxstatus1_ext32b<= 0;
+ rxstatus2_ext32b<= 0;
+ rxstatus3_ext32b<= 0;
+ rxstatus4_ext32b<= 0;
+ rxstatus5_ext32b<= 0;
+ rxstatus6_ext32b<= 0;
+ rxstatus7_ext32b<= 0;
+ rxdataskip0_ext32b<= 0;
+ rxdataskip1_ext32b<= 0;
+ rxdataskip2_ext32b<= 0;
+ rxdataskip3_ext32b<= 0;
+ rxdataskip4_ext32b<= 0;
+ rxdataskip5_ext32b<= 0;
+ rxdataskip6_ext32b<= 0;
+ rxdataskip7_ext32b<= 0;
+ rxblkst0_ext32b<= 0;
+ rxblkst1_ext32b<= 0;
+ rxblkst2_ext32b<= 0;
+ rxblkst3_ext32b<= 0;
+ rxblkst4_ext32b<= 0;
+ rxblkst5_ext32b<= 0;
+ rxblkst6_ext32b<= 0;
+ rxblkst7_ext32b<= 0;
+ rxsynchd0_ext32b<= 0;
+ rxsynchd1_ext32b<= 0;
+ rxsynchd2_ext32b<= 0;
+ rxsynchd3_ext32b<= 0;
+ rxsynchd4_ext32b<= 0;
+ rxsynchd5_ext32b<= 0;
+ rxsynchd6_ext32b<= 0;
+ rxsynchd7_ext32b<= 0;
+ rxvalid0_ext32b<= 0;
+ rxvalid1_ext32b<= 0;
+ rxvalid2_ext32b<= 0;
+ rxvalid3_ext32b<= 0;
+ rxvalid4_ext32b<= 0;
+ rxvalid5_ext32b<= 0;
+ rxvalid6_ext32b<= 0;
+ rxvalid7_ext32b<= 0;
+ end
+ else begin
+ phystatus0_ext32b<= phystatus0_ext_r_32b;
+ phystatus1_ext32b<= phystatus1_ext_r_32b;
+ phystatus2_ext32b<= phystatus2_ext_r_32b;
+ phystatus3_ext32b<= phystatus3_ext_r_32b;
+ phystatus4_ext32b<= phystatus4_ext_r_32b;
+ phystatus5_ext32b<= phystatus5_ext_r_32b;
+ phystatus6_ext32b<= phystatus6_ext_r_32b;
+ phystatus7_ext32b<= phystatus7_ext_r_32b;
+ rxdata0_ext32b<= rxdata0_ext_r_32b;
+ rxdata1_ext32b<= rxdata1_ext_r_32b;
+ rxdata2_ext32b<= rxdata2_ext_r_32b;
+ rxdata3_ext32b<= rxdata3_ext_r_32b;
+ rxdata4_ext32b<= rxdata4_ext_r_32b;
+ rxdata5_ext32b<= rxdata5_ext_r_32b;
+ rxdata6_ext32b<= rxdata6_ext_r_32b;
+ rxdata7_ext32b<= rxdata7_ext_r_32b;
+ rxdatak0_ext32b<= rxdatak0_ext_r_32b;
+ rxdatak1_ext32b<= rxdatak1_ext_r_32b;
+ rxdatak2_ext32b<= rxdatak2_ext_r_32b;
+ rxdatak3_ext32b<= rxdatak3_ext_r_32b;
+ rxdatak4_ext32b<= rxdatak4_ext_r_32b;
+ rxdatak5_ext32b<= rxdatak5_ext_r_32b;
+ rxdatak6_ext32b<= rxdatak6_ext_r_32b;
+ rxdatak7_ext32b<= rxdatak7_ext_r_32b;
+ rxelecidle0_ext32b<= rxelecidle0_ext_r_32b;
+ rxelecidle1_ext32b<= rxelecidle1_ext_r_32b;
+ rxelecidle2_ext32b<= rxelecidle2_ext_r_32b;
+ rxelecidle3_ext32b<= rxelecidle3_ext_r_32b;
+ rxelecidle4_ext32b<= rxelecidle4_ext_r_32b;
+ rxelecidle5_ext32b<= rxelecidle5_ext_r_32b;
+ rxelecidle6_ext32b<= rxelecidle6_ext_r_32b;
+ rxelecidle7_ext32b<= rxelecidle7_ext_r_32b;
+ rxfreqlocked0_ext32b<= rxfreqlocked0_ext_r_32b;
+ rxfreqlocked1_ext32b<= rxfreqlocked1_ext_r_32b;
+ rxfreqlocked2_ext32b<= rxfreqlocked2_ext_r_32b;
+ rxfreqlocked3_ext32b<= rxfreqlocked3_ext_r_32b;
+ rxfreqlocked4_ext32b<= rxfreqlocked4_ext_r_32b;
+ rxfreqlocked5_ext32b<= rxfreqlocked5_ext_r_32b;
+ rxfreqlocked6_ext32b<= rxfreqlocked6_ext_r_32b;
+ rxfreqlocked7_ext32b<= rxfreqlocked7_ext_r_32b;
+ rxstatus0_ext32b<= rxstatus0_ext_r_32b;
+ rxstatus1_ext32b<= rxstatus1_ext_r_32b;
+ rxstatus2_ext32b<= rxstatus2_ext_r_32b;
+ rxstatus3_ext32b<= rxstatus3_ext_r_32b;
+ rxstatus4_ext32b<= rxstatus4_ext_r_32b;
+ rxstatus5_ext32b<= rxstatus5_ext_r_32b;
+ rxstatus6_ext32b<= rxstatus6_ext_r_32b;
+ rxstatus7_ext32b<= rxstatus7_ext_r_32b;
+ rxdataskip0_ext32b<= rxdataskip0_ext_r_32b;
+ rxdataskip1_ext32b<= rxdataskip1_ext_r_32b;
+ rxdataskip2_ext32b<= rxdataskip2_ext_r_32b;
+ rxdataskip3_ext32b<= rxdataskip3_ext_r_32b;
+ rxdataskip4_ext32b<= rxdataskip4_ext_r_32b;
+ rxdataskip5_ext32b<= rxdataskip5_ext_r_32b;
+ rxdataskip6_ext32b<= rxdataskip6_ext_r_32b;
+ rxdataskip7_ext32b<= rxdataskip7_ext_r_32b;
+ rxblkst0_ext32b<= rxblkst0_ext_r_32b;
+ rxblkst1_ext32b<= rxblkst1_ext_r_32b;
+ rxblkst2_ext32b<= rxblkst2_ext_r_32b;
+ rxblkst3_ext32b<= rxblkst3_ext_r_32b;
+ rxblkst4_ext32b<= rxblkst4_ext_r_32b;
+ rxblkst5_ext32b<= rxblkst5_ext_r_32b;
+ rxblkst6_ext32b<= rxblkst6_ext_r_32b;
+ rxblkst7_ext32b<= rxblkst7_ext_r_32b;
+ rxsynchd0_ext32b<= rxsynchd0_ext_r_32b;
+ rxsynchd1_ext32b<= rxsynchd1_ext_r_32b;
+ rxsynchd2_ext32b<= rxsynchd2_ext_r_32b;
+ rxsynchd3_ext32b<= rxsynchd3_ext_r_32b;
+ rxsynchd4_ext32b<= rxsynchd4_ext_r_32b;
+ rxsynchd5_ext32b<= rxsynchd5_ext_r_32b;
+ rxsynchd6_ext32b<= rxsynchd6_ext_r_32b;
+ rxsynchd7_ext32b<= rxsynchd7_ext_r_32b;
+ rxvalid0_ext32b<= rxvalid0_ext_r_32b;
+ rxvalid1_ext32b<= rxvalid1_ext_r_32b;
+ rxvalid2_ext32b<= rxvalid2_ext_r_32b;
+ rxvalid3_ext32b<= rxvalid3_ext_r_32b;
+ rxvalid4_ext32b<= rxvalid4_ext_r_32b;
+ rxvalid5_ext32b<= rxvalid5_ext_r_32b;
+ rxvalid6_ext32b<= rxvalid6_ext_r_32b;
+ rxvalid7_ext32b<= rxvalid7_ext_r_32b;
+ end
+ end
+
+ always @(posedge sim_pipe8_pclk or negedge aclr) begin
+ if (aclr == 1'b0) begin
+ cnt <=4'h0;
+ phystatus0_ext_r_32b <= 0;
+ phystatus1_ext_r_32b <= 0;
+ phystatus2_ext_r_32b <= 0;
+ phystatus3_ext_r_32b <= 0;
+ phystatus4_ext_r_32b <= 0;
+ phystatus5_ext_r_32b <= 0;
+ phystatus6_ext_r_32b <= 0;
+ phystatus7_ext_r_32b <= 0;
+ rxelecidle0_ext_r_32b <= 0;
+ rxelecidle1_ext_r_32b <= 0;
+ rxelecidle2_ext_r_32b <= 0;
+ rxelecidle3_ext_r_32b <= 0;
+ rxelecidle4_ext_r_32b <= 0;
+ rxelecidle5_ext_r_32b <= 0;
+ rxelecidle6_ext_r_32b <= 0;
+ rxelecidle7_ext_r_32b <= 0;
+ rxfreqlocked0_ext_r_32b <= 0;
+ rxfreqlocked1_ext_r_32b <= 0;
+ rxfreqlocked2_ext_r_32b <= 0;
+ rxfreqlocked3_ext_r_32b <= 0;
+ rxfreqlocked4_ext_r_32b <= 0;
+ rxfreqlocked5_ext_r_32b <= 0;
+ rxfreqlocked6_ext_r_32b <= 0;
+ rxfreqlocked7_ext_r_32b <= 0;
+ rxstatus0_ext_r_32b <= 0;
+ rxstatus1_ext_r_32b <= 0;
+ rxstatus2_ext_r_32b <= 0;
+ rxstatus3_ext_r_32b <= 0;
+ rxstatus4_ext_r_32b <= 0;
+ rxstatus5_ext_r_32b <= 0;
+ rxstatus6_ext_r_32b <= 0;
+ rxstatus7_ext_r_32b <= 0;
+ rxdataskip0_ext_r_32b <= 0;
+ rxdataskip1_ext_r_32b <= 0;
+ rxdataskip2_ext_r_32b <= 0;
+ rxdataskip3_ext_r_32b <= 0;
+ rxdataskip4_ext_r_32b <= 0;
+ rxdataskip5_ext_r_32b <= 0;
+ rxdataskip6_ext_r_32b <= 0;
+ rxdataskip7_ext_r_32b <= 0;
+ rxblkst0_ext_r_32b <= 0;
+ rxblkst1_ext_r_32b <= 0;
+ rxblkst2_ext_r_32b <= 0;
+ rxblkst3_ext_r_32b <= 0;
+ rxblkst4_ext_r_32b <= 0;
+ rxblkst5_ext_r_32b <= 0;
+ rxblkst6_ext_r_32b <= 0;
+ rxblkst7_ext_r_32b <= 0;
+ rxsynchd0_ext_r_32b <= 0;
+ rxsynchd1_ext_r_32b <= 0;
+ rxsynchd2_ext_r_32b <= 0;
+ rxsynchd3_ext_r_32b <= 0;
+ rxsynchd4_ext_r_32b <= 0;
+ rxsynchd5_ext_r_32b <= 0;
+ rxsynchd6_ext_r_32b <= 0;
+ rxsynchd7_ext_r_32b <= 0;
+ rxvalid0_ext_r_32b <= 0;
+ rxvalid1_ext_r_32b <= 0;
+ rxvalid2_ext_r_32b <= 0;
+ rxvalid3_ext_r_32b <= 0;
+ rxvalid4_ext_r_32b <= 0;
+ rxvalid5_ext_r_32b <= 0;
+ rxvalid6_ext_r_32b <= 0;
+ rxvalid7_ext_r_32b <= 0;
+ {rxdata0_ext_r_32b, rxdatak0_ext_r_32b}<=36'h0;
+ {rxdata1_ext_r_32b, rxdatak1_ext_r_32b}<=36'h0;
+ {rxdata2_ext_r_32b, rxdatak2_ext_r_32b}<=36'h0;
+ {rxdata3_ext_r_32b, rxdatak3_ext_r_32b}<=36'h0;
+ {rxdata4_ext_r_32b, rxdatak4_ext_r_32b}<=36'h0;
+ {rxdata5_ext_r_32b, rxdatak5_ext_r_32b}<=36'h0;
+ {rxdata6_ext_r_32b, rxdatak6_ext_r_32b}<=36'h0;
+ {rxdata7_ext_r_32b, rxdatak7_ext_r_32b}<=36'h0;
+ end
+ else begin
+ if (rxvalid_ext==1'b1) begin
+ cnt_rx <=cnt_rx+2'h1;
+ end
+ else begin
+ cnt_rx <=2'h0;
+ end
+
+ if (cnt_rx==2'b11) begin
+ {rxdata0_ext_r_32b, rxdatak0_ext_r_32b}<= (rxvalid0_ext==1'b0)?36'h0:{rxdata0_ext,rxdata0_ext_i_32b[23:0], rxdatak0_ext, rxdatak0_ext_i_32b[2:0]};
+ {rxdata1_ext_r_32b, rxdatak1_ext_r_32b}<= (rxvalid1_ext==1'b0)?36'h0:{rxdata1_ext,rxdata1_ext_i_32b[23:0], rxdatak1_ext, rxdatak1_ext_i_32b[2:0]};
+ {rxdata2_ext_r_32b, rxdatak2_ext_r_32b}<= (rxvalid2_ext==1'b0)?36'h0:{rxdata2_ext,rxdata2_ext_i_32b[23:0], rxdatak2_ext, rxdatak2_ext_i_32b[2:0]};
+ {rxdata3_ext_r_32b, rxdatak3_ext_r_32b}<= (rxvalid3_ext==1'b0)?36'h0:{rxdata3_ext,rxdata3_ext_i_32b[23:0], rxdatak3_ext, rxdatak3_ext_i_32b[2:0]};
+ {rxdata4_ext_r_32b, rxdatak4_ext_r_32b}<= (rxvalid4_ext==1'b0)?36'h0:{rxdata4_ext,rxdata4_ext_i_32b[23:0], rxdatak4_ext, rxdatak4_ext_i_32b[2:0]};
+ {rxdata5_ext_r_32b, rxdatak5_ext_r_32b}<= (rxvalid5_ext==1'b0)?36'h0:{rxdata5_ext,rxdata5_ext_i_32b[23:0], rxdatak5_ext, rxdatak5_ext_i_32b[2:0]};
+ {rxdata6_ext_r_32b, rxdatak6_ext_r_32b}<= (rxvalid6_ext==1'b0)?36'h0:{rxdata6_ext,rxdata6_ext_i_32b[23:0], rxdatak6_ext, rxdatak6_ext_i_32b[2:0]};
+ {rxdata7_ext_r_32b, rxdatak7_ext_r_32b}<= (rxvalid7_ext==1'b0)?36'h0:{rxdata7_ext,rxdata7_ext_i_32b[23:0], rxdatak7_ext, rxdatak7_ext_i_32b[2:0]};
+ end
+
+ if (1==1) begin
+ cnt <=cnt+2'h1;
+ phystatus0_ext_r_32b <= ((phystatus0_ext_r_32b==1'b0)||(cnt==2'b11))?phystatus0_ext:1'b1;
+ phystatus1_ext_r_32b <= ((phystatus1_ext_r_32b==1'b0)||(cnt==2'b11))?phystatus1_ext:1'b1;
+ phystatus2_ext_r_32b <= ((phystatus2_ext_r_32b==1'b0)||(cnt==2'b11))?phystatus2_ext:1'b1;
+ phystatus3_ext_r_32b <= ((phystatus3_ext_r_32b==1'b0)||(cnt==2'b11))?phystatus3_ext:1'b1;
+ phystatus4_ext_r_32b <= ((phystatus4_ext_r_32b==1'b0)||(cnt==2'b11))?phystatus4_ext:1'b1;
+ phystatus5_ext_r_32b <= ((phystatus5_ext_r_32b==1'b0)||(cnt==2'b11))?phystatus5_ext:1'b1;
+ phystatus6_ext_r_32b <= ((phystatus6_ext_r_32b==1'b0)||(cnt==2'b11))?phystatus6_ext:1'b1;
+ phystatus7_ext_r_32b <= ((phystatus7_ext_r_32b==1'b0)||(cnt==2'b11))?phystatus7_ext:1'b1;
+ rxelecidle0_ext_r_32b <= rxelecidle0_ext;
+ rxelecidle1_ext_r_32b <= rxelecidle1_ext;
+ rxelecidle2_ext_r_32b <= rxelecidle2_ext;
+ rxelecidle3_ext_r_32b <= rxelecidle3_ext;
+ rxelecidle4_ext_r_32b <= rxelecidle4_ext;
+ rxelecidle5_ext_r_32b <= rxelecidle5_ext;
+ rxelecidle6_ext_r_32b <= rxelecidle6_ext;
+ rxelecidle7_ext_r_32b <= rxelecidle7_ext;
+ rxfreqlocked0_ext_r_32b <= rxfreqlocked0_ext;
+ rxfreqlocked1_ext_r_32b <= rxfreqlocked1_ext;
+ rxfreqlocked2_ext_r_32b <= rxfreqlocked2_ext;
+ rxfreqlocked3_ext_r_32b <= rxfreqlocked3_ext;
+ rxfreqlocked4_ext_r_32b <= rxfreqlocked4_ext;
+ rxfreqlocked5_ext_r_32b <= rxfreqlocked5_ext;
+ rxfreqlocked6_ext_r_32b <= rxfreqlocked6_ext;
+ rxfreqlocked7_ext_r_32b <= rxfreqlocked7_ext;
+ rxstatus0_ext_r_32b <= ((rxstatus0_ext_r_32b==3'h4)||(rxstatus0_ext_r_32b==3'h0)||(cnt==2'b11))?rxstatus0_ext:3'h3;
+ rxstatus1_ext_r_32b <= ((rxstatus1_ext_r_32b==3'h4)||(rxstatus1_ext_r_32b==3'h0)||(cnt==2'b11))?rxstatus1_ext:3'h3;
+ rxstatus2_ext_r_32b <= ((rxstatus2_ext_r_32b==3'h4)||(rxstatus2_ext_r_32b==3'h0)||(cnt==2'b11))?rxstatus2_ext:3'h3;
+ rxstatus3_ext_r_32b <= ((rxstatus3_ext_r_32b==3'h4)||(rxstatus3_ext_r_32b==3'h0)||(cnt==2'b11))?rxstatus3_ext:3'h3;
+ rxstatus4_ext_r_32b <= ((rxstatus4_ext_r_32b==3'h4)||(rxstatus4_ext_r_32b==3'h0)||(cnt==2'b11))?rxstatus4_ext:3'h3;
+ rxstatus5_ext_r_32b <= ((rxstatus5_ext_r_32b==3'h4)||(rxstatus5_ext_r_32b==3'h0)||(cnt==2'b11))?rxstatus5_ext:3'h3;
+ rxstatus6_ext_r_32b <= ((rxstatus6_ext_r_32b==3'h4)||(rxstatus6_ext_r_32b==3'h0)||(cnt==2'b11))?rxstatus6_ext:3'h3;
+ rxstatus7_ext_r_32b <= ((rxstatus7_ext_r_32b==3'h4)||(rxstatus7_ext_r_32b==3'h0)||(cnt==2'b11))?rxstatus7_ext:3'h3;
+ rxdataskip0_ext_r_32b <= rxdataskip0_ext;
+ rxdataskip1_ext_r_32b <= rxdataskip1_ext;
+ rxdataskip2_ext_r_32b <= rxdataskip2_ext;
+ rxdataskip3_ext_r_32b <= rxdataskip3_ext;
+ rxdataskip4_ext_r_32b <= rxdataskip4_ext;
+ rxdataskip5_ext_r_32b <= rxdataskip5_ext;
+ rxdataskip6_ext_r_32b <= rxdataskip6_ext;
+ rxdataskip7_ext_r_32b <= rxdataskip7_ext;
+ rxblkst0_ext_r_32b <= rxblkst0_ext;
+ rxblkst1_ext_r_32b <= rxblkst1_ext;
+ rxblkst2_ext_r_32b <= rxblkst2_ext;
+ rxblkst3_ext_r_32b <= rxblkst3_ext;
+ rxblkst4_ext_r_32b <= rxblkst4_ext;
+ rxblkst5_ext_r_32b <= rxblkst5_ext;
+ rxblkst6_ext_r_32b <= rxblkst6_ext;
+ rxblkst7_ext_r_32b <= rxblkst7_ext;
+ rxsynchd0_ext_r_32b <= rxsynchd0_ext;
+ rxsynchd1_ext_r_32b <= rxsynchd1_ext;
+ rxsynchd2_ext_r_32b <= rxsynchd2_ext;
+ rxsynchd3_ext_r_32b <= rxsynchd3_ext;
+ rxsynchd4_ext_r_32b <= rxsynchd4_ext;
+ rxsynchd5_ext_r_32b <= rxsynchd5_ext;
+ rxsynchd6_ext_r_32b <= rxsynchd6_ext;
+ rxsynchd7_ext_r_32b <= rxsynchd7_ext;
+ rxvalid0_ext_r_32b <= rxvalid0_ext;
+ rxvalid1_ext_r_32b <= rxvalid1_ext;
+ rxvalid2_ext_r_32b <= rxvalid2_ext;
+ rxvalid3_ext_r_32b <= rxvalid3_ext;
+ rxvalid4_ext_r_32b <= rxvalid4_ext;
+ rxvalid5_ext_r_32b <= rxvalid5_ext;
+ rxvalid6_ext_r_32b <= rxvalid6_ext;
+ rxvalid7_ext_r_32b <= rxvalid7_ext;
+ end
+ end
+ end
+
+ generate
+ for (i=0;i<3;i=i+1) begin : g_pipe
+ always @(posedge sim_pipe8_pclk or negedge aclr) begin
+ if (aclr == 1'b0) begin
+ rxdata0_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata1_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata2_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata3_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata4_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata5_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata6_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata7_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+
+ rxdatak0_ext_i_32b[i] <= 1'h0;
+ rxdatak1_ext_i_32b[i] <= 1'h0;
+ rxdatak2_ext_i_32b[i] <= 1'h0;
+ rxdatak3_ext_i_32b[i] <= 1'h0;
+ rxdatak4_ext_i_32b[i] <= 1'h0;
+ rxdatak5_ext_i_32b[i] <= 1'h0;
+ rxdatak6_ext_i_32b[i] <= 1'h0;
+ rxdatak7_ext_i_32b[i] <= 1'h0;
+ end
+ else begin
+ if (cnt_rx==i) begin
+ rxdata0_ext_i_32b[((i+1)*8)-1:i*8] <= rxdata0_ext[7:0];
+ rxdata1_ext_i_32b[((i+1)*8)-1:i*8] <= rxdata1_ext[7:0];
+ rxdata2_ext_i_32b[((i+1)*8)-1:i*8] <= rxdata2_ext[7:0];
+ rxdata3_ext_i_32b[((i+1)*8)-1:i*8] <= rxdata3_ext[7:0];
+ rxdata4_ext_i_32b[((i+1)*8)-1:i*8] <= rxdata4_ext[7:0];
+ rxdata5_ext_i_32b[((i+1)*8)-1:i*8] <= rxdata5_ext[7:0];
+ rxdata6_ext_i_32b[((i+1)*8)-1:i*8] <= rxdata6_ext[7:0];
+ rxdata7_ext_i_32b[((i+1)*8)-1:i*8] <= rxdata7_ext[7:0];
+
+ rxdatak0_ext_i_32b[i] <= rxdatak0_ext;
+ rxdatak1_ext_i_32b[i] <= rxdatak1_ext;
+ rxdatak2_ext_i_32b[i] <= rxdatak2_ext;
+ rxdatak3_ext_i_32b[i] <= rxdatak3_ext;
+ rxdatak4_ext_i_32b[i] <= rxdatak4_ext;
+ rxdatak5_ext_i_32b[i] <= rxdatak5_ext;
+ rxdatak6_ext_i_32b[i] <= rxdatak6_ext;
+ rxdatak7_ext_i_32b[i] <= rxdatak7_ext;
+ end
+ else if (((cnt_rx==0) && (i>0)) || (cnt_rx==i-1)) begin
+ rxdata0_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata1_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata2_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata3_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata4_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata5_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata6_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+ rxdata7_ext_i_32b[((i+1)*8)-1:i*8] <= 8'h0;
+
+ rxdatak0_ext_i_32b[i] <= 1'h0;
+ rxdatak1_ext_i_32b[i] <= 1'h0;
+ rxdatak2_ext_i_32b[i] <= 1'h0;
+ rxdatak3_ext_i_32b[i] <= 1'h0;
+ rxdatak4_ext_i_32b[i] <= 1'h0;
+ rxdatak5_ext_i_32b[i] <= 1'h0;
+ rxdatak6_ext_i_32b[i] <= 1'h0;
+ rxdatak7_ext_i_32b[i] <= 1'h0;
+ end
+ end
+ end
+ end
+ endgenerate
+
+endmodule
+
+module sim_txpipe_8bit_to_32_bit (
+ input sim_pipe8_pclk,
+ input sim_pipe32_pclk,
+ input aclr,
+ input pipe_mode_simu_only,
+
+ input [2 : 0] eidleinfersel0,
+ input [2 : 0] eidleinfersel1,
+ input [2 : 0] eidleinfersel2,
+ input [2 : 0] eidleinfersel3,
+ input [2 : 0] eidleinfersel4,
+ input [2 : 0] eidleinfersel5,
+ input [2 : 0] eidleinfersel6,
+ input [2 : 0] eidleinfersel7,
+ input [1 : 0] powerdown0,
+ input [1 : 0] powerdown1,
+ input [1 : 0] powerdown2,
+ input [1 : 0] powerdown3,
+ input [1 : 0] powerdown4,
+ input [1 : 0] powerdown5,
+ input [1 : 0] powerdown6,
+ input [1 : 0] powerdown7,
+ input rxpolarity0,
+ input rxpolarity1,
+ input rxpolarity2,
+ input rxpolarity3,
+ input rxpolarity4,
+ input rxpolarity5,
+ input rxpolarity6,
+ input rxpolarity7,
+ input txcompl0,
+ input txcompl1,
+ input txcompl2,
+ input txcompl3,
+ input txcompl4,
+ input txcompl5,
+ input txcompl6,
+ input txcompl7,
+ input [31 : 0] txdata0,
+ input [31 : 0] txdata1,
+ input [31 : 0] txdata2,
+ input [31 : 0] txdata3,
+ input [31 : 0] txdata4,
+ input [31 : 0] txdata5,
+ input [31 : 0] txdata6,
+ input [31 : 0] txdata7,
+ input [3 : 0] txdatak0,
+ input [3 : 0] txdatak1,
+ input [3 : 0] txdatak2,
+ input [3 : 0] txdatak3,
+ input [3 : 0] txdatak4,
+ input [3 : 0] txdatak5,
+ input [3 : 0] txdatak6,
+ input [3 : 0] txdatak7,
+ //input txdatavalid0,
+ //input txdatavalid1,
+ //input txdatavalid2,
+ //input txdatavalid3,
+ //input txdatavalid4,
+ //input txdatavalid5,
+ //input txdatavalid6,
+ //input txdatavalid7,
+ input txdetectrx0,
+ input txdetectrx1,
+ input txdetectrx2,
+ input txdetectrx3,
+ input txdetectrx4,
+ input txdetectrx5,
+ input txdetectrx6,
+ input txdetectrx7,
+ input txelecidle0,
+ input txelecidle1,
+ input txelecidle2,
+ input txelecidle3,
+ input txelecidle4,
+ input txelecidle5,
+ input txelecidle6,
+ input txelecidle7,
+ input [2 : 0] txmargin0,
+ input [2 : 0] txmargin1,
+ input [2 : 0] txmargin2,
+ input [2 : 0] txmargin3,
+ input [2 : 0] txmargin4,
+ input [2 : 0] txmargin5,
+ input [2 : 0] txmargin6,
+ input [2 : 0] txmargin7,
+ input txdeemph0,
+ input txdeemph1,
+ input txdeemph2,
+ input txdeemph3,
+ input txdeemph4,
+ input txdeemph5,
+ input txdeemph6,
+ input txdeemph7,
+ input txblkst0,
+ input txblkst1,
+ input txblkst2,
+ input txblkst3,
+ input txblkst4,
+ input txblkst5,
+ input txblkst6,
+ input txblkst7,
+ input [1 : 0] txsynchd0,
+ input [1 : 0] txsynchd1,
+ input [1 : 0] txsynchd2,
+ input [1 : 0] txsynchd3,
+ input [1 : 0] txsynchd4,
+ input [1 : 0] txsynchd5,
+ input [1 : 0] txsynchd6,
+ input [1 : 0] txsynchd7,
+ input [17 : 0] currentcoeff0,
+ input [17 : 0] currentcoeff1,
+ input [17 : 0] currentcoeff2,
+ input [17 : 0] currentcoeff3,
+ input [17 : 0] currentcoeff4,
+ input [17 : 0] currentcoeff5,
+ input [17 : 0] currentcoeff6,
+ input [17 : 0] currentcoeff7,
+ input [2 : 0] currentrxpreset0,
+ input [2 : 0] currentrxpreset1,
+ input [2 : 0] currentrxpreset2,
+ input [2 : 0] currentrxpreset3,
+ input [2 : 0] currentrxpreset4,
+ input [2 : 0] currentrxpreset5,
+ input [2 : 0] currentrxpreset6,
+ input [2 : 0] currentrxpreset7,
+
+ output [2 : 0] eidleinfersel0_ext,
+ output [2 : 0] eidleinfersel1_ext,
+ output [2 : 0] eidleinfersel2_ext,
+ output [2 : 0] eidleinfersel3_ext,
+ output [2 : 0] eidleinfersel4_ext,
+ output [2 : 0] eidleinfersel5_ext,
+ output [2 : 0] eidleinfersel6_ext,
+ output [2 : 0] eidleinfersel7_ext,
+ output [1 : 0] powerdown0_ext,
+ output [1 : 0] powerdown1_ext,
+ output [1 : 0] powerdown2_ext,
+ output [1 : 0] powerdown3_ext,
+ output [1 : 0] powerdown4_ext,
+ output [1 : 0] powerdown5_ext,
+ output [1 : 0] powerdown6_ext,
+ output [1 : 0] powerdown7_ext,
+ output rxpolarity0_ext,
+ output rxpolarity1_ext,
+ output rxpolarity2_ext,
+ output rxpolarity3_ext,
+ output rxpolarity4_ext,
+ output rxpolarity5_ext,
+ output rxpolarity6_ext,
+ output rxpolarity7_ext,
+ output txcompl0_ext,
+ output txcompl1_ext,
+ output txcompl2_ext,
+ output txcompl3_ext,
+ output txcompl4_ext,
+ output txcompl5_ext,
+ output txcompl6_ext,
+ output txcompl7_ext,
+ output [7 : 0] txdata0_ext,
+ output [7 : 0] txdata1_ext,
+ output [7 : 0] txdata2_ext,
+ output [7 : 0] txdata3_ext,
+ output [7 : 0] txdata4_ext,
+ output [7 : 0] txdata5_ext,
+ output [7 : 0] txdata6_ext,
+ output [7 : 0] txdata7_ext,
+ output txdatak0_ext,
+ output txdatak1_ext,
+ output txdatak2_ext,
+ output txdatak3_ext,
+ output txdatak4_ext,
+ output txdatak5_ext,
+ output txdatak6_ext,
+ output txdatak7_ext,
+ output txdetectrx0_ext,
+ output txdetectrx1_ext,
+ output txdetectrx2_ext,
+ output txdetectrx3_ext,
+ output txdetectrx4_ext,
+ output txdetectrx5_ext,
+ output txdetectrx6_ext,
+ output txdetectrx7_ext,
+ output txelecidle0_ext,
+ output txelecidle1_ext,
+ output txelecidle2_ext,
+ output txelecidle3_ext,
+ output txelecidle4_ext,
+ output txelecidle5_ext,
+ output txelecidle6_ext,
+ output txelecidle7_ext,
+ output [2 : 0] txmargin0_ext,
+ output [2 : 0] txmargin1_ext,
+ output [2 : 0] txmargin2_ext,
+ output [2 : 0] txmargin3_ext,
+ output [2 : 0] txmargin4_ext,
+ output [2 : 0] txmargin5_ext,
+ output [2 : 0] txmargin6_ext,
+ output [2 : 0] txmargin7_ext,
+ output txdeemph0_ext,
+ output txdeemph1_ext,
+ output txdeemph2_ext,
+ output txdeemph3_ext,
+ output txdeemph4_ext,
+ output txdeemph5_ext,
+ output txdeemph6_ext,
+ output txdeemph7_ext,
+ output txblkst0_ext,
+ output txblkst1_ext,
+ output txblkst2_ext,
+ output txblkst3_ext,
+ output txblkst4_ext,
+ output txblkst5_ext,
+ output txblkst6_ext,
+ output txblkst7_ext,
+ output [1 : 0] txsynchd0_ext,
+ output [1 : 0] txsynchd1_ext,
+ output [1 : 0] txsynchd2_ext,
+ output [1 : 0] txsynchd3_ext,
+ output [1 : 0] txsynchd4_ext,
+ output [1 : 0] txsynchd5_ext,
+ output [1 : 0] txsynchd6_ext,
+ output [1 : 0] txsynchd7_ext,
+ output [17 : 0] currentcoeff0_ext,
+ output [17 : 0] currentcoeff1_ext,
+ output [17 : 0] currentcoeff2_ext,
+ output [17 : 0] currentcoeff3_ext,
+ output [17 : 0] currentcoeff4_ext,
+ output [17 : 0] currentcoeff5_ext,
+ output [17 : 0] currentcoeff6_ext,
+ output [17 : 0] currentcoeff7_ext,
+ output [2 : 0] currentrxpreset0_ext,
+ output [2 : 0] currentrxpreset1_ext,
+ output [2 : 0] currentrxpreset2_ext,
+ output [2 : 0] currentrxpreset3_ext,
+ output [2 : 0] currentrxpreset4_ext,
+ output [2 : 0] currentrxpreset5_ext,
+ output [2 : 0] currentrxpreset6_ext,
+ output [2 : 0] currentrxpreset7_ext
+
+ );
+
+ reg [1:0] cnt_tx;
+ wire txelecidle;
+
+ assign txelecidle = txelecidle0&
+ txelecidle1&
+ txelecidle2&
+ txelecidle3&
+ txelecidle4&
+ txelecidle5&
+ txelecidle6&
+ txelecidle7;
+
+ always @(posedge sim_pipe8_pclk or negedge aclr) begin
+ if (aclr == 1'b0) begin
+ cnt_tx <=2'h0;
+ end
+ else begin
+ if (txelecidle==1'b0) begin
+ cnt_tx <=cnt_tx+2'h1;
+ end
+ else begin
+ cnt_tx <=2'h0;
+ end
+ end
+ end
+
+ assign txdata0_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdata0[7:0]: (cnt_tx==2'b01)?txdata0[15:8] : (cnt_tx==2'b10)?txdata0[23:16] : txdata0[31:24];
+ assign txdata1_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdata1[7:0]: (cnt_tx==2'b01)?txdata1[15:8] : (cnt_tx==2'b10)?txdata1[23:16] : txdata1[31:24];
+ assign txdata2_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdata2[7:0]: (cnt_tx==2'b01)?txdata2[15:8] : (cnt_tx==2'b10)?txdata2[23:16] : txdata2[31:24];
+ assign txdata3_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdata3[7:0]: (cnt_tx==2'b01)?txdata3[15:8] : (cnt_tx==2'b10)?txdata3[23:16] : txdata3[31:24];
+ assign txdata4_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdata4[7:0]: (cnt_tx==2'b01)?txdata4[15:8] : (cnt_tx==2'b10)?txdata4[23:16] : txdata4[31:24];
+ assign txdata5_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdata5[7:0]: (cnt_tx==2'b01)?txdata5[15:8] : (cnt_tx==2'b10)?txdata5[23:16] : txdata5[31:24];
+ assign txdata6_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdata6[7:0]: (cnt_tx==2'b01)?txdata6[15:8] : (cnt_tx==2'b10)?txdata6[23:16] : txdata6[31:24];
+ assign txdata7_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdata7[7:0]: (cnt_tx==2'b01)?txdata7[15:8] : (cnt_tx==2'b10)?txdata7[23:16] : txdata7[31:24];
+ assign txdatak0_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdatak0[ 0]: (cnt_tx==2'b01)?txdatak0[ 1] : (cnt_tx==2'b10)?txdatak0[ 2] : txdatak0[ 3];
+ assign txdatak1_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdatak1[ 0]: (cnt_tx==2'b01)?txdatak1[ 1] : (cnt_tx==2'b10)?txdatak1[ 2] : txdatak1[ 3];
+ assign txdatak2_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdatak2[ 0]: (cnt_tx==2'b01)?txdatak2[ 1] : (cnt_tx==2'b10)?txdatak2[ 2] : txdatak2[ 3];
+ assign txdatak3_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdatak3[ 0]: (cnt_tx==2'b01)?txdatak3[ 1] : (cnt_tx==2'b10)?txdatak3[ 2] : txdatak3[ 3];
+ assign txdatak4_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdatak4[ 0]: (cnt_tx==2'b01)?txdatak4[ 1] : (cnt_tx==2'b10)?txdatak4[ 2] : txdatak4[ 3];
+ assign txdatak5_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdatak5[ 0]: (cnt_tx==2'b01)?txdatak5[ 1] : (cnt_tx==2'b10)?txdatak5[ 2] : txdatak5[ 3];
+ assign txdatak6_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdatak6[ 0]: (cnt_tx==2'b01)?txdatak6[ 1] : (cnt_tx==2'b10)?txdatak6[ 2] : txdatak6[ 3];
+ assign txdatak7_ext = (pipe_mode_simu_only==1'b0)?0:(cnt_tx==2'b00)?txdatak7[ 0]: (cnt_tx==2'b01)?txdatak7[ 1] : (cnt_tx==2'b10)?txdatak7[ 2] : txdatak7[ 3];
+
+ assign eidleinfersel0_ext = (pipe_mode_simu_only==1'b0)?0:eidleinfersel0 ;
+ assign eidleinfersel1_ext = (pipe_mode_simu_only==1'b0)?0:eidleinfersel1 ;
+ assign eidleinfersel2_ext = (pipe_mode_simu_only==1'b0)?0:eidleinfersel2 ;
+ assign eidleinfersel3_ext = (pipe_mode_simu_only==1'b0)?0:eidleinfersel3 ;
+ assign eidleinfersel4_ext = (pipe_mode_simu_only==1'b0)?0:eidleinfersel4 ;
+ assign eidleinfersel5_ext = (pipe_mode_simu_only==1'b0)?0:eidleinfersel5 ;
+ assign eidleinfersel6_ext = (pipe_mode_simu_only==1'b0)?0:eidleinfersel6 ;
+ assign eidleinfersel7_ext = (pipe_mode_simu_only==1'b0)?0:eidleinfersel7 ;
+ assign powerdown0_ext = (pipe_mode_simu_only==1'b0)?0:powerdown0 ;
+ assign powerdown1_ext = (pipe_mode_simu_only==1'b0)?0:powerdown1 ;
+ assign powerdown2_ext = (pipe_mode_simu_only==1'b0)?0:powerdown2 ;
+ assign powerdown3_ext = (pipe_mode_simu_only==1'b0)?0:powerdown3 ;
+ assign powerdown4_ext = (pipe_mode_simu_only==1'b0)?0:powerdown4 ;
+ assign powerdown5_ext = (pipe_mode_simu_only==1'b0)?0:powerdown5 ;
+ assign powerdown6_ext = (pipe_mode_simu_only==1'b0)?0:powerdown6 ;
+ assign powerdown7_ext = (pipe_mode_simu_only==1'b0)?0:powerdown7 ;
+ assign rxpolarity0_ext = (pipe_mode_simu_only==1'b0)?0:rxpolarity0 ;
+ assign rxpolarity1_ext = (pipe_mode_simu_only==1'b0)?0:rxpolarity1 ;
+ assign rxpolarity2_ext = (pipe_mode_simu_only==1'b0)?0:rxpolarity2 ;
+ assign rxpolarity3_ext = (pipe_mode_simu_only==1'b0)?0:rxpolarity3 ;
+ assign rxpolarity4_ext = (pipe_mode_simu_only==1'b0)?0:rxpolarity4 ;
+ assign rxpolarity5_ext = (pipe_mode_simu_only==1'b0)?0:rxpolarity5 ;
+ assign rxpolarity6_ext = (pipe_mode_simu_only==1'b0)?0:rxpolarity6 ;
+ assign rxpolarity7_ext = (pipe_mode_simu_only==1'b0)?0:rxpolarity7 ;
+ assign txcompl0_ext = (pipe_mode_simu_only==1'b0)?0:txcompl0 ;
+ assign txcompl1_ext = (pipe_mode_simu_only==1'b0)?0:txcompl1 ;
+ assign txcompl2_ext = (pipe_mode_simu_only==1'b0)?0:txcompl2 ;
+ assign txcompl3_ext = (pipe_mode_simu_only==1'b0)?0:txcompl3 ;
+ assign txcompl4_ext = (pipe_mode_simu_only==1'b0)?0:txcompl4 ;
+ assign txcompl5_ext = (pipe_mode_simu_only==1'b0)?0:txcompl5 ;
+ assign txcompl6_ext = (pipe_mode_simu_only==1'b0)?0:txcompl6 ;
+ assign txcompl7_ext = (pipe_mode_simu_only==1'b0)?0:txcompl7 ;
+
+ assign txdetectrx0_ext = (pipe_mode_simu_only==1'b0)?0:txdetectrx0 ;
+ assign txdetectrx1_ext = (pipe_mode_simu_only==1'b0)?0:txdetectrx1 ;
+ assign txdetectrx2_ext = (pipe_mode_simu_only==1'b0)?0:txdetectrx2 ;
+ assign txdetectrx3_ext = (pipe_mode_simu_only==1'b0)?0:txdetectrx3 ;
+ assign txdetectrx4_ext = (pipe_mode_simu_only==1'b0)?0:txdetectrx4 ;
+ assign txdetectrx5_ext = (pipe_mode_simu_only==1'b0)?0:txdetectrx5 ;
+ assign txdetectrx6_ext = (pipe_mode_simu_only==1'b0)?0:txdetectrx6 ;
+ assign txdetectrx7_ext = (pipe_mode_simu_only==1'b0)?0:txdetectrx7 ;
+ assign txelecidle0_ext = (pipe_mode_simu_only==1'b0)?0:txelecidle0 ;
+ assign txelecidle1_ext = (pipe_mode_simu_only==1'b0)?0:txelecidle1 ;
+ assign txelecidle2_ext = (pipe_mode_simu_only==1'b0)?0:txelecidle2 ;
+ assign txelecidle3_ext = (pipe_mode_simu_only==1'b0)?0:txelecidle3 ;
+ assign txelecidle4_ext = (pipe_mode_simu_only==1'b0)?0:txelecidle4 ;
+ assign txelecidle5_ext = (pipe_mode_simu_only==1'b0)?0:txelecidle5 ;
+ assign txelecidle6_ext = (pipe_mode_simu_only==1'b0)?0:txelecidle6 ;
+ assign txelecidle7_ext = (pipe_mode_simu_only==1'b0)?0:txelecidle7 ;
+ assign txmargin0_ext = (pipe_mode_simu_only==1'b0)?0:txmargin0 ;
+ assign txmargin1_ext = (pipe_mode_simu_only==1'b0)?0:txmargin1 ;
+ assign txmargin2_ext = (pipe_mode_simu_only==1'b0)?0:txmargin2 ;
+ assign txmargin3_ext = (pipe_mode_simu_only==1'b0)?0:txmargin3 ;
+ assign txmargin4_ext = (pipe_mode_simu_only==1'b0)?0:txmargin4 ;
+ assign txmargin5_ext = (pipe_mode_simu_only==1'b0)?0:txmargin5 ;
+ assign txmargin6_ext = (pipe_mode_simu_only==1'b0)?0:txmargin6 ;
+ assign txmargin7_ext = (pipe_mode_simu_only==1'b0)?0:txmargin7 ;
+ assign txdeemph0_ext = (pipe_mode_simu_only==1'b0)?0:txdeemph0 ;
+ assign txdeemph1_ext = (pipe_mode_simu_only==1'b0)?0:txdeemph1 ;
+ assign txdeemph2_ext = (pipe_mode_simu_only==1'b0)?0:txdeemph2 ;
+ assign txdeemph3_ext = (pipe_mode_simu_only==1'b0)?0:txdeemph3 ;
+ assign txdeemph4_ext = (pipe_mode_simu_only==1'b0)?0:txdeemph4 ;
+ assign txdeemph5_ext = (pipe_mode_simu_only==1'b0)?0:txdeemph5 ;
+ assign txdeemph6_ext = (pipe_mode_simu_only==1'b0)?0:txdeemph6 ;
+ assign txdeemph7_ext = (pipe_mode_simu_only==1'b0)?0:txdeemph7 ;
+ assign txblkst0_ext = (pipe_mode_simu_only==1'b0)?0:txblkst0 ;
+ assign txblkst1_ext = (pipe_mode_simu_only==1'b0)?0:txblkst1 ;
+ assign txblkst2_ext = (pipe_mode_simu_only==1'b0)?0:txblkst2 ;
+ assign txblkst3_ext = (pipe_mode_simu_only==1'b0)?0:txblkst3 ;
+ assign txblkst4_ext = (pipe_mode_simu_only==1'b0)?0:txblkst4 ;
+ assign txblkst5_ext = (pipe_mode_simu_only==1'b0)?0:txblkst5 ;
+ assign txblkst6_ext = (pipe_mode_simu_only==1'b0)?0:txblkst6 ;
+ assign txblkst7_ext = (pipe_mode_simu_only==1'b0)?0:txblkst7 ;
+ assign txsynchd0_ext = (pipe_mode_simu_only==1'b0)?0:txsynchd0 ;
+ assign txsynchd1_ext = (pipe_mode_simu_only==1'b0)?0:txsynchd1 ;
+ assign txsynchd2_ext = (pipe_mode_simu_only==1'b0)?0:txsynchd2 ;
+ assign txsynchd3_ext = (pipe_mode_simu_only==1'b0)?0:txsynchd3 ;
+ assign txsynchd4_ext = (pipe_mode_simu_only==1'b0)?0:txsynchd4 ;
+ assign txsynchd5_ext = (pipe_mode_simu_only==1'b0)?0:txsynchd5 ;
+ assign txsynchd6_ext = (pipe_mode_simu_only==1'b0)?0:txsynchd6 ;
+ assign txsynchd7_ext = (pipe_mode_simu_only==1'b0)?0:txsynchd7 ;
+ assign currentcoeff0_ext = (pipe_mode_simu_only==1'b0)?0:currentcoeff0 ;
+ assign currentcoeff1_ext = (pipe_mode_simu_only==1'b0)?0:currentcoeff1 ;
+ assign currentcoeff2_ext = (pipe_mode_simu_only==1'b0)?0:currentcoeff2 ;
+ assign currentcoeff3_ext = (pipe_mode_simu_only==1'b0)?0:currentcoeff3 ;
+ assign currentcoeff4_ext = (pipe_mode_simu_only==1'b0)?0:currentcoeff4 ;
+ assign currentcoeff5_ext = (pipe_mode_simu_only==1'b0)?0:currentcoeff5 ;
+ assign currentcoeff6_ext = (pipe_mode_simu_only==1'b0)?0:currentcoeff6 ;
+ assign currentcoeff7_ext = (pipe_mode_simu_only==1'b0)?0:currentcoeff7 ;
+ assign currentrxpreset0_ext = (pipe_mode_simu_only==1'b0)?0:currentrxpreset0 ;
+ assign currentrxpreset1_ext = (pipe_mode_simu_only==1'b0)?0:currentrxpreset1 ;
+ assign currentrxpreset2_ext = (pipe_mode_simu_only==1'b0)?0:currentrxpreset2 ;
+ assign currentrxpreset3_ext = (pipe_mode_simu_only==1'b0)?0:currentrxpreset3 ;
+ assign currentrxpreset4_ext = (pipe_mode_simu_only==1'b0)?0:currentrxpreset4 ;
+ assign currentrxpreset5_ext = (pipe_mode_simu_only==1'b0)?0:currentrxpreset5 ;
+ assign currentrxpreset6_ext = (pipe_mode_simu_only==1'b0)?0:currentrxpreset6 ;
+ assign currentrxpreset7_ext = (pipe_mode_simu_only==1'b0)?0:currentrxpreset7 ;
+
+endmodule
+
+
+
+module altpcie_hip_256_pipen1b # (
+
+ parameter ACDS_V10=1,
+ parameter MEM_CHECK=0,
+ parameter USE_INTERNAL_250MHZ_PLL = 1,
+ parameter pll_refclk_freq = "100 MHz", //legal value = "100 MHz", "125 MHz"
+
+ parameter enable_slot_register = "false",
+ parameter pcie_mode = "shared_mode",
+ parameter bypass_cdc = "false",
+ parameter enable_rx_buffer_checking = "false",
+ parameter single_rx_detect = 4'b0,
+ parameter use_crc_forwarding = "false",
+ parameter gen123_lane_rate_mode = "gen1",
+ parameter lane_mask = "x4",
+ parameter disable_link_x2_support = "false",
+ parameter hip_hard_reset = "disable",
+ parameter dis_paritychk = "enable",
+ parameter wrong_device_id = "disable",
+ parameter data_pack_rx = "disable",
+ parameter ast_width = "rx_tx_64",
+ parameter rx_sop_ctrl = "boundary_64",
+ parameter rx_ast_parity = "disable",
+ parameter tx_ast_parity = "disable",
+ parameter ltssm_1ms_timeout = "disable",
+ parameter ltssm_freqlocked_check = "disable",
+ parameter deskew_comma = "skp_eieos_deskw",
+ parameter port_link_number = 8'b1,
+ parameter device_number = 5'b0,
+ parameter bypass_clk_switch = "TRUE",
+ parameter pipex1_debug_sel = "disable",
+ parameter pclk_out_sel = "pclk",
+ parameter vendor_id = 16'b1000101110010,
+ parameter device_id = 16'b1,
+ parameter revision_id = 8'b1,
+ parameter class_code = 24'b111111110000000000000000,
+ parameter subsystem_vendor_id = 16'b1000101110010,
+ parameter subsystem_device_id = 16'b1,
+ parameter no_soft_reset = "false",
+ parameter maximum_current = 3'b0,
+ parameter d1_support = "false",
+ parameter d2_support = "false",
+ parameter d0_pme = "false",
+ parameter d1_pme = "false",
+ parameter d2_pme = "false",
+ parameter d3_hot_pme = "false",
+ parameter d3_cold_pme = "false",
+ parameter use_aer = "false",
+ parameter low_priority_vc = "single_vc",
+ parameter disable_snoop_packet = "false",
+ parameter max_payload_size = "payload_512",
+ parameter surprise_down_error_support = "false",
+ parameter dll_active_report_support = "false",
+ parameter extend_tag_field = "false",
+ parameter endpoint_l0_latency = 3'b0,
+ parameter endpoint_l1_latency = 3'b0,
+ parameter indicator = 3'b111,
+ parameter slot_power_scale = 2'b0,
+ parameter max_link_width = "x4",
+ parameter enable_l1_aspm = "false",
+ parameter l1_exit_latency_sameclock = 3'b0,
+ parameter l1_exit_latency_diffclock = 3'b0,
+ parameter hot_plug_support = 7'b0,
+ parameter slot_power_limit = 8'b0,
+ parameter slot_number = 13'b0,
+ parameter diffclock_nfts_count = 8'b0,
+ parameter sameclock_nfts_count = 8'b0,
+ parameter completion_timeout = "abcd",
+ parameter enable_completion_timeout_disable = "true",
+ parameter extended_tag_reset = "false",
+ parameter ecrc_check_capable = "true",
+ parameter ecrc_gen_capable = "true",
+ parameter no_command_completed = "true",
+ parameter msi_multi_message_capable = "count_4",
+ parameter msi_64bit_addressing_capable = "true",
+ parameter msi_masking_capable = "false",
+ parameter msi_support = "true",
+ parameter interrupt_pin = "inta",
+ parameter enable_function_msix_support = "true",
+ parameter msix_table_size = 11'b0,
+ parameter msix_table_bir = 3'b0,
+ parameter msix_table_offset = 29'b0,
+ parameter msix_pba_bir = 3'b0,
+ parameter msix_pba_offset = 29'b0,
+ parameter bridge_port_vga_enable = "false",
+ parameter bridge_port_ssid_support = "false",
+ parameter ssvid = 16'b0,
+ parameter ssid = 16'b0,
+ parameter eie_before_nfts_count = 4'b100,
+ parameter gen2_diffclock_nfts_count = 8'b11111111,
+ parameter gen2_sameclock_nfts_count = 8'b11111111,
+ parameter deemphasis_enable = "false",
+ parameter pcie_spec_version = "v2",
+ parameter l0_exit_latency_sameclock = 3'b110,
+ parameter l0_exit_latency_diffclock = 3'b110,
+ parameter rx_ei_l0s = "disable",
+ parameter l2_async_logic = "enable",
+ parameter aspm_config_management = "true",
+ parameter atomic_op_routing = "false",
+ parameter atomic_op_completer_32bit = "false",
+ parameter atomic_op_completer_64bit = "false",
+ parameter cas_completer_128bit = "false",
+ parameter ltr_mechanism = "false",
+ parameter tph_completer = "false",
+ parameter extended_format_field = "true",
+ parameter atomic_malformed = "false",
+ parameter flr_capability = "true",
+ parameter enable_adapter_half_rate_mode = "false",
+ parameter vc0_clk_enable = "true",
+ parameter register_pipe_signals = "false",
+ parameter bar0_io_space = "false",
+ parameter bar0_64bit_mem_space = "true",
+ parameter bar0_prefetchable = "true",
+ parameter bar0_size_mask = 28'b1111111111111111111111111111,
+ parameter bar1_io_space = "false",
+ parameter bar1_64bit_mem_space = "false",
+ parameter bar1_prefetchable = "false",
+ parameter bar1_size_mask = 28'b0,
+ parameter bar2_io_space = "false",
+ parameter bar2_64bit_mem_space = "false",
+ parameter bar2_prefetchable = "false",
+ parameter bar2_size_mask = 28'b0,
+ parameter bar3_io_space = "false",
+ parameter bar3_64bit_mem_space = "false",
+ parameter bar3_prefetchable = "false",
+ parameter bar3_size_mask = 28'b0,
+ parameter bar4_io_space = "false",
+ parameter bar4_64bit_mem_space = "false",
+ parameter bar4_prefetchable = "false",
+ parameter bar4_size_mask = 28'b0,
+ parameter bar5_io_space = "false",
+ parameter bar5_64bit_mem_space = "false",
+ parameter bar5_prefetchable = "false",
+ parameter bar5_size_mask = 28'b0,
+ parameter expansion_base_address_register = 32'b0,
+ parameter io_window_addr_width = "window_32_bit",
+ parameter prefetchable_mem_window_addr_width = "prefetch_32",
+ parameter skp_os_gen3_count = 11'b0,
+ parameter tx_cdc_almost_empty = 4'b101,
+ parameter rx_cdc_almost_full = 4'b1100,
+ parameter tx_cdc_almost_full = 4'b1100,
+ parameter rx_l0s_count_idl = 8'b0,
+ parameter cdc_dummy_insert_limit = 4'b1011,
+ parameter ei_delay_powerdown_count = 8'b1010,
+ parameter millisecond_cycle_count = 20'b0,
+ parameter skp_os_schedule_count = 11'b0,
+ parameter fc_init_timer = 11'b10000000000,
+ parameter l01_entry_latency = 5'b11111,
+ parameter flow_control_update_count = 5'b11110,
+ parameter flow_control_timeout_count = 8'b11001000,
+ parameter vc0_rx_flow_ctrl_posted_header = 8'b110010,
+ parameter vc0_rx_flow_ctrl_posted_data = 12'b101101000,
+ parameter vc0_rx_flow_ctrl_nonposted_header = 8'b110110,
+ parameter vc0_rx_flow_ctrl_nonposted_data = 8'b0,
+ parameter vc0_rx_flow_ctrl_compl_header = 8'b1110000,
+ parameter vc0_rx_flow_ctrl_compl_data = 12'b111000000,
+ parameter rx_ptr0_posted_dpram_min = 11'b0,
+ parameter rx_ptr0_posted_dpram_max = 11'b0,
+ parameter rx_ptr0_nonposted_dpram_min = 11'b0,
+ parameter rx_ptr0_nonposted_dpram_max = 11'b0,
+ parameter retry_buffer_last_active_address = 11'b11111111111,
+ parameter retry_buffer_memory_settings = 30'b0,
+ parameter vc0_rx_buffer_memory_settings = 30'b0,
+ parameter bist_memory_settings = 75'b0,
+ parameter credit_buffer_allocation_aux = "balanced",
+ parameter iei_enable_settings = "gen2_infei_infsd_gen1_infei_sd",
+ parameter vsec_id = 16'b1000101110010,
+ parameter cvp_rate_sel = "full_rate",
+ parameter hard_reset_bypass = "true",
+ parameter cvp_data_compressed = "false",
+ parameter cvp_data_encrypted = "false",
+ parameter cvp_mode_reset = "false",
+ parameter cvp_clk_reset = "false",
+ parameter in_cvp_mode = "not_cvp_mode",
+ parameter vsec_cap = 4'b0,
+ parameter jtag_id = 32'b0,
+ parameter user_id = 16'b0,
+ parameter cseb_extend_pci = "false",
+ parameter cseb_extend_pcie = "false",
+ parameter cseb_cpl_status_during_cvp = "config_retry_status",
+ parameter cseb_route_to_avl_rx_st = "cseb",
+ parameter cseb_config_bypass = "disable",
+ parameter cseb_cpl_tag_checking = "enable",
+ parameter cseb_bar_match_checking = "enable",
+ parameter cseb_min_error_checking = "false",
+ parameter cseb_temp_busy_crs = "completer_abort",
+ parameter gen3_diffclock_nfts_count = 8'b10000000,
+ parameter gen3_sameclock_nfts_count = 8'b10000000,
+ parameter gen3_coeff_errchk = "enable",
+ parameter gen3_paritychk = "enable",
+ parameter gen3_coeff_delay_count = 7'b1111101,
+ parameter gen3_coeff_1 = 18'b0,
+ parameter gen3_coeff_1_sel = "coeff_1",
+ parameter gen3_coeff_1_preset_hint = 3'b0,
+ parameter gen3_coeff_1_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_1_nxtber_more = "g3_coeff_1_nxtber_more",
+ parameter gen3_coeff_1_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_1_nxtber_less = "g3_coeff_1_nxtber_less",
+ parameter gen3_coeff_1_reqber = 5'b0,
+ parameter gen3_coeff_1_ber_meas = 6'b0,
+ parameter gen3_coeff_2 = 18'b0,
+ parameter gen3_coeff_2_sel = "coeff_2",
+ parameter gen3_coeff_2_preset_hint = 3'b0,
+ parameter gen3_coeff_2_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_2_nxtber_more = "g3_coeff_2_nxtber_more",
+ parameter gen3_coeff_2_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_2_nxtber_less = "g3_coeff_2_nxtber_less",
+ parameter gen3_coeff_2_reqber = 5'b0,
+ parameter gen3_coeff_2_ber_meas = 6'b0,
+ parameter gen3_coeff_3 = 18'b0,
+ parameter gen3_coeff_3_sel = "coeff_3",
+ parameter gen3_coeff_3_preset_hint = 3'b0,
+ parameter gen3_coeff_3_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_3_nxtber_more = "g3_coeff_3_nxtber_more",
+ parameter gen3_coeff_3_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_3_nxtber_less = "g3_coeff_3_nxtber_less",
+ parameter gen3_coeff_3_reqber = 5'b0,
+ parameter gen3_coeff_3_ber_meas = 6'b0,
+ parameter gen3_coeff_4 = 18'b0,
+ parameter gen3_coeff_4_sel = "coeff_4",
+ parameter gen3_coeff_4_preset_hint = 3'b0,
+ parameter gen3_coeff_4_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_4_nxtber_more = "g3_coeff_4_nxtber_more",
+ parameter gen3_coeff_4_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_4_nxtber_less = "g3_coeff_4_nxtber_less",
+ parameter gen3_coeff_4_reqber = 5'b0,
+ parameter gen3_coeff_4_ber_meas = 6'b0,
+ parameter gen3_coeff_5 = 18'b0,
+ parameter gen3_coeff_5_sel = "coeff_5",
+ parameter gen3_coeff_5_preset_hint = 3'b0,
+ parameter gen3_coeff_5_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_5_nxtber_more = "g3_coeff_5_nxtber_more",
+ parameter gen3_coeff_5_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_5_nxtber_less = "g3_coeff_5_nxtber_less",
+ parameter gen3_coeff_5_reqber = 5'b0,
+ parameter gen3_coeff_5_ber_meas = 6'b0,
+ parameter gen3_coeff_6 = 18'b0,
+ parameter gen3_coeff_6_sel = "coeff_6",
+ parameter gen3_coeff_6_preset_hint = 3'b0,
+ parameter gen3_coeff_6_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_6_nxtber_more = "g3_coeff_6_nxtber_more",
+ parameter gen3_coeff_6_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_6_nxtber_less = "g3_coeff_6_nxtber_less",
+ parameter gen3_coeff_6_reqber = 5'b0,
+ parameter gen3_coeff_6_ber_meas = 6'b0,
+ parameter gen3_coeff_7 = 18'b0,
+ parameter gen3_coeff_7_sel = "coeff_7",
+ parameter gen3_coeff_7_preset_hint = 3'b0,
+ parameter gen3_coeff_7_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_7_nxtber_more = "g3_coeff_7_nxtber_more",
+ parameter gen3_coeff_7_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_7_nxtber_less = "g3_coeff_7_nxtber_less",
+ parameter gen3_coeff_7_reqber = 5'b0,
+ parameter gen3_coeff_7_ber_meas = 6'b0,
+ parameter gen3_coeff_8 = 18'b0,
+ parameter gen3_coeff_8_sel = "coeff_8",
+ parameter gen3_coeff_8_preset_hint = 3'b0,
+ parameter gen3_coeff_8_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_8_nxtber_more = "g3_coeff_8_nxtber_more",
+ parameter gen3_coeff_8_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_8_nxtber_less = "g3_coeff_8_nxtber_less",
+ parameter gen3_coeff_8_reqber = 5'b0,
+ parameter gen3_coeff_8_ber_meas = 6'b0,
+ parameter gen3_coeff_9 = 18'b0,
+ parameter gen3_coeff_9_sel = "coeff_9",
+ parameter gen3_coeff_9_preset_hint = 3'b0,
+ parameter gen3_coeff_9_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_9_nxtber_more = "g3_coeff_9_nxtber_more",
+ parameter gen3_coeff_9_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_9_nxtber_less = "g3_coeff_9_nxtber_less",
+ parameter gen3_coeff_9_reqber = 5'b0,
+ parameter gen3_coeff_9_ber_meas = 6'b0,
+ parameter gen3_coeff_10 = 18'b0,
+ parameter gen3_coeff_10_sel = "coeff_10",
+ parameter gen3_coeff_10_preset_hint = 3'b0,
+ parameter gen3_coeff_10_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_10_nxtber_more = "g3_coeff_10_nxtber_more",
+ parameter gen3_coeff_10_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_10_nxtber_less = "g3_coeff_10_nxtber_less",
+ parameter gen3_coeff_10_reqber = 5'b0,
+ parameter gen3_coeff_10_ber_meas = 6'b0,
+ parameter gen3_coeff_11 = 18'b0,
+ parameter gen3_coeff_11_sel = "coeff_11",
+ parameter gen3_coeff_11_preset_hint = 3'b0,
+ parameter gen3_coeff_11_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_11_nxtber_more = "g3_coeff_11_nxtber_more",
+ parameter gen3_coeff_11_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_11_nxtber_less = "g3_coeff_11_nxtber_less",
+ parameter gen3_coeff_11_reqber = 5'b0,
+ parameter gen3_coeff_11_ber_meas = 6'b0,
+ parameter gen3_coeff_12 = 18'b0,
+ parameter gen3_coeff_12_sel = "coeff_12",
+ parameter gen3_coeff_12_preset_hint = 3'b0,
+ parameter gen3_coeff_12_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_12_nxtber_more = "g3_coeff_12_nxtber_more",
+ parameter gen3_coeff_12_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_12_nxtber_less = "g3_coeff_12_nxtber_less",
+ parameter gen3_coeff_12_reqber = 5'b0,
+ parameter gen3_coeff_12_ber_meas = 6'b0,
+ parameter gen3_coeff_13 = 18'b0,
+ parameter gen3_coeff_13_sel = "coeff_13",
+ parameter gen3_coeff_13_preset_hint = 3'b0,
+ parameter gen3_coeff_13_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_13_nxtber_more = "g3_coeff_13_nxtber_more",
+ parameter gen3_coeff_13_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_13_nxtber_less = "g3_coeff_13_nxtber_less",
+ parameter gen3_coeff_13_reqber = 5'b0,
+ parameter gen3_coeff_13_ber_meas = 6'b0,
+ parameter gen3_coeff_14 = 18'b0,
+ parameter gen3_coeff_14_sel = "coeff_14",
+ parameter gen3_coeff_14_preset_hint = 3'b0,
+ parameter gen3_coeff_14_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_14_nxtber_more = "g3_coeff_14_nxtber_more",
+ parameter gen3_coeff_14_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_14_nxtber_less = "g3_coeff_14_nxtber_less",
+ parameter gen3_coeff_14_reqber = 5'b0,
+ parameter gen3_coeff_14_ber_meas = 6'b0,
+ parameter gen3_coeff_15 = 18'b0,
+ parameter gen3_coeff_15_sel = "coeff_15",
+ parameter gen3_coeff_15_preset_hint = 3'b0,
+ parameter gen3_coeff_15_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_15_nxtber_more = "g3_coeff_15_nxtber_more",
+ parameter gen3_coeff_15_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_15_nxtber_less = "g3_coeff_15_nxtber_less",
+ parameter gen3_coeff_15_reqber = 5'b0,
+ parameter gen3_coeff_15_ber_meas = 6'b0,
+ parameter gen3_coeff_16 = 18'b0,
+ parameter gen3_coeff_16_sel = "coeff_16",
+ parameter gen3_coeff_16_preset_hint = 3'b0,
+ parameter gen3_coeff_16_nxtber_more_ptr = 4'b0,
+ parameter gen3_coeff_16_nxtber_more = "g3_coeff_16_nxtber_more",
+ parameter gen3_coeff_16_nxtber_less_ptr = 4'b0,
+ parameter gen3_coeff_16_nxtber_less = "g3_coeff_16_nxtber_less",
+ parameter gen3_coeff_16_reqber = 5'b0,
+ parameter gen3_coeff_16_ber_meas = 6'b0,
+ parameter gen3_preset_coeff_1 = 18'b0,
+ parameter gen3_preset_coeff_2 = 18'b0,
+ parameter gen3_preset_coeff_3 = 18'b0,
+ parameter gen3_preset_coeff_4 = 18'b0,
+ parameter gen3_preset_coeff_5 = 18'b0,
+ parameter gen3_preset_coeff_6 = 18'b0,
+ parameter gen3_preset_coeff_7 = 18'b0,
+ parameter gen3_preset_coeff_8 = 18'b0,
+ parameter gen3_preset_coeff_9 = 18'b0,
+ parameter gen3_preset_coeff_10 = 18'b0,
+ parameter gen3_rxfreqlock_counter = 20'b0
+
+
+ //Serdes related parameters
+) (
+ // Reset signals
+ input simu_mode,
+ input pipe_mode,
+ input crst,
+ input srst,
+ input hiphardreset,
+ input npor,
+ output reset_status,
+
+ // Clock
+ input pld_clk,
+ input pclk_in,
+ output clk250_out,
+ output clk500_out,
+ output rc_pll_locked,
+
+ // Serdes related
+ input cal_blk_clk,
+ input refclk,
+
+ // HIP control signals
+ input [1 : 0] mode,
+ input [4 : 0] hpg_ctrler,
+ input [1 : 0] swctmod,
+ input [2 : 0] swdn_in,
+ input [6 : 0] swup_in,
+ input [31 : 0] test_in,
+
+ // Input PIPE simulation _ext for simulation only
+ input phystatus0_ext,
+ input phystatus1_ext,
+ input phystatus2_ext,
+ input phystatus3_ext,
+ input phystatus4_ext,
+ input phystatus5_ext,
+ input phystatus6_ext,
+ input phystatus7_ext,
+ input [7 : 0] rxdata0_ext,
+ input [7 : 0] rxdata1_ext,
+ input [7 : 0] rxdata2_ext,
+ input [7 : 0] rxdata3_ext,
+ input [7 : 0] rxdata4_ext,
+ input [7 : 0] rxdata5_ext,
+ input [7 : 0] rxdata6_ext,
+ input [7 : 0] rxdata7_ext,
+ input rxdatak0_ext,
+ input rxdatak1_ext,
+ input rxdatak2_ext,
+ input rxdatak3_ext,
+ input rxdatak4_ext,
+ input rxdatak5_ext,
+ input rxdatak6_ext,
+ input rxdatak7_ext,
+ input rxelecidle0_ext,
+ input rxelecidle1_ext,
+ input rxelecidle2_ext,
+ input rxelecidle3_ext,
+ input rxelecidle4_ext,
+ input rxelecidle5_ext,
+ input rxelecidle6_ext,
+ input rxelecidle7_ext,
+ input rxfreqlocked0_ext,
+ input rxfreqlocked1_ext,
+ input rxfreqlocked2_ext,
+ input rxfreqlocked3_ext,
+ input rxfreqlocked4_ext,
+ input rxfreqlocked5_ext,
+ input rxfreqlocked6_ext,
+ input rxfreqlocked7_ext,
+ input [2 : 0] rxstatus0_ext,
+ input [2 : 0] rxstatus1_ext,
+ input [2 : 0] rxstatus2_ext,
+ input [2 : 0] rxstatus3_ext,
+ input [2 : 0] rxstatus4_ext,
+ input [2 : 0] rxstatus5_ext,
+ input [2 : 0] rxstatus6_ext,
+ input [2 : 0] rxstatus7_ext,
+ input rxdataskip0_ext,
+ input rxdataskip1_ext,
+ input rxdataskip2_ext,
+ input rxdataskip3_ext,
+ input rxdataskip4_ext,
+ input rxdataskip5_ext,
+ input rxdataskip6_ext,
+ input rxdataskip7_ext,
+ input rxblkst0_ext,
+ input rxblkst1_ext,
+ input rxblkst2_ext,
+ input rxblkst3_ext,
+ input rxblkst4_ext,
+ input rxblkst5_ext,
+ input rxblkst6_ext,
+ input rxblkst7_ext,
+ input [1 : 0] rxsynchd0_ext,
+ input [1 : 0] rxsynchd1_ext,
+ input [1 : 0] rxsynchd2_ext,
+ input [1 : 0] rxsynchd3_ext,
+ input [1 : 0] rxsynchd4_ext,
+ input [1 : 0] rxsynchd5_ext,
+ input [1 : 0] rxsynchd6_ext,
+ input [1 : 0] rxsynchd7_ext,
+ input rxvalid0_ext,
+ input rxvalid1_ext,
+ input rxvalid2_ext,
+ input rxvalid3_ext,
+ input rxvalid4_ext,
+ input rxvalid5_ext,
+ input rxvalid6_ext,
+ input rxvalid7_ext,
+
+ // Application signals inputs
+ input [4 : 0] aer_msi_num,
+ input app_int_sts,
+ input [4 : 0] app_msi_num,
+ input app_msi_req,
+ input [2 : 0] app_msi_tc,
+ input [4 : 0] pex_msi_num,
+ input [11 : 0] lmi_addr,
+ input [31 : 0] lmi_din,
+ input lmi_rden,
+ input lmi_wren,
+ input pm_auxpwr,
+ input [9 : 0] pm_data,
+ input pme_to_cr,
+ input pm_event,
+ input rx_st_mask,
+ input rx_st_ready,
+ input [255 : 0] tx_st_data,
+ input [1 :0] tx_st_empty,
+ input [3 :0] tx_st_eop,
+ input [3 :0] tx_st_err,
+ input [31:0] tx_st_parity,
+ input [3 :0] tx_st_sop,
+ input tx_st_valid,
+ input [12:0] cfglink2csrpld,
+ input [6 :0] cpl_err,
+ input cpl_pending,
+ input tl_slotclk_cfg,
+
+ // Input for internal test port (PE/TE)
+ input entest,
+ input frzlogic,
+ input frzreg,
+ input [7 : 0] idrcv,
+ input [7 : 0] idrpl,
+ input bistenrcv,
+ input bistenrpl,
+ input bistscanen,
+ input bistscanin,
+ input bisttesten,
+ input memhiptestenable,
+ input memredenscan,
+ input memredscen,
+ input memredscin,
+ input memredsclk,
+ input memredscrst,
+ input memredscsel,
+ input memregscanen,
+ input memregscanin,
+ input scanmoden,
+ input usermode,
+ input scanshiftn,
+ input nfrzdrv,
+ input plniotri,
+
+ // Input for past QII 10.0 support
+ input [31 : 0] csebrddata,
+ input [3 : 0] csebrddataparity,
+ input [2 : 0] csebrdresponse,
+ input csebwaitrequest,
+ input [2 : 0] csebwrresponse,
+ input csebwrrespvalid,
+ input [43 : 0] dbgpipex1rx,
+
+
+ // Output Pipe interface
+ output [2 : 0] eidleinfersel0_ext,
+ output [2 : 0] eidleinfersel1_ext,
+ output [2 : 0] eidleinfersel2_ext,
+ output [2 : 0] eidleinfersel3_ext,
+ output [2 : 0] eidleinfersel4_ext,
+ output [2 : 0] eidleinfersel5_ext,
+ output [2 : 0] eidleinfersel6_ext,
+ output [2 : 0] eidleinfersel7_ext,
+ output [1 : 0] powerdown0_ext,
+ output [1 : 0] powerdown1_ext,
+ output [1 : 0] powerdown2_ext,
+ output [1 : 0] powerdown3_ext,
+ output [1 : 0] powerdown4_ext,
+ output [1 : 0] powerdown5_ext,
+ output [1 : 0] powerdown6_ext,
+ output [1 : 0] powerdown7_ext,
+ output rxpolarity0_ext,
+ output rxpolarity1_ext,
+ output rxpolarity2_ext,
+ output rxpolarity3_ext,
+ output rxpolarity4_ext,
+ output rxpolarity5_ext,
+ output rxpolarity6_ext,
+ output rxpolarity7_ext,
+ output txcompl0_ext,
+ output txcompl1_ext,
+ output txcompl2_ext,
+ output txcompl3_ext,
+ output txcompl4_ext,
+ output txcompl5_ext,
+ output txcompl6_ext,
+ output txcompl7_ext,
+ output [7 : 0] txdata0_ext,
+ output [7 : 0] txdata1_ext,
+ output [7 : 0] txdata2_ext,
+ output [7 : 0] txdata3_ext,
+ output [7 : 0] txdata4_ext,
+ output [7 : 0] txdata5_ext,
+ output [7 : 0] txdata6_ext,
+ output [7 : 0] txdata7_ext,
+ output txdatak0_ext,
+ output txdatak1_ext,
+ output txdatak2_ext,
+ output txdatak3_ext,
+ output txdatak4_ext,
+ output txdatak5_ext,
+ output txdatak6_ext,
+ output txdatak7_ext,
+ output txdatavalid0_ext,
+ output txdatavalid1_ext,
+ output txdatavalid2_ext,
+ output txdatavalid3_ext,
+ output txdatavalid4_ext,
+ output txdatavalid5_ext,
+ output txdatavalid6_ext,
+ output txdatavalid7_ext,
+ output txdetectrx0_ext,
+ output txdetectrx1_ext,
+ output txdetectrx2_ext,
+ output txdetectrx3_ext,
+ output txdetectrx4_ext,
+ output txdetectrx5_ext,
+ output txdetectrx6_ext,
+ output txdetectrx7_ext,
+ output txelecidle0_ext,
+ output txelecidle1_ext,
+ output txelecidle2_ext,
+ output txelecidle3_ext,
+ output txelecidle4_ext,
+ output txelecidle5_ext,
+ output txelecidle6_ext,
+ output txelecidle7_ext,
+ output [2 : 0] txmargin0_ext,
+ output [2 : 0] txmargin1_ext,
+ output [2 : 0] txmargin2_ext,
+ output [2 : 0] txmargin3_ext,
+ output [2 : 0] txmargin4_ext,
+ output [2 : 0] txmargin5_ext,
+ output [2 : 0] txmargin6_ext,
+ output [2 : 0] txmargin7_ext,
+ output txdeemph0_ext,
+ output txdeemph1_ext,
+ output txdeemph2_ext,
+ output txdeemph3_ext,
+ output txdeemph4_ext,
+ output txdeemph5_ext,
+ output txdeemph6_ext,
+ output txdeemph7_ext,
+ output txblkst0_ext,
+ output txblkst1_ext,
+ output txblkst2_ext,
+ output txblkst3_ext,
+ output txblkst4_ext,
+ output txblkst5_ext,
+ output txblkst6_ext,
+ output txblkst7_ext,
+ output [1 : 0] txsynchd0_ext,
+ output [1 : 0] txsynchd1_ext,
+ output [1 : 0] txsynchd2_ext,
+ output [1 : 0] txsynchd3_ext,
+ output [1 : 0] txsynchd4_ext,
+ output [1 : 0] txsynchd5_ext,
+ output [1 : 0] txsynchd6_ext,
+ output [1 : 0] txsynchd7_ext,
+ output [17 : 0] currentcoeff0_ext,
+ output [17 : 0] currentcoeff1_ext,
+ output [17 : 0] currentcoeff2_ext,
+ output [17 : 0] currentcoeff3_ext,
+ output [17 : 0] currentcoeff4_ext,
+ output [17 : 0] currentcoeff5_ext,
+ output [17 : 0] currentcoeff6_ext,
+ output [17 : 0] currentcoeff7_ext,
+ output [2 : 0] currentrxpreset0_ext,
+ output [2 : 0] currentrxpreset1_ext,
+ output [2 : 0] currentrxpreset2_ext,
+ output [2 : 0] currentrxpreset3_ext,
+ output [2 : 0] currentrxpreset4_ext,
+ output [2 : 0] currentrxpreset5_ext,
+ output [2 : 0] currentrxpreset6_ext,
+ output [2 : 0] currentrxpreset7_ext,
+
+
+ // Output HIP Status signals
+ output coreclkout,
+ output [1 : 0] currentspeed,
+ output derr_cor_ext_rcv,
+ output derr_cor_ext_rcv1,
+ output derr_cor_ext_rpl,
+ output derr_rpl,
+ output dlup,
+ output dlup_exit,
+ output resetstatus,
+ output ratetiedtognd,
+ output ev128ns,
+ output ev1us,
+ output hotrst_exit,
+ output [3 : 0] int_status,
+ output l2_exit,
+ output [3 : 0] lane_act,
+ output [4 : 0] ltssmstate,
+ output [1 : 0] rate,
+ output [127 : 0] test_out,
+
+ // Output Application interface
+ output app_int_ack,
+ output app_msi_ack,
+ output lmi_ack,
+ output [31 : 0] lmi_dout,
+ output pme_to_sr,
+ output [7 : 0] rx_st_bardec1,
+ output [7 : 0] rx_st_bardec2,
+ output [31 : 0] rx_st_be,
+ output [255 : 0] rx_st_data,
+ output [1 : 0] rx_st_empty,
+ output [3 : 0] rx_st_eop,
+ output [3 : 0] rx_st_err,
+ output [31 : 0] rx_st_parity,
+ output [3 : 0] rx_st_sop,
+ output [3 : 0] rx_st_valid,
+ output serr_out,
+ output [6 : 0] swdnout,
+ output [2 : 0] swupout,
+ output [3 : 0] tl_cfg_add,
+ output [31 : 0] tl_cfg_ctl,
+ output [52 : 0] tl_cfg_sts,
+ output [11 : 0] tx_cred_datafccp,
+ output [11 : 0] tx_cred_datafcnp,
+ output [11 : 0] tx_cred_datafcp,
+ output [5 : 0] tx_cred_fchipcons,
+ output [5 : 0] tx_cred_fcinfinite,
+ output [7 : 0] tx_cred_hdrfccp,
+ output [7 : 0] tx_cred_hdrfcnp,
+ output [7 : 0] tx_cred_hdrfcp,
+ output tx_st_ready,
+
+ // serial interface
+ input rx_in0,
+ input rx_in1,
+ input rx_in2,
+ input rx_in3,
+ input rx_in4,
+ input rx_in5,
+ input rx_in6,
+ input rx_in7,
+
+ output tx_out0,
+ output tx_out1,
+ output tx_out2,
+ output tx_out3,
+ output tx_out4,
+ output tx_out5,
+ output tx_out6,
+ output tx_out7,
+
+ // Output for past QII 10.0 support
+ output [32 : 0] csebaddr,
+ output [4 : 0] csebaddrparity,
+ output [3 : 0] csebbe,
+ output csebisshadow,
+ output csebrden,
+ output [31 : 0] csebwrdata,
+ output [3 : 0] csebwrdataparity,
+ output csebwren,
+ output csebwrrespreq,
+
+ // Output for internal test port (PE/TE)
+ output bistdonearcv,
+ output bistdonearcv1,
+ output bistdonearpl,
+ output bistdonebrcv,
+ output bistdonebrcv1,
+ output bistdonebrpl,
+ output bistpassrcv,
+ output bistpassrcv1,
+ output bistpassrpl,
+ output bistscanoutrcv,
+ output bistscanoutrcv1,
+ output bistscanoutrpl,
+ output memredscout,
+ output memregscanout,
+ output wakeoen
+ );
+
+ function [8*25:1] low_str;
+ // Convert parameter strings to lower case
+ input [8*25:1] input_string;
+ reg [8*25:1] return_string;
+ reg [8*25:1] reg_string;
+ reg [8:1] tmp;
+ reg [8:1] conv_char;
+ integer byte_count;
+ begin
+ reg_string = input_string;
+ for (byte_count = 25; byte_count >= 1; byte_count = byte_count - 1) begin
+ tmp = reg_string[8*25:(8*(25-1)+1)];
+ reg_string = reg_string << 8;
+ if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
+ begin
+ conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
+ return_string = {return_string, conv_char};
+ end
+ else
+ return_string = {return_string, tmp};
+ end
+ low_str = return_string;
+ end
+ endfunction
+
+ function [8*25:1] get_core_clk_divider_param;
+ input [8*25:1] l_ast_width;
+ input [8*25:1] l_gen123_lane_rate_mode;
+ input [8*25:1] l_lane_mask;
+ begin
+ if ((low_str(l_ast_width)=="rx_tx_64" ) && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x1")) get_core_clk_divider_param="div_4"; // Gen1 : pllfixedclk = 250MHz
+ else if ((low_str(l_ast_width)=="rx_tx_64" ) && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x2")) get_core_clk_divider_param="div_4";
+ else if ((low_str(l_ast_width)=="rx_tx_64" ) && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x4")) get_core_clk_divider_param="div_2";
+ else if ((low_str(l_ast_width)=="rx_tx_64" ) && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x8")) get_core_clk_divider_param="div_1";
+ else if ((low_str(l_ast_width)=="rx_tx_64" ) && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x1")) get_core_clk_divider_param="div_8"; // Gen2 : pllfixedclk = 500MHz
+ else if ((low_str(l_ast_width)=="rx_tx_64" ) && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x2")) get_core_clk_divider_param="div_2";
+ else if ((low_str(l_ast_width)=="rx_tx_64" ) && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x4")) get_core_clk_divider_param="div_2";
+ else if ((low_str(l_ast_width)=="rx_tx_64" ) && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x8")) get_core_clk_divider_param="div_1"; //NA
+
+ else if ((low_str(l_ast_width)=="rx_tx_128") && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x1")) get_core_clk_divider_param="div_4"; // Gen1 : pllfixedclk = 250MHz
+ else if ((low_str(l_ast_width)=="rx_tx_128") && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x2")) get_core_clk_divider_param="div_4";
+ else if ((low_str(l_ast_width)=="rx_tx_128") && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x4")) get_core_clk_divider_param="div_2";
+ else if ((low_str(l_ast_width)=="rx_tx_128") && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x8")) get_core_clk_divider_param="div_2";
+ else if ((low_str(l_ast_width)=="rx_tx_128") && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x1")) get_core_clk_divider_param="div_8"; // Gen2 : pllfixedclk = 500MHz
+ else if ((low_str(l_ast_width)=="rx_tx_128") && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x2")) get_core_clk_divider_param="div_4";
+ else if ((low_str(l_ast_width)=="rx_tx_128") && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x4")) get_core_clk_divider_param="div_4";
+ else if ((low_str(l_ast_width)=="rx_tx_128") && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x8")) get_core_clk_divider_param="div_2";
+
+ else if ((low_str(l_ast_width)=="rx_tx_256") && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x1")) get_core_clk_divider_param="div_4"; // Gen1 : pllfixedclk = 250MHz
+ else if ((low_str(l_ast_width)=="rx_tx_256") && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x2")) get_core_clk_divider_param="div_4";
+ else if ((low_str(l_ast_width)=="rx_tx_256") && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x4")) get_core_clk_divider_param="div_2";
+ else if ((low_str(l_ast_width)=="rx_tx_256") && (low_str(l_gen123_lane_rate_mode)=="gen1" ) && (low_str(l_lane_mask)=="x8")) get_core_clk_divider_param="div_2";
+ else if ((low_str(l_ast_width)=="rx_tx_256") && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x1")) get_core_clk_divider_param="div_8"; // Gen2 : pllfixedclk = 500MHz
+ else if ((low_str(l_ast_width)=="rx_tx_256") && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x2")) get_core_clk_divider_param="div_4";
+ else if ((low_str(l_ast_width)=="rx_tx_256") && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x4")) get_core_clk_divider_param="div_4";
+ else if ((low_str(l_ast_width)=="rx_tx_256") && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x8")) get_core_clk_divider_param="div_4";
+ else get_core_clk_divider_param="div_1";
+ end
+ endfunction
+
+ function integer is_pld_clk_250MHz;
+ input [8*25:1] l_ast_width;
+ input [8*25:1] l_gen123_lane_rate_mode;
+ input [8*25:1] l_lane_mask;
+ begin
+ if ((low_str(l_ast_width)=="rx_tx_64" ) && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x4")) is_pld_clk_250MHz=USE_INTERNAL_250MHZ_PLL;
+ else if ((low_str(l_ast_width)=="rx_tx_128") && (low_str(l_gen123_lane_rate_mode)=="gen1_gen2") && (low_str(l_lane_mask)=="x8")) is_pld_clk_250MHz=USE_INTERNAL_250MHZ_PLL;
+ else is_pld_clk_250MHz=0;
+ end
+ endfunction
+ localparam PLD_CLK_IS_250MHZ = is_pld_clk_250MHz(ast_width, gen123_lane_rate_mode, lane_mask);
+
+ // Convert parameter strings to lower case
+ genvar i;
+
+ localparam ST_DATA_WIDTH=(low_str(ast_width)=="rx_tx_256")?256:(low_str(ast_width)=="rx_tx_128")?128:64;
+ localparam ST_BE_WIDTH =(low_str(ast_width)=="rx_tx_256")? 32:(low_str(ast_width)=="rx_tx_128")? 16: 8;
+ localparam ST_CTRL_WIDTH=(low_str(ast_width)=="rx_tx_256")? 4:(low_str(ast_width)=="rx_tx_128")? 2: 1;
+
+ localparam lanes = (low_str(lane_mask)=="x1")?1:(low_str(lane_mask)=="x2")?2:(low_str(lane_mask)=="x4")?4:8; //legal value: 1+
+ localparam enable_ch0_pclk_out = (lanes==8)?"false":"true";
+ localparam enable_ch01_pclk_out = ((lanes==2)||(lanes==4))?"pclk_ch1":"pclk_ch0";
+
+ localparam national_inst_thru_enhance = "false";
+ localparam vc_enable = "single_vc" ;
+ localparam bypass_tl = "false";
+ localparam vc1_clk_enable = "false";
+ localparam vc_arbitration = "single_vc";
+ localparam enable_rx_reordering = "false";
+
+ localparam starting_channel_number = 0; //legal value: 0+
+ localparam protocol_version = (low_str(gen123_lane_rate_mode)=="gen1")?"Gen 1":
+ (low_str(gen123_lane_rate_mode)=="gen1_gen2")?"Gen 2":"<invalid>"; //legal value: "gen1", "gen2"
+
+ localparam core_clk_sel = "pld_clk";
+ localparam core_clk_out_sel = "div_1";
+ localparam core_clk_source = "pll_fixed_clk";
+ localparam core_clk_divider = get_core_clk_divider_param(ast_width, gen123_lane_rate_mode, lane_mask);
+ localparam deser_factor = 32;
+ localparam hip_enable = "true";
+
+ localparam [127:0] ONES = 128'HFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF;
+ localparam [127:0] ZEROS = 128'H0000_0000_0000_0000_0000_0000_0000_0000;
+
+// SERDES
+//
+ //input from reset controller
+ wire [lanes-1:0] serdes_gxb_powerdown; // TODO Confirm with PCS team
+ wire serdes_pll_powerdown;
+ wire serdes_fixedclk;
+ wire open_locked;
+ wire open_fbclkout;
+ wire fboutclk_fixedclk;
+ wire open_fbclk_serdes;
+ wire [lanes-1:0] serdes_tx_digitalreset;
+ wire [lanes-1:0] serdes_rx_analogreset; // for rx pma
+ wire [lanes-1:0] serdes_rx_digitalreset; //for rx pcs
+
+
+ //clk signal
+
+ //pipe interface ports
+ wire [lanes * deser_factor - 1:0] serdes_pipe_txdata;
+ wire [((lanes * deser_factor)/8) - 1:0] serdes_pipe_txdatak;
+ wire [lanes - 1:0] serdes_pipe_txdetectrx_loopback;
+ wire [lanes - 1:0] serdes_pipe_txcompliance;
+ wire [lanes - 1:0] serdes_pipe_txelecidle;
+ wire [lanes - 1:0] serdes_pipe_txdeemph;
+ wire [lanes*3 - 1:0] serdes_pipe_txmargin;
+ wire [lanes*2 - 1:0] serdes_pipe_rate;
+ wire [lanes*2 - 1:0] serdes_pipe_powerdown;
+
+ wire [lanes * deser_factor - 1:0] serdes_pipe_rxdata;
+ wire [((lanes * deser_factor)/8) - 1:0] serdes_pipe_rxdatak;
+ wire [lanes - 1:0] serdes_pipe_rxvalid;
+ wire [lanes - 1:0] serdes_pipe_rxpolarity;
+ wire [lanes - 1:0] serdes_pipe_rxelecidle;
+ wire [lanes - 1:0] serdes_pipe_phystatus;
+ wire [lanes*3 - 1:0] serdes_pipe_rxstatus;
+
+ //non-PIPE ports
+ //MM ports
+ wire [lanes*3-1:0] serdes_rx_eidleinfersel;
+ wire [lanes-1:0] serdes_rx_set_locktodata;
+ wire [lanes-1:0] serdes_rx_set_locktoref;
+ wire [lanes-1:0] serdes_tx_invpolarity;
+ wire [lanes*2-1:0] serdes_rx_errdetect;
+ wire [lanes*2-1:0] serdes_rx_disperr;
+ wire [lanes*2-1:0] serdes_rx_patterndetect;
+ wire [lanes*2-1:0] serdes_rx_syncstatus;
+ wire [lanes-1:0] serdes_rx_phase_comp_fifo_error;
+ wire [lanes-1:0] serdes_tx_phase_comp_fifo_error;
+ wire [lanes-1:0] serdes_rx_is_lockedtoref;
+ wire [lanes-1:0] serdes_rx_signaldetect;
+ wire [lanes-1:0] serdes_rx_is_lockedtodata;
+ wire serdes_pll_locked;
+ wire serdes_cal_blk_powerdown;
+ wire serdes_cal_blk_clk;
+
+ //non-MM ports
+ wire [lanes-1:0] serdes_rx_serial_data;
+ wire [lanes-1:0] serdes_tx_serial_data;
+ wire serdes_pipe_pclk;
+ wire serdes_pipe_pclkch1 ;
+ wire serdes_pllfixedclkch0;
+ wire serdes_pllfixedclkch1;
+ wire serdes_pipe_pclkcentral ;
+ wire serdes_pllfixedclkcentral;
+
+ wire mserdes_pipe_pclk;
+ wire mserdes_pipe_pclkch1 ;
+ wire mserdes_pllfixedclkch0;
+ wire mserdes_pllfixedclkch1;
+ wire mserdes_pipe_pclkcentral ;
+ wire mserdes_pllfixedclkcentral;
+
+ wire sim_pipe32_pclk;
+
+ // reset controller signal
+ wire rst_ctrl_rx_pll_locked ; //TODO connect to something
+ wire rst_ctrl_rxanalogreset ;
+ wire rst_ctrl_rxdigitalreset ;
+ wire rst_ctrl_gxb_powerdown ;
+ wire rst_ctrl_txdigitalreset ;
+
+ tri0 pipe_mode_simu_only;// When 1 indicates HIP Pipe simulation only (without Serdes)
+
+ // Pull to known values
+ wire unconnected_wire = 1'b0;
+ wire [512:0] unconnected_bus = {512{1'b0}};
+
+ ////////////////////////////////////////////////////////////////////////////////////
+ //
+ // Application AST interface
+ //
+ wire [255 : 0] txstdata;
+ wire [1 : 0] txstempty;
+ wire [3 : 0] txsteop;
+ wire [3 : 0] txsterr;
+ wire [31 : 0] txstparity;
+ wire [3 : 0] txstsop;
+ wire txstvalid;
+ wire txstready;
+
+ wire rxstmask;
+ wire rxstready;
+ wire [7 : 0] rxstbardec1;
+ wire [7 : 0] rxstbardec2;
+ wire [31 : 0] rxstbe;
+ wire [255 : 0] rxstdata;
+ wire [1 : 0] rxstempty;
+ wire [3 : 0] rxsteop;
+ wire [3 : 0] rxsterr;
+ wire [31 : 0] rxstparity;
+ wire [3 : 0] rxstsop;
+ wire [3 : 0] rxstvalid;
+
+ assign ratetiedtognd = 1'b0;
+ assign txstdata = (ST_DATA_WIDTH==256)?tx_st_data [ST_DATA_WIDTH-1 :0]:(ST_DATA_WIDTH==128)?{128'h0,tx_st_data [ST_DATA_WIDTH-1 :0]}:{192'h0,tx_st_data [ST_DATA_WIDTH-1 :0]};
+ assign txsteop = (ST_DATA_WIDTH==256)?tx_st_eop [ST_CTRL_WIDTH-1 :0]:(ST_DATA_WIDTH==128)?{2'h0 ,tx_st_eop [ST_CTRL_WIDTH-1 :0]}:{3'h0 ,tx_st_eop [ST_CTRL_WIDTH-1 :0]};
+ assign txsterr = (ST_DATA_WIDTH==256)?tx_st_err [ST_CTRL_WIDTH-1 :0]:(ST_DATA_WIDTH==128)?{2'h0 ,tx_st_err [ST_CTRL_WIDTH-1 :0]}:{3'h0 ,tx_st_err [ST_CTRL_WIDTH-1 :0]};
+ assign txstparity = (ST_DATA_WIDTH==256)?tx_st_parity[ST_BE_WIDTH-1 :0]:(ST_DATA_WIDTH==128)?{16'h0 ,tx_st_parity[ST_BE_WIDTH-1 :0]}:{24'h0 ,tx_st_parity[ST_BE_WIDTH-1 :0]};
+ assign txstsop = (ST_DATA_WIDTH==256)?tx_st_sop [ST_CTRL_WIDTH-1 :0]:(ST_DATA_WIDTH==128)?{2'h0 ,tx_st_sop [ST_CTRL_WIDTH-1 :0]}:{3'h0 ,tx_st_sop [ST_CTRL_WIDTH-1 :0]};
+ assign txstvalid = tx_st_valid ;
+ assign txstempty = tx_st_empty [1 :0];
+ assign tx_st_ready= txstready ;
+
+ assign rxstmask = rx_st_mask ;
+ assign rxstready = rx_st_ready;
+ assign rx_st_bardec1[7 :0] = rxstbardec1[7 :0];
+ assign rx_st_bardec2[7 :0] = rxstbardec2[7 :0];
+ assign rx_st_be [ST_BE_WIDTH-1 :0] = rxstbe [ST_BE_WIDTH-1 :0];
+ assign rx_st_data [ST_DATA_WIDTH-1:0] = rxstdata [ST_DATA_WIDTH-1:0];
+ assign rx_st_empty [1 :0] = rxstempty [1 :0];
+ assign rx_st_eop [ST_CTRL_WIDTH-1:0] = rxsteop [ST_CTRL_WIDTH-1:0];
+ assign rx_st_err [ST_CTRL_WIDTH-1:0] = rxsterr [ST_CTRL_WIDTH-1:0];
+ assign rx_st_parity [ST_BE_WIDTH-1 :0] = rxstparity [ST_BE_WIDTH-1 :0];
+ assign rx_st_sop [ST_CTRL_WIDTH-1:0] = rxstsop [ST_CTRL_WIDTH-1:0];
+ assign rx_st_valid [ST_CTRL_WIDTH-1:0] = rxstvalid [ST_CTRL_WIDTH-1:0];
+
+ ////////////////////////////////////////////////////////////////////////////////////
+ //
+ // PIPE signals interface
+ //
+ wire phystatus0 ;// HIP input
+ wire phystatus1 ;// HIP input
+ wire phystatus2 ;// HIP input
+ wire phystatus3 ;// HIP input
+ wire phystatus4 ;// HIP input
+ wire phystatus5 ;// HIP input
+ wire phystatus6 ;// HIP input
+ wire phystatus7 ;// HIP input
+ wire rxblkst0 = 1'b0;// HIP input
+ wire rxblkst1 = 1'b0;// HIP input
+ wire rxblkst2 = 1'b0;// HIP input
+ wire rxblkst3 = 1'b0;// HIP input
+ wire rxblkst4 = 1'b0;// HIP input
+ wire rxblkst5 = 1'b0;// HIP input
+ wire rxblkst6 = 1'b0;// HIP input
+ wire rxblkst7 = 1'b0;// HIP input
+ wire [31 : 0] rxdata0 ;// HIP input [31 : 0]
+ wire [31 : 0] rxdata1 ;// HIP input [31 : 0]
+ wire [31 : 0] rxdata2 ;// HIP input [31 : 0]
+ wire [31 : 0] rxdata3 ;// HIP input [31 : 0]
+ wire [31 : 0] rxdata4 ;// HIP input [31 : 0]
+ wire [31 : 0] rxdata5 ;// HIP input [31 : 0]
+ wire [31 : 0] rxdata6 ;// HIP input [31 : 0]
+ wire [31 : 0] rxdata7 ;// HIP input [31 : 0]
+ wire [3 : 0] rxdatak0 ;// HIP input [3 : 0]
+ wire [3 : 0] rxdatak1 ;// HIP input [3 : 0]
+ wire [3 : 0] rxdatak2 ;// HIP input [3 : 0]
+ wire [3 : 0] rxdatak3 ;// HIP input [3 : 0]
+ wire [3 : 0] rxdatak4 ;// HIP input [3 : 0]
+ wire [3 : 0] rxdatak5 ;// HIP input [3 : 0]
+ wire [3 : 0] rxdatak6 ;// HIP input [3 : 0]
+ wire [3 : 0] rxdatak7 ;// HIP input [3 : 0]
+ wire rxdataskip0 = 1'b0;// HIP input
+ wire rxdataskip1 = 1'b0;// HIP input
+ wire rxdataskip2 = 1'b0;// HIP input
+ wire rxdataskip3 = 1'b0;// HIP input
+ wire rxdataskip4 = 1'b0;// HIP input
+ wire rxdataskip5 = 1'b0;// HIP input
+ wire rxdataskip6 = 1'b0;// HIP input
+ wire rxdataskip7 = 1'b0;// HIP input
+ wire rxelecidle0 ;// HIP input
+ wire rxelecidle1 ;// HIP input
+ wire rxelecidle2 ;// HIP input
+ wire rxelecidle3 ;// HIP input
+ wire rxelecidle4 ;// HIP input
+ wire rxelecidle5 ;// HIP input
+ wire rxelecidle6 ;// HIP input
+ wire rxelecidle7 ;// HIP input
+ wire rxfreqlocked0 = 1'b0;// HIP input
+ wire rxfreqlocked1 = 1'b0;// HIP input
+ wire rxfreqlocked2 = 1'b0;// HIP input
+ wire rxfreqlocked3 = 1'b0;// HIP input
+ wire rxfreqlocked4 = 1'b0;// HIP input
+ wire rxfreqlocked5 = 1'b0;// HIP input
+ wire rxfreqlocked6 = 1'b0;// HIP input
+ wire rxfreqlocked7 = 1'b0;// HIP input
+ wire [2 : 0] rxstatus0 ;// HIP input [2 : 0]
+ wire [2 : 0] rxstatus1 ;// HIP input [2 : 0]
+ wire [2 : 0] rxstatus2 ;// HIP input [2 : 0]
+ wire [2 : 0] rxstatus3 ;// HIP input [2 : 0]
+ wire [2 : 0] rxstatus4 ;// HIP input [2 : 0]
+ wire [2 : 0] rxstatus5 ;// HIP input [2 : 0]
+ wire [2 : 0] rxstatus6 ;// HIP input [2 : 0]
+ wire [2 : 0] rxstatus7 ;// HIP input [2 : 0]
+ wire [1 : 0] rxsynchd0 = 2'b00;// HIP input [1 : 0]
+ wire [1 : 0] rxsynchd1 = 2'b00;// HIP input [1 : 0]
+ wire [1 : 0] rxsynchd2 = 2'b00;// HIP input [1 : 0]
+ wire [1 : 0] rxsynchd3 = 2'b00;// HIP input [1 : 0]
+ wire [1 : 0] rxsynchd4 = 2'b00;// HIP input [1 : 0]
+ wire [1 : 0] rxsynchd5 = 2'b00;// HIP input [1 : 0]
+ wire [1 : 0] rxsynchd6 = 2'b00;// HIP input [1 : 0]
+ wire [1 : 0] rxsynchd7 = 2'b00;// HIP input [1 : 0]
+ wire rxvalid0 ;// HIP input
+ wire rxvalid1 ;// HIP input
+ wire rxvalid2 ;// HIP input
+ wire rxvalid3 ;// HIP input
+ wire rxvalid4 ;// HIP input
+ wire rxvalid5 ;// HIP input
+ wire rxvalid6 ;// HIP input
+ wire rxvalid7 ;// HIP input
+ wire [17 : 0] currentcoeff0 ;// HIP output [17 : 0]
+ wire [17 : 0] currentcoeff1 ;// HIP output [17 : 0]
+ wire [17 : 0] currentcoeff2 ;// HIP output [17 : 0]
+ wire [17 : 0] currentcoeff3 ;// HIP output [17 : 0]
+ wire [17 : 0] currentcoeff4 ;// HIP output [17 : 0]
+ wire [17 : 0] currentcoeff5 ;// HIP output [17 : 0]
+ wire [17 : 0] currentcoeff6 ;// HIP output [17 : 0]
+ wire [17 : 0] currentcoeff7 ;// HIP output [17 : 0]
+ wire [2 : 0] currentrxpreset0 ;// HIP output [2 : 0]
+ wire [2 : 0] currentrxpreset1 ;// HIP output [2 : 0]
+ wire [2 : 0] currentrxpreset2 ;// HIP output [2 : 0]
+ wire [2 : 0] currentrxpreset3 ;// HIP output [2 : 0]
+ wire [2 : 0] currentrxpreset4 ;// HIP output [2 : 0]
+ wire [2 : 0] currentrxpreset5 ;// HIP output [2 : 0]
+ wire [2 : 0] currentrxpreset6 ;// HIP output [2 : 0]
+ wire [2 : 0] currentrxpreset7 ;// HIP output [2 : 0]
+ wire [2 : 0] eidleinfersel0 ;// HIP output [2 : 0]
+ wire [2 : 0] eidleinfersel1 ;// HIP output [2 : 0]
+ wire [2 : 0] eidleinfersel2 ;// HIP output [2 : 0]
+ wire [2 : 0] eidleinfersel3 ;// HIP output [2 : 0]
+ wire [2 : 0] eidleinfersel4 ;// HIP output [2 : 0]
+ wire [2 : 0] eidleinfersel5 ;// HIP output [2 : 0]
+ wire [2 : 0] eidleinfersel6 ;// HIP output [2 : 0]
+ wire [2 : 0] eidleinfersel7 ;// HIP output [2 : 0]
+ wire [1 : 0] powerdown0 ;// HIP output [1 : 0]
+ wire [1 : 0] powerdown1 ;// HIP output [1 : 0]
+ wire [1 : 0] powerdown2 ;// HIP output [1 : 0]
+ wire [1 : 0] powerdown3 ;// HIP output [1 : 0]
+ wire [1 : 0] powerdown4 ;// HIP output [1 : 0]
+ wire [1 : 0] powerdown5 ;// HIP output [1 : 0]
+ wire [1 : 0] powerdown6 ;// HIP output [1 : 0]
+ wire [1 : 0] powerdown7 ;// HIP output [1 : 0]
+ wire rxpolarity0 ;// HIP output
+ wire rxpolarity1 ;// HIP output
+ wire rxpolarity2 ;// HIP output
+ wire rxpolarity3 ;// HIP output
+ wire rxpolarity4 ;// HIP output
+ wire rxpolarity5 ;// HIP output
+ wire rxpolarity6 ;// HIP output
+ wire rxpolarity7 ;// HIP output
+ wire txblkst0 ;// HIP output
+ wire txblkst1 ;// HIP output
+ wire txblkst2 ;// HIP output
+ wire txblkst3 ;// HIP output
+ wire txblkst4 ;// HIP output
+ wire txblkst5 ;// HIP output
+ wire txblkst6 ;// HIP output
+ wire txblkst7 ;// HIP output
+ wire txcompl0 ;// HIP output
+ wire txcompl1 ;// HIP output
+ wire txcompl2 ;// HIP output
+ wire txcompl3 ;// HIP output
+ wire txcompl4 ;// HIP output
+ wire txcompl5 ;// HIP output
+ wire txcompl6 ;// HIP output
+ wire txcompl7 ;// HIP output
+ wire [31 : 0] txdata0 ;// HIP output [31 : 0]
+ wire [31 : 0] txdata1 ;// HIP output [31 : 0]
+ wire [31 : 0] txdata2 ;// HIP output [31 : 0]
+ wire [31 : 0] txdata3 ;// HIP output [31 : 0]
+ wire [31 : 0] txdata4 ;// HIP output [31 : 0]
+ wire [31 : 0] txdata5 ;// HIP output [31 : 0]
+ wire [31 : 0] txdata6 ;// HIP output [31 : 0]
+ wire [31 : 0] txdata7 ;// HIP output [31 : 0]
+ wire [3 : 0] txdatak0 ;// HIP output [3 : 0]
+ wire [3 : 0] txdatak1 ;// HIP output [3 : 0]
+ wire [3 : 0] txdatak2 ;// HIP output [3 : 0]
+ wire [3 : 0] txdatak3 ;// HIP output [3 : 0]
+ wire [3 : 0] txdatak4 ;// HIP output [3 : 0]
+ wire [3 : 0] txdatak5 ;// HIP output [3 : 0]
+ wire [3 : 0] txdatak6 ;// HIP output [3 : 0]
+ wire [3 : 0] txdatak7 ;// HIP output [3 : 0]
+ wire txdatavalid0 ;// Going nowhere to remove
+ wire txdatavalid1 ;// Going nowhere to remove
+ wire txdatavalid2 ;// Going nowhere to remove
+ wire txdatavalid3 ;// Going nowhere to remove
+ wire txdatavalid4 ;// Going nowhere to remove
+ wire txdatavalid5 ;// Going nowhere to remove
+ wire txdatavalid6 ;// Going nowhere to remove
+ wire txdatavalid7 ;// Going nowhere to remove
+ wire txdeemph0 ;// HIP output
+ wire txdeemph1 ;// HIP output
+ wire txdeemph2 ;// HIP output
+ wire txdeemph3 ;// HIP output
+ wire txdeemph4 ;// HIP output
+ wire txdeemph5 ;// HIP output
+ wire txdeemph6 ;// HIP output
+ wire txdeemph7 ;// HIP output
+ wire txdetectrx0 ;// HIP output
+ wire txdetectrx1 ;// HIP output
+ wire txdetectrx2 ;// HIP output
+ wire txdetectrx3 ;// HIP output
+ wire txdetectrx4 ;// HIP output
+ wire txdetectrx5 ;// HIP output
+ wire txdetectrx6 ;// HIP output
+ wire txdetectrx7 ;// HIP output
+ wire txelecidle0 ;// HIP output
+ wire txelecidle1 ;// HIP output
+ wire txelecidle2 ;// HIP output
+ wire txelecidle3 ;// HIP output
+ wire txelecidle4 ;// HIP output
+ wire txelecidle5 ;// HIP output
+ wire txelecidle6 ;// HIP output
+ wire txelecidle7 ;// HIP output
+ wire [2 : 0] txmargin0 ;// HIP output [2 : 0]
+ wire [2 : 0] txmargin1 ;// HIP output [2 : 0]
+ wire [2 : 0] txmargin2 ;// HIP output [2 : 0]
+ wire [2 : 0] txmargin3 ;// HIP output [2 : 0]
+ wire [2 : 0] txmargin4 ;// HIP output [2 : 0]
+ wire [2 : 0] txmargin5 ;// HIP output [2 : 0]
+ wire [2 : 0] txmargin6 ;// HIP output [2 : 0]
+ wire [2 : 0] txmargin7 ;// HIP output [2 : 0]
+ wire [1 : 0] txsynchd0 ;// HIP output [1 : 0]
+ wire [1 : 0] txsynchd1 ;// HIP output [1 : 0]
+ wire [1 : 0] txsynchd2 ;// HIP output [1 : 0]
+ wire [1 : 0] txsynchd3 ;// HIP output [1 : 0]
+ wire [1 : 0] txsynchd4 ;// HIP output [1 : 0]
+ wire [1 : 0] txsynchd5 ;// HIP output [1 : 0]
+ wire [1 : 0] txsynchd6 ;// HIP output [1 : 0]
+ wire [1 : 0] txsynchd7 ;// HIP output [1 : 0]
+
+ wire [ 1:0 ] rate0;
+ wire [ 1:0 ] rate1;
+ wire [ 1:0 ] rate2;
+ wire [ 1:0 ] rate3;
+ wire [ 1:0 ] rate4;
+ wire [ 1:0 ] rate5;
+ wire [ 1:0 ] rate6;
+ wire [ 1:0 ] rate7;
+
+ wire phystatus0_ext32b;
+ wire phystatus1_ext32b;
+ wire phystatus2_ext32b;
+ wire phystatus3_ext32b;
+ wire phystatus4_ext32b;
+ wire phystatus5_ext32b;
+ wire phystatus6_ext32b;
+ wire phystatus7_ext32b;
+ wire [31 : 0] rxdata0_ext32b;
+ wire [31 : 0] rxdata1_ext32b;
+ wire [31 : 0] rxdata2_ext32b;
+ wire [31 : 0] rxdata3_ext32b;
+ wire [31 : 0] rxdata4_ext32b;
+ wire [31 : 0] rxdata5_ext32b;
+ wire [31 : 0] rxdata6_ext32b;
+ wire [31 : 0] rxdata7_ext32b;
+ wire [3 : 0] rxdatak0_ext32b;
+ wire [3 : 0] rxdatak1_ext32b;
+ wire [3 : 0] rxdatak2_ext32b;
+ wire [3 : 0] rxdatak3_ext32b;
+ wire [3 : 0] rxdatak4_ext32b;
+ wire [3 : 0] rxdatak5_ext32b;
+ wire [3 : 0] rxdatak6_ext32b;
+ wire [3 : 0] rxdatak7_ext32b;
+ wire rxelecidle0_ext32b;
+ wire rxelecidle1_ext32b;
+ wire rxelecidle2_ext32b;
+ wire rxelecidle3_ext32b;
+ wire rxelecidle4_ext32b;
+ wire rxelecidle5_ext32b;
+ wire rxelecidle6_ext32b;
+ wire rxelecidle7_ext32b;
+ wire rxfreqlocked0_ext32b;
+ wire rxfreqlocked1_ext32b;
+ wire rxfreqlocked2_ext32b;
+ wire rxfreqlocked3_ext32b;
+ wire rxfreqlocked4_ext32b;
+ wire rxfreqlocked5_ext32b;
+ wire rxfreqlocked6_ext32b;
+ wire rxfreqlocked7_ext32b;
+ wire [2 : 0] rxstatus0_ext32b;
+ wire [2 : 0] rxstatus1_ext32b;
+ wire [2 : 0] rxstatus2_ext32b;
+ wire [2 : 0] rxstatus3_ext32b;
+ wire [2 : 0] rxstatus4_ext32b;
+ wire [2 : 0] rxstatus5_ext32b;
+ wire [2 : 0] rxstatus6_ext32b;
+ wire [2 : 0] rxstatus7_ext32b;
+ wire rxdataskip0_ext32b;
+ wire rxdataskip1_ext32b;
+ wire rxdataskip2_ext32b;
+ wire rxdataskip3_ext32b;
+ wire rxdataskip4_ext32b;
+ wire rxdataskip5_ext32b;
+ wire rxdataskip6_ext32b;
+ wire rxdataskip7_ext32b;
+ wire rxblkst0_ext32b;
+ wire rxblkst1_ext32b;
+ wire rxblkst2_ext32b;
+ wire rxblkst3_ext32b;
+ wire rxblkst4_ext32b;
+ wire rxblkst5_ext32b;
+ wire rxblkst6_ext32b;
+ wire rxblkst7_ext32b;
+ wire [1 : 0] rxsynchd0_ext32b;
+ wire [1 : 0] rxsynchd1_ext32b;
+ wire [1 : 0] rxsynchd2_ext32b;
+ wire [1 : 0] rxsynchd3_ext32b;
+ wire [1 : 0] rxsynchd4_ext32b;
+ wire [1 : 0] rxsynchd5_ext32b;
+ wire [1 : 0] rxsynchd6_ext32b;
+ wire [1 : 0] rxsynchd7_ext32b;
+ wire rxvalid0_ext32b;
+ wire rxvalid1_ext32b;
+ wire rxvalid2_ext32b;
+ wire rxvalid3_ext32b;
+ wire rxvalid4_ext32b;
+ wire rxvalid5_ext32b;
+ wire rxvalid6_ext32b;
+ wire rxvalid7_ext32b;
+
+ // PLD Application clocks core_clkout
+ wire coreclkout_hip;
+ wire pld_clk_hip;
+ wire pll_250_locked;
+ wire pll_250_pld_clk;
+
+ // serial assignment
+
+
+ alt5gxb_reset_controller alt5gxb_reset_controller0
+ (
+ .async_reset (pipe_mode|~npor), // I
+ .test_sim (test_in[0]), // I
+ .fifo_err (1'b0), // I
+ .inclk (pld_clk_hip), // I
+ .inclk_eq_125mhz (1'b0), // I
+ .pll_locked (serdes_pll_locked), // I
+ .rx_pll_locked (rc_pll_locked), // I //???
+
+ .rxanalogreset (rst_ctrl_rxanalogreset ), // O
+ .rxdigitalreset (rst_ctrl_rxdigitalreset ), // O
+ .gxb_powerdown (rst_ctrl_gxb_powerdown ), // O
+ .txdigitalreset (rst_ctrl_txdigitalreset ) // O
+ );
+
+ generate
+ begin : serdes_rst
+ for (i=0;i<lanes;i=i+1) begin : g_serdes_rst
+ assign serdes_gxb_powerdown [i] = rst_ctrl_gxb_powerdown;
+ assign serdes_tx_digitalreset[i] = rst_ctrl_txdigitalreset;
+ assign serdes_rx_analogreset [i] = rst_ctrl_rxanalogreset;
+ assign serdes_rx_digitalreset[i] = rst_ctrl_rxdigitalreset;
+ end
+ end
+ endgenerate
+
+
+ generate begin : hip_wysiwyg
+ if (lanes==1) begin
+ // TX
+
+ assign serdes_pipe_rate[1:0] = rate0[1:0]; // Currently only Gen2 rate0[1] is unconnected
+
+ assign serdes_pipe_txdata[31 :0 ] = txdata0;
+
+ assign serdes_pipe_txdatak[ 3: 0] = txdatak0;
+
+ assign serdes_pipe_txcompliance[0] = txcompl0;
+
+ assign serdes_pipe_txelecidle[0] = txelecidle0;
+
+ assign serdes_pipe_txdeemph[0] = txdeemph0;
+
+ assign serdes_pipe_txmargin[ 2: 0] = txmargin0;
+
+ assign serdes_pipe_powerdown[ 1 : 0] = powerdown0;
+
+ assign serdes_pipe_rxpolarity[0] = rxpolarity0 ;
+
+ assign serdes_pipe_txdetectrx_loopback[0] = txdetectrx0;
+
+ assign tx_out0 = serdes_tx_serial_data[0];
+
+ //RX
+ //
+ assign serdes_rx_serial_data[0]=rx_in0;
+
+ assign serdes_rx_eidleinfersel[2:0] = eidleinfersel0;
+
+ assign rxdata0 = (pipe_mode_simu_only==1'b1)?rxdata0_ext32b :serdes_pipe_rxdata[31 :0 ];
+
+ assign rxdatak0 = (pipe_mode_simu_only==1'b1)?rxdatak0_ext32b :serdes_pipe_rxdatak[ 3: 0] ;
+
+ assign rxvalid0 = (pipe_mode_simu_only==1'b1)?rxvalid0_ext32b :serdes_pipe_rxvalid[0] ;
+
+ assign rxelecidle0 = (pipe_mode_simu_only==1'b1)?rxelecidle0_ext32b:serdes_pipe_rxelecidle[0] ;
+
+ assign phystatus0 = (pipe_mode_simu_only==1'b1)?phystatus0_ext32b :serdes_pipe_phystatus[0] ;
+
+ assign rxstatus0 = (pipe_mode_simu_only==1'b1)?rxstatus0_ext32b :serdes_pipe_rxstatus[ 2: 0];
+
+ assign mserdes_pipe_pclk = serdes_pipe_pclk;
+ assign mserdes_pipe_pclkch1 = unconnected_wire;
+ assign mserdes_pllfixedclkch0 = serdes_pllfixedclkch0;
+ assign mserdes_pllfixedclkch1 = unconnected_wire;
+ assign mserdes_pipe_pclkcentral = unconnected_wire;
+ assign mserdes_pllfixedclkcentral= unconnected_wire;
+
+ assign rxdata1 = (pipe_mode_simu_only==1'b1)?rxdata1_ext32b :unconnected_bus[31:0];
+ assign rxdata2 = (pipe_mode_simu_only==1'b1)?rxdata2_ext32b :unconnected_bus[31:0];
+ assign rxdata3 = (pipe_mode_simu_only==1'b1)?rxdata3_ext32b :unconnected_bus[31:0];
+ assign rxdata4 = (pipe_mode_simu_only==1'b1)?rxdata4_ext32b :unconnected_bus[31:0];
+ assign rxdata5 = (pipe_mode_simu_only==1'b1)?rxdata5_ext32b :unconnected_bus[31:0];
+ assign rxdata6 = (pipe_mode_simu_only==1'b1)?rxdata6_ext32b :unconnected_bus[31:0];
+ assign rxdata7 = (pipe_mode_simu_only==1'b1)?rxdata7_ext32b :unconnected_bus[31:0];
+
+ assign rxdatak1 = (pipe_mode_simu_only==1'b1)?rxdatak1_ext32b :unconnected_bus[3:0] ;
+ assign rxdatak2 = (pipe_mode_simu_only==1'b1)?rxdatak2_ext32b :unconnected_bus[3:0] ;
+ assign rxdatak3 = (pipe_mode_simu_only==1'b1)?rxdatak3_ext32b :unconnected_bus[3:0] ;
+ assign rxdatak4 = (pipe_mode_simu_only==1'b1)?rxdatak4_ext32b :unconnected_bus[3:0] ;
+ assign rxdatak5 = (pipe_mode_simu_only==1'b1)?rxdatak5_ext32b :unconnected_bus[3:0] ;
+ assign rxdatak6 = (pipe_mode_simu_only==1'b1)?rxdatak6_ext32b :unconnected_bus[3:0] ;
+ assign rxdatak7 = (pipe_mode_simu_only==1'b1)?rxdatak7_ext32b :unconnected_bus[3:0] ;
+
+ assign rxvalid1 = (pipe_mode_simu_only==1'b1)?rxvalid1_ext32b :unconnected_wire;
+ assign rxvalid2 = (pipe_mode_simu_only==1'b1)?rxvalid2_ext32b :unconnected_wire;
+ assign rxvalid3 = (pipe_mode_simu_only==1'b1)?rxvalid3_ext32b :unconnected_wire;
+ assign rxvalid4 = (pipe_mode_simu_only==1'b1)?rxvalid4_ext32b :unconnected_wire;
+ assign rxvalid5 = (pipe_mode_simu_only==1'b1)?rxvalid5_ext32b :unconnected_wire;
+ assign rxvalid6 = (pipe_mode_simu_only==1'b1)?rxvalid6_ext32b :unconnected_wire;
+ assign rxvalid7 = (pipe_mode_simu_only==1'b1)?rxvalid7_ext32b :unconnected_wire;
+
+ assign rxelecidle1 = (pipe_mode_simu_only==1'b1)?rxelecidle1_ext32b:unconnected_wire;
+ assign rxelecidle2 = (pipe_mode_simu_only==1'b1)?rxelecidle2_ext32b:unconnected_wire;
+ assign rxelecidle3 = (pipe_mode_simu_only==1'b1)?rxelecidle3_ext32b:unconnected_wire;
+ assign rxelecidle4 = (pipe_mode_simu_only==1'b1)?rxelecidle4_ext32b:unconnected_wire;
+ assign rxelecidle5 = (pipe_mode_simu_only==1'b1)?rxelecidle5_ext32b:unconnected_wire;
+ assign rxelecidle6 = (pipe_mode_simu_only==1'b1)?rxelecidle6_ext32b:unconnected_wire;
+ assign rxelecidle7 = (pipe_mode_simu_only==1'b1)?rxelecidle7_ext32b:unconnected_wire;
+
+ assign phystatus1 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire;
+ assign phystatus2 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire;
+ assign phystatus3 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire;
+ assign phystatus4 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire;
+ assign phystatus5 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire;
+ assign phystatus6 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire;
+ assign phystatus7 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire;
+
+ assign rxstatus1 = (pipe_mode_simu_only==1'b1)?rxstatus1_ext32b :unconnected_bus[2:0];
+ assign rxstatus2 = (pipe_mode_simu_only==1'b1)?rxstatus2_ext32b :unconnected_bus[2:0];
+ assign rxstatus3 = (pipe_mode_simu_only==1'b1)?rxstatus3_ext32b :unconnected_bus[2:0];
+ assign rxstatus4 = (pipe_mode_simu_only==1'b1)?rxstatus4_ext32b :unconnected_bus[2:0];
+ assign rxstatus5 = (pipe_mode_simu_only==1'b1)?rxstatus5_ext32b :unconnected_bus[2:0];
+ assign rxstatus6 = (pipe_mode_simu_only==1'b1)?rxstatus6_ext32b :unconnected_bus[2:0];
+ assign rxstatus7 = (pipe_mode_simu_only==1'b1)?rxstatus7_ext32b :unconnected_bus[2:0];
+
+ end
+ else if (lanes==2) begin
+ // TX
+
+ assign serdes_pipe_rate[1:0] = rate0[1:0];
+ assign serdes_pipe_rate[3:2] = rate1[1:0];
+
+ assign serdes_pipe_txdata[31 :0 ] = txdata0;
+ assign serdes_pipe_txdata[63 :32 ] = txdata1;
+
+ assign serdes_pipe_txdatak[ 3: 0] = txdatak0;
+ assign serdes_pipe_txdatak[ 7: 4] = txdatak1;
+
+ assign serdes_pipe_txcompliance[0] = txcompl0;
+ assign serdes_pipe_txcompliance[1] = txcompl1;
+
+ assign serdes_pipe_txelecidle[0] = txelecidle0;
+ assign serdes_pipe_txelecidle[1] = txelecidle1;
+
+ assign serdes_pipe_txdeemph[0] = txdeemph0;
+ assign serdes_pipe_txdeemph[1] = txdeemph1;
+
+ assign serdes_pipe_txmargin[ 2: 0] = txmargin0;
+ assign serdes_pipe_txmargin[ 5: 3] = txmargin1;
+
+ assign serdes_pipe_powerdown[ 1 : 0] = powerdown0;
+ assign serdes_pipe_powerdown[ 3 : 2] = powerdown1;
+
+ assign serdes_pipe_rxpolarity[0] = rxpolarity0 ;
+ assign serdes_pipe_rxpolarity[1] = rxpolarity1 ;
+
+ assign serdes_pipe_txdetectrx_loopback[0] = txdetectrx0;
+ assign serdes_pipe_txdetectrx_loopback[1] = txdetectrx1;
+
+ assign tx_out0 = serdes_tx_serial_data[0];
+ assign tx_out1 = serdes_tx_serial_data[1];
+
+ //RX
+ //
+ assign serdes_rx_serial_data[0]=rx_in0;
+ assign serdes_rx_serial_data[1]=rx_in1;
+
+ assign serdes_rx_eidleinfersel[2:0] = eidleinfersel0;
+ assign serdes_rx_eidleinfersel[5:3] = eidleinfersel1;
+
+ assign rxdata0 = (pipe_mode_simu_only==1'b1)?rxdata0_ext32b :serdes_pipe_rxdata[31 :0 ];
+ assign rxdata1 = (pipe_mode_simu_only==1'b1)?rxdata1_ext32b :serdes_pipe_rxdata[63 :32 ];
+
+ assign rxdatak0 = (pipe_mode_simu_only==1'b1)?rxdatak0_ext32b :serdes_pipe_rxdatak[ 3: 0] ;
+ assign rxdatak1 = (pipe_mode_simu_only==1'b1)?rxdatak1_ext32b :serdes_pipe_rxdatak[ 7: 4] ;
+
+ assign rxvalid0 = (pipe_mode_simu_only==1'b1)?rxvalid0_ext32b :serdes_pipe_rxvalid[0] ;
+ assign rxvalid1 = (pipe_mode_simu_only==1'b1)?rxvalid1_ext32b :serdes_pipe_rxvalid[1] ;
+
+ assign rxelecidle0 = (pipe_mode_simu_only==1'b1)?rxelecidle0_ext32b:serdes_pipe_rxelecidle[0] ;
+ assign rxelecidle1 = (pipe_mode_simu_only==1'b1)?rxelecidle1_ext32b:serdes_pipe_rxelecidle[1] ;
+
+ assign phystatus0 = (pipe_mode_simu_only==1'b1)?phystatus0_ext32b :serdes_pipe_phystatus[0] ;
+ assign phystatus1 = (pipe_mode_simu_only==1'b1)?phystatus1_ext32b :serdes_pipe_phystatus[1] ;
+
+ assign rxstatus0 = (pipe_mode_simu_only==1'b1)?rxstatus0_ext32b :serdes_pipe_rxstatus[ 2: 0];
+ assign rxstatus1 = (pipe_mode_simu_only==1'b1)?rxstatus1_ext32b :serdes_pipe_rxstatus[ 5: 3];
+
+ assign mserdes_pipe_pclk = unconnected_wire;
+ assign mserdes_pipe_pclkch1 = serdes_pipe_pclkch1;
+ assign mserdes_pllfixedclkch0 = unconnected_wire;
+ assign mserdes_pllfixedclkch1 = serdes_pllfixedclkch1 ;
+ assign mserdes_pipe_pclkcentral = unconnected_wire;
+ assign mserdes_pllfixedclkcentral= unconnected_wire;
+
+ assign phystatus2 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+ assign phystatus3 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+ assign phystatus4 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+ assign phystatus5 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+ assign phystatus6 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+ assign phystatus7 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+
+ end
+ else if (lanes==4) begin
+ // TX
+ assign serdes_pipe_rate[1:0] = rate0[1:0];
+ assign serdes_pipe_rate[3:2] = rate1[1:0];
+ assign serdes_pipe_rate[5:4] = rate2[1:0];
+ assign serdes_pipe_rate[7:6] = rate3[1:0];
+
+ assign serdes_pipe_txdata[31 :0 ] = txdata0;
+ assign serdes_pipe_txdata[63 :32 ] = txdata1;
+ assign serdes_pipe_txdata[95 :64 ] = txdata2;
+ assign serdes_pipe_txdata[127:96 ] = txdata3;
+
+ assign serdes_pipe_txdatak[ 3: 0] = txdatak0;
+ assign serdes_pipe_txdatak[ 7: 4] = txdatak1;
+ assign serdes_pipe_txdatak[11: 8] = txdatak2;
+ assign serdes_pipe_txdatak[15:12] = txdatak3;
+
+ assign serdes_pipe_txcompliance[0] = txcompl0;
+ assign serdes_pipe_txcompliance[1] = txcompl1;
+ assign serdes_pipe_txcompliance[2] = txcompl2;
+ assign serdes_pipe_txcompliance[3] = txcompl3;
+
+ assign serdes_pipe_txelecidle[0] = txelecidle0;
+ assign serdes_pipe_txelecidle[1] = txelecidle1;
+ assign serdes_pipe_txelecidle[2] = txelecidle2;
+ assign serdes_pipe_txelecidle[3] = txelecidle3;
+
+ assign serdes_pipe_txdeemph[0] = txdeemph0;
+ assign serdes_pipe_txdeemph[1] = txdeemph1;
+ assign serdes_pipe_txdeemph[2] = txdeemph2;
+ assign serdes_pipe_txdeemph[3] = txdeemph3;
+
+ assign serdes_pipe_txmargin[ 2: 0] = txmargin0;
+ assign serdes_pipe_txmargin[ 5: 3] = txmargin1;
+ assign serdes_pipe_txmargin[ 8: 6] = txmargin2;
+ assign serdes_pipe_txmargin[11: 9] = txmargin3;
+
+ assign serdes_pipe_powerdown[ 1 : 0] = powerdown0;
+ assign serdes_pipe_powerdown[ 3 : 2] = powerdown1;
+ assign serdes_pipe_powerdown[ 5 : 4] = powerdown2;
+ assign serdes_pipe_powerdown[ 7 : 6] = powerdown3;
+
+ assign serdes_pipe_rxpolarity[0] = rxpolarity0 ;
+ assign serdes_pipe_rxpolarity[1] = rxpolarity1 ;
+ assign serdes_pipe_rxpolarity[2] = rxpolarity2 ;
+ assign serdes_pipe_rxpolarity[3] = rxpolarity3 ;
+
+ assign serdes_pipe_txdetectrx_loopback[0] = txdetectrx0;
+ assign serdes_pipe_txdetectrx_loopback[1] = txdetectrx1;
+ assign serdes_pipe_txdetectrx_loopback[2] = txdetectrx2;
+ assign serdes_pipe_txdetectrx_loopback[3] = txdetectrx3;
+
+ assign tx_out0 = serdes_tx_serial_data[0];
+ assign tx_out1 = serdes_tx_serial_data[1];
+ assign tx_out2 = serdes_tx_serial_data[2];
+ assign tx_out3 = serdes_tx_serial_data[3];
+
+ //RX
+ //
+ assign serdes_rx_serial_data[0]=rx_in0;
+ assign serdes_rx_serial_data[1]=rx_in1;
+ assign serdes_rx_serial_data[2]=rx_in2;
+ assign serdes_rx_serial_data[3]=rx_in3;
+
+ assign serdes_rx_eidleinfersel[2:0] = eidleinfersel0;
+ assign serdes_rx_eidleinfersel[5:3] = eidleinfersel1;
+ assign serdes_rx_eidleinfersel[8:6] = eidleinfersel2;
+ assign serdes_rx_eidleinfersel[11:9]= eidleinfersel3;
+
+ assign rxdata0 = (pipe_mode_simu_only==1'b1)?rxdata0_ext32b :serdes_pipe_rxdata[31 :0 ];
+ assign rxdata1 = (pipe_mode_simu_only==1'b1)?rxdata1_ext32b :serdes_pipe_rxdata[63 :32 ];
+ assign rxdata2 = (pipe_mode_simu_only==1'b1)?rxdata2_ext32b :serdes_pipe_rxdata[95 :64 ];
+ assign rxdata3 = (pipe_mode_simu_only==1'b1)?rxdata3_ext32b :serdes_pipe_rxdata[127:96 ];
+
+ assign rxdatak0 = (pipe_mode_simu_only==1'b1)?rxdatak0_ext32b :serdes_pipe_rxdatak[ 3: 0] ;
+ assign rxdatak1 = (pipe_mode_simu_only==1'b1)?rxdatak1_ext32b :serdes_pipe_rxdatak[ 7: 4] ;
+ assign rxdatak2 = (pipe_mode_simu_only==1'b1)?rxdatak2_ext32b :serdes_pipe_rxdatak[11: 8] ;
+ assign rxdatak3 = (pipe_mode_simu_only==1'b1)?rxdatak3_ext32b :serdes_pipe_rxdatak[15:12] ;
+
+ assign rxvalid0 = (pipe_mode_simu_only==1'b1)?rxvalid0_ext32b :serdes_pipe_rxvalid[0] ;
+ assign rxvalid1 = (pipe_mode_simu_only==1'b1)?rxvalid1_ext32b :serdes_pipe_rxvalid[1] ;
+ assign rxvalid2 = (pipe_mode_simu_only==1'b1)?rxvalid2_ext32b :serdes_pipe_rxvalid[2] ;
+ assign rxvalid3 = (pipe_mode_simu_only==1'b1)?rxvalid3_ext32b :serdes_pipe_rxvalid[3] ;
+
+ assign rxelecidle0 = (pipe_mode_simu_only==1'b1)?rxelecidle0_ext32b:serdes_pipe_rxelecidle[0] ;
+ assign rxelecidle1 = (pipe_mode_simu_only==1'b1)?rxelecidle1_ext32b:serdes_pipe_rxelecidle[1] ;
+ assign rxelecidle2 = (pipe_mode_simu_only==1'b1)?rxelecidle2_ext32b:serdes_pipe_rxelecidle[2] ;
+ assign rxelecidle3 = (pipe_mode_simu_only==1'b1)?rxelecidle3_ext32b:serdes_pipe_rxelecidle[3] ;
+
+ assign phystatus0 = (pipe_mode_simu_only==1'b1)?phystatus0_ext32b :serdes_pipe_phystatus[0] ;
+ assign phystatus1 = (pipe_mode_simu_only==1'b1)?phystatus1_ext32b :serdes_pipe_phystatus[1] ;
+ assign phystatus2 = (pipe_mode_simu_only==1'b1)?phystatus2_ext32b :serdes_pipe_phystatus[2] ;
+ assign phystatus3 = (pipe_mode_simu_only==1'b1)?phystatus3_ext32b :serdes_pipe_phystatus[3] ;
+
+ assign rxstatus0 = (pipe_mode_simu_only==1'b1)?rxstatus0_ext32b :serdes_pipe_rxstatus[ 2: 0];
+ assign rxstatus1 = (pipe_mode_simu_only==1'b1)?rxstatus1_ext32b :serdes_pipe_rxstatus[ 5: 3];
+ assign rxstatus2 = (pipe_mode_simu_only==1'b1)?rxstatus2_ext32b :serdes_pipe_rxstatus[ 8: 6];
+ assign rxstatus3 = (pipe_mode_simu_only==1'b1)?rxstatus3_ext32b :serdes_pipe_rxstatus[11: 9];
+
+ assign mserdes_pipe_pclk = unconnected_wire;
+ assign mserdes_pipe_pclkch1 = serdes_pipe_pclkch1;
+ assign mserdes_pllfixedclkch0 = unconnected_wire;
+ assign mserdes_pllfixedclkch1 = serdes_pllfixedclkch1;
+ assign mserdes_pipe_pclkcentral = unconnected_wire;
+ assign mserdes_pllfixedclkcentral= unconnected_wire;
+
+ assign phystatus4 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+ assign phystatus5 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+ assign phystatus6 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+ assign phystatus7 = (pipe_mode_simu_only==1'b1)?1'b0 :unconnected_wire ;
+
+ end
+ else begin // x8
+ // TX
+ assign serdes_pipe_rate[1 : 0] = rate0[1:0];
+ assign serdes_pipe_rate[3 : 2] = rate1[1:0];
+ assign serdes_pipe_rate[5 : 4] = rate2[1:0];
+ assign serdes_pipe_rate[7 : 6] = rate3[1:0];
+ assign serdes_pipe_rate[9 : 8] = rate4[1:0];
+ assign serdes_pipe_rate[11:10] = rate5[1:0];
+ assign serdes_pipe_rate[13:12] = rate6[1:0];
+ assign serdes_pipe_rate[15:14] = rate7[1:0];
+
+ assign serdes_pipe_txdata[31 :0 ] = txdata0;
+ assign serdes_pipe_txdata[63 :32 ] = txdata1;
+ assign serdes_pipe_txdata[95 :64 ] = txdata2;
+ assign serdes_pipe_txdata[127:96 ] = txdata3;
+ assign serdes_pipe_txdata[159:128] = txdata4;
+ assign serdes_pipe_txdata[191:160] = txdata5;
+ assign serdes_pipe_txdata[223:192] = txdata6;
+ assign serdes_pipe_txdata[255:224] = txdata7;
+
+ assign serdes_pipe_txdatak[ 3: 0] = txdatak0;
+ assign serdes_pipe_txdatak[ 7: 4] = txdatak1;
+ assign serdes_pipe_txdatak[11: 8] = txdatak2;
+ assign serdes_pipe_txdatak[15:12] = txdatak3;
+ assign serdes_pipe_txdatak[19:16] = txdatak4;
+ assign serdes_pipe_txdatak[23:20] = txdatak5;
+ assign serdes_pipe_txdatak[27:24] = txdatak6;
+ assign serdes_pipe_txdatak[31:28] = txdatak7;
+
+ assign serdes_pipe_txcompliance[0] = txcompl0;
+ assign serdes_pipe_txcompliance[1] = txcompl1;
+ assign serdes_pipe_txcompliance[2] = txcompl2;
+ assign serdes_pipe_txcompliance[3] = txcompl3;
+ assign serdes_pipe_txcompliance[4] = txcompl4;
+ assign serdes_pipe_txcompliance[5] = txcompl5;
+ assign serdes_pipe_txcompliance[6] = txcompl6;
+ assign serdes_pipe_txcompliance[7] = txcompl7;
+
+ assign serdes_pipe_txelecidle[0] = txelecidle0;
+ assign serdes_pipe_txelecidle[1] = txelecidle1;
+ assign serdes_pipe_txelecidle[2] = txelecidle2;
+ assign serdes_pipe_txelecidle[3] = txelecidle3;
+ assign serdes_pipe_txelecidle[4] = txelecidle4;
+ assign serdes_pipe_txelecidle[5] = txelecidle5;
+ assign serdes_pipe_txelecidle[6] = txelecidle6;
+ assign serdes_pipe_txelecidle[7] = txelecidle7;
+
+ assign serdes_pipe_txdeemph[0] = txdeemph0;
+ assign serdes_pipe_txdeemph[1] = txdeemph1;
+ assign serdes_pipe_txdeemph[2] = txdeemph2;
+ assign serdes_pipe_txdeemph[3] = txdeemph3;
+ assign serdes_pipe_txdeemph[4] = txdeemph4;
+ assign serdes_pipe_txdeemph[5] = txdeemph5;
+ assign serdes_pipe_txdeemph[6] = txdeemph6;
+ assign serdes_pipe_txdeemph[7] = txdeemph7;
+
+ assign serdes_pipe_txmargin[ 2: 0] = txmargin0;
+ assign serdes_pipe_txmargin[ 5: 3] = txmargin1;
+ assign serdes_pipe_txmargin[ 8: 6] = txmargin2;
+ assign serdes_pipe_txmargin[11: 9] = txmargin3;
+ assign serdes_pipe_txmargin[14:12] = txmargin4;
+ assign serdes_pipe_txmargin[17:15] = txmargin5;
+ assign serdes_pipe_txmargin[20:18] = txmargin6;
+ assign serdes_pipe_txmargin[23:21] = txmargin7;
+
+ assign serdes_pipe_powerdown[ 1 : 0] = powerdown0;
+ assign serdes_pipe_powerdown[ 3 : 2] = powerdown1;
+ assign serdes_pipe_powerdown[ 5 : 4] = powerdown2;
+ assign serdes_pipe_powerdown[ 7 : 6] = powerdown3;
+ assign serdes_pipe_powerdown[ 9 : 8] = powerdown4;
+ assign serdes_pipe_powerdown[11 :10] = powerdown5;
+ assign serdes_pipe_powerdown[13 :12] = powerdown6;
+ assign serdes_pipe_powerdown[15 :14] = powerdown7;
+
+ assign serdes_pipe_rxpolarity[0] = rxpolarity0 ;
+ assign serdes_pipe_rxpolarity[1] = rxpolarity1 ;
+ assign serdes_pipe_rxpolarity[2] = rxpolarity2 ;
+ assign serdes_pipe_rxpolarity[3] = rxpolarity3 ;
+ assign serdes_pipe_rxpolarity[4] = rxpolarity4 ;
+ assign serdes_pipe_rxpolarity[5] = rxpolarity5 ;
+ assign serdes_pipe_rxpolarity[6] = rxpolarity6 ;
+ assign serdes_pipe_rxpolarity[7] = rxpolarity7 ;
+
+ assign serdes_pipe_txdetectrx_loopback[0] = txdetectrx0;
+ assign serdes_pipe_txdetectrx_loopback[1] = txdetectrx1;
+ assign serdes_pipe_txdetectrx_loopback[2] = txdetectrx2;
+ assign serdes_pipe_txdetectrx_loopback[3] = txdetectrx3;
+ assign serdes_pipe_txdetectrx_loopback[4] = txdetectrx4;
+ assign serdes_pipe_txdetectrx_loopback[5] = txdetectrx5;
+ assign serdes_pipe_txdetectrx_loopback[6] = txdetectrx6;
+ assign serdes_pipe_txdetectrx_loopback[7] = txdetectrx7;
+
+ assign tx_out0 = serdes_tx_serial_data[0];
+ assign tx_out1 = serdes_tx_serial_data[1];
+ assign tx_out2 = serdes_tx_serial_data[2];
+ assign tx_out3 = serdes_tx_serial_data[3];
+ assign tx_out4 = serdes_tx_serial_data[4];
+ assign tx_out5 = serdes_tx_serial_data[5];
+ assign tx_out6 = serdes_tx_serial_data[6];
+ assign tx_out7 = serdes_tx_serial_data[7];
+
+ //RX
+ //
+ assign serdes_rx_serial_data[0]=rx_in0;
+ assign serdes_rx_serial_data[1]=rx_in1;
+ assign serdes_rx_serial_data[2]=rx_in2;
+ assign serdes_rx_serial_data[3]=rx_in3;
+ assign serdes_rx_serial_data[4]=rx_in4;
+ assign serdes_rx_serial_data[5]=rx_in5;
+ assign serdes_rx_serial_data[6]=rx_in6;
+ assign serdes_rx_serial_data[7]=rx_in7;
+
+ assign serdes_rx_eidleinfersel[2:0] = eidleinfersel0;
+ assign serdes_rx_eidleinfersel[5:3] = eidleinfersel1;
+ assign serdes_rx_eidleinfersel[8:6] = eidleinfersel2;
+ assign serdes_rx_eidleinfersel[11:9] = eidleinfersel3;
+ assign serdes_rx_eidleinfersel[14:12] = eidleinfersel4;
+ assign serdes_rx_eidleinfersel[17:15] = eidleinfersel5;
+ assign serdes_rx_eidleinfersel[20:18] = eidleinfersel6;
+ assign serdes_rx_eidleinfersel[23:21] = eidleinfersel7;
+
+ assign rxdata0 = (pipe_mode_simu_only==1'b1)?rxdata0_ext32b :serdes_pipe_rxdata[31 :0 ];
+ assign rxdata1 = (pipe_mode_simu_only==1'b1)?rxdata1_ext32b :serdes_pipe_rxdata[63 :32 ];
+ assign rxdata2 = (pipe_mode_simu_only==1'b1)?rxdata2_ext32b :serdes_pipe_rxdata[95 :64 ];
+ assign rxdata3 = (pipe_mode_simu_only==1'b1)?rxdata3_ext32b :serdes_pipe_rxdata[127:96 ];
+ assign rxdata4 = (pipe_mode_simu_only==1'b1)?rxdata4_ext32b :serdes_pipe_rxdata[159:128];
+ assign rxdata5 = (pipe_mode_simu_only==1'b1)?rxdata5_ext32b :serdes_pipe_rxdata[191:160];
+ assign rxdata6 = (pipe_mode_simu_only==1'b1)?rxdata6_ext32b :serdes_pipe_rxdata[223:192];
+ assign rxdata7 = (pipe_mode_simu_only==1'b1)?rxdata7_ext32b :serdes_pipe_rxdata[255:224];
+
+ assign rxdatak0 = (pipe_mode_simu_only==1'b1)?rxdatak0_ext32b :serdes_pipe_rxdatak[ 3: 0] ;
+ assign rxdatak1 = (pipe_mode_simu_only==1'b1)?rxdatak1_ext32b :serdes_pipe_rxdatak[ 7: 4] ;
+ assign rxdatak2 = (pipe_mode_simu_only==1'b1)?rxdatak2_ext32b :serdes_pipe_rxdatak[11: 8] ;
+ assign rxdatak3 = (pipe_mode_simu_only==1'b1)?rxdatak3_ext32b :serdes_pipe_rxdatak[15:12] ;
+ assign rxdatak4 = (pipe_mode_simu_only==1'b1)?rxdatak4_ext32b :serdes_pipe_rxdatak[19:16] ;
+ assign rxdatak5 = (pipe_mode_simu_only==1'b1)?rxdatak5_ext32b :serdes_pipe_rxdatak[23:20] ;
+ assign rxdatak6 = (pipe_mode_simu_only==1'b1)?rxdatak6_ext32b :serdes_pipe_rxdatak[27:24] ;
+ assign rxdatak7 = (pipe_mode_simu_only==1'b1)?rxdatak7_ext32b :serdes_pipe_rxdatak[31:28] ;
+
+ assign rxvalid0 = (pipe_mode_simu_only==1'b1)?rxvalid0_ext32b :serdes_pipe_rxvalid[0] ;
+ assign rxvalid1 = (pipe_mode_simu_only==1'b1)?rxvalid1_ext32b :serdes_pipe_rxvalid[1] ;
+ assign rxvalid2 = (pipe_mode_simu_only==1'b1)?rxvalid2_ext32b :serdes_pipe_rxvalid[2] ;
+ assign rxvalid3 = (pipe_mode_simu_only==1'b1)?rxvalid3_ext32b :serdes_pipe_rxvalid[3] ;
+ assign rxvalid4 = (pipe_mode_simu_only==1'b1)?rxvalid4_ext32b :serdes_pipe_rxvalid[4] ;
+ assign rxvalid5 = (pipe_mode_simu_only==1'b1)?rxvalid5_ext32b :serdes_pipe_rxvalid[5] ;
+ assign rxvalid6 = (pipe_mode_simu_only==1'b1)?rxvalid6_ext32b :serdes_pipe_rxvalid[6] ;
+ assign rxvalid7 = (pipe_mode_simu_only==1'b1)?rxvalid7_ext32b :serdes_pipe_rxvalid[7] ;
+
+ assign rxelecidle0 = (pipe_mode_simu_only==1'b1)?rxelecidle0_ext32b:serdes_pipe_rxelecidle[0] ;
+ assign rxelecidle1 = (pipe_mode_simu_only==1'b1)?rxelecidle1_ext32b:serdes_pipe_rxelecidle[1] ;
+ assign rxelecidle2 = (pipe_mode_simu_only==1'b1)?rxelecidle2_ext32b:serdes_pipe_rxelecidle[2] ;
+ assign rxelecidle3 = (pipe_mode_simu_only==1'b1)?rxelecidle3_ext32b:serdes_pipe_rxelecidle[3] ;
+ assign rxelecidle4 = (pipe_mode_simu_only==1'b1)?rxelecidle4_ext32b:serdes_pipe_rxelecidle[4] ;
+ assign rxelecidle5 = (pipe_mode_simu_only==1'b1)?rxelecidle5_ext32b:serdes_pipe_rxelecidle[5] ;
+ assign rxelecidle6 = (pipe_mode_simu_only==1'b1)?rxelecidle6_ext32b:serdes_pipe_rxelecidle[6] ;
+ assign rxelecidle7 = (pipe_mode_simu_only==1'b1)?rxelecidle7_ext32b:serdes_pipe_rxelecidle[7] ;
+
+ assign phystatus0 = (pipe_mode_simu_only==1'b1)?phystatus0_ext32b :serdes_pipe_phystatus[0] ;
+ assign phystatus1 = (pipe_mode_simu_only==1'b1)?phystatus1_ext32b :serdes_pipe_phystatus[1] ;
+ assign phystatus2 = (pipe_mode_simu_only==1'b1)?phystatus2_ext32b :serdes_pipe_phystatus[2] ;
+ assign phystatus3 = (pipe_mode_simu_only==1'b1)?phystatus3_ext32b :serdes_pipe_phystatus[3] ;
+ assign phystatus4 = (pipe_mode_simu_only==1'b1)?phystatus4_ext32b :serdes_pipe_phystatus[4] ;
+ assign phystatus5 = (pipe_mode_simu_only==1'b1)?phystatus5_ext32b :serdes_pipe_phystatus[5] ;
+ assign phystatus6 = (pipe_mode_simu_only==1'b1)?phystatus6_ext32b :serdes_pipe_phystatus[6] ;
+ assign phystatus7 = (pipe_mode_simu_only==1'b1)?phystatus7_ext32b :serdes_pipe_phystatus[7] ;
+
+ assign rxstatus0 = (pipe_mode_simu_only==1'b1)?rxstatus0_ext32b :serdes_pipe_rxstatus[ 2: 0];
+ assign rxstatus1 = (pipe_mode_simu_only==1'b1)?rxstatus1_ext32b :serdes_pipe_rxstatus[ 5: 3];
+ assign rxstatus2 = (pipe_mode_simu_only==1'b1)?rxstatus2_ext32b :serdes_pipe_rxstatus[ 8: 6];
+ assign rxstatus3 = (pipe_mode_simu_only==1'b1)?rxstatus3_ext32b :serdes_pipe_rxstatus[11: 9];
+ assign rxstatus4 = (pipe_mode_simu_only==1'b1)?rxstatus4_ext32b :serdes_pipe_rxstatus[14:12];
+ assign rxstatus5 = (pipe_mode_simu_only==1'b1)?rxstatus5_ext32b :serdes_pipe_rxstatus[17:15];
+ assign rxstatus6 = (pipe_mode_simu_only==1'b1)?rxstatus6_ext32b :serdes_pipe_rxstatus[20:18];
+ assign rxstatus7 = (pipe_mode_simu_only==1'b1)?rxstatus7_ext32b :serdes_pipe_rxstatus[23:21];
+
+ assign mserdes_pipe_pclk = unconnected_wire;
+ assign mserdes_pipe_pclkch1 = unconnected_wire;
+ assign mserdes_pllfixedclkch0 = unconnected_wire;
+ assign mserdes_pllfixedclkch1 = unconnected_wire;
+ assign mserdes_pipe_pclkcentral = serdes_pipe_pclkcentral;
+ assign mserdes_pllfixedclkcentral= serdes_pllfixedclkcentral;
+ end
+ end
+ endgenerate
+
+ assign rate = (pipe_mode_simu_only==1'b1)?rate0:2'b00;
+ assign rc_pll_locked = (pipe_mode_simu_only==1)?1'b1 :(PLD_CLK_IS_250MHZ==0)?serdes_pll_locked:pll_250_locked;
+
+ generate begin : g_hip_coreclkout_gclk
+ if (PLD_CLK_IS_250MHZ==0) begin
+ global u_global_buffer_coreclkout (.in(coreclkout_hip), .out(coreclkout));
+ assign pld_clk_hip = pld_clk;
+ assign pll_250_locked = 1'b1;
+
+ end
+ else begin
+ wire fbclkout;
+ wire open_locked;
+ wire open_fbclkout;
+
+ assign pld_clk_hip = pll_250_pld_clk;
+
+ generic_pll # ( .reference_clock_frequency("250.0 MHz"), .output_clock_frequency("250.0 MHz") )
+ u_pll_coreclkout ( .refclk(coreclkout_hip), .outclk(coreclkout), .locked(pll_250_locked), .fboutclk(fbclkout), .rst((pipe_mode_simu_only==1)?1'b0:~serdes_pll_locked), .fbclk(fbclkout));
+
+ generic_pll # ( .reference_clock_frequency("250.0 MHz"), .output_clock_frequency("250.0 MHz") )
+ u_pll_pldclk ( .refclk(coreclkout_hip), .outclk(pll_250_pld_clk), .locked(open_locked), .fboutclk(open_fbclkout), .rst((pipe_mode_simu_only==1)?1'b0:~serdes_pll_locked), .fbclk(fbclkout));
+ end
+ end
+ endgenerate
+
+ stratixv_hssi_gen3_pcie_hip # (
+ .func_mode("enable"),
+ .bonding_mode(((low_str(gen123_lane_rate_mode)=="gen1_gen2_gen3")&&(low_str(lane_mask)=="x8"))?"x8_g3" :
+ (low_str(lane_mask)=="x8")?"x8_g1g2":
+ (low_str(lane_mask)=="x4")?"x4" :
+ (low_str(lane_mask)=="x2")?"x2" :"x1"),
+ .prot_mode((low_str(gen123_lane_rate_mode)=="gen1_gen2_gen3")?"pipe_g3":
+ (low_str(gen123_lane_rate_mode)=="gen1_gen2")?"pipe_g2":"pipe_g1"),
+ .vc_enable(vc_enable),
+ .enable_slot_register(enable_slot_register),
+ .pcie_mode(pcie_mode),
+ .bypass_cdc(bypass_cdc),
+ .enable_rx_reordering(enable_rx_reordering),
+ .enable_rx_buffer_checking(enable_rx_buffer_checking),
+ .single_rx_detect_data(single_rx_detect),
+ .use_crc_forwarding(use_crc_forwarding),
+ .bypass_tl(bypass_tl),
+ .gen123_lane_rate_mode(gen123_lane_rate_mode),
+ .lane_mask(lane_mask),
+ .disable_link_x2_support(disable_link_x2_support),
+ .national_inst_thru_enhance(national_inst_thru_enhance),
+ .hip_hard_reset(hip_hard_reset),
+ .dis_paritychk(dis_paritychk),
+ .wrong_device_id(wrong_device_id),
+ .data_pack_rx(data_pack_rx),
+ .ast_width(ast_width),
+ .rx_sop_ctrl((low_str(ast_width)=="rx_tx_256")? "boundary_256":rx_sop_ctrl),
+ .rx_ast_parity(rx_ast_parity),
+ .tx_ast_parity(tx_ast_parity),
+ .ltssm_1ms_timeout(ltssm_1ms_timeout),
+ .ltssm_freqlocked_check(ltssm_freqlocked_check),
+ .deskew_comma(deskew_comma),
+ .port_link_number_data(port_link_number),
+ .device_number_data(device_number),
+ .bypass_clk_switch(bypass_clk_switch),
+ .core_clk_out_sel(core_clk_out_sel),
+ .core_clk_divider(core_clk_divider),
+ .core_clk_source(core_clk_source),
+ .core_clk_sel(core_clk_sel),
+ .enable_ch0_pclk_out(enable_ch0_pclk_out),
+ .enable_ch01_pclk_out(enable_ch01_pclk_out),
+ .pipex1_debug_sel(pipex1_debug_sel),
+ .pclk_out_sel(pclk_out_sel),
+ .vendor_id_data(vendor_id),
+ .device_id_data(device_id),
+ .revision_id_data(revision_id),
+ .class_code_data(class_code),
+ .subsystem_vendor_id_data(subsystem_vendor_id),
+ .subsystem_device_id_data(subsystem_device_id),
+ .no_soft_reset(no_soft_reset),
+ .maximum_current_data(maximum_current),
+ .d1_support(d1_support),
+ .d2_support(d2_support),
+ .d0_pme(d0_pme),
+ .d1_pme(d1_pme),
+ .d2_pme(d2_pme),
+ .d3_hot_pme(d3_hot_pme),
+ .d3_cold_pme(d3_cold_pme),
+ .use_aer(use_aer),
+ .low_priority_vc(low_priority_vc),
+ .vc_arbitration(vc_arbitration),
+ .disable_snoop_packet(disable_snoop_packet),
+ .max_payload_size(max_payload_size),
+ .surprise_down_error_support(surprise_down_error_support),
+ .dll_active_report_support(dll_active_report_support),
+ .extend_tag_field(extend_tag_field),
+ .endpoint_l0_latency_data(endpoint_l0_latency),
+ .endpoint_l1_latency_data(endpoint_l1_latency),
+ .indicator_data(indicator),
+ .slot_power_scale_data(slot_power_scale),
+ .max_link_width(lane_mask),
+ .enable_l1_aspm(enable_l1_aspm),
+ .l1_exit_latency_sameclock_data(l1_exit_latency_sameclock),
+ .l1_exit_latency_diffclock_data(l1_exit_latency_diffclock),
+ .hot_plug_support_data(hot_plug_support),
+ .slot_power_limit_data(slot_power_limit),
+ .slot_number_data(slot_number),
+ .diffclock_nfts_count_data(diffclock_nfts_count),
+ .sameclock_nfts_count_data(sameclock_nfts_count),
+ .completion_timeout(completion_timeout),
+ .enable_completion_timeout_disable(enable_completion_timeout_disable),
+ .extended_tag_reset(extended_tag_reset),
+ .ecrc_check_capable(ecrc_check_capable),
+ .ecrc_gen_capable(ecrc_gen_capable),
+ .no_command_completed(no_command_completed),
+ .msi_multi_message_capable(msi_multi_message_capable),
+ .msi_64bit_addressing_capable(msi_64bit_addressing_capable),
+ .msi_masking_capable(msi_masking_capable),
+ .msi_support(msi_support),
+ .interrupt_pin(interrupt_pin),
+ .enable_function_msix_support(enable_function_msix_support),
+ .msix_table_size_data(msix_table_size),
+ .msix_table_bir_data(msix_table_bir),
+ .msix_table_offset_data(msix_table_offset),
+ .msix_pba_bir_data(msix_pba_bir),
+ .msix_pba_offset_data(msix_pba_offset),
+ .bridge_port_vga_enable(bridge_port_vga_enable),
+ .bridge_port_ssid_support(bridge_port_ssid_support),
+ .ssvid_data(ssvid),
+ .ssid_data(ssid),
+ .eie_before_nfts_count_data(eie_before_nfts_count),
+ .gen2_diffclock_nfts_count_data(gen2_diffclock_nfts_count),
+ .gen2_sameclock_nfts_count_data(gen2_sameclock_nfts_count),
+ .deemphasis_enable(deemphasis_enable),
+ .pcie_spec_version(pcie_spec_version),
+ .l0_exit_latency_sameclock_data(l0_exit_latency_sameclock),
+ .l0_exit_latency_diffclock_data(l0_exit_latency_diffclock),
+ .rx_ei_l0s(rx_ei_l0s),
+ .l2_async_logic(l2_async_logic),
+ .aspm_config_management(aspm_config_management),
+ .atomic_op_routing(atomic_op_routing),
+ .atomic_op_completer_32bit(atomic_op_completer_32bit),
+ .atomic_op_completer_64bit(atomic_op_completer_64bit),
+ .cas_completer_128bit(cas_completer_128bit),
+ .ltr_mechanism(ltr_mechanism),
+ .tph_completer(tph_completer),
+ .extended_format_field(extended_format_field),
+ .atomic_malformed(atomic_malformed),
+ .flr_capability(flr_capability),
+ .enable_adapter_half_rate_mode(enable_adapter_half_rate_mode),
+ .vc0_clk_enable(vc0_clk_enable),
+ .vc1_clk_enable(vc1_clk_enable),
+ .register_pipe_signals(register_pipe_signals),
+ .bar0_io_space(bar0_io_space),
+ .bar0_64bit_mem_space(bar0_64bit_mem_space),
+ .bar0_prefetchable(bar0_prefetchable),
+ .bar0_size_mask_data(bar0_size_mask),
+ .bar1_io_space(bar1_io_space),
+ .bar1_64bit_mem_space(bar1_64bit_mem_space),
+ .bar1_prefetchable(bar1_prefetchable),
+ .bar1_size_mask_data(bar1_size_mask),
+ .bar2_io_space(bar2_io_space),
+ .bar2_64bit_mem_space(bar2_64bit_mem_space),
+ .bar2_prefetchable(bar2_prefetchable),
+ .bar2_size_mask_data(bar2_size_mask),
+ .bar3_io_space(bar3_io_space),
+ .bar3_64bit_mem_space(bar3_64bit_mem_space),
+ .bar3_prefetchable(bar3_prefetchable),
+ .bar3_size_mask_data(bar3_size_mask),
+ .bar4_io_space(bar4_io_space),
+ .bar4_64bit_mem_space(bar4_64bit_mem_space),
+ .bar4_prefetchable(bar4_prefetchable),
+ .bar4_size_mask_data(bar4_size_mask),
+ .bar5_io_space(bar5_io_space),
+ .bar5_64bit_mem_space(bar5_64bit_mem_space),
+ .bar5_prefetchable(bar5_prefetchable),
+ .bar5_size_mask_data(bar5_size_mask),
+ .expansion_base_address_register_data(expansion_base_address_register),
+ .io_window_addr_width(io_window_addr_width),
+ .prefetchable_mem_window_addr_width(prefetchable_mem_window_addr_width),
+ .skp_os_gen3_count_data(skp_os_gen3_count),
+ .tx_cdc_almost_empty_data(tx_cdc_almost_empty),
+ .rx_cdc_almost_full_data(rx_cdc_almost_full),
+ .tx_cdc_almost_full_data(tx_cdc_almost_full),
+ .rx_l0s_count_idl_data(rx_l0s_count_idl),
+ .cdc_dummy_insert_limit_data(cdc_dummy_insert_limit),
+ .ei_delay_powerdown_count_data(ei_delay_powerdown_count),
+ .millisecond_cycle_count_data(millisecond_cycle_count),
+ .skp_os_schedule_count_data(skp_os_schedule_count),
+ .fc_init_timer_data(fc_init_timer),
+ .l01_entry_latency_data(l01_entry_latency),
+ .flow_control_update_count_data(flow_control_update_count),
+ .flow_control_timeout_count_data(flow_control_timeout_count),
+ .vc0_rx_flow_ctrl_posted_header_data(vc0_rx_flow_ctrl_posted_header),
+ .vc0_rx_flow_ctrl_posted_data_data(vc0_rx_flow_ctrl_posted_data),
+ .vc0_rx_flow_ctrl_nonposted_header_data(vc0_rx_flow_ctrl_nonposted_header),
+ .vc0_rx_flow_ctrl_nonposted_data_data(vc0_rx_flow_ctrl_nonposted_data),
+ .vc0_rx_flow_ctrl_compl_header_data(vc0_rx_flow_ctrl_compl_header),
+ .vc0_rx_flow_ctrl_compl_data_data(vc0_rx_flow_ctrl_compl_data),
+ .rx_ptr0_posted_dpram_min_data(rx_ptr0_posted_dpram_min),
+ .rx_ptr0_posted_dpram_max_data(rx_ptr0_posted_dpram_max),
+ .rx_ptr0_nonposted_dpram_min_data(rx_ptr0_nonposted_dpram_min),
+ .rx_ptr0_nonposted_dpram_max_data(rx_ptr0_nonposted_dpram_max),
+ .retry_buffer_last_active_address_data(retry_buffer_last_active_address),
+ .retry_buffer_memory_settings_data(retry_buffer_memory_settings),
+ .vc0_rx_buffer_memory_settings_data(vc0_rx_buffer_memory_settings),
+ .bist_memory_settings_data(bist_memory_settings),
+ .credit_buffer_allocation_aux(credit_buffer_allocation_aux),
+ .iei_enable_settings(iei_enable_settings),
+ .vsec_id_data(vsec_id),
+ .cvp_rate_sel(cvp_rate_sel),
+ .hard_reset_bypass(hard_reset_bypass),
+ .cvp_data_compressed(cvp_data_compressed),
+ .cvp_data_encrypted(cvp_data_encrypted),
+ .cvp_mode_reset(cvp_mode_reset),
+ .cvp_clk_reset(cvp_clk_reset),
+ .in_cvp_mode(in_cvp_mode),
+ .vsec_cap_data(vsec_cap),
+ .jtag_id_data(jtag_id),
+ .user_id_data(user_id),
+ .cseb_extend_pci(cseb_extend_pci),
+ .cseb_extend_pcie(cseb_extend_pcie),
+ .cseb_cpl_status_during_cvp(cseb_cpl_status_during_cvp),
+ .cseb_route_to_avl_rx_st(cseb_route_to_avl_rx_st),
+ .cseb_config_bypass(cseb_config_bypass),
+ .cseb_cpl_tag_checking(cseb_cpl_tag_checking),
+ .cseb_bar_match_checking(cseb_bar_match_checking),
+ .cseb_min_error_checking(cseb_min_error_checking),
+ .cseb_temp_busy_crs(cseb_temp_busy_crs),
+ .gen3_diffclock_nfts_count_data(gen3_diffclock_nfts_count),
+ .gen3_sameclock_nfts_count_data(gen3_sameclock_nfts_count),
+ .gen3_coeff_errchk(gen3_coeff_errchk),
+ .gen3_paritychk(gen3_paritychk),
+ .gen3_coeff_delay_count_data(gen3_coeff_delay_count),
+ .gen3_coeff_1_data(gen3_coeff_1),
+ .gen3_coeff_1_sel(gen3_coeff_1_sel),
+ .gen3_coeff_1_preset_hint_data(gen3_coeff_1_preset_hint),
+ .gen3_coeff_1_nxtber_more_ptr(gen3_coeff_1_nxtber_more_ptr),
+ .gen3_coeff_1_nxtber_more(gen3_coeff_1_nxtber_more),
+ .gen3_coeff_1_nxtber_less_ptr(gen3_coeff_1_nxtber_less_ptr),
+ .gen3_coeff_1_nxtber_less(gen3_coeff_1_nxtber_less),
+ .gen3_coeff_1_reqber_data(gen3_coeff_1_reqber),
+ .gen3_coeff_1_ber_meas_data(gen3_coeff_1_ber_meas),
+ .gen3_coeff_2_data(gen3_coeff_2),
+ .gen3_coeff_2_sel(gen3_coeff_2_sel),
+ .gen3_coeff_2_preset_hint_data(gen3_coeff_2_preset_hint),
+ .gen3_coeff_2_nxtber_more_ptr(gen3_coeff_2_nxtber_more_ptr),
+ .gen3_coeff_2_nxtber_more(gen3_coeff_2_nxtber_more),
+ .gen3_coeff_2_nxtber_less_ptr(gen3_coeff_2_nxtber_less_ptr),
+ .gen3_coeff_2_nxtber_less(gen3_coeff_2_nxtber_less),
+ .gen3_coeff_2_reqber_data(gen3_coeff_2_reqber),
+ .gen3_coeff_2_ber_meas_data(gen3_coeff_2_ber_meas),
+ .gen3_coeff_3_data(gen3_coeff_3),
+ .gen3_coeff_3_sel(gen3_coeff_3_sel),
+ .gen3_coeff_3_preset_hint_data(gen3_coeff_3_preset_hint),
+ .gen3_coeff_3_nxtber_more_ptr(gen3_coeff_3_nxtber_more_ptr),
+ .gen3_coeff_3_nxtber_more(gen3_coeff_3_nxtber_more),
+ .gen3_coeff_3_nxtber_less_ptr(gen3_coeff_3_nxtber_less_ptr),
+ .gen3_coeff_3_nxtber_less(gen3_coeff_3_nxtber_less),
+ .gen3_coeff_3_reqber_data(gen3_coeff_3_reqber),
+ .gen3_coeff_3_ber_meas_data(gen3_coeff_3_ber_meas),
+ .gen3_coeff_4_data(gen3_coeff_4),
+ .gen3_coeff_4_sel(gen3_coeff_4_sel),
+ .gen3_coeff_4_preset_hint_data(gen3_coeff_4_preset_hint),
+ .gen3_coeff_4_nxtber_more_ptr(gen3_coeff_4_nxtber_more_ptr),
+ .gen3_coeff_4_nxtber_more(gen3_coeff_4_nxtber_more),
+ .gen3_coeff_4_nxtber_less_ptr(gen3_coeff_4_nxtber_less_ptr),
+ .gen3_coeff_4_nxtber_less(gen3_coeff_4_nxtber_less),
+ .gen3_coeff_4_reqber_data(gen3_coeff_4_reqber),
+ .gen3_coeff_4_ber_meas_data(gen3_coeff_4_ber_meas),
+ .gen3_coeff_5_data(gen3_coeff_5),
+ .gen3_coeff_5_sel(gen3_coeff_5_sel),
+ .gen3_coeff_5_preset_hint_data(gen3_coeff_5_preset_hint),
+ .gen3_coeff_5_nxtber_more_ptr(gen3_coeff_5_nxtber_more_ptr),
+ .gen3_coeff_5_nxtber_more(gen3_coeff_5_nxtber_more),
+ .gen3_coeff_5_nxtber_less_ptr(gen3_coeff_5_nxtber_less_ptr),
+ .gen3_coeff_5_nxtber_less(gen3_coeff_5_nxtber_less),
+ .gen3_coeff_5_reqber_data(gen3_coeff_5_reqber),
+ .gen3_coeff_5_ber_meas_data(gen3_coeff_5_ber_meas),
+ .gen3_coeff_6_data(gen3_coeff_6),
+ .gen3_coeff_6_sel(gen3_coeff_6_sel),
+ .gen3_coeff_6_preset_hint_data(gen3_coeff_6_preset_hint),
+ .gen3_coeff_6_nxtber_more_ptr(gen3_coeff_6_nxtber_more_ptr),
+ .gen3_coeff_6_nxtber_more(gen3_coeff_6_nxtber_more),
+ .gen3_coeff_6_nxtber_less_ptr(gen3_coeff_6_nxtber_less_ptr),
+ .gen3_coeff_6_nxtber_less(gen3_coeff_6_nxtber_less),
+ .gen3_coeff_6_reqber_data(gen3_coeff_6_reqber),
+ .gen3_coeff_6_ber_meas_data(gen3_coeff_6_ber_meas),
+ .gen3_coeff_7_data(gen3_coeff_7),
+ .gen3_coeff_7_sel(gen3_coeff_7_sel),
+ .gen3_coeff_7_preset_hint_data(gen3_coeff_7_preset_hint),
+ .gen3_coeff_7_nxtber_more_ptr(gen3_coeff_7_nxtber_more_ptr),
+ .gen3_coeff_7_nxtber_more(gen3_coeff_7_nxtber_more),
+ .gen3_coeff_7_nxtber_less_ptr(gen3_coeff_7_nxtber_less_ptr),
+ .gen3_coeff_7_nxtber_less(gen3_coeff_7_nxtber_less),
+ .gen3_coeff_7_reqber_data(gen3_coeff_7_reqber),
+ .gen3_coeff_7_ber_meas_data(gen3_coeff_7_ber_meas),
+ .gen3_coeff_8_data(gen3_coeff_8),
+ .gen3_coeff_8_sel(gen3_coeff_8_sel),
+ .gen3_coeff_8_preset_hint_data(gen3_coeff_8_preset_hint),
+ .gen3_coeff_8_nxtber_more_ptr(gen3_coeff_8_nxtber_more_ptr),
+ .gen3_coeff_8_nxtber_more(gen3_coeff_8_nxtber_more),
+ .gen3_coeff_8_nxtber_less_ptr(gen3_coeff_8_nxtber_less_ptr),
+ .gen3_coeff_8_nxtber_less(gen3_coeff_8_nxtber_less),
+ .gen3_coeff_8_reqber_data(gen3_coeff_8_reqber),
+ .gen3_coeff_8_ber_meas_data(gen3_coeff_8_ber_meas),
+ .gen3_coeff_9_data(gen3_coeff_9),
+ .gen3_coeff_9_sel(gen3_coeff_9_sel),
+ .gen3_coeff_9_preset_hint_data(gen3_coeff_9_preset_hint),
+ .gen3_coeff_9_nxtber_more_ptr(gen3_coeff_9_nxtber_more_ptr),
+ .gen3_coeff_9_nxtber_more(gen3_coeff_9_nxtber_more),
+ .gen3_coeff_9_nxtber_less_ptr(gen3_coeff_9_nxtber_less_ptr),
+ .gen3_coeff_9_nxtber_less(gen3_coeff_9_nxtber_less),
+ .gen3_coeff_9_reqber_data(gen3_coeff_9_reqber),
+ .gen3_coeff_9_ber_meas_data(gen3_coeff_9_ber_meas),
+ .gen3_coeff_10_data(gen3_coeff_10),
+ .gen3_coeff_10_sel(gen3_coeff_10_sel),
+ .gen3_coeff_10_preset_hint_data(gen3_coeff_10_preset_hint),
+ .gen3_coeff_10_nxtber_more_ptr(gen3_coeff_10_nxtber_more_ptr),
+ .gen3_coeff_10_nxtber_more(gen3_coeff_10_nxtber_more),
+ .gen3_coeff_10_nxtber_less_ptr(gen3_coeff_10_nxtber_less_ptr),
+ .gen3_coeff_10_nxtber_less(gen3_coeff_10_nxtber_less),
+ .gen3_coeff_10_reqber_data(gen3_coeff_10_reqber),
+ .gen3_coeff_10_ber_meas_data(gen3_coeff_10_ber_meas),
+ .gen3_coeff_11_data(gen3_coeff_11),
+ .gen3_coeff_11_sel(gen3_coeff_11_sel),
+ .gen3_coeff_11_preset_hint_data(gen3_coeff_11_preset_hint),
+ .gen3_coeff_11_nxtber_more_ptr(gen3_coeff_11_nxtber_more_ptr),
+ .gen3_coeff_11_nxtber_more(gen3_coeff_11_nxtber_more),
+ .gen3_coeff_11_nxtber_less_ptr(gen3_coeff_11_nxtber_less_ptr),
+ .gen3_coeff_11_nxtber_less(gen3_coeff_11_nxtber_less),
+ .gen3_coeff_11_reqber_data(gen3_coeff_11_reqber),
+ .gen3_coeff_11_ber_meas_data(gen3_coeff_11_ber_meas),
+ .gen3_coeff_12_data(gen3_coeff_12),
+ .gen3_coeff_12_sel(gen3_coeff_12_sel),
+ .gen3_coeff_12_preset_hint_data(gen3_coeff_12_preset_hint),
+ .gen3_coeff_12_nxtber_more_ptr(gen3_coeff_12_nxtber_more_ptr),
+ .gen3_coeff_12_nxtber_more(gen3_coeff_12_nxtber_more),
+ .gen3_coeff_12_nxtber_less_ptr(gen3_coeff_12_nxtber_less_ptr),
+ .gen3_coeff_12_nxtber_less(gen3_coeff_12_nxtber_less),
+ .gen3_coeff_12_reqber_data(gen3_coeff_12_reqber),
+ .gen3_coeff_12_ber_meas_data(gen3_coeff_12_ber_meas),
+ .gen3_coeff_13_data(gen3_coeff_13),
+ .gen3_coeff_13_sel(gen3_coeff_13_sel),
+ .gen3_coeff_13_preset_hint_data(gen3_coeff_13_preset_hint),
+ .gen3_coeff_13_nxtber_more_ptr(gen3_coeff_13_nxtber_more_ptr),
+ .gen3_coeff_13_nxtber_more(gen3_coeff_13_nxtber_more),
+ .gen3_coeff_13_nxtber_less_ptr(gen3_coeff_13_nxtber_less_ptr),
+ .gen3_coeff_13_nxtber_less(gen3_coeff_13_nxtber_less),
+ .gen3_coeff_13_reqber_data(gen3_coeff_13_reqber),
+ .gen3_coeff_13_ber_meas_data(gen3_coeff_13_ber_meas),
+ .gen3_coeff_14_data(gen3_coeff_14),
+ .gen3_coeff_14_sel(gen3_coeff_14_sel),
+ .gen3_coeff_14_preset_hint_data(gen3_coeff_14_preset_hint),
+ .gen3_coeff_14_nxtber_more_ptr(gen3_coeff_14_nxtber_more_ptr),
+ .gen3_coeff_14_nxtber_more(gen3_coeff_14_nxtber_more),
+ .gen3_coeff_14_nxtber_less_ptr(gen3_coeff_14_nxtber_less_ptr),
+ .gen3_coeff_14_nxtber_less(gen3_coeff_14_nxtber_less),
+ .gen3_coeff_14_reqber_data(gen3_coeff_14_reqber),
+ .gen3_coeff_14_ber_meas_data(gen3_coeff_14_ber_meas),
+ .gen3_coeff_15_data(gen3_coeff_15),
+ .gen3_coeff_15_sel(gen3_coeff_15_sel),
+ .gen3_coeff_15_preset_hint_data(gen3_coeff_15_preset_hint),
+ .gen3_coeff_15_nxtber_more_ptr(gen3_coeff_15_nxtber_more_ptr),
+ .gen3_coeff_15_nxtber_more(gen3_coeff_15_nxtber_more),
+ .gen3_coeff_15_nxtber_less_ptr(gen3_coeff_15_nxtber_less_ptr),
+ .gen3_coeff_15_nxtber_less(gen3_coeff_15_nxtber_less),
+ .gen3_coeff_15_reqber_data(gen3_coeff_15_reqber),
+ .gen3_coeff_15_ber_meas_data(gen3_coeff_15_ber_meas),
+ .gen3_coeff_16_data(gen3_coeff_16),
+ .gen3_coeff_16_sel(gen3_coeff_16_sel),
+ .gen3_coeff_16_preset_hint_data(gen3_coeff_16_preset_hint),
+ .gen3_coeff_16_nxtber_more_ptr(gen3_coeff_16_nxtber_more_ptr),
+ .gen3_coeff_16_nxtber_more(gen3_coeff_16_nxtber_more),
+ .gen3_coeff_16_nxtber_less_ptr(gen3_coeff_16_nxtber_less_ptr),
+ .gen3_coeff_16_nxtber_less(gen3_coeff_16_nxtber_less),
+ .gen3_coeff_16_reqber_data(gen3_coeff_16_reqber),
+ .gen3_coeff_16_ber_meas_data(gen3_coeff_16_ber_meas),
+ .gen3_preset_coeff_1_data(gen3_preset_coeff_1),
+ .gen3_preset_coeff_2_data(gen3_preset_coeff_2),
+ .gen3_preset_coeff_3_data(gen3_preset_coeff_3),
+ .gen3_preset_coeff_4_data(gen3_preset_coeff_4),
+ .gen3_preset_coeff_5_data(gen3_preset_coeff_5),
+ .gen3_preset_coeff_6_data(gen3_preset_coeff_6),
+ .gen3_preset_coeff_7_data(gen3_preset_coeff_7),
+ .gen3_preset_coeff_8_data(gen3_preset_coeff_8),
+ .gen3_preset_coeff_9_data(gen3_preset_coeff_9),
+ .gen3_preset_coeff_10_data(gen3_preset_coeff_10),
+ .gen3_rxfreqlock_counter_data(gen3_rxfreqlock_counter)
+ ) stratixv_hssi_gen3_pcie_hip (
+ .aermsinum (aer_msi_num ),
+ .appintasts (app_int_sts ),
+ .appmsinum (app_msi_num ),
+ .appmsireq (app_msi_req ),
+ .appmsitc (app_msi_tc ),
+ .bistenrcv (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:bistenrcv ),
+ .bistenrpl (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:bistenrpl ),
+ .bistscanen (((ACDS_V10==1)||(MEM_CHECK==0))?1'b0:bistscanen),
+ .bistscanin (((ACDS_V10==1)||(MEM_CHECK==0))?1'b0:bistscanin),
+ .bisttesten (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:bisttesten),
+ .cfglink2csrpld (cfglink2csrpld ), //??
+ .coreclkin (pld_clk_hip ),//
+ .corecrst (crst ),//
+ .corepor (~npor ),//
+ .corerst (~npor ),//
+ .coresrst (srst ),//
+
+ .cplerr (cpl_err ),//
+ .cplpending (cpl_pending ),//
+
+ .csebrddata ((ACDS_V10==1)?32'h0 :csebrddata ),//
+ .csebrddataparity ((ACDS_V10==1)?4'h0 :csebrddataparity),//
+ .csebrdresponse ((ACDS_V10==1)?3'h0 :csebrdresponse ),//
+ .csebwaitrequest ((ACDS_V10==1)?1'b0 :csebwaitrequest ),//
+ .csebwrresponse ((ACDS_V10==1)?3'h0 :csebwrresponse ),//
+ .csebwrrespvalid ((ACDS_V10==1)?1'b0 :csebwrrespvalid ),//
+ .dbgpipex1rx ((ACDS_V10==1)?44'h0 :dbgpipex1rx ),//
+ .entest ((ACDS_V10==1)?1'b0 :entest ),
+ .frzlogic (frzlogic ),
+ .frzreg (frzreg ),
+ .hpgctrler (hpg_ctrler ),
+ .idrcv (idrcv ),
+ .idrpl (idrpl ),
+ .lmiaddr (lmi_addr ),//
+ .lmidin (lmi_din ),//
+ .lmirden (lmi_rden ),//
+ .lmiwren (lmi_wren ),//
+ .memhiptestenable (((ACDS_V10==1)||(MEM_CHECK==0))?1'b0:memhiptestenable ),
+ .memredenscan (((ACDS_V10==1)||(MEM_CHECK==0))?1'b0:memredenscan ),
+ .memredscen (((ACDS_V10==1)||(MEM_CHECK==0))?1'b0:memredscen ),
+ .memredscin (((ACDS_V10==1)||(MEM_CHECK==0))?1'b0:memredscin ),
+ .memredsclk (((ACDS_V10==1)||(MEM_CHECK==0))?1'b0:memredsclk ),
+ .memredscrst (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:memredscrst ),
+ .memredscsel (((ACDS_V10==1)||(MEM_CHECK==0))?1'b0:memredscsel ),
+ .memregscanen (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:memregscanen ),
+ .memregscanin (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:memregscanin ),
+ .mode (mode ),
+ .nfrzdrv (((ACDS_V10==1)||(MEM_CHECK==0))?1'b0:nfrzdrv ),
+ .npor (npor ),
+ .pclkcentral ((pipe_mode_simu_only==1'b1)? sim_pipe32_pclk: mserdes_pipe_pclkcentral), //TODO check rules for pclk for central vs cho
+ .pclkch0 ((pipe_mode_simu_only==1'b1)? sim_pipe32_pclk: mserdes_pipe_pclk),
+ .pclkch1 ((pipe_mode_simu_only==1'b1)? sim_pipe32_pclk: mserdes_pipe_pclkch1),//TODO FIX SIMULATION MODEL which misses this port add this ports
+ .pexmsinum (pex_msi_num ),
+ .phyrst (~npor ), //
+ .physrst (srst ), //
+ .phystatus0 (phystatus0 ),
+ .phystatus1 (phystatus1 ),
+ .phystatus2 (phystatus2 ),
+ .phystatus3 (phystatus3 ),
+ .phystatus4 (phystatus4 ),
+ .phystatus5 (phystatus5 ),
+ .phystatus6 (phystatus6 ),
+ .phystatus7 (phystatus7 ),
+ .pldclk (pld_clk_hip ), //
+ .pldrst (~npor ), // Removed IO connected to ~npor
+ .pldsrst (srst ), // Removed IO connected to ~npor,
+ .pllfixedclkcentral ((pipe_mode_simu_only==1'b0)? mserdes_pllfixedclkcentral:(low_str(gen123_lane_rate_mode)=="gen1_gen2")?clk500_out:clk250_out), //TODO add this ports
+ .pllfixedclkch0 ((pipe_mode_simu_only==1'b0)? mserdes_pllfixedclkch0 :(low_str(gen123_lane_rate_mode)=="gen1_gen2")?clk500_out:clk250_out), //TODO add this ports
+ .pllfixedclkch1 ((pipe_mode_simu_only==1'b0)? mserdes_pllfixedclkch1 :(low_str(gen123_lane_rate_mode)=="gen1_gen2")?clk500_out:clk250_out), //TODO FIX SIM MODEL which misses this port add this ports
+ .plniotri (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:plniotri),
+ .pmauxpwr (pm_auxpwr ),
+ .pmdata (pm_data ),
+ .pmetocr (pme_to_cr ),
+ .pmevent (pm_event ),
+ //.rxblkst0 (rxblkst0 ),//TODO Gen3
+ //.rxblkst1 (rxblkst1 ),//TODO Gen3
+ //.rxblkst2 (rxblkst2 ),//TODO Gen3
+ //.rxblkst3 (rxblkst3 ),//TODO Gen3
+ //.rxblkst4 (rxblkst4 ),//TODO Gen3
+ //.rxblkst5 (rxblkst5 ),//TODO Gen3
+ //.rxblkst6 (rxblkst6 ),//TODO Gen3
+ //.rxblkst7 (rxblkst7 ),//TODO Gen3
+ .rxdata0 (rxdata0 ),
+ .rxdata1 (rxdata1 ),
+ .rxdata2 (rxdata2 ),
+ .rxdata3 (rxdata3 ),
+ .rxdata4 (rxdata4 ),
+ .rxdata5 (rxdata5 ),
+ .rxdata6 (rxdata6 ),
+ .rxdata7 (rxdata7 ),
+ .rxdatak0 (rxdatak0 ),
+ .rxdatak1 (rxdatak1 ),
+ .rxdatak2 (rxdatak2 ),
+ .rxdatak3 (rxdatak3 ),
+ .rxdatak4 (rxdatak4 ),
+ .rxdatak5 (rxdatak5 ),
+ .rxdatak6 (rxdatak6 ),
+ .rxdatak7 (rxdatak7 ),
+ .rxdataskip0 (rxdataskip0 ),//TODO Gen3
+ .rxdataskip1 (rxdataskip1 ),//TODO Gen3
+ .rxdataskip2 (rxdataskip2 ),//TODO Gen3
+ .rxdataskip3 (rxdataskip3 ),//TODO Gen3
+ .rxdataskip4 (rxdataskip4 ),//TODO Gen3
+ .rxdataskip5 (rxdataskip5 ),//TODO Gen3
+ .rxdataskip6 (rxdataskip6 ),//TODO Gen3
+ .rxdataskip7 (rxdataskip7 ),//TODO Gen3
+ .rxelecidle0 (rxelecidle0 ),
+ .rxelecidle1 (rxelecidle1 ),
+ .rxelecidle2 (rxelecidle2 ),
+ .rxelecidle3 (rxelecidle3 ),
+ .rxelecidle4 (rxelecidle4 ),
+ .rxelecidle5 (rxelecidle5 ),
+ .rxelecidle6 (rxelecidle6 ),
+ .rxelecidle7 (rxelecidle7 ),
+ .rxfreqlocked0 (rxfreqlocked0 ),//TODO Gen3
+ .rxfreqlocked1 (rxfreqlocked1 ),//TODO Gen3
+ .rxfreqlocked2 (rxfreqlocked2 ),//TODO Gen3
+ .rxfreqlocked3 (rxfreqlocked3 ),//TODO Gen3
+ .rxfreqlocked4 (rxfreqlocked4 ),//TODO Gen3
+ .rxfreqlocked5 (rxfreqlocked5 ),//TODO Gen3
+ .rxfreqlocked6 (rxfreqlocked6 ),//TODO Gen3
+ .rxfreqlocked7 (rxfreqlocked7 ),//TODO Gen3
+ .rxstatus0 (rxstatus0 ),
+ .rxstatus1 (rxstatus1 ),
+ .rxstatus2 (rxstatus2 ),
+ .rxstatus3 (rxstatus3 ),
+ .rxstatus4 (rxstatus4 ),
+ .rxstatus5 (rxstatus5 ),
+ .rxstatus6 (rxstatus6 ),
+ .rxstatus7 (rxstatus7 ),
+ .rxstmask (rxstmask ),//
+ .rxstready (rxstready ),//
+ .rxsynchd0 (rxsynchd0 ),//TODO Gen3
+ .rxsynchd1 (rxsynchd1 ),//TODO Gen3
+ .rxsynchd2 (rxsynchd2 ),//TODO Gen3
+ .rxsynchd3 (rxsynchd3 ),//TODO Gen3
+ .rxsynchd4 (rxsynchd4 ),//TODO Gen3
+ .rxsynchd5 (rxsynchd5 ),//TODO Gen3
+ .rxsynchd6 (rxsynchd6 ),//TODO Gen3
+ .rxsynchd7 (rxsynchd7 ),//TODO Gen3
+ .rxvalid0 (rxvalid0 ),
+ .rxvalid1 (rxvalid1 ),
+ .rxvalid2 (rxvalid2 ),
+ .rxvalid3 (rxvalid3 ),
+ .rxvalid4 (rxvalid4 ),
+ .rxvalid5 (rxvalid5 ),
+ .rxvalid6 (rxvalid6 ),
+ .rxvalid7 (rxvalid7 ),
+ .scanmoden (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:scanmoden),
+ .scanshiftn (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:scanshiftn),
+ .slotclkcfg (tl_slotclk_cfg ),
+ .swctmod (swctmod ),
+// should be tied down at var_core.v
+// .swdnin (swdn_in ),
+// .swupin (swup_in ),
+ .swdnin (3'b000 ),
+ .swupin (7'b0000000 ),
+ .testinhip (test_in ),
+ .txstdata (txstdata ),//
+ .txstempty (txstempty ),//
+ .txsteop (txsteop ),//
+ .txsterr (txsterr ),//
+ .txstparity (txstparity ),//
+ .txstsop (txstsop ),//
+ .txstvalid (txstvalid ),//
+ .usermode (((ACDS_V10==1)||(MEM_CHECK==0))?1'b1:usermode),
+ .hiphardreset (hiphardreset),
+
+ .appintaack (app_int_ack ),
+ .appmsiack (app_msi_ack ),
+ .bistdonearcv (bistdonearcv ),
+ .bistdonearcv1 (bistdonearcv1 ),
+ .bistdonearpl (bistdonearpl ),
+ .bistdonebrcv (bistdonebrcv ),
+ .bistdonebrcv1 (bistdonebrcv1 ),
+ .bistdonebrpl (bistdonebrpl ),
+ .bistpassrcv (bistpassrcv ),
+ .bistpassrcv1 (bistpassrcv1 ),
+ .bistpassrpl (bistpassrpl ),
+ .bistscanoutrcv (bistscanoutrcv ),
+ .bistscanoutrcv1 (bistscanoutrcv1 ),
+ .bistscanoutrpl (bistscanoutrpl ),
+ .coreclkout (coreclkout_hip ),
+ .csebaddr (csebaddr ),
+ .csebaddrparity (csebaddrparity ),
+ .csebbe (csebbe ),
+ .csebisshadow (csebisshadow ),
+ .csebrden (csebrden ),
+ .csebwrdata (csebwrdata ),
+ .csebwrdataparity (csebwrdataparity ),
+ .csebwren (csebwren ),
+ .csebwrrespreq (csebwrrespreq ),
+ .currentcoeff0 (currentcoeff0 ),
+ .currentcoeff1 (currentcoeff1 ),
+ .currentcoeff2 (currentcoeff2 ),
+ .currentcoeff3 (currentcoeff3 ),
+ .currentcoeff4 (currentcoeff4 ),
+ .currentcoeff5 (currentcoeff5 ),
+ .currentcoeff6 (currentcoeff6 ),
+ .currentcoeff7 (currentcoeff7 ),
+ .currentrxpreset0 (currentrxpreset0 ),
+ .currentrxpreset1 (currentrxpreset1 ),
+ .currentrxpreset2 (currentrxpreset2 ),
+ .currentrxpreset3 (currentrxpreset3 ),
+ .currentrxpreset4 (currentrxpreset4 ),
+ .currentrxpreset5 (currentrxpreset5 ),
+ .currentrxpreset6 (currentrxpreset6 ),
+ .currentrxpreset7 (currentrxpreset7 ),
+ .currentspeed (currentspeed ),
+ .derrcorextrcv (derr_cor_ext_rcv ),
+ .derrcorextrcv1 (derr_cor_ext_rcv1 ),
+ .derrcorextrpl (derr_cor_ext_rpl ),
+ .derrrpl (derr_rpl ),
+ .dlup (dlup ),
+ .dlupexit (dlup_exit ),
+ .eidleinfersel0 (eidleinfersel0 ),
+ .eidleinfersel1 (eidleinfersel1 ),
+ .eidleinfersel2 (eidleinfersel2 ),
+ .eidleinfersel3 (eidleinfersel3 ),
+ .eidleinfersel4 (eidleinfersel4 ),
+ .eidleinfersel5 (eidleinfersel5 ),
+ .eidleinfersel6 (eidleinfersel6 ),
+ .eidleinfersel7 (eidleinfersel7 ),
+ .ev128ns (ev128ns ),
+ .ev1us (ev1us ),
+ .hotrstexit (hotrst_exit ),
+ .intstatus (int_status ),
+ .l2exit (l2_exit ),
+ .laneact (lane_act ),
+ .lmiack (lmi_ack ),
+ .lmidout (lmi_dout ),
+ .ltssmstate (ltssmstate ),
+ .memredscout (memredscout ),
+ .memregscanout (memregscanout ),
+ .pmetosr (pme_to_sr ),
+ .powerdown0 (powerdown0 ),
+ .powerdown1 (powerdown1 ),
+ .powerdown2 (powerdown2 ),
+ .powerdown3 (powerdown3 ),
+ .powerdown4 (powerdown4 ),
+ .powerdown5 (powerdown5 ),
+ .powerdown6 (powerdown6 ),
+ .powerdown7 (powerdown7 ),
+ .rate0 (rate0 ),
+ .rate1 (rate1 ),
+ .rate2 (rate2 ),
+ .rate3 (rate3 ),
+ .rate4 (rate4 ),
+ .rate5 (rate5 ),
+ .rate6 (rate6 ),
+ .rate7 (rate7 ),
+ .resetstatus (resetstatus ),
+ .rxpolarity0 (rxpolarity0 ),
+ .rxpolarity1 (rxpolarity1 ),
+ .rxpolarity2 (rxpolarity2 ),
+ .rxpolarity3 (rxpolarity3 ),
+ .rxpolarity4 (rxpolarity4 ),
+ .rxpolarity5 (rxpolarity5 ),
+ .rxpolarity6 (rxpolarity6 ),
+ .rxpolarity7 (rxpolarity7 ),
+ .rxstbardec1 (rxstbardec1 ),//
+ .rxstbardec2 (rxstbardec2 ),//
+ .rxstbe (rxstbe ),//
+ .rxstdata (rxstdata ),//
+ .rxstempty (rxstempty ),//
+ .rxsteop (rxsteop ),//
+ .rxsterr (rxsterr ),//
+ .rxstparity (rxstparity ),//
+ .rxstsop (rxstsop ),//
+ .rxstvalid (rxstvalid ),//
+ .serrout (serr_out ),
+ .swdnout (swdnout ),
+ .swupout (swupout ),
+ .testouthip (test_out ),
+ .tlcfgadd (tl_cfg_add ),
+ .tlcfgctl (tl_cfg_ctl ),
+ .tlcfgsts (tl_cfg_sts ),
+ .txblkst0 (txblkst0 ),
+ .txblkst1 (txblkst1 ),
+ .txblkst2 (txblkst2 ),
+ .txblkst3 (txblkst3 ),
+ .txblkst4 (txblkst4 ),
+ .txblkst5 (txblkst5 ),
+ .txblkst6 (txblkst6 ),
+ .txblkst7 (txblkst7 ),
+ .txcompl0 (txcompl0 ),
+ .txcompl1 (txcompl1 ),
+ .txcompl2 (txcompl2 ),
+ .txcompl3 (txcompl3 ),
+ .txcompl4 (txcompl4 ),
+ .txcompl5 (txcompl5 ),
+ .txcompl6 (txcompl6 ),
+ .txcompl7 (txcompl7 ),
+ .txcreddatafccp (tx_cred_datafccp ),
+ .txcreddatafcnp (tx_cred_datafcnp ),
+ .txcreddatafcp (tx_cred_datafcp ),
+ .txcredfchipcons (tx_cred_fchipcons ),
+ .txcredfcinfinite (tx_cred_fcinfinite ),
+ .txcredhdrfccp (tx_cred_hdrfccp ),
+ .txcredhdrfcnp (tx_cred_hdrfcnp ),
+ .txcredhdrfcp (tx_cred_hdrfcp ),
+ .txdata0 (txdata0 ),
+ .txdata1 (txdata1 ),
+ .txdata2 (txdata2 ),
+ .txdata3 (txdata3 ),
+ .txdata4 (txdata4 ),
+ .txdata5 (txdata5 ),
+ .txdata6 (txdata6 ),
+ .txdata7 (txdata7 ),
+ .txdatak0 (txdatak0 ),
+ .txdatak1 (txdatak1 ),
+ .txdatak2 (txdatak2 ),
+ .txdatak3 (txdatak3 ),
+ .txdatak4 (txdatak4 ),
+ .txdatak5 (txdatak5 ),
+ .txdatak6 (txdatak6 ),
+ .txdatak7 (txdatak7 ),
+ .txdeemph0 (txdeemph0 ),
+ .txdeemph1 (txdeemph1 ),
+ .txdeemph2 (txdeemph2 ),
+ .txdeemph3 (txdeemph3 ),
+ .txdeemph4 (txdeemph4 ),
+ .txdeemph5 (txdeemph5 ),
+ .txdeemph6 (txdeemph6 ),
+ .txdeemph7 (txdeemph7 ),
+ .txdetectrx0 (txdetectrx0 ),
+ .txdetectrx1 (txdetectrx1 ),
+ .txdetectrx2 (txdetectrx2 ),
+ .txdetectrx3 (txdetectrx3 ),
+ .txdetectrx4 (txdetectrx4 ),
+ .txdetectrx5 (txdetectrx5 ),
+ .txdetectrx6 (txdetectrx6 ),
+ .txdetectrx7 (txdetectrx7 ),
+ .txelecidle0 (txelecidle0 ),
+ .txelecidle1 (txelecidle1 ),
+ .txelecidle2 (txelecidle2 ),
+ .txelecidle3 (txelecidle3 ),
+ .txelecidle4 (txelecidle4 ),
+ .txelecidle5 (txelecidle5 ),
+ .txelecidle6 (txelecidle6 ),
+ .txelecidle7 (txelecidle7 ),
+ .txmargin0 (txmargin0 ),
+ .txmargin1 (txmargin1 ),
+ .txmargin2 (txmargin2 ),
+ .txmargin3 (txmargin3 ),
+ .txmargin4 (txmargin4 ),
+ .txmargin5 (txmargin5 ),
+ .txmargin6 (txmargin6 ),
+ .txmargin7 (txmargin7 ),
+ .txstready (txstready ),
+ .txsynchd0 (txsynchd0 ),
+ .txsynchd1 (txsynchd1 ),
+ .txsynchd2 (txsynchd2 ),
+ .txsynchd3 (txsynchd3 ),
+ .txsynchd4 (txsynchd4 ),
+ .txsynchd5 (txsynchd5 ),
+ .txsynchd6 (txsynchd6 ),
+ .txsynchd7 (txsynchd7 ),
+ .wakeoen (wakeoen )
+ );
+
+
+ //TODO promote serdes_fixedclk as an input 125Mhz clock to the variant
+ generic_pll # ( .reference_clock_frequency("100.0 MHz"), .output_clock_frequency("125.0 MHz") )
+ u_pll_serdes_fixedclk ( .refclk(refclk), .outclk(serdes_fixedclk), .locked(locked_serdes), .fboutclk(fboutclk_fixedclk), .rst((pipe_mode_simu_only==1)?1'b1:~npor), .fbclk(fboutclk_fixedclk));
+
+ assign serdes_pll_powerdown = rst_ctrl_gxb_powerdown;
+ assign serdes_cal_blk_powerdown = 1'b0;
+ assign serdes_cal_blk_clk = 1'b0;
+ assign serdes_rx_set_locktodata[lanes-1:0]= {lanes{1'b0}};
+ assign serdes_rx_set_locktoref [lanes-1:0]= {lanes{1'b0}};
+ assign serdes_tx_invpolarity [lanes-1:0]= {lanes{1'b0}};
+
+ sv_xcvr_pipe_native #(
+ .lanes (lanes ), //legal value: 1+
+ .starting_channel_number (starting_channel_number ), //legal value: 0+
+ .protocol_version (protocol_version ), //legal value: "gen1", "gen2"
+ .deser_factor (deser_factor ),
+ .pll_refclk_freq (pll_refclk_freq ), //legal value = "100 MHz", "125 MHz"
+ .hip_enable (hip_enable )
+ ) sv_xcvr_pipe_native (
+ .pll_powerdown ((pipe_mode_simu_only==1'b1)?1'b0 :serdes_pll_powerdown ), //
+ .tx_digitalreset ((pipe_mode_simu_only==1'b1)?ONES[lanes-1:0]:serdes_tx_digitalreset [lanes-1:0]), //
+ .rx_analogreset ((pipe_mode_simu_only==1'b1)?ONES[lanes-1:0]:serdes_rx_analogreset [lanes-1:0]), //
+ .tx_analogreset (ZEROS[lanes-1:0]), //
+ .rx_digitalreset ((pipe_mode_simu_only==1'b1)?ONES[lanes-1:0]:serdes_rx_digitalreset [lanes-1:0]), //
+
+ //clk signal
+ .pll_ref_clk ((pipe_mode_simu_only==1'b1)?1'b0:refclk), //
+ .fixedclk ((pipe_mode_simu_only==1'b1)?1'b0:serdes_fixedclk), //
+
+ //pipe interface ports
+ .pipe_txdata (serdes_pipe_txdata [lanes * deser_factor - 1:0]), //
+ .pipe_txdatak (serdes_pipe_txdatak [((lanes * deser_factor)/8) - 1:0] ), //
+ .pipe_txdetectrx_loopback (serdes_pipe_txdetectrx_loopback[lanes - 1:0] ), //?
+ .pipe_txcompliance (serdes_pipe_txcompliance [lanes - 1:0] ), //
+ .pipe_txelecidle (serdes_pipe_txelecidle [lanes - 1:0] ), //
+ .pipe_txdeemph (serdes_pipe_txdeemph [lanes - 1:0] ), //
+ .pipe_txmargin (serdes_pipe_txmargin [lanes * 3 - 1:0] ), //
+ .pipe_rate (serdes_pipe_rate [lanes * 2 - 1:0] ),
+ .pipe_powerdown (serdes_pipe_powerdown [lanes * 2 - 1:0]), //
+
+ .pipe_rxdata (serdes_pipe_rxdata [lanes * deser_factor - 1:0] ), //
+ .pipe_rxdatak (serdes_pipe_rxdatak [((lanes * deser_factor)/8) - 1:0]), //
+ .pipe_rxvalid (serdes_pipe_rxvalid [lanes - 1:0] ), //
+ .pipe_rxpolarity (serdes_pipe_rxpolarity [lanes - 1:0] ), //
+ .pipe_rxelecidle (serdes_pipe_rxelecidle [lanes - 1:0] ), //
+ .pipe_phystatus (serdes_pipe_phystatus [lanes - 1:0] ), //
+ .pipe_rxstatus (serdes_pipe_rxstatus [lanes * 3 - 1:0] ), //
+
+ //non-PIPE ports
+ .rx_eidleinfersel (serdes_rx_eidleinfersel [lanes*3 -1:0]),
+ .rx_set_locktodata (serdes_rx_set_locktodata [lanes-1:0] ),
+ .rx_set_locktoref (serdes_rx_set_locktoref [lanes-1:0] ),
+ .tx_invpolarity (serdes_tx_invpolarity [lanes-1:0] ),
+ .rx_errdetect (serdes_rx_errdetect [lanes*2-1:0]),
+ .rx_disperr (serdes_rx_disperr [lanes*2-1:0]),
+ .rx_patterndetect (serdes_rx_patterndetect [lanes*2-1:0] ),
+ .rx_syncstatus (serdes_rx_syncstatus [lanes*2-1:0] ),
+ .rx_phase_comp_fifo_error (serdes_rx_phase_comp_fifo_error[lanes-1:0] ),
+ .tx_phase_comp_fifo_error (serdes_tx_phase_comp_fifo_error[lanes-1:0] ),
+ .rx_is_lockedtoref (serdes_rx_is_lockedtoref [lanes-1:0] ),
+ .rx_signaldetect (serdes_rx_signaldetect [lanes-1:0] ),
+ .rx_is_lockedtodata (serdes_rx_is_lockedtodata [lanes-1:0] ),
+ .pll_locked (serdes_pll_locked ),
+ //.cal_blk_powerdown (serdes_cal_blk_powerdown ),
+
+ //non-MM ports
+ .rx_serial_data (serdes_rx_serial_data[lanes-1:0] ),
+ .tx_serial_data (serdes_tx_serial_data[lanes-1:0] ),
+
+ .pllfixedclkcentral (serdes_pllfixedclkcentral ),
+ .pllfixedclkch0 (serdes_pllfixedclkch0 ),
+ .pllfixedclkch1 (serdes_pllfixedclkch1 ),
+ .pipe_pclk (serdes_pipe_pclk ),
+ .pipe_pclkch1 (serdes_pipe_pclkch1 ),
+ .pipe_pclkcentral (serdes_pipe_pclkcentral )
+ //.cal_blk_clk ((pipe_mode_simu_only==1'b1)?1'b0:serdes_cal_blk_clk)
+ );
+
+
+////////////////////////////////////////////////////////////////////////////
+// Simulation only
+
+// synthesis translate_off
+
+ assign pipe_mode_simu_only = pipe_mode;
+
+ altpcie_pll_100_250 refclk_to_250mhz
+ (
+ .areset (1'b0),
+ .c0 (clk250_out),
+ .inclk0 (refclk)
+ );
+
+
+ altpcie_pll_125_250 pll_250mhz_to_500mhz (
+ .areset (1'b0),
+ .c0 (clk500_out),
+ .inclk0 (clk250_out)
+ );
+
+ sim_txpipe_8bit_to_32_bit sim_txpipe_8bit_to_32_bit (
+ .sim_pipe8_pclk (pclk_in),
+ .sim_pipe32_pclk (sim_pipe32_pclk),
+ .aclr (npor),
+ .pipe_mode_simu_only (pipe_mode_simu_only),
+
+ .eidleinfersel0 (eidleinfersel0 ),
+ .eidleinfersel1 (eidleinfersel1 ),
+ .eidleinfersel2 (eidleinfersel2 ),
+ .eidleinfersel3 (eidleinfersel3 ),
+ .eidleinfersel4 (eidleinfersel4 ),
+ .eidleinfersel5 (eidleinfersel5 ),
+ .eidleinfersel6 (eidleinfersel6 ),
+ .eidleinfersel7 (eidleinfersel7 ),
+ .powerdown0 (powerdown0 ),
+ .powerdown1 (powerdown1 ),
+ .powerdown2 (powerdown2 ),
+ .powerdown3 (powerdown3 ),
+ .powerdown4 (powerdown4 ),
+ .powerdown5 (powerdown5 ),
+ .powerdown6 (powerdown6 ),
+ .powerdown7 (powerdown7 ),
+ .rxpolarity0 (rxpolarity0 ),
+ .rxpolarity1 (rxpolarity1 ),
+ .rxpolarity2 (rxpolarity2 ),
+ .rxpolarity3 (rxpolarity3 ),
+ .rxpolarity4 (rxpolarity4 ),
+ .rxpolarity5 (rxpolarity5 ),
+ .rxpolarity6 (rxpolarity6 ),
+ .rxpolarity7 (rxpolarity7 ),
+ .txcompl0 (txcompl0 ),
+ .txcompl1 (txcompl1 ),
+ .txcompl2 (txcompl2 ),
+ .txcompl3 (txcompl3 ),
+ .txcompl4 (txcompl4 ),
+ .txcompl5 (txcompl5 ),
+ .txcompl6 (txcompl6 ),
+ .txcompl7 (txcompl7 ),
+ .txdata0 (txdata0 ),
+ .txdata1 (txdata1 ),
+ .txdata2 (txdata2 ),
+ .txdata3 (txdata3 ),
+ .txdata4 (txdata4 ),
+ .txdata5 (txdata5 ),
+ .txdata6 (txdata6 ),
+ .txdata7 (txdata7 ),
+ .txdatak0 (txdatak0 ),
+ .txdatak1 (txdatak1 ),
+ .txdatak2 (txdatak2 ),
+ .txdatak3 (txdatak3 ),
+ .txdatak4 (txdatak4 ),
+ .txdatak5 (txdatak5 ),
+ .txdatak6 (txdatak6 ),
+ .txdatak7 (txdatak7 ),
+ //.txdatavalid0 (txdatavalid0 ),
+ //.txdatavalid1 (txdatavalid1 ),
+ //.txdatavalid2 (txdatavalid2 ),
+ //.txdatavalid3 (txdatavalid3 ),
+ //.txdatavalid4 (txdatavalid4 ),
+ //.txdatavalid5 (txdatavalid5 ),
+ //.txdatavalid6 (txdatavalid6 ),
+ //.txdatavalid7 (txdatavalid7 ),
+ .txdetectrx0 (txdetectrx0 ),
+ .txdetectrx1 (txdetectrx1 ),
+ .txdetectrx2 (txdetectrx2 ),
+ .txdetectrx3 (txdetectrx3 ),
+ .txdetectrx4 (txdetectrx4 ),
+ .txdetectrx5 (txdetectrx5 ),
+ .txdetectrx6 (txdetectrx6 ),
+ .txdetectrx7 (txdetectrx7 ),
+ .txelecidle0 (txelecidle0 ),
+ .txelecidle1 (txelecidle1 ),
+ .txelecidle2 (txelecidle2 ),
+ .txelecidle3 (txelecidle3 ),
+ .txelecidle4 (txelecidle4 ),
+ .txelecidle5 (txelecidle5 ),
+ .txelecidle6 (txelecidle6 ),
+ .txelecidle7 (txelecidle7 ),
+ .txmargin0 (txmargin0 ),
+ .txmargin1 (txmargin1 ),
+ .txmargin2 (txmargin2 ),
+ .txmargin3 (txmargin3 ),
+ .txmargin4 (txmargin4 ),
+ .txmargin5 (txmargin5 ),
+ .txmargin6 (txmargin6 ),
+ .txmargin7 (txmargin7 ),
+ .txdeemph0 (txdeemph0 ),
+ .txdeemph1 (txdeemph1 ),
+ .txdeemph2 (txdeemph2 ),
+ .txdeemph3 (txdeemph3 ),
+ .txdeemph4 (txdeemph4 ),
+ .txdeemph5 (txdeemph5 ),
+ .txdeemph6 (txdeemph6 ),
+ .txdeemph7 (txdeemph7 ),
+ .txblkst0 (txblkst0 ),
+ .txblkst1 (txblkst1 ),
+ .txblkst2 (txblkst2 ),
+ .txblkst3 (txblkst3 ),
+ .txblkst4 (txblkst4 ),
+ .txblkst5 (txblkst5 ),
+ .txblkst6 (txblkst6 ),
+ .txblkst7 (txblkst7 ),
+ .txsynchd0 (txsynchd0 ),
+ .txsynchd1 (txsynchd1 ),
+ .txsynchd2 (txsynchd2 ),
+ .txsynchd3 (txsynchd3 ),
+ .txsynchd4 (txsynchd4 ),
+ .txsynchd5 (txsynchd5 ),
+ .txsynchd6 (txsynchd6 ),
+ .txsynchd7 (txsynchd7 ),
+ .currentcoeff0 (currentcoeff0 ),
+ .currentcoeff1 (currentcoeff1 ),
+ .currentcoeff2 (currentcoeff2 ),
+ .currentcoeff3 (currentcoeff3 ),
+ .currentcoeff4 (currentcoeff4 ),
+ .currentcoeff5 (currentcoeff5 ),
+ .currentcoeff6 (currentcoeff6 ),
+ .currentcoeff7 (currentcoeff7 ),
+ .currentrxpreset0 (currentrxpreset0 ),
+ .currentrxpreset1 (currentrxpreset1 ),
+ .currentrxpreset2 (currentrxpreset2 ),
+ .currentrxpreset3 (currentrxpreset3 ),
+ .currentrxpreset4 (currentrxpreset4 ),
+ .currentrxpreset5 (currentrxpreset5 ),
+ .currentrxpreset6 (currentrxpreset6 ),
+ .currentrxpreset7 (currentrxpreset7 ),
+
+ .eidleinfersel0_ext (eidleinfersel0_ext ),
+ .eidleinfersel1_ext (eidleinfersel1_ext ),
+ .eidleinfersel2_ext (eidleinfersel2_ext ),
+ .eidleinfersel3_ext (eidleinfersel3_ext ),
+ .eidleinfersel4_ext (eidleinfersel4_ext ),
+ .eidleinfersel5_ext (eidleinfersel5_ext ),
+ .eidleinfersel6_ext (eidleinfersel6_ext ),
+ .eidleinfersel7_ext (eidleinfersel7_ext ),
+ .powerdown0_ext (powerdown0_ext ),
+ .powerdown1_ext (powerdown1_ext ),
+ .powerdown2_ext (powerdown2_ext ),
+ .powerdown3_ext (powerdown3_ext ),
+ .powerdown4_ext (powerdown4_ext ),
+ .powerdown5_ext (powerdown5_ext ),
+ .powerdown6_ext (powerdown6_ext ),
+ .powerdown7_ext (powerdown7_ext ),
+ .rxpolarity0_ext (rxpolarity0_ext ),
+ .rxpolarity1_ext (rxpolarity1_ext ),
+ .rxpolarity2_ext (rxpolarity2_ext ),
+ .rxpolarity3_ext (rxpolarity3_ext ),
+ .rxpolarity4_ext (rxpolarity4_ext ),
+ .rxpolarity5_ext (rxpolarity5_ext ),
+ .rxpolarity6_ext (rxpolarity6_ext ),
+ .rxpolarity7_ext (rxpolarity7_ext ),
+ .txcompl0_ext (txcompl0_ext ),
+ .txcompl1_ext (txcompl1_ext ),
+ .txcompl2_ext (txcompl2_ext ),
+ .txcompl3_ext (txcompl3_ext ),
+ .txcompl4_ext (txcompl4_ext ),
+ .txcompl5_ext (txcompl5_ext ),
+ .txcompl6_ext (txcompl6_ext ),
+ .txcompl7_ext (txcompl7_ext ),
+ .txdata0_ext (txdata0_ext ),
+ .txdata1_ext (txdata1_ext ),
+ .txdata2_ext (txdata2_ext ),
+ .txdata3_ext (txdata3_ext ),
+ .txdata4_ext (txdata4_ext ),
+ .txdata5_ext (txdata5_ext ),
+ .txdata6_ext (txdata6_ext ),
+ .txdata7_ext (txdata7_ext ),
+ .txdatak0_ext (txdatak0_ext ),
+ .txdatak1_ext (txdatak1_ext ),
+ .txdatak2_ext (txdatak2_ext ),
+ .txdatak3_ext (txdatak3_ext ),
+ .txdatak4_ext (txdatak4_ext ),
+ .txdatak5_ext (txdatak5_ext ),
+ .txdatak6_ext (txdatak6_ext ),
+ .txdatak7_ext (txdatak7_ext ),
+ //.txdatavalid0_ext (txdatavalid0_ext ),
+ //.txdatavalid1_ext (txdatavalid1_ext ),
+ //.txdatavalid2_ext (txdatavalid2_ext ),
+ //.txdatavalid3_ext (txdatavalid3_ext ),
+ //.txdatavalid4_ext (txdatavalid4_ext ),
+ //.txdatavalid5_ext (txdatavalid5_ext ),
+ //.txdatavalid6_ext (txdatavalid6_ext ),
+ //.txdatavalid7_ext (txdatavalid7_ext ),
+ .txdetectrx0_ext (txdetectrx0_ext ),
+ .txdetectrx1_ext (txdetectrx1_ext ),
+ .txdetectrx2_ext (txdetectrx2_ext ),
+ .txdetectrx3_ext (txdetectrx3_ext ),
+ .txdetectrx4_ext (txdetectrx4_ext ),
+ .txdetectrx5_ext (txdetectrx5_ext ),
+ .txdetectrx6_ext (txdetectrx6_ext ),
+ .txdetectrx7_ext (txdetectrx7_ext ),
+ .txelecidle0_ext (txelecidle0_ext ),
+ .txelecidle1_ext (txelecidle1_ext ),
+ .txelecidle2_ext (txelecidle2_ext ),
+ .txelecidle3_ext (txelecidle3_ext ),
+ .txelecidle4_ext (txelecidle4_ext ),
+ .txelecidle5_ext (txelecidle5_ext ),
+ .txelecidle6_ext (txelecidle6_ext ),
+ .txelecidle7_ext (txelecidle7_ext ),
+ .txmargin0_ext (txmargin0_ext ),
+ .txmargin1_ext (txmargin1_ext ),
+ .txmargin2_ext (txmargin2_ext ),
+ .txmargin3_ext (txmargin3_ext ),
+ .txmargin4_ext (txmargin4_ext ),
+ .txmargin5_ext (txmargin5_ext ),
+ .txmargin6_ext (txmargin6_ext ),
+ .txmargin7_ext (txmargin7_ext ),
+ .txdeemph0_ext (txdeemph0_ext ),
+ .txdeemph1_ext (txdeemph1_ext ),
+ .txdeemph2_ext (txdeemph2_ext ),
+ .txdeemph3_ext (txdeemph3_ext ),
+ .txdeemph4_ext (txdeemph4_ext ),
+ .txdeemph5_ext (txdeemph5_ext ),
+ .txdeemph6_ext (txdeemph6_ext ),
+ .txdeemph7_ext (txdeemph7_ext ),
+ .txblkst0_ext (txblkst0_ext ),
+ .txblkst1_ext (txblkst1_ext ),
+ .txblkst2_ext (txblkst2_ext ),
+ .txblkst3_ext (txblkst3_ext ),
+ .txblkst4_ext (txblkst4_ext ),
+ .txblkst5_ext (txblkst5_ext ),
+ .txblkst6_ext (txblkst6_ext ),
+ .txblkst7_ext (txblkst7_ext ),
+ .txsynchd0_ext (txsynchd0_ext ),
+ .txsynchd1_ext (txsynchd1_ext ),
+ .txsynchd2_ext (txsynchd2_ext ),
+ .txsynchd3_ext (txsynchd3_ext ),
+ .txsynchd4_ext (txsynchd4_ext ),
+ .txsynchd5_ext (txsynchd5_ext ),
+ .txsynchd6_ext (txsynchd6_ext ),
+ .txsynchd7_ext (txsynchd7_ext ),
+ .currentcoeff0_ext (currentcoeff0_ext ),
+ .currentcoeff1_ext (currentcoeff1_ext ),
+ .currentcoeff2_ext (currentcoeff2_ext ),
+ .currentcoeff3_ext (currentcoeff3_ext ),
+ .currentcoeff4_ext (currentcoeff4_ext ),
+ .currentcoeff5_ext (currentcoeff5_ext ),
+ .currentcoeff6_ext (currentcoeff6_ext ),
+ .currentcoeff7_ext (currentcoeff7_ext ),
+ .currentrxpreset0_ext (currentrxpreset0_ext ),
+ .currentrxpreset1_ext (currentrxpreset1_ext ),
+ .currentrxpreset2_ext (currentrxpreset2_ext ),
+ .currentrxpreset3_ext (currentrxpreset3_ext ),
+ .currentrxpreset4_ext (currentrxpreset4_ext ),
+ .currentrxpreset5_ext (currentrxpreset5_ext ),
+ .currentrxpreset6_ext (currentrxpreset6_ext ),
+ .currentrxpreset7_ext (currentrxpreset7_ext )
+
+ );
+
+
+ sim_rxpipe_8bit_to_32_bit sim_rxpipe_8bit_to_32_bit (
+ // Input PIPE simulation _ext for simulation only
+ .sim_pipe8_pclk (pclk_in),
+ .aclr (npor),
+
+ .phystatus0_ext (phystatus0_ext ),
+ .phystatus1_ext (phystatus1_ext ),
+ .phystatus2_ext (phystatus2_ext ),
+ .phystatus3_ext (phystatus3_ext ),
+ .phystatus4_ext (phystatus4_ext ),
+ .phystatus5_ext (phystatus5_ext ),
+ .phystatus6_ext (phystatus6_ext ),
+ .phystatus7_ext (phystatus7_ext ),
+ .rxdata0_ext (rxdata0_ext ),
+ .rxdata1_ext (rxdata1_ext ),
+ .rxdata2_ext (rxdata2_ext ),
+ .rxdata3_ext (rxdata3_ext ),
+ .rxdata4_ext (rxdata4_ext ),
+ .rxdata5_ext (rxdata5_ext ),
+ .rxdata6_ext (rxdata6_ext ),
+ .rxdata7_ext (rxdata7_ext ),
+ .rxdatak0_ext (rxdatak0_ext ),
+ .rxdatak1_ext (rxdatak1_ext ),
+ .rxdatak2_ext (rxdatak2_ext ),
+ .rxdatak3_ext (rxdatak3_ext ),
+ .rxdatak4_ext (rxdatak4_ext ),
+ .rxdatak5_ext (rxdatak5_ext ),
+ .rxdatak6_ext (rxdatak6_ext ),
+ .rxdatak7_ext (rxdatak7_ext ),
+ .rxelecidle0_ext (rxelecidle0_ext ),
+ .rxelecidle1_ext (rxelecidle1_ext ),
+ .rxelecidle2_ext (rxelecidle2_ext ),
+ .rxelecidle3_ext (rxelecidle3_ext ),
+ .rxelecidle4_ext (rxelecidle4_ext ),
+ .rxelecidle5_ext (rxelecidle5_ext ),
+ .rxelecidle6_ext (rxelecidle6_ext ),
+ .rxelecidle7_ext (rxelecidle7_ext ),
+ .rxfreqlocked0_ext (rxfreqlocked0_ext ),
+ .rxfreqlocked1_ext (rxfreqlocked1_ext ),
+ .rxfreqlocked2_ext (rxfreqlocked2_ext ),
+ .rxfreqlocked3_ext (rxfreqlocked3_ext ),
+ .rxfreqlocked4_ext (rxfreqlocked4_ext ),
+ .rxfreqlocked5_ext (rxfreqlocked5_ext ),
+ .rxfreqlocked6_ext (rxfreqlocked6_ext ),
+ .rxfreqlocked7_ext (rxfreqlocked7_ext ),
+ .rxstatus0_ext (rxstatus0_ext ),
+ .rxstatus1_ext (rxstatus1_ext ),
+ .rxstatus2_ext (rxstatus2_ext ),
+ .rxstatus3_ext (rxstatus3_ext ),
+ .rxstatus4_ext (rxstatus4_ext ),
+ .rxstatus5_ext (rxstatus5_ext ),
+ .rxstatus6_ext (rxstatus6_ext ),
+ .rxstatus7_ext (rxstatus7_ext ),
+ .rxdataskip0_ext (rxdataskip0_ext ),
+ .rxdataskip1_ext (rxdataskip1_ext ),
+ .rxdataskip2_ext (rxdataskip2_ext ),
+ .rxdataskip3_ext (rxdataskip3_ext ),
+ .rxdataskip4_ext (rxdataskip4_ext ),
+ .rxdataskip5_ext (rxdataskip5_ext ),
+ .rxdataskip6_ext (rxdataskip6_ext ),
+ .rxdataskip7_ext (rxdataskip7_ext ),
+ .rxblkst0_ext (rxblkst0_ext ),
+ .rxblkst1_ext (rxblkst1_ext ),
+ .rxblkst2_ext (rxblkst2_ext ),
+ .rxblkst3_ext (rxblkst3_ext ),
+ .rxblkst4_ext (rxblkst4_ext ),
+ .rxblkst5_ext (rxblkst5_ext ),
+ .rxblkst6_ext (rxblkst6_ext ),
+ .rxblkst7_ext (rxblkst7_ext ),
+ .rxsynchd0_ext (rxsynchd0_ext ),
+ .rxsynchd1_ext (rxsynchd1_ext ),
+ .rxsynchd2_ext (rxsynchd2_ext ),
+ .rxsynchd3_ext (rxsynchd3_ext ),
+ .rxsynchd4_ext (rxsynchd4_ext ),
+ .rxsynchd5_ext (rxsynchd5_ext ),
+ .rxsynchd6_ext (rxsynchd6_ext ),
+ .rxsynchd7_ext (rxsynchd7_ext ),
+ .rxvalid0_ext (rxvalid0_ext ),
+ .rxvalid1_ext (rxvalid1_ext ),
+ .rxvalid2_ext (rxvalid2_ext ),
+ .rxvalid3_ext (rxvalid3_ext ),
+ .rxvalid4_ext (rxvalid4_ext ),
+ .rxvalid5_ext (rxvalid5_ext ),
+ .rxvalid6_ext (rxvalid6_ext ),
+ .rxvalid7_ext (rxvalid7_ext ),
+
+ .sim_pipe32_pclk (sim_pipe32_pclk ),
+ .phystatus0_ext32b (phystatus0_ext32b ),
+ .phystatus1_ext32b (phystatus1_ext32b ),
+ .phystatus2_ext32b (phystatus2_ext32b ),
+ .phystatus3_ext32b (phystatus3_ext32b ),
+ .phystatus4_ext32b (phystatus4_ext32b ),
+ .phystatus5_ext32b (phystatus5_ext32b ),
+ .phystatus6_ext32b (phystatus6_ext32b ),
+ .phystatus7_ext32b (phystatus7_ext32b ),
+ .rxdata0_ext32b (rxdata0_ext32b ),
+ .rxdata1_ext32b (rxdata1_ext32b ),
+ .rxdata2_ext32b (rxdata2_ext32b ),
+ .rxdata3_ext32b (rxdata3_ext32b ),
+ .rxdata4_ext32b (rxdata4_ext32b ),
+ .rxdata5_ext32b (rxdata5_ext32b ),
+ .rxdata6_ext32b (rxdata6_ext32b ),
+ .rxdata7_ext32b (rxdata7_ext32b ),
+ .rxdatak0_ext32b (rxdatak0_ext32b ),
+ .rxdatak1_ext32b (rxdatak1_ext32b ),
+ .rxdatak2_ext32b (rxdatak2_ext32b ),
+ .rxdatak3_ext32b (rxdatak3_ext32b ),
+ .rxdatak4_ext32b (rxdatak4_ext32b ),
+ .rxdatak5_ext32b (rxdatak5_ext32b ),
+ .rxdatak6_ext32b (rxdatak6_ext32b ),
+ .rxdatak7_ext32b (rxdatak7_ext32b ),
+ .rxelecidle0_ext32b (rxelecidle0_ext32b ),
+ .rxelecidle1_ext32b (rxelecidle1_ext32b ),
+ .rxelecidle2_ext32b (rxelecidle2_ext32b ),
+ .rxelecidle3_ext32b (rxelecidle3_ext32b ),
+ .rxelecidle4_ext32b (rxelecidle4_ext32b ),
+ .rxelecidle5_ext32b (rxelecidle5_ext32b ),
+ .rxelecidle6_ext32b (rxelecidle6_ext32b ),
+ .rxelecidle7_ext32b (rxelecidle7_ext32b ),
+ .rxfreqlocked0_ext32b (rxfreqlocked0_ext32b ),
+ .rxfreqlocked1_ext32b (rxfreqlocked1_ext32b ),
+ .rxfreqlocked2_ext32b (rxfreqlocked2_ext32b ),
+ .rxfreqlocked3_ext32b (rxfreqlocked3_ext32b ),
+ .rxfreqlocked4_ext32b (rxfreqlocked4_ext32b ),
+ .rxfreqlocked5_ext32b (rxfreqlocked5_ext32b ),
+ .rxfreqlocked6_ext32b (rxfreqlocked6_ext32b ),
+ .rxfreqlocked7_ext32b (rxfreqlocked7_ext32b ),
+ .rxstatus0_ext32b (rxstatus0_ext32b ),
+ .rxstatus1_ext32b (rxstatus1_ext32b ),
+ .rxstatus2_ext32b (rxstatus2_ext32b ),
+ .rxstatus3_ext32b (rxstatus3_ext32b ),
+ .rxstatus4_ext32b (rxstatus4_ext32b ),
+ .rxstatus5_ext32b (rxstatus5_ext32b ),
+ .rxstatus6_ext32b (rxstatus6_ext32b ),
+ .rxstatus7_ext32b (rxstatus7_ext32b ),
+ .rxdataskip0_ext32b (rxdataskip0_ext32b ),
+ .rxdataskip1_ext32b (rxdataskip1_ext32b ),
+ .rxdataskip2_ext32b (rxdataskip2_ext32b ),
+ .rxdataskip3_ext32b (rxdataskip3_ext32b ),
+ .rxdataskip4_ext32b (rxdataskip4_ext32b ),
+ .rxdataskip5_ext32b (rxdataskip5_ext32b ),
+ .rxdataskip6_ext32b (rxdataskip6_ext32b ),
+ .rxdataskip7_ext32b (rxdataskip7_ext32b ),
+ .rxblkst0_ext32b (rxblkst0_ext32b ),
+ .rxblkst1_ext32b (rxblkst1_ext32b ),
+ .rxblkst2_ext32b (rxblkst2_ext32b ),
+ .rxblkst3_ext32b (rxblkst3_ext32b ),
+ .rxblkst4_ext32b (rxblkst4_ext32b ),
+ .rxblkst5_ext32b (rxblkst5_ext32b ),
+ .rxblkst6_ext32b (rxblkst6_ext32b ),
+ .rxblkst7_ext32b (rxblkst7_ext32b ),
+ .rxsynchd0_ext32b (rxsynchd0_ext32b ),
+ .rxsynchd1_ext32b (rxsynchd1_ext32b ),
+ .rxsynchd2_ext32b (rxsynchd2_ext32b ),
+ .rxsynchd3_ext32b (rxsynchd3_ext32b ),
+ .rxsynchd4_ext32b (rxsynchd4_ext32b ),
+ .rxsynchd5_ext32b (rxsynchd5_ext32b ),
+ .rxsynchd6_ext32b (rxsynchd6_ext32b ),
+ .rxsynchd7_ext32b (rxsynchd7_ext32b ),
+ .rxvalid0_ext32b (rxvalid0_ext32b ),
+ .rxvalid1_ext32b (rxvalid1_ext32b ),
+ .rxvalid2_ext32b (rxvalid2_ext32b ),
+ .rxvalid3_ext32b (rxvalid3_ext32b ),
+ .rxvalid4_ext32b (rxvalid4_ext32b ),
+ .rxvalid5_ext32b (rxvalid5_ext32b ),
+ .rxvalid6_ext32b (rxvalid6_ext32b ),
+ .rxvalid7_ext32b (rxvalid7_ext32b )
+ );
+
+// synthesis translate_on
+
+
+endmodule
+
+
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+//////////////////////////////////////////////////////////////////////////////////////////////
+//
+// Ve// rilog file generated by X-HDL - Revision 3.2.54 Aug. 8 <=; 2005
+// Fri Nov 4 10:07:57 2005
+//
+// Input file : D:/cvs_build/projects/pci_express_r1/altera/src/vhdl/top/alt4gxb_reset_controller.vhd
+// Design name : alt4gxb_reset_controller
+// Author :
+// Company :
+//
+// Description :
+//
+//
+//////////////////////////////////////////////////////////////////////////////////////////////
+//
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// Logic Core: PCI Express Megacore Function
+// Company: Altera Corporation.
+// www.altera.com
+// Author: IPBU SIO Group
+//
+// Description: Altera PCI Express MegaCore Reset controller for Alt2gxb
+//
+// Copyright (c) 2005 Altera Corporation. All rights reserved. This source code
+// is highly confidential and proprietary information of Altera and is being
+// provided in accordance with and subject to the protections of a
+// Non-Disclosure Agreement which governs its use and disclosure. Altera
+// products and services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws. Altera
+// assumes no responsibility or liability arising out of the application or use
+// of this source code.
+//
+// For Best Viewing Set tab stops to 4 spaces.
+//
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// Reset Controller for the ALT2GXB
+//
+//
+module alt5gxb_reset_controller
+ (input inclk,
+ input async_reset,
+ input test_sim,
+ input pll_locked,
+ input rx_pll_locked,
+ input fifo_err,
+ input inclk_eq_125mhz,
+ output gxb_powerdown,
+ output txdigitalreset,
+ output rxanalogreset,
+ output rxdigitalreset
+) ;
+
+ localparam [19:0] WS_SIM = 20'h00020;
+ localparam [19:0] WS_1MS_10000 = 20'h186a0;
+ localparam [19:0] WS_1MS_12500 = 20'h1e848;
+ localparam [19:0] WS_1MS_15625 = 20'h2625a;
+ localparam [19:0] WS_1MS_25000 = 20'h3d090;
+ localparam [1:0] idle = 0;
+ localparam [1:0] strobe_txpll_locked = 1;
+ localparam [1:0] stable_tx_pll = 2;
+ localparam [1:0] wait_state = 3;
+// Suppressing R102 here because gxb_powredown takes out the whole alt2gxb and no clock
+// will be running
+ reg [1:0] rst_ctrl_sm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+ reg [19:0] waitstate_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+
+ reg txdigitalreset_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+ reg rxanalogreset_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+ reg rxdigitalreset_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+ reg ws_tmr_eq_0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+ reg ld_ws_tmr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+ reg ld_ws_tmr_short /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+reg [2:0] rx_pll_locked_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+reg rx_pll_locked_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+
+ assign gxb_powerdown = async_reset ;
+ assign txdigitalreset = txdigitalreset_r ;
+ assign rxanalogreset = rxanalogreset_r ;
+ assign rxdigitalreset = rxdigitalreset_r ;
+
+ always @(posedge inclk or posedge async_reset)
+ begin
+ if (async_reset == 1'b1)
+ begin
+ txdigitalreset_r <= 1'b1 ;
+ rxanalogreset_r <= 1'b1 ;
+ rxdigitalreset_r <= 1'b1 ;
+ waitstate_timer <= 20'hFFFFF ;
+ rst_ctrl_sm <= strobe_txpll_locked ;
+ ws_tmr_eq_0 <= 1'b0 ;
+ ld_ws_tmr <= 1'b1 ;
+ ld_ws_tmr_short <= 1'b0 ;
+ rx_pll_locked_cnt <= 3'h0;
+ rx_pll_locked_r <= 1'b0;
+ end
+ else
+ begin
+ // add hysterisis for losing lock
+ if (rx_pll_locked == 1'b1)
+ rx_pll_locked_cnt <= 3'h7;
+ else if (rx_pll_locked_cnt == 3'h0)
+ rx_pll_locked_cnt <= 3'h0;
+ else if (rx_pll_locked == 1'b0)
+ rx_pll_locked_cnt <= rx_pll_locked_cnt - 1;
+
+ rx_pll_locked_r <= (rx_pll_locked_cnt != 3'h0);
+
+ if (ld_ws_tmr == 1'b1)
+ begin
+ if (test_sim == 1'b1)
+ begin
+ waitstate_timer <= WS_SIM ;
+ end
+ else if (inclk_eq_125mhz == 1'b1)
+ begin
+ waitstate_timer <= WS_1MS_12500 ;
+ end
+ else
+ begin
+ waitstate_timer <= WS_1MS_25000 ;
+ end
+ end
+ else if (ld_ws_tmr_short == 1'b1)
+ waitstate_timer <= WS_SIM ;
+ else if (waitstate_timer != 20'h00000)
+ begin
+ waitstate_timer <= waitstate_timer - 1 ;
+ end
+ if (ld_ws_tmr == 1'b1 | ld_ws_tmr_short)
+ begin
+ ws_tmr_eq_0 <= 1'b0 ;
+ end
+ else if (waitstate_timer == 20'h00000)
+ begin
+ ws_tmr_eq_0 <= 1'b1 ;
+ end
+ else
+ begin
+ ws_tmr_eq_0 <= 1'b0 ;
+ end
+ case (rst_ctrl_sm)
+ idle :
+ begin
+ if (rx_pll_locked_r == 1'b1)
+ begin
+ if (fifo_err == 1'b1)
+ rst_ctrl_sm <= stable_tx_pll ;
+ else
+ rst_ctrl_sm <= idle ;
+ end
+ else
+ begin
+ rst_ctrl_sm <= strobe_txpll_locked ;
+ ld_ws_tmr <= 1'b1 ;
+ end
+ end
+ strobe_txpll_locked :
+ begin
+ ld_ws_tmr <= 1'b0 ;
+ if (pll_locked == 1'b1 & ws_tmr_eq_0 == 1'b1)
+ begin
+ rst_ctrl_sm <= stable_tx_pll ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ else
+ begin
+ rst_ctrl_sm <= strobe_txpll_locked ;
+ txdigitalreset_r <= 1'b1 ;
+ rxanalogreset_r <= 1'b1 ;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ end
+ stable_tx_pll :
+ begin
+ if (rx_pll_locked_r == 1'b1)
+ begin
+ rst_ctrl_sm <= wait_state ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b1 ;
+ ld_ws_tmr_short <= 1'b1 ;
+ end
+ else
+ begin
+ rst_ctrl_sm <= stable_tx_pll ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ end
+ wait_state :
+ begin
+ if (rx_pll_locked_r == 1'b1)
+ begin
+ ld_ws_tmr_short <= 1'b0 ;
+ if (ld_ws_tmr_short == 1'b0 & ws_tmr_eq_0 == 1'b1)
+ begin
+ rst_ctrl_sm <= idle ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b0 ;
+ end
+ else
+ begin
+ rst_ctrl_sm <= wait_state ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ end
+ else
+ begin
+ rst_ctrl_sm <= stable_tx_pll ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ end
+ default :
+ begin
+ rst_ctrl_sm <= idle ;
+ waitstate_timer <= 20'hFFFFF ;
+ end
+ endcase
+ end
+ end
+endmodule
+
+
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// For Mentor cosim
+`ifdef ALTPCIETB_COSIM_MENTOR
+
+module global (in, out);
+ input in;
+ output out;
+
+ assign out = in;
+endmodule
+
+`endif
+// synthesis translate_on
+
diff --git a/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v b/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v
new file mode 100644
index 0000000000000000000000000000000000000000..2563ef7b2977bc3ce07f4013b5edd7d18ac268fd
Binary files /dev/null and b/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v differ
diff --git a/ip_compiler_for_pci_express-library/altpcie_pclk_align.v b/ip_compiler_for_pci_express-library/altpcie_pclk_align.v
new file mode 100644
index 0000000000000000000000000000000000000000..d21a18ef1cacfb30eb7350243a1a4f7ccbf225e4
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pclk_align.v
@@ -0,0 +1,463 @@
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// Logic Core: PCI Express Megacore Function
+// Company: Altera Corporation.
+// www.altera.com
+// Author: IPBU SIO Group
+//
+// Description: Altera PCI Express MegaCore function clk phase alignment
+// module for S4GX ES silicon
+//
+// Copyright 2009 Altera Corporation. All rights reserved. This source code
+// is highly confidential and proprietary information of Altera and is being
+// provided in accordance with and subject to the protections of a
+// Non-Disclosure Agreement which governs its use and disclosure. Altera
+// products and services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws. Altera
+// assumes no responsibility or liability arising out of the application or use
+// of this source code.
+//
+// For Best Viewing Set tab stops to 4 spaces.
+//
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+
+module altpcie_pclk_align
+(
+rst,
+clock,
+offset,
+onestep,
+onestep_dir,
+PCLK_Master,
+PCLK_Slave,
+PhaseUpDown,
+PhaseStep,
+PhaseDone,
+AlignLock,
+PhaseDone_reg,
+compout_reg,
+pcie_sw_in,
+pcie_sw_out
+
+);
+
+
+input rst;
+input clock;
+input [7:0] offset;
+input onestep;
+input onestep_dir;
+input PCLK_Master;
+input PCLK_Slave;
+input PhaseDone;
+output PhaseUpDown;
+output PhaseStep;
+output AlignLock;
+output PhaseDone_reg;
+output compout_reg;
+input pcie_sw_in;
+output pcie_sw_out;
+
+reg PhaseUpDown;
+reg PhaseStep;
+reg AlignLock;
+
+wire PhaseDone_reg = 0;
+wire compout_reg = 0;
+
+
+localparam DREG_SIZE = 128;
+localparam BIAS_ONE = 1;
+
+
+reg [3:0] align_sm;
+localparam INIT = 0;
+localparam EVAL = 1;
+localparam ADVC = 2;
+localparam DELY = 3;
+localparam BACK = 4;
+localparam ERR = 5;
+localparam DONE = 6;
+localparam MNUL = 7;
+// debug txt
+reg [4 * 8 -1 :0] align_sm_txt;
+always@(align_sm)
+ case(align_sm)
+ INIT: align_sm_txt = "init";
+ EVAL: align_sm_txt = "eval";
+ ADVC: align_sm_txt = "advc";
+ DELY: align_sm_txt = "dely";
+ BACK: align_sm_txt = "back";
+ ERR: align_sm_txt = "err";
+ DONE: align_sm_txt = "done";
+ MNUL: align_sm_txt = "mnul";
+ endcase
+
+
+reg [DREG_SIZE-1: 0] delay_reg;
+integer i;
+reg all_zero;
+reg all_one;
+reg chk_req;
+wire chk_ack;
+reg [7:0] chk_cnt;
+reg chk_ack_r;
+reg chk_ack_rr;
+reg chk_ok;
+
+// controls
+reg found_zero; // found all zeros
+reg found_meta; // found metastable region
+reg found_one; // found all ones
+reg [7:0] window_cnt; // count the number of taps between all zero and all ones
+reg clr_window_cnt;
+reg inc_window_cnt;
+reg dec_window_cnt;
+reg half_window_cnt;
+reg [1:0] retrain_cnt;
+reg pcie_sw_r;
+reg pcie_sw_rr;
+reg pcie_sw_out;
+
+assign chk_ack = chk_cnt[7];
+
+always @ (posedge PCLK_Master or posedge rst)
+ begin
+ if (rst)
+ begin
+ delay_reg <= {DREG_SIZE{1'b0}};
+ all_zero <= 1'b1;
+ all_one <= 1'b0;
+ chk_cnt <= 0;
+ end
+
+ else
+ begin
+ delay_reg[0] <= PCLK_Slave;
+ for (i = 1; i < DREG_SIZE; i = i + 1)
+ delay_reg[i] <= delay_reg[i-1];
+
+ // discount the first two flops which are sync flops
+ if (chk_cnt == 8'h80)
+ begin
+ all_zero <= ~|delay_reg[DREG_SIZE-1:2];
+ all_one <= &delay_reg[DREG_SIZE-1:2];
+ end
+
+
+ // handshake with slow clock
+ if (chk_req & (chk_cnt == 8'h8f))
+ chk_cnt <= 0;
+ else if (chk_cnt == 8'h8f)
+ chk_cnt <= chk_cnt;
+ else
+ chk_cnt <= chk_cnt + 1;
+
+ end
+ end
+
+
+always @ (posedge clock or posedge rst)
+ begin
+ if (rst)
+ begin
+ align_sm <= INIT;
+ chk_req <= 0;
+ chk_ack_r <= 0;
+ chk_ack_rr <= 0;
+ chk_ok <= 0;
+ found_zero <= 0;
+ found_meta <= 0;
+ found_one <= 0;
+ PhaseUpDown <= 0;
+ PhaseStep <= 0;
+ window_cnt <= 8'h00;
+ clr_window_cnt <= 0;
+ inc_window_cnt <= 0;
+ dec_window_cnt <= 0;
+ half_window_cnt <= 0;
+ AlignLock <= 0;
+ retrain_cnt <= 0;
+ end
+ else
+ begin
+
+ chk_ack_r <= chk_ack;
+ chk_ack_rr <= chk_ack_r;
+
+ if ((chk_ack_rr == 0) & (chk_ack_r == 1))
+ chk_ok <= 1;
+ else
+ chk_ok <= 0;
+
+ if (align_sm == DONE)
+ AlignLock <= 1'b1;
+
+ if (clr_window_cnt)
+ window_cnt <= offset;
+ else if (window_cnt == 8'hff)
+ window_cnt <= window_cnt;
+ else if (inc_window_cnt)
+ window_cnt <= window_cnt + 1;
+ else if (dec_window_cnt & (window_cnt > 0))
+ window_cnt <= window_cnt - 1;
+ else if (half_window_cnt)
+ window_cnt <= {1'b0,window_cnt[7:1]};
+
+ // limit the number of retrains
+ if (retrain_cnt == 2'b11)
+ retrain_cnt <= retrain_cnt;
+ else if (align_sm == ERR)
+ retrain_cnt <= retrain_cnt + 1;
+
+ case (align_sm)
+
+ INIT:
+ begin
+ chk_req <= 1;
+ align_sm <= EVAL;
+ clr_window_cnt <= 1;
+
+ found_zero <= 0;
+ found_meta <= 0;
+ found_one <= 0;
+ end
+
+ EVAL:
+ if (chk_ok)
+ begin
+ chk_req <= 0;
+ clr_window_cnt <= 0;
+ casex ({found_zero,found_meta,found_one})
+ 3'b000 : // init case
+ begin
+ if (all_zero)
+ begin
+ found_zero <= 1;
+ PhaseUpDown <= 0;
+ PhaseStep <= 1;
+ align_sm <= ADVC;
+ end
+ else if (all_one)
+ begin
+ found_one <= 1;
+ PhaseUpDown <= 1;
+ PhaseStep <= 1;
+ align_sm <= DELY;
+ end
+ else
+ begin
+ found_meta <= 1;
+ PhaseUpDown <= 0;
+ PhaseStep <= 1;
+ align_sm <= ADVC;
+ end
+ end
+
+ 3'b010 : // metasable, delay till get all zero
+ begin
+ if (all_zero)
+ begin
+ found_zero <= 1;
+ PhaseUpDown <= 0;
+ PhaseStep <= 0;
+ align_sm <= INIT;
+ inc_window_cnt <= 0;
+ end
+ else
+ begin
+ PhaseUpDown <= 1;
+ PhaseStep <= 1;
+ align_sm <= DELY;
+ end
+ end
+
+ 3'b110 : // look for all one and compute window
+ begin
+ if (all_one)
+ begin
+ found_one <= 1;
+ PhaseStep <= 1;
+ align_sm <= BACK;
+ if (BIAS_ONE)
+ begin
+ clr_window_cnt <= 1;
+ PhaseUpDown <= 0;
+ end
+ else
+ begin
+ PhaseUpDown <= 1;
+ half_window_cnt <= 1;
+ end
+ end
+ else
+ begin
+ PhaseUpDown <= 0;
+ PhaseStep <= 1;
+ align_sm <= ADVC;
+ inc_window_cnt <= 1;
+ end
+ end
+
+ 3'b100 : // keep advancing to look for metasable phase
+ begin
+ PhaseUpDown <= 0;
+ PhaseStep <= 1;
+ align_sm <= ADVC;
+ if (all_zero == 0) // got either metsable or ones and found the window edge
+ begin
+ found_meta <= 1;
+ inc_window_cnt <= 1;
+ end
+ end
+
+ 3'b001 : // keep delaying to look for metasable phase
+ begin
+ PhaseUpDown <= 1;
+ PhaseStep <= 1;
+ align_sm <= DELY;
+ if (all_one == 0) // got either metsable or ones and found the window edge
+ begin
+ found_meta <= 1;
+ inc_window_cnt <= 1;
+ end
+ end
+
+
+ 3'b011 : // look for all zero and compute window
+ begin
+ if (all_zero)
+ begin
+ found_zero <= 1;
+ PhaseStep <= 0;
+ PhaseUpDown <= 0;
+ align_sm <= INIT;
+
+ if (BIAS_ONE == 0) // if bias to one, go back all the way
+ half_window_cnt <= 1;
+ else
+ inc_window_cnt <= 1;
+ end
+ else
+ begin
+ PhaseUpDown <= 1;
+ PhaseStep <= 1;
+ align_sm <= DELY;
+ inc_window_cnt <= 1;
+ end
+ end
+
+ 3'b111 : // middling the setup hold window
+ begin
+ if (window_cnt > 0)
+ begin
+ PhaseStep <= 1;
+ align_sm <= BACK;
+ dec_window_cnt <= 1;
+ end
+ else
+ align_sm <= DONE;
+
+ end
+
+ 3'b101 : // error case should never happen
+ begin
+ align_sm <= ERR;
+ clr_window_cnt <= 1;
+ found_zero <= 0;
+ found_one <= 0;
+ found_meta <= 0;
+ end
+
+ endcase
+ end
+
+ ADVC:
+ begin
+ inc_window_cnt <= 0;
+ if (PhaseDone == 0)
+ begin
+ PhaseStep <= 0;
+ chk_req <= 1;
+ align_sm <= EVAL;
+ end
+ end
+
+ DELY:
+ begin
+ inc_window_cnt <= 0;
+ if (PhaseDone == 0)
+ begin
+ PhaseStep <= 0;
+ chk_req <= 1;
+ align_sm <= EVAL;
+ end
+ end
+
+
+ BACK:
+ begin
+ half_window_cnt <= 0;
+ dec_window_cnt <= 0;
+ inc_window_cnt <= 0;
+ clr_window_cnt <= 0;
+ if (PhaseDone == 0)
+ begin
+ PhaseStep <= 0;
+ chk_req <= 1;
+ align_sm <= EVAL;
+ end
+ end
+
+ DONE:
+ begin
+ if (chk_ok)
+ chk_req <= 0;
+
+ if (onestep) // manual adjust
+ begin
+ align_sm <= MNUL;
+ PhaseStep <= 1;
+ PhaseUpDown <= onestep_dir;
+ end
+ end
+
+ MNUL:
+ if (PhaseDone == 0)
+ begin
+ PhaseStep <= 0;
+ chk_req <= 1;
+ align_sm <= DONE;
+ end
+
+ ERR:
+ begin
+ clr_window_cnt <= 0;
+ align_sm <= INIT;
+ end
+
+ default:
+ align_sm <= INIT;
+
+ endcase
+ end
+ end
+
+// synchronization for pcie_sw
+always @ (posedge PCLK_Master or posedge rst)
+ begin
+ if (rst)
+ begin
+ pcie_sw_r <= 0;
+ pcie_sw_rr <= 0;
+ pcie_sw_out <= 0;
+ end
+ else
+ begin
+ pcie_sw_r <= pcie_sw_in;
+ pcie_sw_rr <= pcie_sw_r;
+ pcie_sw_out <= pcie_sw_rr;
+ end
+ end
+endmodule
diff --git a/ip_compiler_for_pci_express-library/altpcie_pclk_pll.v b/ip_compiler_for_pci_express-library/altpcie_pclk_pll.v
new file mode 100644
index 0000000000000000000000000000000000000000..bb5e2da0d597af0b67724fb52b5124348604dc2d
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pclk_pll.v
@@ -0,0 +1,389 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pclk_pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 132 02/25/2009 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pclk_pll (
+ inclk0,
+ phasecounterselect,
+ phasestep,
+ phaseupdown,
+ scanclk,
+ c0,
+ c1,
+ locked,
+ phasedone);
+
+ input inclk0;
+ input [3:0] phasecounterselect;
+ input phasestep;
+ input phaseupdown;
+ input scanclk;
+ output c0;
+ output c1;
+ output locked;
+ output phasedone;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [3:0] phasecounterselect;
+ tri0 phasestep;
+ tri0 phaseupdown;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [9:0] sub_wire0;
+ wire sub_wire3;
+ wire sub_wire4;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire locked = sub_wire3;
+ wire phasedone = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+ altpll altpll_component (
+ .phasestep (phasestep),
+ .phaseupdown (phaseupdown),
+ .inclk (sub_wire6),
+ .phasecounterselect (phasecounterselect),
+ .scanclk (scanclk),
+ .clk (sub_wire0),
+ .locked (sub_wire3),
+ .phasedone (sub_wire4),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .pfdena (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.charge_pump_current_bits = 1,
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 10000,
+ altpll_component.intended_device_family = "Stratix IV",
+ altpll_component.loop_filter_c_bits = 0,
+ altpll_component.loop_filter_r_bits = 27,
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altpcie_pclk_pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.m = 12,
+ altpll_component.m_initial = 1,
+ altpll_component.m_ph = 0,
+ altpll_component.n = 1,
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "Left_Right",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_fbout = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_USED",
+ altpll_component.port_phasedone = "PORT_USED",
+ altpll_component.port_phasestep = "PORT_USED",
+ altpll_component.port_phaseupdown = "PORT_USED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_USED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clk6 = "PORT_UNUSED",
+ altpll_component.port_clk7 = "PORT_UNUSED",
+ altpll_component.port_clk8 = "PORT_UNUSED",
+ altpll_component.port_clk9 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.self_reset_on_loss_lock = "OFF",
+ altpll_component.using_fbmimicbidir_port = "OFF",
+ altpll_component.vco_post_scale = 1,
+ altpll_component.width_clock = 10,
+ altpll_component.c0_high = 6,
+ altpll_component.c0_initial = 1,
+ altpll_component.c0_low = 6,
+ altpll_component.c0_mode = "even",
+ altpll_component.c0_ph = 0,
+ altpll_component.c1_high = 6,
+ altpll_component.c1_initial = 1,
+ altpll_component.c1_low = 6,
+ altpll_component.c1_mode = "even",
+ altpll_component.c1_ph = 0,
+ altpll_component.clk0_counter = "c0",
+ altpll_component.clk1_counter = "c1";
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "305.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CHARGE_PUMP_CURRENT_BITS NUMERIC "1"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: LOOP_FILTER_C_BITS NUMERIC "0"
+// Retrieval info: CONSTANT: LOOP_FILTER_R_BITS NUMERIC "27"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: M NUMERIC "6"
+// Retrieval info: CONSTANT: M_INITIAL NUMERIC "1"
+// Retrieval info: CONSTANT: M_PH NUMERIC "0"
+// Retrieval info: CONSTANT: N NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
+// Retrieval info: CONSTANT: VCO_POST_SCALE NUMERIC "2"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
+// Retrieval info: CONSTANT: c0_high NUMERIC "3"
+// Retrieval info: CONSTANT: c0_initial NUMERIC "1"
+// Retrieval info: CONSTANT: c0_low NUMERIC "3"
+// Retrieval info: CONSTANT: c0_mode STRING "even"
+// Retrieval info: CONSTANT: c0_ph NUMERIC "0"
+// Retrieval info: CONSTANT: c1_high NUMERIC "3"
+// Retrieval info: CONSTANT: c1_initial NUMERIC "1"
+// Retrieval info: CONSTANT: c1_low NUMERIC "3"
+// Retrieval info: CONSTANT: c1_mode STRING "even"
+// Retrieval info: CONSTANT: c1_ph NUMERIC "0"
+// Retrieval info: CONSTANT: clk0_counter STRING "c0"
+// Retrieval info: CONSTANT: clk1_counter STRING "c1"
+// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]"
+// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
+// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
+// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
+// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
+// Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pclk_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/ip_compiler_for_pci_express-library/altpcie_phasefifo.v b/ip_compiler_for_pci_express-library/altpcie_phasefifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..3ed5f8ffe62ca88c7f2bb69546751adb84eb6f30
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_phasefifo.v
@@ -0,0 +1,188 @@
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+// synthesis verilog_input_version verilog_2001
+// turn off superfluous verilog processor warnings
+// altera message_level Level1
+// altera message_off 10034 10035 10036 10037 10230 10240 10030
+//-----------------------------------------------------------------------------
+// Title : PCI Express Reference Design Example Application
+// Project : PCI Express MegaCore function
+//-----------------------------------------------------------------------------
+// File : altpcie_phasefifo.v
+// Author : Altera Corporation
+//-----------------------------------------------------------------------------
+// Description :
+// This module allows data to pass between two clock domains where the
+// frequency is identical but with different phase offset
+//-----------------------------------------------------------------------------
+// Copyright (c) 2008 Altera Corporation. All rights reserved. Altera products are
+// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
+// other intellectual property laws.
+//
+// This reference design file, and your use thereof, is subject to and governed by
+// the terms and conditions of the applicable Altera Reference Design License Agreement.
+// By using this reference design file, you indicate your acceptance of such terms and
+// conditions between you and Altera Corporation. In the event that you do not agree with
+// such terms and conditions, you may not use the reference design file. Please promptly
+// destroy any copies you have made.
+//
+// This reference design file being provided on an "as-is" basis and as an accommodation
+// and therefore all warranties, representations or guarantees of any kind
+// (whether express, implied or statutory) including, without limitation, warranties of
+// merchantability, non-infringement, or fitness for a particular purpose, are
+// specifically disclaimed. By making this reference design file available, Altera
+// expressly does not recommend, suggest or require that this reference design file be
+// used in combination with any other product not provided by Altera.
+//-----------------------------------------------------------------------------
+module altpcie_phasefifo (
+ npor,
+ wclk,
+ wdata,
+ rclk,
+ rdata
+ );
+
+ parameter DATA_SIZE = 20;
+ parameter DDR_MODE = 0;
+
+ input npor;
+ input wclk;
+ input[DATA_SIZE - 1:0] wdata;
+ input rclk;
+ output [DATA_SIZE - 1:0] rdata;
+ wire [DATA_SIZE - 1:0] rdata;
+
+ reg rerror;
+
+ reg[3-DDR_MODE:0] waddr;
+ reg[3:0] raddr;
+ reg strobe_r;
+ reg strobe_rr;
+
+ reg npor_rd_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+ reg npor_rd_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+
+ reg npor_wr_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+ reg npor_wr_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
+
+ altsyncram #(
+ .intended_device_family ( "Stratix GX"),
+ .operation_mode ( "DUAL_PORT"),
+ .width_a (DATA_SIZE),
+ .widthad_a (4-DDR_MODE),
+ .numwords_a (2**(4-DDR_MODE)),
+ .width_b (DATA_SIZE / (DDR_MODE + 1)),
+ .widthad_b (4),
+ .numwords_b (16),
+ .lpm_type ( "altsyncram"),
+ .width_byteena_a ( 1),
+ .outdata_reg_b ( "CLOCK1"),
+ .indata_aclr_a ( "NONE"),
+ .wrcontrol_aclr_a ( "NONE"),
+ .address_aclr_a ( "NONE"),
+ .address_reg_b ( "CLOCK1"),
+ .address_aclr_b ( "NONE"),
+ .outdata_aclr_b ( "NONE"),
+ .ram_block_type ( "AUTO")
+
+
+
+ ) altsyncram_component(
+ .wren_a(1'b1),
+ .wren_b(1'b0),
+ .rden_b(1'b1),
+ .data_a(wdata),
+ .data_b({(DATA_SIZE / (DDR_MODE + 1)){1'b1}}),
+ .address_a(waddr),
+ .address_b(raddr),
+ .clock0(wclk),
+ .clock1(rclk),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a({{1'b1}}),
+ .byteena_b({{1'b1}}),
+ .q_a(),
+ .q_b(rdata[(DATA_SIZE / (DDR_MODE + 1))-1:0])
+ );
+
+ // reset synchronizers
+ always @(negedge npor or posedge rclk)
+ begin
+ if (npor == 1'b0)
+ begin
+ npor_rd_r <= 0;
+ npor_rd_rr <= 0;
+ end
+ else
+ begin
+ npor_rd_r <= 1;
+ npor_rd_rr <= npor_rd_r;
+ end
+ end
+
+ always @(negedge npor or posedge wclk)
+ begin
+ if (npor == 1'b0)
+ begin
+ npor_wr_r <= 0;
+ npor_wr_rr <= 0;
+ end
+ else
+ begin
+ npor_wr_r <= 1;
+ npor_wr_rr <= npor_wr_r;
+ end
+ end
+
+
+ //------------------------------------------------------------
+ // Read and Write address pointer keeps incrementing
+ // When write pointer is at "8", bit 3 of the address bus is
+ // propogated to the read side like a strobe.
+ // On the rising edge of this strobe, it should line up with read
+ // address pointer = 0x5 if the two clocks are the exact frequency
+ //----------------------------------------------------------
+
+ always @(negedge npor_rd_rr or posedge rclk)
+ begin
+ if (npor_rd_rr == 1'b0)
+ begin
+ raddr <= 4'h0 ;
+ strobe_r <= 1'b0 ;
+ strobe_rr <= 1'b0 ;
+ rerror <= 1'b0 ;
+ end
+ else
+ begin
+ strobe_r <= DDR_MODE ? waddr[2] : waddr[3] ;
+ strobe_rr <= strobe_r ;
+ raddr <= raddr + 1'b1 ;
+ if (strobe_r == 1'b1 & strobe_rr == 1'b0 & (raddr > 4'h9))
+ begin
+ rerror <= 1'b1 ;
+ end
+ if (rerror == 1'b1)
+ begin
+ $display("PhaseFIFO Frequency mismatch Error!\n");
+ $stop;
+ end
+ end
+ end
+
+ always @(negedge npor_wr_rr or posedge wclk)
+ begin
+ if (npor_wr_rr == 1'b0)
+ begin
+ waddr <= DDR_MODE ? 3'h2 : 4'h4 ;
+ end
+ else
+ begin
+ waddr <= waddr + 1'b1;
+ end
+ end
+endmodule
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_100_125.v b/ip_compiler_for_pci_express-library/altpcie_pll_100_125.v
new file mode 100644
index 0000000000000000000000000000000000000000..8ab1801b412a90c5cfb1c633154dcaa0f0659d43
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_100_125.v
@@ -0,0 +1,229 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_100_125.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 175 10/25/2005 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_100_125 (
+ areset,
+ inclk0,
+ c0,
+ locked);
+
+ input areset;
+ input inclk0;
+ output c0;
+ output locked;
+
+ wire [5:0] sub_wire0;
+ wire sub_wire2;
+ wire [0:0] sub_wire3 = 1'h0;
+ wire [0:0] sub_wire5 = 1'h1;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire locked = sub_wire2;
+ wire [5:0] sub_wire4 = {sub_wire3, sub_wire3, sub_wire3, sub_wire3, sub_wire3, sub_wire5};
+ wire sub_wire6 = inclk0;
+ wire [1:0] sub_wire7 = {sub_wire3, sub_wire6};
+ wire [3:0] sub_wire8 = {sub_wire3, sub_wire3, sub_wire3, sub_wire3};
+
+ altpll altpll_component (
+ .clkena (sub_wire4),
+ .inclk (sub_wire7),
+ .extclkena (sub_wire8),
+ .areset (areset),
+ .clk (sub_wire0),
+ .locked (sub_wire2)
+ // synopsys translate_off
+ ,
+ .scanclk (),
+ .pllena (),
+ .sclkout1 (),
+ .sclkout0 (),
+ .fbin (),
+ .scandone (),
+ .clkloss (),
+ .extclk (),
+ .clkswitch (),
+ .pfdena (),
+ .scanaclr (),
+ .clkbad (),
+ .scandata (),
+ .enable1 (),
+ .scandataout (),
+ .enable0 (),
+ .scanwrite (),
+ .activeclock (),
+ .scanread ()
+ // synopsys translate_on
+ );
+ defparam
+ altpll_component.bandwidth = 500000,
+ altpll_component.bandwidth_type = "CUSTOM",
+ altpll_component.clk0_divide_by = 4,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 5,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 10000,
+ altpll_component.intended_device_family = "Stratix GX",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "ENHANCED",
+ altpll_component.spread_frequency = 0,
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
+// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_waveforms.html FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_wave*.jpg FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_100_250.v b/ip_compiler_for_pci_express-library/altpcie_pll_100_250.v
new file mode 100644
index 0000000000000000000000000000000000000000..c24e42dd2db5793c0b5dec954b51be318e0c5a96
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_100_250.v
@@ -0,0 +1,219 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_100_250.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 175 10/25/2005 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_100_250 (
+ areset,
+ inclk0,
+ c0);
+
+ input areset;
+ input inclk0;
+ output c0;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire2 = 1'h0;
+ wire [0:0] sub_wire4 = 1'h1;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire [5:0] sub_wire3 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire4};
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire2, sub_wire5};
+ wire [3:0] sub_wire7 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2};
+
+ altpll altpll_component (
+ .clkena (sub_wire3),
+ .inclk (sub_wire6),
+ .extclkena (sub_wire7),
+ .areset (areset),
+ .clk (sub_wire0)
+ // synopsys translate_off
+ ,
+ .scanclk (),
+ .pllena (),
+ .sclkout1 (),
+ .sclkout0 (),
+ .fbin (),
+ .scandone (),
+ .clkloss (),
+ .extclk (),
+ .clkswitch (),
+ .pfdena (),
+ .scanaclr (),
+ .clkbad (),
+ .scandata (),
+ .enable1 (),
+ .scandataout (),
+ .enable0 (),
+ .scanwrite (),
+ .locked (),
+ .activeclock (),
+ .scanread ()
+ // synopsys translate_on
+ );
+ defparam
+ altpll_component.bandwidth = 500000,
+ altpll_component.bandwidth_type = "CUSTOM",
+ altpll_component.clk0_divide_by = 2,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 5,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 10000,
+ altpll_component.intended_device_family = "Stratix GX",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "ENHANCED",
+ altpll_component.spread_frequency = 0;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "250.000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
+// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_waveforms.html FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_wave*.jpg FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_125_250.v b/ip_compiler_for_pci_express-library/altpcie_pll_125_250.v
new file mode 100644
index 0000000000000000000000000000000000000000..4525f45fde4a9d593a12da8e69b665d769a220aa
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_125_250.v
@@ -0,0 +1,218 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_125_250.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Internal Build 139 08/21/2005 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_125_250 (
+ areset,
+ inclk0,
+ c0);
+
+ input areset;
+ input inclk0;
+ output c0;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire2 = 1'h0;
+ wire [0:0] sub_wire4 = 1'h1;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire [5:0] sub_wire3 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire4};
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire2, sub_wire5};
+ wire [3:0] sub_wire7 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2};
+
+ altpll altpll_component (
+ .clkena (sub_wire3),
+ .inclk (sub_wire6),
+ .extclkena (sub_wire7),
+ .areset (areset),
+ .clk (sub_wire0)
+ // synopsys translate_off
+ ,
+ .scanclk (),
+ .pllena (),
+ .sclkout1 (),
+ .sclkout0 (),
+ .fbin (),
+ .scandone (),
+ .clkloss (),
+ .extclk (),
+ .clkswitch (),
+ .pfdena (),
+ .scanaclr (),
+ .clkbad (),
+ .scandata (),
+ .enable1 (),
+ .scandataout (),
+ .enable0 (),
+ .scanwrite (),
+ .locked (),
+ .activeclock (),
+ .scanread ()
+ // synopsys translate_on
+ );
+ defparam
+ altpll_component.bandwidth = 500000,
+ altpll_component.bandwidth_type = "CUSTOM",
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 2,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 8000,
+ altpll_component.intended_device_family = "Stratix GX",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "ENHANCED",
+ altpll_component.spread_frequency = 0;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "250.000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
+// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_waveforms.html FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_125_250_wave*.jpg FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v b/ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v
new file mode 100644
index 0000000000000000000000000000000000000000..7bc834e4b871334ba65e7a23e09b507113df92de
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v
@@ -0,0 +1,219 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_15625_125.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 174 10/19/2005 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_15625_125 (
+ areset,
+ inclk0,
+ c0);
+
+ input areset;
+ input inclk0;
+ output c0;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire2 = 1'h0;
+ wire [0:0] sub_wire4 = 1'h1;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire [5:0] sub_wire3 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire4};
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire2, sub_wire5};
+ wire [3:0] sub_wire7 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2};
+
+ altpll altpll_component (
+ .clkena (sub_wire3),
+ .inclk (sub_wire6),
+ .extclkena (sub_wire7),
+ .areset (areset),
+ .clk (sub_wire0)
+ // synopsys translate_off
+ ,
+ .scanclk (),
+ .pllena (),
+ .sclkout1 (),
+ .sclkout0 (),
+ .fbin (),
+ .scandone (),
+ .clkloss (),
+ .extclk (),
+ .clkswitch (),
+ .pfdena (),
+ .scanaclr (),
+ .clkbad (),
+ .scandata (),
+ .enable1 (),
+ .scandataout (),
+ .enable0 (),
+ .scanwrite (),
+ .locked (),
+ .activeclock (),
+ .scanread ()
+ // synopsys translate_on
+ );
+ defparam
+ altpll_component.bandwidth = 500000,
+ altpll_component.bandwidth_type = "CUSTOM",
+ altpll_component.clk0_divide_by = 5,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 4,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 6400,
+ altpll_component.intended_device_family = "Stratix GX",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "ENHANCED",
+ altpll_component.spread_frequency = 0;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "156.250"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "6400"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
+// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125_waveforms.html FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125_wave*.jpg FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_250_100.v b/ip_compiler_for_pci_express-library/altpcie_pll_250_100.v
new file mode 100644
index 0000000000000000000000000000000000000000..cfc7f555e57d5cadd02376a526056c729ae95788
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_250_100.v
@@ -0,0 +1,227 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_250_100.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Internal Build 205 12/28/2005 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_250_100 (
+ areset,
+ inclk0,
+ c0);
+
+ input areset;
+ input inclk0;
+ output c0;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire2 = 1'h0;
+ wire [0:0] sub_wire4 = 1'h1;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire [5:0] sub_wire3 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire4};
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire2, sub_wire5};
+ wire [3:0] sub_wire7 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2};
+
+ altpll altpll_component (
+ .clkena (sub_wire3),
+ .inclk (sub_wire6),
+ .extclkena (sub_wire7),
+ .areset (areset),
+ .clk (sub_wire0)
+ // synopsys translate_off
+ ,
+ .activeclock (),
+ .clkbad (),
+ .clkloss (),
+ .clkswitch (),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .fbin (),
+ .locked (),
+ .pfdena (),
+ .pllena (),
+ .scanaclr (),
+ .scanclk (),
+ .scandata (),
+ .scandataout (),
+ .scandone (),
+ .scanread (),
+ .scanwrite (),
+ .sclkout0 (),
+ .sclkout1 ()
+ // synopsys translate_on
+ );
+ defparam
+ altpll_component.bandwidth = 500000,
+ altpll_component.bandwidth_type = "CUSTOM",
+ altpll_component.clk0_divide_by = 5,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 2,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 4000,
+ altpll_component.intended_device_family = "Stratix GX",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "ENHANCED",
+ altpll_component.spread_frequency = 0;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "250.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "4000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
+// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_waveforms.html FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_250_wave*.jpg FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_250_100.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_250_100.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_250_100.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_250_100.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_250_100_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_250_100_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_250_100_waveforms.html FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_250_100_wave*.jpg FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy0.v b/ip_compiler_for_pci_express-library/altpcie_pll_phy0.v
new file mode 100644
index 0000000000000000000000000000000000000000..56243ff7047c4e89956a20d916a2924da56b0875
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_phy0.v
@@ -0,0 +1,283 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_phy0.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 176 10/26/2005 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_phy0 (
+ areset,
+ inclk0,
+ c0,
+ c1,
+ c2,
+ locked);
+
+ input areset;
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+ output locked;
+
+ wire [5:0] sub_wire0;
+ wire sub_wire4;
+ wire [0:0] sub_wire5 = 1'h1;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire c2 = sub_wire3;
+ wire locked = sub_wire4;
+ wire [5:0] sub_wire6 = {sub_wire7, sub_wire7, sub_wire7, sub_wire5, sub_wire5, sub_wire5};
+ wire sub_wire8 = inclk0;
+ wire [1:0] sub_wire9 = {sub_wire7, sub_wire8};
+ wire [3:0] sub_wire10 = {sub_wire7, sub_wire7, sub_wire7, sub_wire7};
+
+ altpll altpll_component (
+ .clkena (sub_wire6),
+ .inclk (sub_wire9),
+ .extclkena (sub_wire10),
+ .areset (areset),
+ .clk (sub_wire0),
+ .locked (sub_wire4)
+ // synopsys translate_off
+ ,
+ .scanclk (),
+ .pllena (),
+ .sclkout1 (),
+ .sclkout0 (),
+ .fbin (),
+ .scandone (),
+ .clkloss (),
+ .extclk (),
+ .clkswitch (),
+ .pfdena (),
+ .scanaclr (),
+ .clkbad (),
+ .scandata (),
+ .enable1 (),
+ .scandataout (),
+ .enable0 (),
+ .scanwrite (),
+ .activeclock (),
+ .scanread ()
+ // synopsys translate_on
+ );
+ defparam
+ altpll_component.bandwidth = 500000,
+ altpll_component.bandwidth_type = "CUSTOM",
+ altpll_component.clk0_divide_by = 4,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 5,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 16,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 5,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk2_divide_by = 8,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 5,
+ altpll_component.clk2_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 10000,
+ altpll_component.intended_device_family = "Stratix GX",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "ENHANCED",
+ altpll_component.spread_frequency = 0,
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "31.250"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.500"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "16"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "8"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
+// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @clkena 0 0 1 1 VCC 0 0 0 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 2 VCC 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy0.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy0.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy0.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy0.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy0_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy0_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy0_waveforms.html FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy0_wave*.jpg FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v b/ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v
new file mode 100644
index 0000000000000000000000000000000000000000..5d353164119190b868164f1bc2fa25ff6b8521e7
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v
@@ -0,0 +1,375 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_phy1_62p5.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_phy1_62p5 (
+ areset,
+ inclk0,
+ c0,
+ c1,
+ c2,
+ locked);
+
+ input areset;
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+ output locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [5:0] sub_wire0;
+ wire sub_wire4;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire c2 = sub_wire3;
+ wire locked = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+ altpll altpll_component (
+ .inclk (sub_wire6),
+ .areset (areset),
+ .clk (sub_wire0),
+ .locked (sub_wire4),
+ .activeclock (),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 1,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 1,
+ altpll_component.clk1_phase_shift = "-3200",
+ altpll_component.clk2_divide_by = 2,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 1,
+ altpll_component.clk2_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.gate_lock_signal = "NO",
+ altpll_component.inclk0_input_frequency = 8000,
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_USED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_USED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "62.500000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "375.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.20000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_pll_phy1_62p5.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3200"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5_wave*.jpg FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.ppf TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy2.v b/ip_compiler_for_pci_express-library/altpcie_pll_phy2.v
new file mode 100644
index 0000000000000000000000000000000000000000..fc0183840fea38dfaaae75ae75ecf2b68effb79e
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_phy2.v
@@ -0,0 +1,383 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_phy2.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_phy2 (
+ areset,
+ inclk0,
+ c0,
+ c1,
+ c2,
+ locked);
+
+ input areset;
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+ output locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [5:0] sub_wire0;
+ wire sub_wire4;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire c2 = sub_wire3;
+ wire locked = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+ altpll altpll_component (
+ .inclk (sub_wire6),
+ .areset (areset),
+ .clk (sub_wire0),
+ .locked (sub_wire4),
+ .activeclock (),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth = 500000,
+ altpll_component.bandwidth_type = "CUSTOM",
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 4,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 1,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk2_divide_by = 2,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 1,
+ altpll_component.clk2_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.gate_lock_signal = "NO",
+ altpll_component.inclk0_input_frequency = 8000,
+ altpll_component.intended_device_family = "Stratix II GX",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "Fast",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_USED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_USED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_enable0 = "PORT_UNUSED",
+ altpll_component.port_enable1 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.port_sclkout0 = "PORT_UNUSED",
+ altpll_component.port_sclkout1 = "PORT_UNUSED",
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "31.250000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "62.500000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "250.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "31.25000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_pll_phy2.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "Fast"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2_wave*.jpg FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy2.ppf TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v b/ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v
new file mode 100644
index 0000000000000000000000000000000000000000..31e7f242b9658543fe84caf37f4ffa8239cd7cf1
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v
@@ -0,0 +1,373 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_phy3_62p5.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_phy3_62p5 (
+ areset,
+ inclk0,
+ c0,
+ c1,
+ c2,
+ locked);
+
+ input areset;
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+ output locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [5:0] sub_wire0;
+ wire sub_wire4;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire c2 = sub_wire3;
+ wire locked = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+ altpll altpll_component (
+ .inclk (sub_wire6),
+ .areset (areset),
+ .clk (sub_wire0),
+ .locked (sub_wire4),
+ .activeclock (),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.clk0_phase_shift = "2000",
+ altpll_component.clk1_divide_by = 1,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 2,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk2_divide_by = 2,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 1,
+ altpll_component.clk2_phase_shift = "2000",
+ altpll_component.gate_lock_signal = "NO",
+ altpll_component.inclk0_input_frequency = 8000,
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NO_COMPENSATION",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_USED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_USED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "250.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "62.500000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "375.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "250.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "2.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "2.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_pll_phy3_62p5.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "2000"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "2000"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5_wave*.jpg FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy3_62p5.ppf TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v b/ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v
new file mode 100644
index 0000000000000000000000000000000000000000..544ddb3d11670d26fb94776482f03c0892bb3a17
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v
@@ -0,0 +1,373 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_phy4_62p5.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_phy4_62p5 (
+ areset,
+ inclk0,
+ c0,
+ c1,
+ c2,
+ locked);
+
+ input areset;
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+ output locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [5:0] sub_wire0;
+ wire sub_wire4;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire c2 = sub_wire3;
+ wire locked = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+ altpll altpll_component (
+ .inclk (sub_wire6),
+ .areset (areset),
+ .clk (sub_wire0),
+ .locked (sub_wire4),
+ .activeclock (),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 2,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.clk0_phase_shift = "1500",
+ altpll_component.clk1_divide_by = 1,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 1,
+ altpll_component.clk1_phase_shift = "1500",
+ altpll_component.clk2_divide_by = 4,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 1,
+ altpll_component.clk2_phase_shift = "1500",
+ altpll_component.gate_lock_signal = "NO",
+ altpll_component.inclk0_input_frequency = 4000,
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NO_COMPENSATION",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_USED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_USED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "250.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "62.500000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "250.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "250.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "1.50000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "1.50000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "1.50000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_pll_phy4_62p5.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "1500"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "1500"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "1500"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "4000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v b/ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v
new file mode 100644
index 0000000000000000000000000000000000000000..bac749542256cceef5c936c80f694c97db20e053
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v
@@ -0,0 +1,375 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcie_pll_phy5_62p5.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.1 Internal Build 180 08/06/2009 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2009 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_pll_phy5_62p5 (
+ areset,
+ inclk0,
+ c0,
+ c1,
+ c2,
+ locked);
+
+ input areset;
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+ output locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [5:0] sub_wire0;
+ wire sub_wire4;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire c2 = sub_wire3;
+ wire locked = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+ altpll altpll_component (
+ .inclk (sub_wire6),
+ .areset (areset),
+ .clk (sub_wire0),
+ .locked (sub_wire4),
+ .activeclock (),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.clk0_phase_shift = "1875",
+ altpll_component.clk1_divide_by = 1,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 2,
+ altpll_component.clk1_phase_shift = "-125",
+ altpll_component.clk2_divide_by = 2,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 1,
+ altpll_component.clk2_phase_shift = "1875",
+ altpll_component.gate_lock_signal = "NO",
+ altpll_component.inclk0_input_frequency = 8000,
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NO_COMPENSATION",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_USED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_USED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "250.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "62.500000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "375.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "250.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "1.87500000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-0.12500000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "1.87500000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_pll_phy5_62p5.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "1875"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-125"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "1875"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy5_62p5.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy5_62p5.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy5_62p5.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy5_62p5.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy5_62p5_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy5_62p5_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy5_62p5_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy5_62p5_wave*.jpg FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy5_62p5.ppf TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v b/ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..22e2ce79cdcee6db81e0bded9a53ad1fb767b63d
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v
@@ -0,0 +1,544 @@
+// megafunction wizard: %ALTGX_RECONFIG%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt_c3gxb_reconfig
+
+// ============================================================
+// File Name: altpcie_reconfig_3cgx.v
+// Megafunction Name(s):
+// alt_c3gxb_reconfig
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.0 Internal Build 134 03/09/2011 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt_c3gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=4 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=5 RECONFIG_TOGXB_WIDTH=4 busy offset_cancellation_reset reconfig_clk reconfig_fromgxb reconfig_togxb
+//VERSION_BEGIN 11.0 cbx_alt_c3gxb_reconfig 2011:03:09:22:37:51:SJ cbx_alt_cal 2011:03:09:22:37:51:SJ cbx_alt_dprio 2011:03:09:22:37:51:SJ cbx_altsyncram 2011:03:09:22:37:54:SJ cbx_cycloneii 2011:03:09:22:37:55:SJ cbx_lpm_add_sub 2011:03:09:22:37:56:SJ cbx_lpm_compare 2011:03:09:22:37:56:SJ cbx_lpm_counter 2011:03:09:22:37:56:SJ cbx_lpm_decode 2011:03:09:22:37:56:SJ cbx_lpm_mux 2011:03:09:22:37:56:SJ cbx_lpm_shiftreg 2011:03:09:22:37:56:SJ cbx_mgl 2011:03:09:22:48:24:SJ cbx_stratix 2011:03:09:22:37:58:SJ cbx_stratixii 2011:03:09:22:37:58:SJ cbx_stratixiii 2011:03:09:22:37:58:SJ cbx_stratixv 2011:03:09:22:37:58:SJ cbx_util_mgl 2011:03:09:22:37:57:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+//alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
+//VERSION_BEGIN 11.0 cbx_alt_dprio 2011:03:09:22:37:51:SJ cbx_cycloneii 2011:03:09:22:37:55:SJ cbx_lpm_add_sub 2011:03:09:22:37:56:SJ cbx_lpm_compare 2011:03:09:22:37:56:SJ cbx_lpm_counter 2011:03:09:22:37:56:SJ cbx_lpm_decode 2011:03:09:22:37:56:SJ cbx_lpm_shiftreg 2011:03:09:22:37:56:SJ cbx_mgl 2011:03:09:22:48:24:SJ cbx_stratix 2011:03:09:22:37:58:SJ cbx_stratixii 2011:03:09:22:37:58:SJ VERSION_END
+
+//synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON"} *)
+module altpcie_reconfig_3cgx_alt_dprio_v5k
+ (
+ address,
+ busy,
+ datain,
+ dataout,
+ dpclk,
+ dpriodisable,
+ dprioin,
+ dprioload,
+ dprioout,
+ quad_address,
+ rden,
+ reset,
+ wren,
+ wren_data) /* synthesis synthesis_clearbox=2 */;
+ input [15:0] address;
+ output busy;
+ input [15:0] datain;
+ output [15:0] dataout;
+ input dpclk;
+ output dpriodisable;
+ output dprioin;
+ output dprioload;
+ input dprioout;
+ input [8:0] quad_address;
+ input rden;
+ input reset;
+ input wren;
+ input wren_data;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [15:0] datain;
+ tri0 rden;
+ tri0 reset;
+ tri0 wren;
+ tri0 wren_data;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] addr_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] in_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] rd_out_data_shift_reg;
+ wire [2:0] wire_startup_cntr_d;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] startup_cntr;
+ wire [2:0] wire_startup_cntr_ena;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] state_mc_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] wr_out_data_shift_reg;
+ wire wire_pre_amble_cmpr_aeb;
+ wire wire_pre_amble_cmpr_agb;
+ wire wire_rd_data_output_cmpr_ageb;
+ wire wire_rd_data_output_cmpr_alb;
+ wire wire_state_mc_cmpr_aeb;
+ wire [5:0] wire_state_mc_counter_q;
+ wire [7:0] wire_state_mc_decode_eq;
+ wire wire_dprioin_mux_dataout;
+ wire busy_state;
+ wire idle_state;
+ wire rd_addr_done;
+ wire rd_addr_state;
+ wire rd_data_done;
+ wire rd_data_input_state;
+ wire rd_data_output_state;
+ wire rd_data_state;
+ wire rdinc;
+ wire read_state;
+ wire s0_to_0;
+ wire s0_to_1;
+ wire s1_to_0;
+ wire s1_to_1;
+ wire s2_to_0;
+ wire s2_to_1;
+ wire startup_done;
+ wire startup_idle;
+ wire wr_addr_done;
+ wire wr_addr_state;
+ wire wr_data_done;
+ wire wr_data_state;
+ wire write_state;
+
+ // synopsys translate_off
+ initial
+ addr_shift_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) addr_shift_reg <= 32'b0;
+ else
+ if (wire_pre_amble_cmpr_aeb == 1'b1) addr_shift_reg <= {{2{{2{1'b0}}}}, 1'b0, quad_address[8:0], 2'b10, address};
+ else addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
+ // synopsys translate_off
+ initial
+ in_data_shift_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) in_data_shift_reg <= 16'b0;
+ else if (rd_data_input_state == 1'b1) in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
+ // synopsys translate_off
+ initial
+ rd_out_data_shift_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) rd_out_data_shift_reg <= 16'b0;
+ else
+ if (wire_pre_amble_cmpr_aeb == 1'b1) rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, 1'b0, quad_address, 2'b10};
+ else rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
+ // synopsys translate_off
+ initial
+ startup_cntr[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk)
+ if (wire_startup_cntr_ena[0:0] == 1'b1)
+ if (reset == 1'b1) startup_cntr[0:0] <= 1'b0;
+ else startup_cntr[0:0] <= wire_startup_cntr_d[0:0];
+ // synopsys translate_off
+ initial
+ startup_cntr[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk)
+ if (wire_startup_cntr_ena[1:1] == 1'b1)
+ if (reset == 1'b1) startup_cntr[1:1] <= 1'b0;
+ else startup_cntr[1:1] <= wire_startup_cntr_d[1:1];
+ // synopsys translate_off
+ initial
+ startup_cntr[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk)
+ if (wire_startup_cntr_ena[2:2] == 1'b1)
+ if (reset == 1'b1) startup_cntr[2:2] <= 1'b0;
+ else startup_cntr[2:2] <= wire_startup_cntr_d[2:2];
+ assign
+ wire_startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
+ assign
+ wire_startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
+ // synopsys translate_off
+ initial
+ state_mc_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) state_mc_reg <= 3'b0;
+ else state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
+ // synopsys translate_off
+ initial
+ wr_out_data_shift_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) wr_out_data_shift_reg <= 32'b0;
+ else
+ if (wire_pre_amble_cmpr_aeb == 1'b1) wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, 1'b0, quad_address[8:0], 2'b10, datain};
+ else wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
+ lpm_compare pre_amble_cmpr
+ (
+ .aeb(wire_pre_amble_cmpr_aeb),
+ .agb(wire_pre_amble_cmpr_agb),
+ .ageb(),
+ .alb(),
+ .aleb(),
+ .aneb(),
+ .dataa(wire_state_mc_counter_q),
+ .datab(6'b011111)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ pre_amble_cmpr.lpm_width = 6,
+ pre_amble_cmpr.lpm_type = "lpm_compare";
+ lpm_compare rd_data_output_cmpr
+ (
+ .aeb(),
+ .agb(),
+ .ageb(wire_rd_data_output_cmpr_ageb),
+ .alb(wire_rd_data_output_cmpr_alb),
+ .aleb(),
+ .aneb(),
+ .dataa(wire_state_mc_counter_q),
+ .datab(6'b110000)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rd_data_output_cmpr.lpm_width = 6,
+ rd_data_output_cmpr.lpm_type = "lpm_compare";
+ lpm_compare state_mc_cmpr
+ (
+ .aeb(wire_state_mc_cmpr_aeb),
+ .agb(),
+ .ageb(),
+ .alb(),
+ .aleb(),
+ .aneb(),
+ .dataa(wire_state_mc_counter_q),
+ .datab({6{1'b1}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ state_mc_cmpr.lpm_width = 6,
+ state_mc_cmpr.lpm_type = "lpm_compare";
+ lpm_counter state_mc_counter
+ (
+ .clock(dpclk),
+ .cnt_en((write_state | read_state)),
+ .cout(),
+ .eq(),
+ .q(wire_state_mc_counter_q),
+ .sclr(reset)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .data({6{1'b0}}),
+ .sload(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ state_mc_counter.lpm_port_updown = "PORT_UNUSED",
+ state_mc_counter.lpm_width = 6,
+ state_mc_counter.lpm_type = "lpm_counter";
+ lpm_decode state_mc_decode
+ (
+ .data(state_mc_reg),
+ .eq(wire_state_mc_decode_eq)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0),
+ .enable(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ state_mc_decode.lpm_decodes = 8,
+ state_mc_decode.lpm_width = 3,
+ state_mc_decode.lpm_type = "lpm_decode";
+ or(wire_dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
+ assign
+ busy = busy_state,
+ busy_state = (write_state | read_state),
+ dataout = in_data_shift_reg,
+ dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
+ dprioin = wire_dprioin_mux_dataout,
+ dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
+ idle_state = wire_state_mc_decode_eq[0],
+ rd_addr_done = (rd_addr_state & wire_state_mc_cmpr_aeb),
+ rd_addr_state = (wire_state_mc_decode_eq[5] & startup_done),
+ rd_data_done = (rd_data_state & wire_state_mc_cmpr_aeb),
+ rd_data_input_state = (wire_rd_data_output_cmpr_ageb & rd_data_state),
+ rd_data_output_state = (wire_rd_data_output_cmpr_alb & rd_data_state),
+ rd_data_state = (wire_state_mc_decode_eq[7] & startup_done),
+ rdinc = 1'b0,
+ read_state = (rd_addr_state | rd_data_state),
+ s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
+ s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
+ s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
+ s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
+ startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
+ startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
+ wr_addr_done = (wr_addr_state & wire_state_mc_cmpr_aeb),
+ wr_addr_state = (wire_state_mc_decode_eq[1] & startup_done),
+ wr_data_done = (wr_data_state & wire_state_mc_cmpr_aeb),
+ wr_data_state = (wire_state_mc_decode_eq[3] & startup_done),
+ write_state = (wr_addr_state | wr_data_state);
+endmodule //altpcie_reconfig_3cgx_alt_dprio_v5k
+
+//synthesis_resources = alt_cal_c3gxb 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 114
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0"} *)
+module altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp
+ (
+ busy,
+ offset_cancellation_reset,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb) /* synthesis synthesis_clearbox=2 */;
+ output busy;
+ input offset_cancellation_reset;
+ input reconfig_clk;
+ input [4:0] reconfig_fromgxb;
+ output [3:0] reconfig_togxb;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 offset_cancellation_reset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire wire_calibration_c3gxb_busy;
+ wire [15:0] wire_calibration_c3gxb_dprio_addr;
+ wire [15:0] wire_calibration_c3gxb_dprio_dataout;
+ wire wire_calibration_c3gxb_dprio_rden;
+ wire wire_calibration_c3gxb_dprio_wren;
+ wire [8:0] wire_calibration_c3gxb_quad_addr;
+ wire wire_calibration_c3gxb_retain_addr;
+ wire wire_dprio_busy;
+ wire [15:0] wire_dprio_dataout;
+ wire wire_dprio_dpriodisable;
+ wire wire_dprio_dprioin;
+ wire wire_dprio_dprioload;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
+ reg [11:0] address_pres_reg;
+ wire cal_busy;
+ wire [0:0] cal_dprioout_wire;
+ wire [3:0] cal_testbuses;
+ wire [2:0] channel_address;
+ wire [15:0] dprio_address;
+ wire [8:0] quad_address;
+ wire reconfig_reset_all;
+
+ alt_cal_c3gxb calibration_c3gxb
+ (
+ .busy(wire_calibration_c3gxb_busy),
+ .cal_error(),
+ .clock(reconfig_clk),
+ .dprio_addr(wire_calibration_c3gxb_dprio_addr),
+ .dprio_busy(wire_dprio_busy),
+ .dprio_datain(wire_dprio_dataout),
+ .dprio_dataout(wire_calibration_c3gxb_dprio_dataout),
+ .dprio_rden(wire_calibration_c3gxb_dprio_rden),
+ .dprio_wren(wire_calibration_c3gxb_dprio_wren),
+ .quad_addr(wire_calibration_c3gxb_quad_addr),
+ .remap_addr(address_pres_reg),
+ .reset((offset_cancellation_reset | reconfig_reset_all)),
+ .retain_addr(wire_calibration_c3gxb_retain_addr),
+ .testbuses(cal_testbuses)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .start(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ calibration_c3gxb.channel_address_width = 2,
+ calibration_c3gxb.number_of_channels = 4,
+ calibration_c3gxb.sim_model_mode = "FALSE",
+ calibration_c3gxb.lpm_type = "alt_cal_c3gxb";
+ altpcie_reconfig_3cgx_alt_dprio_v5k dprio
+ (
+ .address(({16{wire_calibration_c3gxb_busy}} & dprio_address)),
+ .busy(wire_dprio_busy),
+ .datain(({16{wire_calibration_c3gxb_busy}} & wire_calibration_c3gxb_dprio_dataout)),
+ .dataout(wire_dprio_dataout),
+ .dpclk(reconfig_clk),
+ .dpriodisable(wire_dprio_dpriodisable),
+ .dprioin(wire_dprio_dprioin),
+ .dprioload(wire_dprio_dprioload),
+ .dprioout(cal_dprioout_wire),
+ .quad_address(address_pres_reg[11:3]),
+ .rden((wire_calibration_c3gxb_busy & wire_calibration_c3gxb_dprio_rden)),
+ .reset(reconfig_reset_all),
+ .wren((wire_calibration_c3gxb_busy & wire_calibration_c3gxb_dprio_wren)),
+ .wren_data(wire_calibration_c3gxb_retain_addr));
+ // synopsys translate_off
+ initial
+ address_pres_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) address_pres_reg <= 12'b0;
+ else address_pres_reg <= {quad_address, channel_address};
+ assign
+ busy = cal_busy,
+ cal_busy = wire_calibration_c3gxb_busy,
+ cal_dprioout_wire = {reconfig_fromgxb[0]},
+ cal_testbuses = {reconfig_fromgxb[4:1]},
+ channel_address = wire_calibration_c3gxb_dprio_addr[14:12],
+ dprio_address = {wire_calibration_c3gxb_dprio_addr[15], address_pres_reg[2:0], wire_calibration_c3gxb_dprio_addr[11:0]},
+ quad_address = wire_calibration_c3gxb_quad_addr,
+ reconfig_reset_all = 1'b0,
+ reconfig_togxb = {wire_calibration_c3gxb_busy, wire_dprio_dprioload, wire_dprio_dpriodisable, wire_dprio_dprioin};
+endmodule //altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_reconfig_3cgx (
+ offset_cancellation_reset,
+ reconfig_clk,
+ reconfig_fromgxb,
+ busy,
+ reconfig_togxb)/* synthesis synthesis_clearbox = 2 */;
+
+ input offset_cancellation_reset;
+ input reconfig_clk;
+ input [4:0] reconfig_fromgxb;
+ output busy;
+ output [3:0] reconfig_togxb;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 offset_cancellation_reset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [3:0] sub_wire0;
+ wire sub_wire1;
+ wire [3:0] reconfig_togxb = sub_wire0[3:0];
+ wire busy = sub_wire1;
+
+ altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp_component (
+ .reconfig_clk (reconfig_clk),
+ .offset_cancellation_reset (offset_cancellation_reset),
+ .reconfig_fromgxb (reconfig_fromgxb),
+ .reconfig_togxb (sub_wire0),
+ .busy (sub_wire1))/* synthesis synthesis_clearbox=2
+ clearbox_macroname = alt_c3gxb_reconfig
+ clearbox_defparam = "cbx_blackbox_list=-lpm_mux;intended_device_family=Cyclone IV GX;number_of_channels=4;number_of_reconfig_ports=1;enable_buf_cal=true;reconfig_fromgxb_width=5;reconfig_togxb_width=4;" */;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADCE NUMERIC "0"
+// Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
+// Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: PRIVATE: PMA NUMERIC "0"
+// Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
+// Retrieval info: CONSTANT: enable_buf_cal STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "5"
+// Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
+// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 INPUT NODEFVAL "reconfig_fromgxb[4..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_fromgxb 0 0 5 0 reconfig_fromgxb 0 0 5 0
+// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+// Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx_bb.v TRUE
diff --git a/ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v b/ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..13b1b950c5a954737f8cfdb57323a68676fa43aa
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v
@@ -0,0 +1,1663 @@
+// megafunction wizard: %ALTGX_RECONFIG%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt2gxb_reconfig
+
+// ============================================================
+// File Name: altpcie_reconfig_4sgx.v
+// Megafunction Name(s):
+// alt2gxb_reconfig
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.0 Internal Build 134 03/09/2011 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt2gxb_reconfig BASE_PORT_WIDTH=1 CBX_AUTO_BLACKBOX="ALL" CHANNEL_ADDRESS_WIDTH=3 DEVICE_FAMILY="Stratix IV" ENABLE_BUF_CAL="TRUE" ENABLE_CHL_ADDR_FOR_ANALOG_CTRL="TRUE" NUMBER_OF_CHANNELS=8 NUMBER_OF_RECONFIG_PORTS=2 READ_BASE_PORT_WIDTH=1 RECONFIG_FROMGXB_WIDTH=34 RECONFIG_TOGXB_WIDTH=4 RX_EQDCGAIN_PORT_WIDTH=3 TX_PREEMP_PORT_WIDTH=5 busy data_valid logical_channel_address offset_cancellation_reset read reconfig_clk reconfig_fromgxb reconfig_mode_sel reconfig_togxb rx_eqctrl rx_eqctrl_out rx_eqdcgain rx_eqdcgain_out tx_preemp_0t tx_preemp_0t_out tx_preemp_1t tx_preemp_1t_out tx_preemp_2t tx_preemp_2t_out tx_vodctrl tx_vodctrl_out write_all
+//VERSION_BEGIN 11.0 cbx_alt2gxb_reconfig 2011:03:09:22:37:51:SJ cbx_alt_cal 2011:03:09:22:37:51:SJ cbx_alt_dprio 2011:03:09:22:37:51:SJ cbx_altsyncram 2011:03:09:22:37:54:SJ cbx_cycloneii 2011:03:09:22:37:55:SJ cbx_lpm_add_sub 2011:03:09:22:37:56:SJ cbx_lpm_compare 2011:03:09:22:37:56:SJ cbx_lpm_counter 2011:03:09:22:37:56:SJ cbx_lpm_decode 2011:03:09:22:37:56:SJ cbx_lpm_mux 2011:03:09:22:37:56:SJ cbx_lpm_shiftreg 2011:03:09:22:37:56:SJ cbx_mgl 2011:03:09:22:48:24:SJ cbx_stratix 2011:03:09:22:37:58:SJ cbx_stratixii 2011:03:09:22:37:58:SJ cbx_stratixiii 2011:03:09:22:37:58:SJ cbx_stratixv 2011:03:09:22:37:58:SJ cbx_util_mgl 2011:03:09:22:37:57:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+//alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
+//VERSION_BEGIN 11.0 cbx_alt_dprio 2011:03:09:22:37:51:SJ cbx_cycloneii 2011:03:09:22:37:55:SJ cbx_lpm_add_sub 2011:03:09:22:37:56:SJ cbx_lpm_compare 2011:03:09:22:37:56:SJ cbx_lpm_counter 2011:03:09:22:37:56:SJ cbx_lpm_decode 2011:03:09:22:37:56:SJ cbx_lpm_shiftreg 2011:03:09:22:37:56:SJ cbx_mgl 2011:03:09:22:48:24:SJ cbx_stratix 2011:03:09:22:37:58:SJ cbx_stratixii 2011:03:09:22:37:58:SJ VERSION_END
+
+//synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON"} *)
+module altpcie_reconfig_4sgx_alt_dprio_2vj
+ (
+ address,
+ busy,
+ datain,
+ dataout,
+ dpclk,
+ dpriodisable,
+ dprioin,
+ dprioload,
+ dprioout,
+ quad_address,
+ rden,
+ reset,
+ wren,
+ wren_data) /* synthesis synthesis_clearbox=2 */;
+ input [15:0] address;
+ output busy;
+ input [15:0] datain;
+ output [15:0] dataout;
+ input dpclk;
+ output dpriodisable;
+ output dprioin;
+ output dprioload;
+ input dprioout;
+ input [8:0] quad_address;
+ input rden;
+ input reset;
+ input wren;
+ input wren_data;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [15:0] datain;
+ tri0 rden;
+ tri0 reset;
+ tri0 wren;
+ tri0 wren_data;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] addr_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] in_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] rd_out_data_shift_reg;
+ wire [2:0] wire_startup_cntr_d;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] startup_cntr;
+ wire [2:0] wire_startup_cntr_ena;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] state_mc_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] wr_out_data_shift_reg;
+ wire wire_pre_amble_cmpr_aeb;
+ wire wire_pre_amble_cmpr_agb;
+ wire wire_rd_data_output_cmpr_ageb;
+ wire wire_rd_data_output_cmpr_alb;
+ wire wire_state_mc_cmpr_aeb;
+ wire [5:0] wire_state_mc_counter_q;
+ wire [7:0] wire_state_mc_decode_eq;
+ wire wire_dprioin_mux_dataout;
+ wire busy_state;
+ wire idle_state;
+ wire rd_addr_done;
+ wire rd_addr_state;
+ wire rd_data_done;
+ wire rd_data_input_state;
+ wire rd_data_output_state;
+ wire rd_data_state;
+ wire rdinc;
+ wire read_state;
+ wire s0_to_0;
+ wire s0_to_1;
+ wire s1_to_0;
+ wire s1_to_1;
+ wire s2_to_0;
+ wire s2_to_1;
+ wire startup_done;
+ wire startup_idle;
+ wire wr_addr_done;
+ wire wr_addr_state;
+ wire wr_data_done;
+ wire wr_data_state;
+ wire write_state;
+
+ // synopsys translate_off
+ initial
+ addr_shift_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) addr_shift_reg <= 32'b0;
+ else
+ if (wire_pre_amble_cmpr_aeb == 1'b1) addr_shift_reg <= {{2{{2{1'b0}}}}, 1'b0, quad_address[8:0], 2'b10, address};
+ else addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
+ // synopsys translate_off
+ initial
+ in_data_shift_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) in_data_shift_reg <= 16'b0;
+ else if (rd_data_input_state == 1'b1) in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
+ // synopsys translate_off
+ initial
+ rd_out_data_shift_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) rd_out_data_shift_reg <= 16'b0;
+ else
+ if (wire_pre_amble_cmpr_aeb == 1'b1) rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, 1'b0, quad_address, 2'b10};
+ else rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
+ // synopsys translate_off
+ initial
+ startup_cntr[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk)
+ if (wire_startup_cntr_ena[0:0] == 1'b1)
+ if (reset == 1'b1) startup_cntr[0:0] <= 1'b0;
+ else startup_cntr[0:0] <= wire_startup_cntr_d[0:0];
+ // synopsys translate_off
+ initial
+ startup_cntr[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk)
+ if (wire_startup_cntr_ena[1:1] == 1'b1)
+ if (reset == 1'b1) startup_cntr[1:1] <= 1'b0;
+ else startup_cntr[1:1] <= wire_startup_cntr_d[1:1];
+ // synopsys translate_off
+ initial
+ startup_cntr[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk)
+ if (wire_startup_cntr_ena[2:2] == 1'b1)
+ if (reset == 1'b1) startup_cntr[2:2] <= 1'b0;
+ else startup_cntr[2:2] <= wire_startup_cntr_d[2:2];
+ assign
+ wire_startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
+ assign
+ wire_startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
+ // synopsys translate_off
+ initial
+ state_mc_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) state_mc_reg <= 3'b0;
+ else state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
+ // synopsys translate_off
+ initial
+ wr_out_data_shift_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge dpclk or posedge reset)
+ if (reset == 1'b1) wr_out_data_shift_reg <= 32'b0;
+ else
+ if (wire_pre_amble_cmpr_aeb == 1'b1) wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, 1'b0, quad_address[8:0], 2'b10, datain};
+ else wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
+ lpm_compare pre_amble_cmpr
+ (
+ .aeb(wire_pre_amble_cmpr_aeb),
+ .agb(wire_pre_amble_cmpr_agb),
+ .ageb(),
+ .alb(),
+ .aleb(),
+ .aneb(),
+ .dataa(wire_state_mc_counter_q),
+ .datab(6'b011111)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ pre_amble_cmpr.lpm_width = 6,
+ pre_amble_cmpr.lpm_type = "lpm_compare";
+ lpm_compare rd_data_output_cmpr
+ (
+ .aeb(),
+ .agb(),
+ .ageb(wire_rd_data_output_cmpr_ageb),
+ .alb(wire_rd_data_output_cmpr_alb),
+ .aleb(),
+ .aneb(),
+ .dataa(wire_state_mc_counter_q),
+ .datab(6'b110000)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rd_data_output_cmpr.lpm_width = 6,
+ rd_data_output_cmpr.lpm_type = "lpm_compare";
+ lpm_compare state_mc_cmpr
+ (
+ .aeb(wire_state_mc_cmpr_aeb),
+ .agb(),
+ .ageb(),
+ .alb(),
+ .aleb(),
+ .aneb(),
+ .dataa(wire_state_mc_counter_q),
+ .datab({6{1'b1}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ state_mc_cmpr.lpm_width = 6,
+ state_mc_cmpr.lpm_type = "lpm_compare";
+ lpm_counter state_mc_counter
+ (
+ .clock(dpclk),
+ .cnt_en((write_state | read_state)),
+ .cout(),
+ .eq(),
+ .q(wire_state_mc_counter_q),
+ .sclr(reset)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .data({6{1'b0}}),
+ .sload(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ state_mc_counter.lpm_port_updown = "PORT_UNUSED",
+ state_mc_counter.lpm_width = 6,
+ state_mc_counter.lpm_type = "lpm_counter";
+ lpm_decode state_mc_decode
+ (
+ .data(state_mc_reg),
+ .eq(wire_state_mc_decode_eq)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0),
+ .enable(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ state_mc_decode.lpm_decodes = 8,
+ state_mc_decode.lpm_width = 3,
+ state_mc_decode.lpm_type = "lpm_decode";
+ or(wire_dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
+ assign
+ busy = busy_state,
+ busy_state = (write_state | read_state),
+ dataout = in_data_shift_reg,
+ dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
+ dprioin = wire_dprioin_mux_dataout,
+ dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
+ idle_state = wire_state_mc_decode_eq[0],
+ rd_addr_done = (rd_addr_state & wire_state_mc_cmpr_aeb),
+ rd_addr_state = (wire_state_mc_decode_eq[5] & startup_done),
+ rd_data_done = (rd_data_state & wire_state_mc_cmpr_aeb),
+ rd_data_input_state = (wire_rd_data_output_cmpr_ageb & rd_data_state),
+ rd_data_output_state = (wire_rd_data_output_cmpr_alb & rd_data_state),
+ rd_data_state = (wire_state_mc_decode_eq[7] & startup_done),
+ rdinc = 1'b0,
+ read_state = (rd_addr_state | rd_data_state),
+ s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
+ s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
+ s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
+ s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
+ startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
+ startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
+ wr_addr_done = (wr_addr_state & wire_state_mc_cmpr_aeb),
+ wr_addr_state = (wire_state_mc_decode_eq[1] & startup_done),
+ wr_data_done = (wr_data_state & wire_state_mc_cmpr_aeb),
+ wr_data_state = (wire_state_mc_decode_eq[3] & startup_done),
+ write_state = (wr_addr_state | wr_data_state);
+endmodule //altpcie_reconfig_4sgx_alt_dprio_2vj
+
+
+//lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=8 LPM_WIDTH=1 LPM_WIDTHS=3 data result sel
+//VERSION_BEGIN 11.0 cbx_lpm_mux 2011:03:09:22:37:56:SJ cbx_mgl 2011:03:09:22:48:24:SJ VERSION_END
+
+//synthesis_resources = lut 3
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_reconfig_4sgx_mux_c6a
+ (
+ data,
+ result,
+ sel) ;
+ input [7:0] data;
+ output [0:0] result;
+ input [2:0] sel;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [7:0] data;
+ tri0 [2:0] sel;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire wire_l1_w0_n0_mux_dataout;
+ wire wire_l1_w0_n1_mux_dataout;
+ wire wire_l1_w0_n2_mux_dataout;
+ wire wire_l1_w0_n3_mux_dataout;
+ wire wire_l2_w0_n0_mux_dataout;
+ wire wire_l2_w0_n1_mux_dataout;
+ wire wire_l3_w0_n0_mux_dataout;
+ wire [13:0] data_wire;
+ wire [0:0] result_wire_ext;
+ wire [8:0] sel_wire;
+
+ assign wire_l1_w0_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[1] : data_wire[0];
+ assign wire_l1_w0_n1_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[3] : data_wire[2];
+ assign wire_l1_w0_n2_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[5] : data_wire[4];
+ assign wire_l1_w0_n3_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[7] : data_wire[6];
+ assign wire_l2_w0_n0_mux_dataout = (sel_wire[4] === 1'b1) ? data_wire[9] : data_wire[8];
+ assign wire_l2_w0_n1_mux_dataout = (sel_wire[4] === 1'b1) ? data_wire[11] : data_wire[10];
+ assign wire_l3_w0_n0_mux_dataout = (sel_wire[8] === 1'b1) ? data_wire[13] : data_wire[12];
+ assign
+ data_wire = {wire_l2_w0_n1_mux_dataout, wire_l2_w0_n0_mux_dataout, wire_l1_w0_n3_mux_dataout, wire_l1_w0_n2_mux_dataout, wire_l1_w0_n1_mux_dataout, wire_l1_w0_n0_mux_dataout, data},
+ result = result_wire_ext,
+ result_wire_ext = {wire_l3_w0_n0_mux_dataout},
+ sel_wire = {sel[2], {3{1'b0}}, sel[1], {3{1'b0}}, sel[0]};
+endmodule //altpcie_reconfig_4sgx_mux_c6a
+
+
+//lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=2 LPM_WIDTH=1 LPM_WIDTHS=1 data result sel
+//VERSION_BEGIN 11.0 cbx_lpm_mux 2011:03:09:22:37:56:SJ cbx_mgl 2011:03:09:22:48:24:SJ VERSION_END
+
+//synthesis_resources = lut 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_reconfig_4sgx_mux_46a
+ (
+ data,
+ result,
+ sel) ;
+ input [1:0] data;
+ output [0:0] result;
+ input [0:0] sel;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [1:0] data;
+ tri0 [0:0] sel;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire wire_l1_w0_n0_mux_dataout;
+ wire [1:0] data_wire;
+ wire [0:0] result_wire_ext;
+ wire [0:0] sel_wire;
+
+ assign wire_l1_w0_n0_mux_dataout = (sel_wire[0] === 1'b1) ? data_wire[1] : data_wire[0];
+ assign
+ data_wire = {data},
+ result = result_wire_ext,
+ result_wire_ext = {wire_l1_w0_n0_mux_dataout},
+ sel_wire = {sel[0]};
+endmodule //altpcie_reconfig_4sgx_mux_46a
+
+//synthesis_resources = alt_cal 1 lpm_add_sub 4 lpm_compare 7 lpm_counter 4 lpm_decode 3 lut 5 reg 149
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0"} *)
+module altpcie_reconfig_4sgx_alt2gxb_reconfig_squ1
+ (
+ busy,
+ data_valid,
+ logical_channel_address,
+ offset_cancellation_reset,
+ read,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_mode_sel,
+ reconfig_togxb,
+ rx_eqctrl,
+ rx_eqctrl_out,
+ rx_eqdcgain,
+ rx_eqdcgain_out,
+ tx_preemp_0t,
+ tx_preemp_0t_out,
+ tx_preemp_1t,
+ tx_preemp_1t_out,
+ tx_preemp_2t,
+ tx_preemp_2t_out,
+ tx_vodctrl,
+ tx_vodctrl_out,
+ write_all) /* synthesis synthesis_clearbox=2 */;
+ output busy;
+ output data_valid;
+ input [2:0] logical_channel_address;
+ input offset_cancellation_reset;
+ input read;
+ input reconfig_clk;
+ input [33:0] reconfig_fromgxb;
+ input [2:0] reconfig_mode_sel;
+ output [3:0] reconfig_togxb;
+ input [3:0] rx_eqctrl;
+ output [3:0] rx_eqctrl_out;
+ input [2:0] rx_eqdcgain;
+ output [2:0] rx_eqdcgain_out;
+ input [4:0] tx_preemp_0t;
+ output [4:0] tx_preemp_0t_out;
+ input [4:0] tx_preemp_1t;
+ output [4:0] tx_preemp_1t_out;
+ input [4:0] tx_preemp_2t;
+ output [4:0] tx_preemp_2t_out;
+ input [2:0] tx_vodctrl;
+ output [2:0] tx_vodctrl_out;
+ input write_all;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [2:0] logical_channel_address;
+ tri0 offset_cancellation_reset;
+ tri0 read;
+ tri0 [2:0] reconfig_mode_sel;
+ tri0 [3:0] rx_eqctrl;
+ tri0 [2:0] rx_eqdcgain;
+ tri0 [4:0] tx_preemp_0t;
+ tri0 [4:0] tx_preemp_1t;
+ tri0 [4:0] tx_preemp_2t;
+ tri0 [2:0] tx_vodctrl;
+ tri0 write_all;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire wire_calibration_busy;
+ wire [15:0] wire_calibration_dprio_addr;
+ wire [15:0] wire_calibration_dprio_dataout;
+ wire wire_calibration_dprio_rden;
+ wire wire_calibration_dprio_wren;
+ wire [8:0] wire_calibration_quad_addr;
+ wire wire_calibration_retain_addr;
+ wire wire_dprio_busy;
+ wire [15:0] wire_dprio_dataout;
+ wire wire_dprio_dpriodisable;
+ wire wire_dprio_dprioin;
+ wire wire_dprio_dprioload;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
+ reg [11:0] address_pres_reg;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg data_valid_reg;
+ wire wire_data_valid_reg_ena;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg dprio_pulse_reg;
+ wire wire_dprio_pulse_reg_ena;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] reconf_mode_sel_reg;
+ wire [3:0] wire_rx_eqctrl_reg_d;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [3:0] rx_eqctrl_reg;
+ wire [3:0] wire_rx_eqctrl_reg_ena;
+ wire [2:0] wire_rx_equalizer_dcgain_reg_d;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] rx_equalizer_dcgain_reg;
+ wire [2:0] wire_rx_equalizer_dcgain_reg_ena;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [1:0] state_mc_reg;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [0:0] tx_preemp_0t_inv_reg;
+ wire wire_tx_preemp_0t_inv_reg_ena;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [0:0] tx_preemp_2t_inv_reg;
+ wire wire_tx_preemp_2t_inv_reg_ena;
+ wire [4:0] wire_tx_preemphasisctrl_1stposttap_reg_d;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [4:0] tx_preemphasisctrl_1stposttap_reg;
+ wire [4:0] wire_tx_preemphasisctrl_1stposttap_reg_ena;
+ wire [3:0] wire_tx_preemphasisctrl_2ndposttap_reg_d;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [3:0] tx_preemphasisctrl_2ndposttap_reg;
+ wire [3:0] wire_tx_preemphasisctrl_2ndposttap_reg_ena;
+ wire [3:0] wire_tx_preemphasisctrl_pretap_reg_d;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [3:0] tx_preemphasisctrl_pretap_reg;
+ wire [3:0] wire_tx_preemphasisctrl_pretap_reg_ena;
+ wire [2:0] wire_tx_vodctrl_reg_d;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] tx_vodctrl_reg;
+ wire [2:0] wire_tx_vodctrl_reg_ena;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg wr_addr_inc_reg;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg wr_rd_pulse_reg;
+ wire wire_wr_rd_pulse_reg_ena;
+ wire wire_wr_rd_pulse_reg_sclr;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg wren_data_reg;
+ wire wire_wren_data_reg_ena;
+ wire [3:0] wire_add_sub1_result;
+ wire [3:0] wire_add_sub10_result;
+ wire [3:0] wire_add_sub11_result;
+ wire [3:0] wire_add_sub2_result;
+ wire wire_cmpr6_agb;
+ wire wire_cmpr7_agb;
+ wire wire_cmpr8_agb;
+ wire wire_cmpr9_agb;
+ wire [2:0] wire_addr_cntr_q;
+ wire [2:0] wire_read_addr_cntr_q;
+ wire [2:0] wire_write_addr_cntr_q;
+ wire [7:0] wire_chl_addr_decode_eq;
+ wire [7:0] wire_reconf_mode_dec_eq;
+ wire [0:0] wire_aeq_ch_done_mux_result;
+ wire [0:0] wire_dprioout_mux_result;
+ wire [15:0] a2gr_dprio_addr;
+ wire [15:0] a2gr_dprio_data;
+ wire a2gr_dprio_rden;
+ wire a2gr_dprio_wren;
+ wire a2gr_dprio_wren_data;
+ wire adce_busy_state;
+ wire adce_state;
+ wire [7:0] aeq_ch_done;
+ wire bonded_skip;
+ wire busy_state;
+ wire cal_busy;
+ wire [2:0] cal_channel_address;
+ wire [2:0] cal_channel_address_out;
+ wire [15:0] cal_dprio_address;
+ wire [1:0] cal_dprioout_wire;
+ wire [8:0] cal_quad_address;
+ wire [31:0] cal_testbuses;
+ wire [1:0] channel_address;
+ wire [1:0] channel_address_out;
+ wire dfe_busy;
+ wire diff_mif_wr_rd_busy;
+ wire [15:0] dprio_datain;
+ wire [15:0] dprio_datain_64_67;
+ wire [15:0] dprio_datain_68_6B;
+ wire [15:0] dprio_datain_7c_7f;
+ wire [15:0] dprio_datain_7c_7f_inv;
+ wire [15:0] dprio_datain_preemp1t;
+ wire [15:0] dprio_datain_vodctrl;
+ wire dprio_pulse;
+ wire en_read_trigger;
+ wire en_write_trigger;
+ wire eyemon_busy;
+ wire header_proc;
+ wire idle_state;
+ wire internal_write_pulse;
+ wire is_adce;
+ wire is_adce_all_control;
+ wire is_adce_continuous_single_control;
+ wire is_adce_one_time_single_control;
+ wire is_adce_single_control;
+ wire is_adce_standby_single_control;
+ wire is_analog_control;
+ wire is_bonded_global_clk_div;
+ wire is_bonded_reconfig;
+ wire is_central_pcs;
+ wire is_cruclk_addr0;
+ wire is_diff_mif;
+ wire is_do_dfe;
+ wire is_do_eyemon;
+ wire is_global_clk_div_mode;
+ wire is_illegal_reg_d;
+ wire is_illegal_reg_out;
+ wire is_pll_address;
+ wire is_protected_bit;
+ wire is_rcxpat_chnl_en_ch;
+ wire is_table_33;
+ wire is_table_59;
+ wire is_table_61;
+ wire is_tier_1;
+ wire is_tier_2;
+ wire is_tx_local_div_ctrl;
+ wire legal_rd_mode_type;
+ wire legal_wr_mode_type;
+ wire local_ch_dec;
+ wire [1:0] logical_pll_sel_num;
+ wire mif_reconfig_done;
+ wire [8:0] quad_address;
+ wire [8:0] quad_address_out;
+ wire rd_pulse;
+ wire read_addr_inc;
+ wire [15:0] read_address;
+ wire read_done;
+ wire read_state;
+ wire read_word_64_67_data_valid;
+ wire read_word_68_6B_data_valid;
+ wire read_word_7c_7f_data_valid;
+ wire read_word_7c_7f_inv_data_valid;
+ wire read_word_done;
+ wire read_word_preemp_1t_data_valid;
+ wire read_word_vodctrl_data_valid;
+ wire [15:0] reconfig_datain;
+ wire reconfig_reset_all;
+ wire reset_addr_done;
+ wire reset_reconf_addr;
+ wire reset_system;
+ wire rx_reconfig;
+ wire s0_to_0;
+ wire s0_to_1;
+ wire s0_to_2;
+ wire s1_to_0;
+ wire s1_to_1;
+ wire s2_to_0;
+ wire start;
+ wire [1:0] state_mc_reg_in;
+ wire transceiver_init;
+ wire [3:0] tx_preemp_0t_out_wire;
+ wire [3:0] tx_preemp_0t_wire;
+ wire [3:0] tx_preemp_2t_out_wire;
+ wire [3:0] tx_preemp_2t_wire;
+ wire tx_reconfig;
+ wire [10:0] w334w;
+ wire [2:0] w_rx_eqa571w;
+ wire [2:0] w_rx_eqb570w;
+ wire [2:0] w_rx_eqc569w;
+ wire [2:0] w_rx_eqd568w;
+ wire [2:0] w_rx_eqv572w;
+ wire wr_pulse;
+ wire write_addr_inc;
+ wire [15:0] write_address;
+ wire write_all_int;
+ wire write_done;
+ wire write_happened;
+ wire write_skip;
+ wire write_state;
+ wire write_word_64_67_data_valid;
+ wire write_word_68_6B_data_valid;
+ wire write_word_7c_7f_data_valid;
+ wire write_word_7c_7f_inv_data_valid;
+ wire write_word_done;
+ wire write_word_preemp1t_data_valid;
+ wire write_word_preemp1ta_data_valid;
+ wire write_word_preemp1tb_data_valid;
+ wire write_word_vodctrl_data_valid;
+ wire write_word_vodctrla_data_valid;
+
+ alt_cal calibration
+ (
+ .busy(wire_calibration_busy),
+ .cal_error(),
+ .clock(reconfig_clk),
+ .dprio_addr(wire_calibration_dprio_addr),
+ .dprio_busy(wire_dprio_busy),
+ .dprio_datain(wire_dprio_dataout),
+ .dprio_dataout(wire_calibration_dprio_dataout),
+ .dprio_rden(wire_calibration_dprio_rden),
+ .dprio_wren(wire_calibration_dprio_wren),
+ .quad_addr(wire_calibration_quad_addr),
+ .remap_addr(address_pres_reg),
+ .reset((offset_cancellation_reset | reconfig_reset_all)),
+ .retain_addr(wire_calibration_retain_addr),
+ .start(start),
+ .testbuses(cal_testbuses),
+ .transceiver_init(transceiver_init));
+ defparam
+ calibration.channel_address_width = 3,
+ calibration.number_of_channels = 8,
+ calibration.sim_model_mode = "FALSE",
+ calibration.lpm_type = "alt_cal";
+ altpcie_reconfig_4sgx_alt_dprio_2vj dprio
+ (
+ .address((({16{wire_calibration_busy}} & cal_dprio_address) | ({16{(~ wire_calibration_busy)}} & a2gr_dprio_addr))),
+ .busy(wire_dprio_busy),
+ .datain((({16{wire_calibration_busy}} & wire_calibration_dprio_dataout) | ({16{(~ wire_calibration_busy)}} & a2gr_dprio_data))),
+ .dataout(wire_dprio_dataout),
+ .dpclk(reconfig_clk),
+ .dpriodisable(wire_dprio_dpriodisable),
+ .dprioin(wire_dprio_dprioin),
+ .dprioload(wire_dprio_dprioload),
+ .dprioout(wire_dprioout_mux_result),
+ .quad_address(quad_address_out),
+ .rden(((wire_calibration_busy & wire_calibration_dprio_rden) | ((~ wire_calibration_busy) & a2gr_dprio_rden))),
+ .reset(reconfig_reset_all),
+ .wren(((wire_calibration_busy & wire_calibration_dprio_wren) | ((~ wire_calibration_busy) & a2gr_dprio_wren))),
+ .wren_data(((wire_calibration_busy & wire_calibration_retain_addr) | ((~ wire_calibration_busy) & a2gr_dprio_wren_data))));
+ // synopsys translate_off
+ initial
+ address_pres_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) address_pres_reg <= 12'b0;
+ else address_pres_reg <= {(({9{cal_busy}} & cal_quad_address) | ({9{(~ cal_busy)}} & quad_address)), ((cal_busy & cal_channel_address[2]) | ((~ cal_busy) & ((is_pll_address | is_central_pcs) | is_bonded_global_clk_div))), ((cal_busy & cal_channel_address[1]) | ((~ cal_busy) & ((((channel_address[1] | is_bonded_global_clk_div) & (~ is_pll_address)) | ((logical_pll_sel_num[1] | (is_table_59 & is_bonded_reconfig)) & is_pll_address)) | is_central_pcs))), ((cal_busy & cal_channel_address[0]) | ((~ cal_busy) & (((((channel_address[0] | is_bonded_global_clk_div) & (~ is_pll_address)) | ((logical_pll_sel_num[0] | (is_table_59 & is_bonded_reconfig)) & is_pll_address)) & (~ is_central_pcs)) | (is_table_61 & is_central_pcs))))};
+ // synopsys translate_off
+ initial
+ data_valid_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) data_valid_reg <= 1'b0;
+ else if (wire_data_valid_reg_ena == 1'b1) data_valid_reg <= (~ (is_illegal_reg_out | reset_system));
+ assign
+ wire_data_valid_reg_ena = (read_state | write_state);
+ // synopsys translate_off
+ initial
+ dprio_pulse_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) dprio_pulse_reg <= 1'b0;
+ else if (wire_dprio_pulse_reg_ena == 1'b1) dprio_pulse_reg <= wire_dprio_busy;
+ assign
+ wire_dprio_pulse_reg_ena = (read_state | write_state);
+ // synopsys translate_off
+ initial
+ reconf_mode_sel_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) reconf_mode_sel_reg <= 3'b0;
+ else reconf_mode_sel_reg <= reconfig_mode_sel;
+ // synopsys translate_off
+ initial
+ rx_eqctrl_reg[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk)
+ if (wire_rx_eqctrl_reg_ena[0:0] == 1'b1) rx_eqctrl_reg[0:0] <= wire_rx_eqctrl_reg_d[0:0];
+ // synopsys translate_off
+ initial
+ rx_eqctrl_reg[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk)
+ if (wire_rx_eqctrl_reg_ena[1:1] == 1'b1) rx_eqctrl_reg[1:1] <= wire_rx_eqctrl_reg_d[1:1];
+ // synopsys translate_off
+ initial
+ rx_eqctrl_reg[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk)
+ if (wire_rx_eqctrl_reg_ena[2:2] == 1'b1) rx_eqctrl_reg[2:2] <= wire_rx_eqctrl_reg_d[2:2];
+ // synopsys translate_off
+ initial
+ rx_eqctrl_reg[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk)
+ if (wire_rx_eqctrl_reg_ena[3:3] == 1'b1) rx_eqctrl_reg[3:3] <= wire_rx_eqctrl_reg_d[3:3];
+ assign
+ wire_rx_eqctrl_reg_d = (({4{read_state}} & (((({{2{1'b0}}, (w_rx_eqv572w[2] & (~ (w_rx_eqv572w[1] ^ w_rx_eqv572w[0]))), (((w_rx_eqv572w[2] & w_rx_eqv572w[1]) & w_rx_eqv572w[0]) | (((~ w_rx_eqv572w[2]) & (~ w_rx_eqv572w[1])) & (~ w_rx_eqv572w[0])))} & {4{(((((w_rx_eqd568w[2] & w_rx_eqd568w[1]) & w_rx_eqd568w[0]) & (~ ((w_rx_eqc569w[2] & w_rx_eqc569w[1]) & w_rx_eqc569w[0]))) & (~ ((w_rx_eqb570w[2] & w_rx_eqb570w[1]) & w_rx_eqb570w[0]))) & (~ ((w_rx_eqa571w[2] & w_rx_eqa571w[1]) & w_rx_eqa571w[0])))}}) | ({1'b0, 1'b1, ((w_rx_eqv572w[2] & w_rx_eqv572w[1]) & w_rx_eqv572w[0]), ((w_rx_eqv572w[2] & (~ w_rx_eqv572w[1])) & (~ w_rx_eqv572w[0]))} & {4{(((((w_rx_eqd568w[2] & w_rx_eqd568w[1]) & w_rx_eqd568w[0]) & ((w_rx_eqc569w[2] & w_rx_eqc569w[1]) & w_rx_eqc569w[0])) & (~ ((w_rx_eqb570w[2] & w_rx_eqb570w[1]) & w_rx_eqb570w[0]))) & (~ ((w_rx_eqa571w[2] & w_rx_eqa571w[1]) & w_rx_eqa571w[0])))}})) | ({w_rx_eqv572w[2], (~ w_rx_eqv572w[2]), (((w_rx_eqv572w[2] & w_rx_eqv572w[1]) & w_rx_eqv572w[0]) | (((~ w_rx_eqv572w[2]) & (~ w_rx_eqv572w[1])) & (~ w_rx_eqv572w[0]))), ((~ w_rx_eqv572w[1]) & (~ (w_rx_eqv572w[2] ^ w_rx_eqv572w[0])))} & {4{(((((w_rx_eqd568w[2] & w_rx_eqd568w[1]) & w_rx_eqd568w[0]) & ((w_rx_eqc569w[2] & w_rx_eqc569w[1]) & w_rx_eqc569w[0])) & ((w_rx_eqb570w[2] & w_rx_eqb570w[1]) & w_rx_eqb570w[0])) & (~ ((w_rx_eqa571w[2] & w_rx_eqa571w[1]) & w_rx_eqa571w[0])))}})) | ({1'b1, ((w_rx_eqv572w[2] | w_rx_eqv572w[1]) | w_rx_eqv572w[0]), (((~ w_rx_eqv572w[1]) & (~ (w_rx_eqv572w[2] ^ w_rx_eqv572w[0]))) | ((w_rx_eqv572w[2] & w_rx_eqv572w[1]) & w_rx_eqv572w[0])), (((~ w_rx_eqv572w[1]) & (~ w_rx_eqv572w[0])) | ((w_rx_eqv572w[2] & w_rx_eqv572w[1]) & w_rx_eqv572w[0]))} & {4{(((((w_rx_eqd568w[2] & w_rx_eqd568w[1]) & w_rx_eqd568w[0]) & ((w_rx_eqc569w[2] & w_rx_eqc569w[1]) & w_rx_eqc569w[0])) & ((w_rx_eqb570w[2] & w_rx_eqb570w[1]) & w_rx_eqb570w[0])) & ((w_rx_eqa571w[2] & w_rx_eqa571w[1]) & w_rx_eqa571w[0]))}}))) | ({4{write_state}} & rx_eqctrl));
+ assign
+ wire_rx_eqctrl_reg_ena = {4{((read_word_68_6B_data_valid & read_state) | (write_state & write_word_68_6B_data_valid))}};
+ // synopsys translate_off
+ initial
+ rx_equalizer_dcgain_reg[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) rx_equalizer_dcgain_reg[0:0] <= 1'b0;
+ else if (wire_rx_equalizer_dcgain_reg_ena[0:0] == 1'b1) rx_equalizer_dcgain_reg[0:0] <= wire_rx_equalizer_dcgain_reg_d[0:0];
+ // synopsys translate_off
+ initial
+ rx_equalizer_dcgain_reg[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) rx_equalizer_dcgain_reg[1:1] <= 1'b0;
+ else if (wire_rx_equalizer_dcgain_reg_ena[1:1] == 1'b1) rx_equalizer_dcgain_reg[1:1] <= wire_rx_equalizer_dcgain_reg_d[1:1];
+ // synopsys translate_off
+ initial
+ rx_equalizer_dcgain_reg[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) rx_equalizer_dcgain_reg[2:2] <= 1'b0;
+ else if (wire_rx_equalizer_dcgain_reg_ena[2:2] == 1'b1) rx_equalizer_dcgain_reg[2:2] <= wire_rx_equalizer_dcgain_reg_d[2:2];
+ assign
+ wire_rx_equalizer_dcgain_reg_d = (({3{read_state}} & {wire_dprio_dataout[10], (wire_dprio_dataout[8] & (~ wire_dprio_dataout[10])), (((wire_dprio_dataout[7] ^ wire_dprio_dataout[8]) ^ wire_dprio_dataout[9]) ^ wire_dprio_dataout[10])}) | ({3{write_state}} & rx_eqdcgain));
+ assign
+ wire_rx_equalizer_dcgain_reg_ena = {3{((read_word_64_67_data_valid & read_state) | (write_state & write_word_64_67_data_valid))}};
+ // synopsys translate_off
+ initial
+ state_mc_reg = 2'b00;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) state_mc_reg <= 2'b0;
+ else state_mc_reg <= state_mc_reg_in;
+ // synopsys translate_off
+ initial
+ tx_preemp_0t_inv_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemp_0t_inv_reg <= 1'b0;
+ else if (wire_tx_preemp_0t_inv_reg_ena == 1'b1) tx_preemp_0t_inv_reg <= ((read_state & wire_dprio_dataout[4]) | (write_state & (~ tx_preemp_0t[4])));
+ assign
+ wire_tx_preemp_0t_inv_reg_ena = ((read_word_7c_7f_inv_data_valid & read_state) | (write_state & write_word_7c_7f_inv_data_valid));
+ // synopsys translate_off
+ initial
+ tx_preemp_2t_inv_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemp_2t_inv_reg <= 1'b0;
+ else if (wire_tx_preemp_2t_inv_reg_ena == 1'b1) tx_preemp_2t_inv_reg <= ((read_state & wire_dprio_dataout[3]) | (write_state & (~ tx_preemp_2t[4])));
+ assign
+ wire_tx_preemp_2t_inv_reg_ena = ((read_word_7c_7f_inv_data_valid & read_state) | (write_state & write_word_7c_7f_inv_data_valid));
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_1stposttap_reg[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_1stposttap_reg[0:0] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_1stposttap_reg_ena[0:0] == 1'b1) tx_preemphasisctrl_1stposttap_reg[0:0] <= wire_tx_preemphasisctrl_1stposttap_reg_d[0:0];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_1stposttap_reg[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_1stposttap_reg[1:1] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_1stposttap_reg_ena[1:1] == 1'b1) tx_preemphasisctrl_1stposttap_reg[1:1] <= wire_tx_preemphasisctrl_1stposttap_reg_d[1:1];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_1stposttap_reg[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_1stposttap_reg[2:2] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_1stposttap_reg_ena[2:2] == 1'b1) tx_preemphasisctrl_1stposttap_reg[2:2] <= wire_tx_preemphasisctrl_1stposttap_reg_d[2:2];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_1stposttap_reg[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_1stposttap_reg[3:3] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_1stposttap_reg_ena[3:3] == 1'b1) tx_preemphasisctrl_1stposttap_reg[3:3] <= wire_tx_preemphasisctrl_1stposttap_reg_d[3:3];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_1stposttap_reg[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_1stposttap_reg[4:4] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_1stposttap_reg_ena[4:4] == 1'b1) tx_preemphasisctrl_1stposttap_reg[4:4] <= wire_tx_preemphasisctrl_1stposttap_reg_d[4:4];
+ assign
+ wire_tx_preemphasisctrl_1stposttap_reg_d = (({5{read_state}} & wire_dprio_dataout[15:11]) | ({5{write_state}} & tx_preemp_1t));
+ assign
+ wire_tx_preemphasisctrl_1stposttap_reg_ena = {5{((read_word_preemp_1t_data_valid & read_state) | (write_state & write_word_preemp1t_data_valid))}};
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_2ndposttap_reg[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_2ndposttap_reg[0:0] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_2ndposttap_reg_ena[0:0] == 1'b1) tx_preemphasisctrl_2ndposttap_reg[0:0] <= wire_tx_preemphasisctrl_2ndposttap_reg_d[0:0];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_2ndposttap_reg[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_2ndposttap_reg[1:1] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_2ndposttap_reg_ena[1:1] == 1'b1) tx_preemphasisctrl_2ndposttap_reg[1:1] <= wire_tx_preemphasisctrl_2ndposttap_reg_d[1:1];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_2ndposttap_reg[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_2ndposttap_reg[2:2] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_2ndposttap_reg_ena[2:2] == 1'b1) tx_preemphasisctrl_2ndposttap_reg[2:2] <= wire_tx_preemphasisctrl_2ndposttap_reg_d[2:2];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_2ndposttap_reg[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_2ndposttap_reg[3:3] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_2ndposttap_reg_ena[3:3] == 1'b1) tx_preemphasisctrl_2ndposttap_reg[3:3] <= wire_tx_preemphasisctrl_2ndposttap_reg_d[3:3];
+ assign
+ wire_tx_preemphasisctrl_2ndposttap_reg_d = (({4{read_state}} & wire_dprio_dataout[7:4]) | ({4{write_state}} & tx_preemp_2t_wire[3:0]));
+ assign
+ wire_tx_preemphasisctrl_2ndposttap_reg_ena = {4{((read_word_7c_7f_data_valid & read_state) | (write_state & write_word_7c_7f_data_valid))}};
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_pretap_reg[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_pretap_reg[0:0] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_pretap_reg_ena[0:0] == 1'b1) tx_preemphasisctrl_pretap_reg[0:0] <= wire_tx_preemphasisctrl_pretap_reg_d[0:0];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_pretap_reg[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_pretap_reg[1:1] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_pretap_reg_ena[1:1] == 1'b1) tx_preemphasisctrl_pretap_reg[1:1] <= wire_tx_preemphasisctrl_pretap_reg_d[1:1];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_pretap_reg[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_pretap_reg[2:2] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_pretap_reg_ena[2:2] == 1'b1) tx_preemphasisctrl_pretap_reg[2:2] <= wire_tx_preemphasisctrl_pretap_reg_d[2:2];
+ // synopsys translate_off
+ initial
+ tx_preemphasisctrl_pretap_reg[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_preemphasisctrl_pretap_reg[3:3] <= 1'b0;
+ else if (wire_tx_preemphasisctrl_pretap_reg_ena[3:3] == 1'b1) tx_preemphasisctrl_pretap_reg[3:3] <= wire_tx_preemphasisctrl_pretap_reg_d[3:3];
+ assign
+ wire_tx_preemphasisctrl_pretap_reg_d = (({4{read_state}} & wire_dprio_dataout[3:0]) | ({4{write_state}} & tx_preemp_0t_wire[3:0]));
+ assign
+ wire_tx_preemphasisctrl_pretap_reg_ena = {4{((read_state & read_word_7c_7f_data_valid) | (write_state & write_word_7c_7f_data_valid))}};
+ // synopsys translate_off
+ initial
+ tx_vodctrl_reg[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_vodctrl_reg[0:0] <= 1'b0;
+ else if (wire_tx_vodctrl_reg_ena[0:0] == 1'b1) tx_vodctrl_reg[0:0] <= wire_tx_vodctrl_reg_d[0:0];
+ // synopsys translate_off
+ initial
+ tx_vodctrl_reg[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_vodctrl_reg[1:1] <= 1'b0;
+ else if (wire_tx_vodctrl_reg_ena[1:1] == 1'b1) tx_vodctrl_reg[1:1] <= wire_tx_vodctrl_reg_d[1:1];
+ // synopsys translate_off
+ initial
+ tx_vodctrl_reg[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) tx_vodctrl_reg[2:2] <= 1'b0;
+ else if (wire_tx_vodctrl_reg_ena[2:2] == 1'b1) tx_vodctrl_reg[2:2] <= wire_tx_vodctrl_reg_d[2:2];
+ assign
+ wire_tx_vodctrl_reg_d = (({3{read_state}} & {((wire_dprio_dataout[14] & wire_dprio_dataout[13]) | (wire_dprio_dataout[15] & (~ wire_dprio_dataout[14]))), ((wire_dprio_dataout[14] & (~ wire_dprio_dataout[13])) | (wire_dprio_dataout[15] & (~ wire_dprio_dataout[14]))), (((~ wire_dprio_dataout[14]) & wire_dprio_dataout[13]) | (wire_dprio_dataout[15] & wire_dprio_dataout[14]))}) | ({3{write_state}} & tx_vodctrl));
+ assign
+ wire_tx_vodctrl_reg_ena = {3{((read_word_vodctrl_data_valid & read_state) | (write_state & write_word_vodctrl_data_valid))}};
+ // synopsys translate_off
+ initial
+ wr_addr_inc_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) wr_addr_inc_reg <= 1'b0;
+ else wr_addr_inc_reg <= (wr_pulse | (((~ wr_pulse) & (~ rd_pulse)) & wr_addr_inc_reg));
+ // synopsys translate_off
+ initial
+ wr_rd_pulse_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) wr_rd_pulse_reg <= 1'b0;
+ else if (wire_wr_rd_pulse_reg_ena == 1'b1)
+ if (wire_wr_rd_pulse_reg_sclr == 1'b1) wr_rd_pulse_reg <= 1'b0;
+ else wr_rd_pulse_reg <= (~ wr_rd_pulse_reg);
+ assign
+ wire_wr_rd_pulse_reg_ena = (dprio_pulse & (~ read_state)),
+ wire_wr_rd_pulse_reg_sclr = ((((reset_system | (is_tier_1 & mif_reconfig_done)) | (is_diff_mif & write_done)) | reset_addr_done) | is_illegal_reg_out);
+ // synopsys translate_off
+ initial
+ wren_data_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
+ if (reconfig_reset_all == 1'b1) wren_data_reg <= 1'b0;
+ else if (wire_wren_data_reg_ena == 1'b1) wren_data_reg <= (((~ wren_data_reg) & rd_pulse) | (wren_data_reg & (~ write_done)));
+ assign
+ wire_wren_data_reg_ena = (is_tier_1 & ((~ is_diff_mif) | (is_diff_mif & diff_mif_wr_rd_busy)));
+ lpm_add_sub add_sub1
+ (
+ .add_sub(tx_preemp_0t[4]),
+ .cout(),
+ .dataa({4{1'b0}}),
+ .datab(tx_preemp_0t[3:0]),
+ .overflow(),
+ .result(wire_add_sub1_result)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .cin(),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ add_sub1.lpm_width = 4,
+ add_sub1.lpm_type = "lpm_add_sub";
+ lpm_add_sub add_sub10
+ (
+ .add_sub((~ tx_preemp_0t_inv_reg[0])),
+ .cout(),
+ .dataa({4{1'b0}}),
+ .datab(tx_preemp_0t_out_wire[3:0]),
+ .overflow(),
+ .result(wire_add_sub10_result)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .cin(),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ add_sub10.lpm_width = 4,
+ add_sub10.lpm_type = "lpm_add_sub";
+ lpm_add_sub add_sub11
+ (
+ .add_sub((~ tx_preemp_2t_inv_reg[0])),
+ .cout(),
+ .dataa({4{1'b0}}),
+ .datab(tx_preemp_2t_out_wire[3:0]),
+ .overflow(),
+ .result(wire_add_sub11_result)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .cin(),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ add_sub11.lpm_width = 4,
+ add_sub11.lpm_type = "lpm_add_sub";
+ lpm_add_sub add_sub2
+ (
+ .add_sub(tx_preemp_2t[4]),
+ .cout(),
+ .dataa({4{1'b0}}),
+ .datab(tx_preemp_2t[3:0]),
+ .overflow(),
+ .result(wire_add_sub2_result)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .cin(),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ add_sub2.lpm_width = 4,
+ add_sub2.lpm_type = "lpm_add_sub";
+ lpm_compare cmpr6
+ (
+ .aeb(),
+ .agb(wire_cmpr6_agb),
+ .ageb(),
+ .alb(),
+ .aleb(),
+ .aneb(),
+ .dataa(rx_eqctrl[3:0]),
+ .datab(4'b1010)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cmpr6.lpm_width = 4,
+ cmpr6.lpm_type = "lpm_compare";
+ lpm_compare cmpr7
+ (
+ .aeb(),
+ .agb(wire_cmpr7_agb),
+ .ageb(),
+ .alb(),
+ .aleb(),
+ .aneb(),
+ .dataa(rx_eqctrl[3:0]),
+ .datab(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cmpr7.lpm_width = 4,
+ cmpr7.lpm_type = "lpm_compare";
+ lpm_compare cmpr8
+ (
+ .aeb(),
+ .agb(wire_cmpr8_agb),
+ .ageb(),
+ .alb(),
+ .aleb(),
+ .aneb(),
+ .dataa(rx_eqctrl[3:0]),
+ .datab(4'b0011)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cmpr8.lpm_width = 4,
+ cmpr8.lpm_type = "lpm_compare";
+ lpm_compare cmpr9
+ (
+ .aeb(),
+ .agb(wire_cmpr9_agb),
+ .ageb(),
+ .alb(),
+ .aleb(),
+ .aneb(),
+ .dataa(rx_eqctrl[3:0]),
+ .datab({4{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cmpr9.lpm_width = 4,
+ cmpr9.lpm_type = "lpm_compare";
+ lpm_counter addr_cntr
+ (
+ .clock(reconfig_clk),
+ .cnt_en(1'b0),
+ .cout(),
+ .data(logical_channel_address),
+ .eq(),
+ .q(wire_addr_cntr_q),
+ .sclr((write_done | reconfig_reset_all)),
+ .sload((idle_state & (write_all | read)))
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ addr_cntr.lpm_modulus = 8,
+ addr_cntr.lpm_port_updown = "PORT_UNUSED",
+ addr_cntr.lpm_width = 3,
+ addr_cntr.lpm_type = "lpm_counter";
+ lpm_counter read_addr_cntr
+ (
+ .clock(reconfig_clk),
+ .cnt_en((read_addr_inc & is_analog_control)),
+ .cout(),
+ .data({(~ tx_reconfig), {2{1'b0}}}),
+ .eq(),
+ .q(wire_read_addr_cntr_q),
+ .sclr(((read_done | reset_system) | reconfig_reset_all)),
+ .sload(((idle_state & read) & (~ tx_reconfig)))
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ read_addr_cntr.lpm_modulus = 6,
+ read_addr_cntr.lpm_port_updown = "PORT_UNUSED",
+ read_addr_cntr.lpm_width = 3,
+ read_addr_cntr.lpm_type = "lpm_counter";
+ lpm_counter write_addr_cntr
+ (
+ .clock(reconfig_clk),
+ .cnt_en(write_addr_inc),
+ .cout(),
+ .data({(~ tx_reconfig), {2{1'b0}}}),
+ .eq(),
+ .q(wire_write_addr_cntr_q),
+ .sclr(((write_done | reset_system) | reconfig_reset_all)),
+ .sload(((idle_state & write_all) & (~ tx_reconfig)))
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ write_addr_cntr.lpm_modulus = 6,
+ write_addr_cntr.lpm_port_updown = "PORT_UNUSED",
+ write_addr_cntr.lpm_width = 3,
+ write_addr_cntr.lpm_type = "lpm_counter";
+ lpm_decode chl_addr_decode
+ (
+ .data(wire_addr_cntr_q),
+ .eq(wire_chl_addr_decode_eq)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0),
+ .enable(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ chl_addr_decode.lpm_decodes = 8,
+ chl_addr_decode.lpm_width = 3,
+ chl_addr_decode.lpm_type = "lpm_decode";
+ lpm_decode reconf_mode_dec
+ (
+ .data(reconf_mode_sel_reg),
+ .eq(wire_reconf_mode_dec_eq)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0),
+ .enable(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ reconf_mode_dec.lpm_decodes = 8,
+ reconf_mode_dec.lpm_width = 3,
+ reconf_mode_dec.lpm_type = "lpm_decode";
+ altpcie_reconfig_4sgx_mux_c6a aeq_ch_done_mux
+ (
+ .data(aeq_ch_done),
+ .result(wire_aeq_ch_done_mux_result),
+ .sel(w334w[2:0]));
+ altpcie_reconfig_4sgx_mux_46a dprioout_mux
+ (
+ .data(cal_dprioout_wire),
+ .result(wire_dprioout_mux_result),
+ .sel(((cal_busy & cal_quad_address[0]) | ((~ cal_busy) & quad_address[0]))));
+ assign
+ a2gr_dprio_addr = ((write_address & {16{write_state}}) | (read_address & {16{read_state}})),
+ a2gr_dprio_data = ((dprio_datain & {16{(~ header_proc)}}) & {16{write_state}}),
+ a2gr_dprio_rden = (rd_pulse & ((~ is_diff_mif) | (is_diff_mif & diff_mif_wr_rd_busy))),
+ a2gr_dprio_wren = (((wr_pulse & (~ wren_data_reg)) & (~ is_analog_control)) & ((~ is_diff_mif) | (is_diff_mif & diff_mif_wr_rd_busy))),
+ a2gr_dprio_wren_data = ((wr_pulse & (wren_data_reg | is_analog_control)) & ((~ is_diff_mif) | (is_diff_mif & diff_mif_wr_rd_busy))),
+ adce_busy_state = 1'b0,
+ adce_state = (state_mc_reg[0:0] & state_mc_reg[1:1]),
+ aeq_ch_done = {8{1'b0}},
+ bonded_skip = 1'b0,
+ busy = (((((~ is_bonded_reconfig) & busy_state) | (is_bonded_reconfig & (((~ is_table_33) & busy_state) | (is_table_33 & (((~ is_bonded_global_clk_div) & busy_state) | is_bonded_global_clk_div))))) | internal_write_pulse) | cal_busy),
+ busy_state = ((((read_state | write_state) | adce_state) | eyemon_busy) | dfe_busy),
+ cal_busy = wire_calibration_busy,
+ cal_channel_address = wire_calibration_dprio_addr[14:12],
+ cal_channel_address_out = address_pres_reg[2:0],
+ cal_dprio_address = {wire_calibration_dprio_addr[15], cal_channel_address_out, wire_calibration_dprio_addr[11:0]},
+ cal_dprioout_wire = {reconfig_fromgxb[17], reconfig_fromgxb[0]},
+ cal_quad_address = wire_calibration_quad_addr,
+ cal_testbuses = {reconfig_fromgxb[33:18], reconfig_fromgxb[16:1]},
+ channel_address = wire_addr_cntr_q[1:0],
+ channel_address_out = (address_pres_reg[1:0] & {2{(~ ((address_pres_reg[2] & address_pres_reg[1]) & address_pres_reg[0]))}}),
+ data_valid = (data_valid_reg & idle_state),
+ dfe_busy = 1'b0,
+ diff_mif_wr_rd_busy = 1'b0,
+ dprio_datain = ((((((((dprio_datain_vodctrl & {16{(write_word_vodctrl_data_valid | write_word_vodctrla_data_valid)}}) | (dprio_datain_preemp1t & {16{((write_word_preemp1t_data_valid | write_word_preemp1ta_data_valid) | write_word_preemp1tb_data_valid)}})) | (dprio_datain_64_67 & {16{write_word_64_67_data_valid}})) | ((dprio_datain_68_6B | {16{local_ch_dec}}) & {16{write_word_68_6B_data_valid}})) | (dprio_datain_7c_7f & {16{write_word_7c_7f_data_valid}})) | (dprio_datain_7c_7f_inv & {16{write_word_7c_7f_inv_data_valid}})) & {16{is_analog_control}}) | ({16{((is_tier_1 | is_tier_2) | is_tx_local_div_ctrl)}} & reconfig_datain)),
+ dprio_datain_64_67 = {wire_dprio_dataout[15:11], {rx_eqdcgain[2], (rx_eqdcgain[2] | (rx_eqdcgain[1] & rx_eqdcgain[0])), (rx_eqdcgain[2] | rx_eqdcgain[1]), ((rx_eqdcgain[2] | rx_eqdcgain[1]) | rx_eqdcgain[0])}, wire_dprio_dataout[6:0]},
+ dprio_datain_68_6B = {wire_dprio_dataout[15], {{3{wire_cmpr6_agb}}, {3{wire_cmpr7_agb}}, {3{wire_cmpr8_agb}}, {3{wire_cmpr9_agb}}, (((((rx_eqctrl[1] & (~ rx_eqctrl[0])) | (((~ rx_eqctrl[3]) & (~ rx_eqctrl[2])) & rx_eqctrl[1])) | ((rx_eqctrl[2] & (~ rx_eqctrl[1])) & rx_eqctrl[0])) | ((rx_eqctrl[3] & rx_eqctrl[2]) & rx_eqctrl[0])) | ((rx_eqctrl[3] & (~ rx_eqctrl[2])) & (~ rx_eqctrl[1]))), ((rx_eqctrl[1] & (rx_eqctrl[0] ^ (rx_eqctrl[2] ^ rx_eqctrl[3]))) | (((rx_eqctrl[3] & rx_eqctrl[2]) & (~ rx_eqctrl[1])) & (~ rx_eqctrl[0]))), (((((((~ (rx_eqctrl[3] ^ rx_eqctrl[2])) & rx_eqctrl[1]) & rx_eqctrl[0]) | ((rx_eqctrl[2] & rx_eqctrl[1]) & (~ rx_eqctrl[0]))) | ((rx_eqctrl[3] & rx_eqctrl[1]) & (~ rx_eqctrl[0]))) | ((rx_eqctrl[3] & rx_eqctrl[2]) & (~ rx_eqctrl[0]))) | (((rx_eqctrl[3] & (~ rx_eqctrl[2])) & (~ rx_eqctrl[1])) & rx_eqctrl[0]))}},
+ dprio_datain_7c_7f = {wire_dprio_dataout[15:8], tx_preemp_2t_wire[3:0], tx_preemp_0t_wire[3:0]},
+ dprio_datain_7c_7f_inv = {wire_dprio_dataout[15:5], (~ tx_preemp_0t[4]), (~ tx_preemp_2t[4]), wire_dprio_dataout[2:0]},
+ dprio_datain_preemp1t = {tx_preemp_1t, wire_dprio_dataout[10:0]},
+ dprio_datain_vodctrl = {{((tx_vodctrl[2] & tx_vodctrl[1]) | (tx_vodctrl[0] & (tx_vodctrl[2] ^ tx_vodctrl[1]))), (tx_vodctrl[2] ^ tx_vodctrl[1]), ((tx_vodctrl[2] & (~ tx_vodctrl[1])) | (tx_vodctrl[0] & (~ (tx_vodctrl[2] ^ tx_vodctrl[1]))))}, wire_dprio_dataout[12:0]},
+ dprio_pulse = ((dprio_pulse_reg ^ wire_dprio_busy) & (~ wire_dprio_busy)),
+ en_read_trigger = legal_rd_mode_type,
+ en_write_trigger = legal_wr_mode_type,
+ eyemon_busy = 1'b0,
+ header_proc = 1'b0,
+ idle_state = ((~ state_mc_reg[0:0]) & (~ state_mc_reg[1:1])),
+ internal_write_pulse = 1'b0,
+ is_adce = ((((is_adce_single_control | is_adce_all_control) | is_adce_continuous_single_control) | is_adce_one_time_single_control) | is_adce_standby_single_control),
+ is_adce_all_control = 1'b0,
+ is_adce_continuous_single_control = 1'b0,
+ is_adce_one_time_single_control = 1'b0,
+ is_adce_single_control = 1'b0,
+ is_adce_standby_single_control = 1'b0,
+ is_analog_control = wire_reconf_mode_dec_eq[0],
+ is_bonded_global_clk_div = 1'b0,
+ is_bonded_reconfig = 1'b0,
+ is_central_pcs = 1'b0,
+ is_cruclk_addr0 = 1'b0,
+ is_diff_mif = 1'b0,
+ is_do_dfe = 1'b0,
+ is_do_eyemon = 1'b0,
+ is_illegal_reg_d = 1'b0,
+ is_illegal_reg_out = 1'b0,
+ is_pll_address = 1'b0,
+ is_protected_bit = 1'b0,
+ is_rcxpat_chnl_en_ch = 1'b0,
+ is_table_33 = 1'b0,
+ is_table_59 = 1'b0,
+ is_table_61 = 1'b0,
+ is_tier_1 = 1'b0,
+ is_tier_2 = 1'b0,
+ is_tx_local_div_ctrl = 1'b0,
+ legal_rd_mode_type = ((~ reconfig_mode_sel[2]) & ((~ reconfig_mode_sel[1]) & (~ reconfig_mode_sel[0]))),
+ legal_wr_mode_type = ((reconfig_mode_sel[2] | (((~ reconfig_mode_sel[2]) & reconfig_mode_sel[1]) & (~ reconfig_mode_sel[0]))) | ((~ reconfig_mode_sel[2]) & (~ reconfig_mode_sel[1]))),
+ local_ch_dec = wire_aeq_ch_done_mux_result,
+ logical_pll_sel_num = {2{1'b0}},
+ mif_reconfig_done = 1'b0,
+ quad_address = {{8{1'b0}}, wire_addr_cntr_q[2]},
+ quad_address_out = address_pres_reg[11:3],
+ rd_pulse = ((((((~ dprio_pulse) & (~ write_done)) & (~ wr_rd_pulse_reg)) & (write_state & (((~ header_proc) & (~ reset_reconf_addr)) & ((~ is_tier_1) | (is_tier_1 & (((((is_rcxpat_chnl_en_ch | is_cruclk_addr0) | write_skip) | bonded_skip) | is_protected_bit) | is_global_clk_div_mode)))))) | ((read_state & (~ dprio_pulse)) & (~ read_done))) & (~ is_illegal_reg_d)),
+ read_addr_inc = (read_state & dprio_pulse),
+ read_address = {1'b0, address_pres_reg[2], channel_address_out, 1'b1, wire_read_addr_cntr_q[2], {6{1'b0}}, (wire_read_addr_cntr_q[2] & wire_read_addr_cntr_q[0]), 1'b0, (wire_read_addr_cntr_q[1] | (wire_read_addr_cntr_q[0] & wire_read_addr_cntr_q[2])), wire_read_addr_cntr_q[0]},
+ read_done = (((read_word_done & read_addr_inc) | (is_illegal_reg_out & read_state)) | reset_system),
+ read_state = (state_mc_reg[0:0] & (~ state_mc_reg[1:1])),
+ read_word_64_67_data_valid = (((dprio_pulse & wire_read_addr_cntr_q[2]) & (~ wire_read_addr_cntr_q[1])) & (~ wire_read_addr_cntr_q[0])),
+ read_word_68_6B_data_valid = (((dprio_pulse & wire_read_addr_cntr_q[2]) & (~ wire_read_addr_cntr_q[1])) & wire_read_addr_cntr_q[0]),
+ read_word_7c_7f_data_valid = (((dprio_pulse & (~ wire_read_addr_cntr_q[2])) & wire_read_addr_cntr_q[1]) & (~ wire_read_addr_cntr_q[0])),
+ read_word_7c_7f_inv_data_valid = (((dprio_pulse & (~ wire_read_addr_cntr_q[2])) & wire_read_addr_cntr_q[1]) & wire_read_addr_cntr_q[0]),
+ read_word_done = ((read_word_68_6B_data_valid & rx_reconfig) | (read_word_7c_7f_inv_data_valid & (~ rx_reconfig))),
+ read_word_preemp_1t_data_valid = (((dprio_pulse & (~ wire_read_addr_cntr_q[2])) & (~ wire_read_addr_cntr_q[1])) & wire_read_addr_cntr_q[0]),
+ read_word_vodctrl_data_valid = (((dprio_pulse & (~ wire_read_addr_cntr_q[2])) & (~ wire_read_addr_cntr_q[1])) & (~ wire_read_addr_cntr_q[0])),
+ reconfig_datain = {16{1'b0}},
+ reconfig_reset_all = 1'b0,
+ reconfig_togxb = {wire_calibration_busy, wire_dprio_dprioload, wire_dprio_dpriodisable, wire_dprio_dprioin},
+ reset_addr_done = 1'b0,
+ reset_reconf_addr = 1'b0,
+ reset_system = 1'b0,
+ rx_eqctrl_out = rx_eqctrl_reg,
+ rx_eqdcgain_out = rx_equalizer_dcgain_reg,
+ rx_reconfig = 1'b1,
+ s0_to_0 = ((idle_state & write_all_int) | read_done),
+ s0_to_1 = (((idle_state & (read & en_read_trigger)) & (~ write_state)) & (~ write_all_int)),
+ s0_to_2 = ((idle_state & ((is_adce | is_do_eyemon) | is_do_dfe)) & ((write_all & ((~ is_bonded_reconfig) | (is_bonded_reconfig & (~ is_bonded_global_clk_div)))) | (is_bonded_reconfig & is_bonded_global_clk_div))),
+ s1_to_0 = (((idle_state & (read & en_read_trigger)) & (~ write_state)) | write_done),
+ s1_to_1 = (idle_state & write_all_int),
+ s2_to_0 = (adce_state & (~ ((adce_busy_state | eyemon_busy) | dfe_busy))),
+ start = 1'b0,
+ state_mc_reg_in = {((s0_to_2 | s1_to_1) | ((((~ s2_to_0) & (~ s1_to_1)) & (~ s1_to_0)) & state_mc_reg[1])), ((s0_to_2 | s0_to_1) | ((((~ s2_to_0) & (~ s0_to_1)) & (~ s0_to_0)) & state_mc_reg[0]))},
+ transceiver_init = 1'b0,
+ tx_preemp_0t_out = {(~ tx_preemp_0t_inv_reg[0]), wire_add_sub10_result},
+ tx_preemp_0t_out_wire = tx_preemphasisctrl_pretap_reg,
+ tx_preemp_0t_wire = wire_add_sub1_result,
+ tx_preemp_1t_out = tx_preemphasisctrl_1stposttap_reg,
+ tx_preemp_2t_out = {(~ tx_preemp_2t_inv_reg[0]), wire_add_sub11_result},
+ tx_preemp_2t_out_wire = tx_preemphasisctrl_2ndposttap_reg,
+ tx_preemp_2t_wire = wire_add_sub2_result,
+ tx_reconfig = 1'b1,
+ tx_vodctrl_out = tx_vodctrl_reg,
+ w334w = {quad_address, channel_address},
+ w_rx_eqa571w = wire_dprio_dataout[14:12],
+ w_rx_eqb570w = wire_dprio_dataout[11:9],
+ w_rx_eqc569w = wire_dprio_dataout[8:6],
+ w_rx_eqd568w = wire_dprio_dataout[5:3],
+ w_rx_eqv572w = wire_dprio_dataout[2:0],
+ wr_pulse = ((((write_state & (~ dprio_pulse)) & (~ write_done)) & ((wr_rd_pulse_reg & ((~ is_tier_1) | ((is_tier_1 & (~ header_proc)) & (((((is_rcxpat_chnl_en_ch | is_cruclk_addr0) | write_skip) | bonded_skip) | is_protected_bit) | is_global_clk_div_mode)))) | ((is_tier_1 & (~ header_proc)) & ((((((~ is_rcxpat_chnl_en_ch) & (~ is_cruclk_addr0)) & (~ write_skip)) & (~ bonded_skip)) & (~ is_protected_bit)) & (~ is_global_clk_div_mode))))) & (~ is_illegal_reg_d)),
+ write_addr_inc = ((write_state & dprio_pulse) & write_happened),
+ write_address = {1'b0, address_pres_reg[2], channel_address_out, 1'b1, wire_write_addr_cntr_q[2], {6{1'b0}}, (wire_write_addr_cntr_q[2] & wire_write_addr_cntr_q[0]), 1'b0, (wire_write_addr_cntr_q[1] | (wire_write_addr_cntr_q[0] & wire_write_addr_cntr_q[2])), wire_write_addr_cntr_q[0]},
+ write_all_int = (((write_all & ((~ is_bonded_reconfig) | (is_bonded_reconfig & (~ is_bonded_global_clk_div)))) | (is_bonded_reconfig & is_bonded_global_clk_div)) & en_write_trigger),
+ write_done = ((((write_word_done & write_addr_inc) & write_happened) | (is_illegal_reg_out & write_state)) | reset_system),
+ write_happened = wr_addr_inc_reg,
+ write_skip = 1'b0,
+ write_state = ((~ state_mc_reg[0:0]) & state_mc_reg[1:1]),
+ write_word_64_67_data_valid = ((wire_write_addr_cntr_q[2] & (~ wire_write_addr_cntr_q[1])) & (~ wire_write_addr_cntr_q[0])),
+ write_word_68_6B_data_valid = ((wire_write_addr_cntr_q[2] & (~ wire_write_addr_cntr_q[1])) & wire_write_addr_cntr_q[0]),
+ write_word_7c_7f_data_valid = (((~ wire_write_addr_cntr_q[2]) & wire_write_addr_cntr_q[1]) & (~ wire_write_addr_cntr_q[0])),
+ write_word_7c_7f_inv_data_valid = (((~ wire_write_addr_cntr_q[2]) & wire_write_addr_cntr_q[1]) & wire_write_addr_cntr_q[0]),
+ write_word_done = (dprio_pulse & ((write_word_68_6B_data_valid & rx_reconfig) | (write_word_7c_7f_inv_data_valid & (~ rx_reconfig)))),
+ write_word_preemp1t_data_valid = (((~ wire_write_addr_cntr_q[2]) & (~ wire_write_addr_cntr_q[1])) & wire_write_addr_cntr_q[0]),
+ write_word_preemp1ta_data_valid = 1'b0,
+ write_word_preemp1tb_data_valid = 1'b0,
+ write_word_vodctrl_data_valid = (((~ wire_write_addr_cntr_q[2]) & (~ wire_write_addr_cntr_q[1])) & (~ wire_write_addr_cntr_q[0])),
+ write_word_vodctrla_data_valid = 1'b0;
+endmodule //altpcie_reconfig_4sgx_alt2gxb_reconfig_squ1
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_reconfig_4sgx (
+ logical_channel_address,
+ offset_cancellation_reset,
+ read,
+ reconfig_clk,
+ reconfig_fromgxb,
+ rx_eqctrl,
+ rx_eqdcgain,
+ tx_preemp_0t,
+ tx_preemp_1t,
+ tx_preemp_2t,
+ tx_vodctrl,
+ write_all,
+ busy,
+ data_valid,
+ reconfig_togxb,
+ rx_eqctrl_out,
+ rx_eqdcgain_out,
+ tx_preemp_0t_out,
+ tx_preemp_1t_out,
+ tx_preemp_2t_out,
+ tx_vodctrl_out)/* synthesis synthesis_clearbox = 2 */;
+
+ input [2:0] logical_channel_address;
+ input offset_cancellation_reset;
+ input read;
+ input reconfig_clk;
+ input [33:0] reconfig_fromgxb;
+ input [3:0] rx_eqctrl;
+ input [2:0] rx_eqdcgain;
+ input [4:0] tx_preemp_0t;
+ input [4:0] tx_preemp_1t;
+ input [4:0] tx_preemp_2t;
+ input [2:0] tx_vodctrl;
+ input write_all;
+ output busy;
+ output data_valid;
+ output [3:0] reconfig_togxb;
+ output [3:0] rx_eqctrl_out;
+ output [2:0] rx_eqdcgain_out;
+ output [4:0] tx_preemp_0t_out;
+ output [4:0] tx_preemp_1t_out;
+ output [4:0] tx_preemp_2t_out;
+ output [2:0] tx_vodctrl_out;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 offset_cancellation_reset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [3:0] sub_wire0;
+ wire [4:0] sub_wire1;
+ wire [2:0] sub_wire2;
+ wire sub_wire3;
+ wire [4:0] sub_wire4;
+ wire sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [4:0] sub_wire7;
+ wire [2:0] sub_wire8;
+ wire [2:0] sub_wire9 = 3'h0;
+ wire [3:0] reconfig_togxb = sub_wire0[3:0];
+ wire [4:0] tx_preemp_2t_out = sub_wire1[4:0];
+ wire [2:0] tx_vodctrl_out = sub_wire2[2:0];
+ wire data_valid = sub_wire3;
+ wire [4:0] tx_preemp_0t_out = sub_wire4[4:0];
+ wire busy = sub_wire5;
+ wire [3:0] rx_eqctrl_out = sub_wire6[3:0];
+ wire [4:0] tx_preemp_1t_out = sub_wire7[4:0];
+ wire [2:0] rx_eqdcgain_out = sub_wire8[2:0];
+
+ altpcie_reconfig_4sgx_alt2gxb_reconfig_squ1 altpcie_reconfig_4sgx_alt2gxb_reconfig_squ1_component (
+ .logical_channel_address (logical_channel_address),
+ .tx_preemp_1t (tx_preemp_1t),
+ .reconfig_fromgxb (reconfig_fromgxb),
+ .tx_preemp_2t (tx_preemp_2t),
+ .tx_vodctrl (tx_vodctrl),
+ .reconfig_clk (reconfig_clk),
+ .tx_preemp_0t (tx_preemp_0t),
+ .write_all (write_all),
+ .read (read),
+ .reconfig_mode_sel (sub_wire9),
+ .rx_eqctrl (rx_eqctrl),
+ .offset_cancellation_reset (offset_cancellation_reset),
+ .rx_eqdcgain (rx_eqdcgain),
+ .reconfig_togxb (sub_wire0),
+ .tx_preemp_2t_out (sub_wire1),
+ .tx_vodctrl_out (sub_wire2),
+ .data_valid (sub_wire3),
+ .tx_preemp_0t_out (sub_wire4),
+ .busy (sub_wire5),
+ .rx_eqctrl_out (sub_wire6),
+ .tx_preemp_1t_out (sub_wire7),
+ .rx_eqdcgain_out (sub_wire8))/* synthesis synthesis_clearbox=2
+ clearbox_macroname = alt2gxb_reconfig
+ clearbox_defparam = "base_port_width=1;cbx_blackbox_list=-lpm_mux;channel_address_width=3;enable_chl_addr_for_analog_ctrl=TRUE;intended_device_family=Stratix IV;number_of_channels=8;number_of_reconfig_ports=2;read_base_port_width=1;rx_eqdcgain_port_width=3;tx_preemp_port_width=5;enable_buf_cal=true;reconfig_fromgxb_width=34;reconfig_togxb_width=4;" */;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADCE NUMERIC "0"
+// Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
+// Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: PMA NUMERIC "1"
+// Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: CONSTANT: BASE_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
+// Retrieval info: CONSTANT: CHANNEL_ADDRESS_WIDTH NUMERIC "3"
+// Retrieval info: CONSTANT: ENABLE_CHL_ADDR_FOR_ANALOG_CTRL STRING "TRUE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
+// Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "2"
+// Retrieval info: CONSTANT: READ_BASE_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_EQDCGAIN_PORT_WIDTH NUMERIC "3"
+// Retrieval info: CONSTANT: TX_PREEMP_PORT_WIDTH NUMERIC "5"
+// Retrieval info: CONSTANT: enable_buf_cal STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "34"
+// Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
+// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+// Retrieval info: USED_PORT: data_valid 0 0 0 0 OUTPUT NODEFVAL "data_valid"
+// Retrieval info: USED_PORT: logical_channel_address 0 0 3 0 INPUT NODEFVAL "logical_channel_address[2..0]"
+// Retrieval info: USED_PORT: read 0 0 0 0 INPUT NODEFVAL "read"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 34 0 INPUT NODEFVAL "reconfig_fromgxb[33..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_eqctrl 0 0 4 0 INPUT NODEFVAL "rx_eqctrl[3..0]"
+// Retrieval info: USED_PORT: rx_eqctrl_out 0 0 4 0 OUTPUT NODEFVAL "rx_eqctrl_out[3..0]"
+// Retrieval info: USED_PORT: rx_eqdcgain 0 0 3 0 INPUT NODEFVAL "rx_eqdcgain[2..0]"
+// Retrieval info: USED_PORT: rx_eqdcgain_out 0 0 3 0 OUTPUT NODEFVAL "rx_eqdcgain_out[2..0]"
+// Retrieval info: USED_PORT: tx_preemp_0t 0 0 5 0 INPUT NODEFVAL "tx_preemp_0t[4..0]"
+// Retrieval info: USED_PORT: tx_preemp_0t_out 0 0 5 0 OUTPUT NODEFVAL "tx_preemp_0t_out[4..0]"
+// Retrieval info: USED_PORT: tx_preemp_1t 0 0 5 0 INPUT NODEFVAL "tx_preemp_1t[4..0]"
+// Retrieval info: USED_PORT: tx_preemp_1t_out 0 0 5 0 OUTPUT NODEFVAL "tx_preemp_1t_out[4..0]"
+// Retrieval info: USED_PORT: tx_preemp_2t 0 0 5 0 INPUT NODEFVAL "tx_preemp_2t[4..0]"
+// Retrieval info: USED_PORT: tx_preemp_2t_out 0 0 5 0 OUTPUT NODEFVAL "tx_preemp_2t_out[4..0]"
+// Retrieval info: USED_PORT: tx_vodctrl 0 0 3 0 INPUT NODEFVAL "tx_vodctrl[2..0]"
+// Retrieval info: USED_PORT: tx_vodctrl_out 0 0 3 0 OUTPUT NODEFVAL "tx_vodctrl_out[2..0]"
+// Retrieval info: USED_PORT: write_all 0 0 0 0 INPUT NODEFVAL "write_all"
+// Retrieval info: CONNECT: @logical_channel_address 0 0 3 0 logical_channel_address 0 0 3 0
+// Retrieval info: CONNECT: @read 0 0 0 0 read 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_fromgxb 0 0 34 0 reconfig_fromgxb 0 0 34 0
+// Retrieval info: CONNECT: @reconfig_mode_sel 0 0 3 0 GND 0 0 3 0
+// Retrieval info: CONNECT: @rx_eqctrl 0 0 4 0 rx_eqctrl 0 0 4 0
+// Retrieval info: CONNECT: @rx_eqdcgain 0 0 3 0 rx_eqdcgain 0 0 3 0
+// Retrieval info: CONNECT: @tx_preemp_0t 0 0 5 0 tx_preemp_0t 0 0 5 0
+// Retrieval info: CONNECT: @tx_preemp_1t 0 0 5 0 tx_preemp_1t 0 0 5 0
+// Retrieval info: CONNECT: @tx_preemp_2t 0 0 5 0 tx_preemp_2t 0 0 5 0
+// Retrieval info: CONNECT: @tx_vodctrl 0 0 3 0 tx_vodctrl 0 0 3 0
+// Retrieval info: CONNECT: @write_all 0 0 0 0 write_all 0 0 0 0
+// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+// Retrieval info: CONNECT: data_valid 0 0 0 0 @data_valid 0 0 0 0
+// Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: rx_eqctrl_out 0 0 4 0 @rx_eqctrl_out 0 0 4 0
+// Retrieval info: CONNECT: rx_eqdcgain_out 0 0 3 0 @rx_eqdcgain_out 0 0 3 0
+// Retrieval info: CONNECT: tx_preemp_0t_out 0 0 5 0 @tx_preemp_0t_out 0 0 5 0
+// Retrieval info: CONNECT: tx_preemp_1t_out 0 0 5 0 @tx_preemp_1t_out 0 0 5 0
+// Retrieval info: CONNECT: tx_preemp_2t_out 0 0 5 0 @tx_preemp_2t_out 0 0 5 0
+// Retrieval info: CONNECT: tx_vodctrl_out 0 0 3 0 @tx_vodctrl_out 0 0 3 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_4sgx_bb.v FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v b/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
new file mode 100644
index 0000000000000000000000000000000000000000..2e0f7e468bdd92dc1538aaccdbe1adb29758c98b
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
@@ -0,0 +1,413 @@
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+//
+//
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+
+module altpcie_rs_serdes (
+ input pld_clk,
+ input [39:0] test_in,
+ input [4:0] ltssm,
+ input npor,
+ input pll_locked,
+ input busy_altgxb_reconfig,
+ input [7:0] rx_pll_locked,
+ input [7:0] rx_freqlocked,
+ input [7:0] rx_signaldetect,
+ input use_c4gx_serdes,
+ input fifo_err,
+ input rc_inclk_eq_125mhz,
+ input detect_mask_rxdrst,
+
+ output txdigitalreset,
+ output rxanalogreset,
+ output rxdigitalreset
+);
+
+ localparam [19:0] WS_SIM = 20'h00020;
+ localparam [19:0] WS_1MS_10000 = 20'h186a0;
+ localparam [19:0] WS_1MS_12500 = 20'h1e848;
+ localparam [19:0] WS_1MS_15625 = 20'h2625a;
+ localparam [19:0] WS_1MS_25000 = 20'h3d090;
+
+ localparam [1:0] STROBE_TXPLL_LOCKED_SD_CNT = 2'b00;
+ localparam [1:0] IDLE_ST_CNT = 2'b01;
+ localparam [1:0] STABLE_TX_PLL_ST_CNT = 2'b10;
+ localparam [1:0] WAIT_STATE_ST_CNT = 2'b11;
+
+ localparam [1:0] IDLE_ST_SD = 2'b00;
+ localparam [1:0] RSET_ST_SD = 2'b01;
+ localparam [1:0] DONE_ST_SD = 2'b10;
+ localparam [1:0] DFLT_ST_SD = 2'b11;
+
+ localparam [4:0] LTSSM_POL = 5'b00010;
+ localparam [4:0] LTSSM_DET = 5'b00000;
+
+ genvar i;
+
+ // Reset
+ wire arst;
+ reg [2:0] arst_r;
+
+ // Test
+ wire test_sim; // When 1 simulation mode
+ wire test_cbb_compliance; // When 1 DUT is under PCIe Compliance board test mode
+
+ (* syn_encoding = "user" *) reg [1:0] serdes_rst_state;
+ reg [19:0] waitstate_timer;
+
+ reg txdigitalreset_r;
+ reg rxanalogreset_r;
+ reg rxdigitalreset_r;
+ reg ws_tmr_eq_0;
+ reg ld_ws_tmr;
+ reg ld_ws_tmr_short;
+ wire rx_pll_freq_locked;
+ reg [7:0] rx_pll_locked_sync_r;
+ reg [2:0] rx_pll_freq_locked_cnt ;
+ reg rx_pll_freq_locked_sync_r ;
+ reg [1:0] busy_altgxb_reconfig_r;
+ wire pll_locked_sync;
+ reg [2:0] pll_locked_r;
+ reg [6:0] pll_locked_cnt;
+ reg pll_locked_stable;
+
+ wire rx_pll_freq_locked_sync;
+ reg [2:0] rx_pll_freq_locked_r;
+
+ wire [7:0] rx_pll_locked_sync;
+ reg [7:0] rx_pll_locked_r;
+ reg [7:0] rx_pll_locked_rr;
+ reg [7:0] rx_pll_locked_rrr;
+
+ wire [7:0] rx_signaldetect_sync;
+ reg [7:0] rx_signaldetect_r;
+ reg [7:0] rx_signaldetect_rr;
+ reg [7:0] rx_signaldetect_rrr;
+
+ reg ltssm_detect; // when 1 , the LTSSM is in detect state
+
+ reg [7:0] rx_sd_strb0;
+ reg [7:0] rx_sd_strb1;
+ wire stable_sd;
+ wire rst_rxpcs_sd;
+ (* syn_encoding = "user" *) reg [1:0] sd_state; //State machine for rx_signaldetect strobing;
+ reg [ 19: 0] rx_sd_idl_cnt;
+
+ assign test_sim =test_in[0];
+ assign test_cbb_compliance =test_in[32];
+
+ // SERDES reset outputs
+ assign txdigitalreset = txdigitalreset_r ;
+ assign rxanalogreset = (use_c4gx_serdes==1'b1)?arst:rxanalogreset_r ;
+ assign rxdigitalreset = (detect_mask_rxdrst==1'b0)?rxdigitalreset_r|rst_rxpcs_sd:(ltssm_detect==1'b1)?1'b0:rxdigitalreset_r | rst_rxpcs_sd;
+
+ //npor Reset Synchronizer on pld_clk
+ always @(posedge pld_clk or negedge npor) begin
+ if (npor == 1'b0) begin
+ arst_r[2:0] <= 3'b111;
+ end
+ else begin
+ arst_r[2:0] <= {arst_r[1],arst_r[0],1'b0};
+ end
+ end
+ assign arst = arst_r[2];
+
+ // Synchronize pll_lock,rx_pll_freq_locked to pld_clk
+ // using 3 level sync circuit
+ assign rx_pll_freq_locked = &(rx_pll_locked_sync_r[7:0] | rx_freqlocked[7:0] );
+ always @(posedge pld_clk or posedge arst) begin
+ if (arst == 1'b1) begin
+ pll_locked_r[2:0] <= 3'b000;
+ rx_pll_freq_locked_r[2:0] <= 3'b000;
+ end
+ else begin
+ pll_locked_r[2:0] <= {pll_locked_r[1],pll_locked_r[0],pll_locked};
+ rx_pll_freq_locked_r[2:0] <= {rx_pll_freq_locked_r[1],rx_pll_freq_locked_r[0],rx_pll_freq_locked};
+ end
+ end
+ assign pll_locked_sync = pll_locked_r[2];
+ assign rx_pll_freq_locked_sync = rx_pll_freq_locked_r[2];
+
+ // Synchronize rx_pll_locked[7:0],rx_signaldetect[7:0] to pld_clk
+ // using 3 level sync circuit
+ generate
+ for (i=0;i<8;i=i+1) begin : g_rx_pll_locked_sync
+ always @(posedge pld_clk or posedge arst) begin
+ if (arst == 1'b1) begin
+ rx_pll_locked_r[i] <= 1'b0;
+ rx_pll_locked_rr[i] <= 1'b0;
+ rx_pll_locked_rrr[i] <= 1'b0;
+
+ rx_signaldetect_r[i] <= 1'b0;
+ rx_signaldetect_rr[i] <= 1'b0;
+ rx_signaldetect_rrr[i] <= 1'b0;
+ end
+ else begin
+ rx_pll_locked_r[i] <= rx_pll_locked[i];
+ rx_pll_locked_rr[i] <= rx_pll_locked_r[i];
+ rx_pll_locked_rrr[i] <= rx_pll_locked_rr[i];
+
+ rx_signaldetect_r[i] <= rx_signaldetect[i];
+ rx_signaldetect_rr[i] <= rx_signaldetect_r[i];
+ rx_signaldetect_rrr[i] <= rx_signaldetect_rr[i];
+ end
+ end
+ assign rx_pll_locked_sync[i] = rx_pll_locked_rrr[i];
+ assign rx_signaldetect_sync[i] = rx_signaldetect_rrr[i];
+ end
+ endgenerate
+
+ always @(posedge pld_clk or posedge arst)
+ begin
+ if (arst == 1'b1) begin
+ txdigitalreset_r <= 1'b1 ;
+ rxanalogreset_r <= 1'b1 ;
+ rxdigitalreset_r <= 1'b1 ;
+ waitstate_timer <= 20'hFFFFF ;
+ serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
+ ws_tmr_eq_0 <= 1'b0 ;
+ ld_ws_tmr <= 1'b1 ;
+ ld_ws_tmr_short <= 1'b0 ;
+ rx_pll_freq_locked_cnt <= 3'h0;
+ rx_pll_freq_locked_sync_r <= 1'b0;
+ rx_pll_locked_sync_r <= 8'h00;
+ busy_altgxb_reconfig_r[1:0] <= 2'b11;
+ pll_locked_cnt <= 7'h0;
+ pll_locked_stable <= 1'b0;
+ ltssm_detect <= 1'b1;
+ end
+ else begin
+ if ((ltssm==5'h0)||(ltssm==5'h1)) begin
+ ltssm_detect <= 1'b1;
+ end
+ else begin
+ ltssm_detect <= 1'b0;
+ end
+ if ( rx_pll_locked_sync[7:0]==8'hFF ) begin
+ rx_pll_locked_sync_r <= 8'hFF;
+ end
+ // add hysteresis for losing lock
+ if (rx_pll_freq_locked_sync == 1'b1) begin
+ rx_pll_freq_locked_cnt <= 3'h7;
+ end
+ else if (rx_pll_freq_locked_cnt == 3'h0) begin
+ rx_pll_freq_locked_cnt <= 3'h0;
+ end
+ else if (rx_pll_freq_locked_sync == 1'b0) begin
+ rx_pll_freq_locked_cnt <= rx_pll_freq_locked_cnt - 3'h1;
+ end
+ rx_pll_freq_locked_sync_r <= (rx_pll_freq_locked_cnt != 3'h0);
+ busy_altgxb_reconfig_r[1] <= busy_altgxb_reconfig_r[0];
+ busy_altgxb_reconfig_r[0] <= busy_altgxb_reconfig;
+
+ if (pll_locked_sync==1'b0) begin
+ pll_locked_cnt <= 7'h0;
+ end
+ else if (pll_locked_cnt < 7'h7F) begin
+ pll_locked_cnt <= pll_locked_cnt+7'h1;
+ end
+ pll_locked_stable <= (pll_locked_cnt==7'h7F)?1'b1:1'b0;
+
+ if (ld_ws_tmr == 1'b1) begin
+ if (test_sim == 1'b1) begin
+ waitstate_timer <= WS_SIM ;
+ end
+ else if (rc_inclk_eq_125mhz == 1'b1) begin
+ waitstate_timer <= WS_1MS_12500 ;
+ end
+ else begin
+ waitstate_timer <= WS_1MS_25000 ;
+ end
+ end
+ else if (ld_ws_tmr_short == 1'b1) begin
+ waitstate_timer <= WS_SIM ;
+ end
+ else if (waitstate_timer != 20'h00000) begin
+ waitstate_timer <= waitstate_timer - 20'h1 ;
+ end
+
+ if (ld_ws_tmr == 1'b1 | ld_ws_tmr_short) begin
+ ws_tmr_eq_0 <= 1'b0 ;
+ end
+ else if (waitstate_timer == 20'h00000) begin
+ ws_tmr_eq_0 <= 1'b1 ;
+ end
+ else begin
+ ws_tmr_eq_0 <= 1'b0 ;
+ end
+
+ case (serdes_rst_state)
+ STROBE_TXPLL_LOCKED_SD_CNT : begin
+ ld_ws_tmr <= 1'b0 ;
+ if ((pll_locked_sync == 1'b1) && (ws_tmr_eq_0 == 1'b1) && (pll_locked_stable==1'b1)) begin
+ serdes_rst_state <= (busy_altgxb_reconfig_r[1]==1'b1)?STROBE_TXPLL_LOCKED_SD_CNT:STABLE_TX_PLL_ST_CNT ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= (busy_altgxb_reconfig_r[1]==1'b1)?1'b1:1'b0;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ else begin
+ serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
+ txdigitalreset_r <= 1'b1 ;
+ rxanalogreset_r <= 1'b1 ;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ end
+ IDLE_ST_CNT : begin
+ if (rx_pll_freq_locked_sync_r == 1'b1) begin
+ if (fifo_err == 1'b1) begin
+ serdes_rst_state <= STABLE_TX_PLL_ST_CNT ;
+ end
+ else begin
+ serdes_rst_state <= IDLE_ST_CNT ;
+ end
+ end
+ else begin
+ serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
+ ld_ws_tmr <= 1'b1 ;
+ end
+ end
+ STABLE_TX_PLL_ST_CNT : begin
+ if (rx_pll_freq_locked_sync_r == 1'b1) begin
+ serdes_rst_state <= WAIT_STATE_ST_CNT ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b1 ;
+ ld_ws_tmr_short <= 1'b1 ;
+ end
+ else begin
+ serdes_rst_state <= STABLE_TX_PLL_ST_CNT ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ end
+ WAIT_STATE_ST_CNT : begin
+ if (rx_pll_freq_locked_sync_r == 1'b1) begin
+ ld_ws_tmr_short <= 1'b0 ;
+ if (ld_ws_tmr_short == 1'b0 & ws_tmr_eq_0 == 1'b1) begin
+ serdes_rst_state <= IDLE_ST_CNT ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b0 ;
+ end
+ else begin
+ serdes_rst_state <= WAIT_STATE_ST_CNT ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ end
+ else begin
+ serdes_rst_state <= STABLE_TX_PLL_ST_CNT ;
+ txdigitalreset_r <= 1'b0 ;
+ rxanalogreset_r <= 1'b0 ;
+ rxdigitalreset_r <= 1'b1 ;
+ end
+ end
+ default : begin
+ serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
+ waitstate_timer <= 20'hFFFFF ;
+ end
+ endcase
+ end
+ end
+
+////////////////////////////////////////////////////////////////
+//
+// Signal detect logic use suffix/prefix _sd
+//
+
+// rx_signaldetect strobing (stable_sd)
+ assign rst_rxpcs_sd = ((test_cbb_compliance==1'b1)||(use_c4gx_serdes==1'b1))?1'b0:sd_state[0];
+ always @(posedge pld_clk or posedge arst) begin
+ if (arst == 1'b1) begin
+ rx_sd_strb0[7:0] <= 8'h00;
+ rx_sd_strb1[7:0] <= 8'h00;
+ end
+ else begin
+ rx_sd_strb0[7:0] <= rx_signaldetect_sync[7:0];
+ rx_sd_strb1[7:0] <= rx_sd_strb0[7:0];
+ end
+ end
+ assign stable_sd = (rx_sd_strb1[7:0] == rx_sd_strb0[7:0]) & (rx_sd_strb1[7:0] != 8'h00);
+
+ //signal detect based reset logic
+ always @(posedge pld_clk or posedge arst) begin
+ if (arst == 1'b1) begin
+ rx_sd_idl_cnt <= 20'h0;
+ sd_state <= IDLE_ST_SD;
+ end
+ else begin
+ case (sd_state)
+
+ IDLE_ST_SD: begin
+ //reset RXPCS on polling.active
+ if (ltssm == LTSSM_POL) begin
+ rx_sd_idl_cnt <= (rx_sd_idl_cnt > 20'd10) ? rx_sd_idl_cnt - 20'd10 : 20'h0;
+ sd_state <= RSET_ST_SD;
+ end
+ else begin //Incoming signal unstable, clear counter
+ if (stable_sd == 1'b0) begin
+ rx_sd_idl_cnt <= 20'h0;
+ end
+ else if ((stable_sd == 1'b1) & (rx_sd_idl_cnt < 20'd750000)) begin
+ rx_sd_idl_cnt <= rx_sd_idl_cnt + 20'h1;
+ end
+ end
+ end
+
+ RSET_ST_SD: begin
+ //Incoming data unstable, back to IDLE_ST_SD iff in detect
+ if (stable_sd == 1'b0) begin
+ rx_sd_idl_cnt <= 20'h0;
+ sd_state <= (ltssm == LTSSM_DET) ? IDLE_ST_SD : RSET_ST_SD;
+ end
+ else begin
+ if ((test_sim == 1'b1) & (rx_sd_idl_cnt >= 20'd32)) begin
+ rx_sd_idl_cnt <= 20'd32;
+ sd_state <= DONE_ST_SD;
+ end
+ else begin
+ if (rx_sd_idl_cnt == 20'd750000) begin
+ rx_sd_idl_cnt <= 20'd750000;
+ sd_state <= DONE_ST_SD;
+ end
+ else if (stable_sd == 1'b1) begin
+ rx_sd_idl_cnt <= rx_sd_idl_cnt + 20'h1;
+ end
+ end
+ end
+ end
+
+ DONE_ST_SD: begin
+ //Incoming data unstable, back to IDLE_ST_SD iff in detect
+ if (stable_sd == 1'b0) begin
+ rx_sd_idl_cnt <= 20'h0;
+ sd_state <= (ltssm == LTSSM_DET) ? IDLE_ST_SD : DONE_ST_SD;
+ end
+ end
+
+ default: begin
+ rx_sd_idl_cnt <= 20'h0;
+ sd_state <= IDLE_ST_SD;
+ end
+
+ endcase
+ end
+ end
+
+endmodule
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v b/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v
new file mode 100644
index 0000000000000000000000000000000000000000..f74c1450103c7105e7dd3165dbdee85cb5f4abfc
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v
@@ -0,0 +1,407 @@
+// megafunction wizard: %ALTGXB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altgxb
+
+// ============================================================
+// File Name: altpcie_serdes_1sgx_x1_12500.v
+// Megafunction Name(s):
+// altgxb
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 176 10/26/2005 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_1sgx_x1_12500 (
+ inclk,
+ pll_areset,
+ pllenable,
+ rx_cruclk,
+ rx_enacdet,
+ rx_in,
+ rxanalogreset,
+ rxdigitalreset,
+ tx_coreclk,
+ tx_in,
+ txdigitalreset,
+ coreclk_out,
+ pll_locked,
+ rx_clkout,
+ rx_freqlocked,
+ rx_locked,
+ rx_out,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_out);
+
+ input [0:0] inclk;
+ input [0:0] pll_areset;
+ input [0:0] pllenable;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_enacdet;
+ input [0:0] rx_in;
+ input [0:0] rxanalogreset;
+ input [0:0] rxdigitalreset;
+ input [0:0] tx_coreclk;
+ input [19:0] tx_in;
+ input [0:0] txdigitalreset;
+ output [0:0] coreclk_out;
+ output [0:0] pll_locked;
+ output [0:0] rx_clkout;
+ output [0:0] rx_freqlocked;
+ output [0:0] rx_locked;
+ output [19:0] rx_out;
+ output [1:0] rx_patterndetect;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_out;
+
+ wire [1:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [19:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [1:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [1:0] rx_patterndetect = sub_wire0[1:0];
+ wire [0:0] tx_out = sub_wire1[0:0];
+ wire [19:0] rx_out = sub_wire2[19:0];
+ wire [0:0] coreclk_out = sub_wire3[0:0];
+ wire [0:0] rx_locked = sub_wire4[0:0];
+ wire [0:0] rx_freqlocked = sub_wire5[0:0];
+ wire [0:0] rx_clkout = sub_wire6[0:0];
+ wire [1:0] rx_syncstatus = sub_wire7[1:0];
+ wire [0:0] pll_locked = sub_wire8[0:0];
+
+ altgxb altgxb_component (
+ .pll_areset (pll_areset),
+ .rx_enacdet (rx_enacdet),
+ .rx_cruclk (rx_cruclk),
+ .pllenable (pllenable),
+ .inclk (inclk),
+ .rx_in (rx_in),
+ .tx_in (tx_in),
+ .rxanalogreset (rxanalogreset),
+ .tx_coreclk (tx_coreclk),
+ .rxdigitalreset (rxdigitalreset),
+ .txdigitalreset (txdigitalreset),
+ .rx_patterndetect (sub_wire0),
+ .tx_out (sub_wire1),
+ .rx_out (sub_wire2),
+ .coreclk_out (sub_wire3),
+ .rx_locked (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .rx_clkout (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .pll_locked (sub_wire8)
+ // synopsys translate_off
+ ,
+ .rx_we (),
+ .rx_coreclk (),
+ .rx_channelaligned (),
+ .rx_bisterr (),
+ .rx_slpbk (),
+ .rx_aclr (),
+ .rx_fifoalmostempty (),
+ .tx_aclr (),
+ .rx_bistdone (),
+ .rx_signaldetect (),
+ .tx_forcedisparity (),
+ .tx_vodctrl (),
+ .rx_equalizerctrl (),
+ .rx_a1a2size (),
+ .tx_srlpbk (),
+ .rx_errdetect (),
+ .rx_re (),
+ .rx_disperr (),
+ .rx_locktodata (),
+ .tx_preemphasisctrl (),
+ .rx_rlv (),
+ .rx_fifoalmostfull (),
+ .rx_bitslip (),
+ .rx_a1a2sizeout (),
+ .rx_locktorefclk (),
+ .rx_ctrldetect (),
+ .tx_ctrlenable ()
+ // synopsys translate_on
+ );
+ defparam
+ altgxb_component.align_pattern = "P0101111100",
+ altgxb_component.align_pattern_length = 10,
+ altgxb_component.allow_gxb_merging = "OFF",
+ altgxb_component.channel_width = 20,
+ altgxb_component.clk_out_mode_reference = "ON",
+ altgxb_component.consider_enable_tx_8b_10b_i1i2_generation = "ON",
+ altgxb_component.consider_instantiate_transmitter_pll_param = "ON",
+ altgxb_component.cru_inclock_period = 8000,
+ altgxb_component.data_rate = 2500,
+ altgxb_component.data_rate_remainder = 0,
+ altgxb_component.disparity_mode = "ON",
+ altgxb_component.dwidth_factor = 2,
+ altgxb_component.enable_tx_8b_10b_i1i2_generation = "OFF",
+ altgxb_component.equalizer_ctrl_setting = 20,
+ altgxb_component.flip_rx_out = "OFF",
+ altgxb_component.flip_tx_in = "OFF",
+ altgxb_component.force_disparity_mode = "OFF",
+ altgxb_component.for_engineering_sample_device = "OFF",
+ altgxb_component.instantiate_transmitter_pll = "ON",
+ altgxb_component.intended_device_family = "Stratix GX",
+ altgxb_component.loopback_mode = "NONE",
+ altgxb_component.lpm_type = "altgxb",
+ altgxb_component.number_of_channels = 1,
+ altgxb_component.number_of_quads = 1,
+ altgxb_component.operation_mode = "DUPLEX",
+ altgxb_component.pll_bandwidth_type = "LOW",
+ altgxb_component.pll_inclock_period = 8000,
+ altgxb_component.preemphasis_ctrl_setting = 10,
+ altgxb_component.protocol = "CUSTOM",
+ altgxb_component.reverse_loopback_mode = "NONE",
+ altgxb_component.run_length_enable = "OFF",
+ altgxb_component.rx_bandwidth_type = "NEW_LOW",
+ altgxb_component.rx_data_rate = 2500,
+ altgxb_component.rx_data_rate_remainder = 0,
+ altgxb_component.rx_enable_dc_coupling = "OFF",
+ altgxb_component.rx_force_signal_detect = "ON",
+ altgxb_component.rx_ppm_setting = 1000,
+ altgxb_component.signal_threshold_select = 530,
+ altgxb_component.tx_termination = 2,
+ altgxb_component.use_8b_10b_mode = "OFF",
+ altgxb_component.use_auto_bit_slip = "ON",
+ altgxb_component.use_channel_align = "OFF",
+ altgxb_component.use_double_data_mode = "ON",
+ altgxb_component.use_equalizer_ctrl_signal = "OFF",
+ altgxb_component.use_generic_fifo = "OFF",
+ altgxb_component.use_preemphasis_ctrl_signal = "OFF",
+ altgxb_component.use_rate_match_fifo = "OFF",
+ altgxb_component.use_rx_clkout = "ON",
+ altgxb_component.use_rx_coreclk = "OFF",
+ altgxb_component.use_rx_cruclk = "ON",
+ altgxb_component.use_self_test_mode = "OFF",
+ altgxb_component.use_symbol_align = "ON",
+ altgxb_component.use_tx_coreclk = "ON",
+ altgxb_component.use_vod_ctrl_signal = "OFF",
+ altgxb_component.vod_ctrl_setting = 800;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADD_GENERIC_FIFO_WE_SYNCH_REGISTER STRING "0"
+// Retrieval info: PRIVATE: ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: PRIVATE: ALIGN_PATTERN_LENGTH STRING "10"
+// Retrieval info: PRIVATE: CHANNEL_WIDTH STRING "20"
+// Retrieval info: PRIVATE: CLK_OUT_MODE_REFERENCE STRING "1"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "0"
+// Retrieval info: PRIVATE: EQU_SETTING STRING "2"
+// Retrieval info: PRIVATE: FLIP_ALIGN_PATTERN STRING "0"
+// Retrieval info: PRIVATE: FLIP_RX_OUT STRING "0"
+// Retrieval info: PRIVATE: FLIP_TX_IN STRING "0"
+// Retrieval info: PRIVATE: FOR_ENGINEERING_SAMPLE_DEVICE STRING "0"
+// Retrieval info: PRIVATE: GXB_QUAD_MERGE STRING "0"
+// Retrieval info: PRIVATE: INFINIBAND_INVALID_CODE STRING "0"
+// Retrieval info: PRIVATE: INSTANTIATE_TRANSMITTER_PLL STRING "1"
+// Retrieval info: PRIVATE: LOOPBACK_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;pll_areset;rx_in;rx_coreclk;rx_cruclk"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "rx_aclr;rx_bitslip;rx_enacdet;rx_we;rx_re"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "rx_slpbk;rx_a1a2size;rx_equalizerctrl;rx_locktorefclk;rx_locktodata"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "tx_in;tx_coreclk;tx_aclr;tx_ctrlenable;tx_forcedisparity"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "tx_srlpbk;tx_vodctrl;tx_preemphasisctrl;txdigitalreset;rxdigitalreset"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_5 STRING "rxanalogreset;pllenable;pll_locked;coreclk_out;rx_out"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_6 STRING "rx_clkout;rx_locked;rx_freqlocked;rx_rlv;rx_syncstatus"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_7 STRING "rx_patterndetect;rx_ctrldetect;rx_errdetect;rx_disperr;rx_signaldetect"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_8 STRING "rx_fifoalmostempty;rx_fifoalmostfull;rx_channelaligned;rx_bisterr;rx_bistdone"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_9 STRING "rx_a1a2sizeout;tx_out"
+// Retrieval info: PRIVATE: NUMBER_OF_CHANNELS STRING "1"
+// Retrieval info: PRIVATE: OP_MODE STRING "Duplex"
+// Retrieval info: PRIVATE: PLL_ACLR STRING "1"
+// Retrieval info: PRIVATE: PLL_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: PRIVATE: PLL_DC_COUPLING STRING "1"
+// Retrieval info: PRIVATE: PLL_ENABLE STRING "1"
+// Retrieval info: PRIVATE: PLL_LOCKED STRING "1"
+// Retrieval info: PRIVATE: PREEMPHASIS_SETTING STRING "2"
+// Retrieval info: PRIVATE: PREEMPHASIS_SIGNAL STRING "0"
+// Retrieval info: PRIVATE: PROTOCOL STRING "CUSTOM"
+// Retrieval info: PRIVATE: REVERSE_LOOPBACK_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: RLV STRING "5"
+// Retrieval info: PRIVATE: RX_A1A2 STRING "0"
+// Retrieval info: PRIVATE: RX_A1A2SIZEOUT STRING "0"
+// Retrieval info: PRIVATE: RX_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: PRIVATE: RX_BASE_INPUT_TYPE STRING ""
+// Retrieval info: PRIVATE: RX_BISTDONE STRING "0"
+// Retrieval info: PRIVATE: RX_BISTERR STRING "0"
+// Retrieval info: PRIVATE: RX_BITSLIP STRING "0"
+// Retrieval info: PRIVATE: RX_CLKOUT STRING "1"
+// Retrieval info: PRIVATE: RX_CLR STRING "1"
+// Retrieval info: PRIVATE: RX_CTRLDETECT STRING "0"
+// Retrieval info: PRIVATE: RX_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: RX_DISPERR STRING "0"
+// Retrieval info: PRIVATE: RX_ENACDET STRING "1"
+// Retrieval info: PRIVATE: RX_ERRDETECT STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOALMOSTEMPTY STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOALMOSTFULL STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOEMPTY STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOFULL STRING "0"
+// Retrieval info: PRIVATE: RX_FORCE_SIGNAL_DETECT STRING "1"
+// Retrieval info: PRIVATE: RX_FREQLOCKED STRING "1"
+// Retrieval info: PRIVATE: RX_FREQUENCY STRING "125.0000"
+// Retrieval info: PRIVATE: RX_LOCKED STRING "1"
+// Retrieval info: PRIVATE: RX_LOCKTODATA STRING "0"
+// Retrieval info: PRIVATE: RX_LOCKTOREFCLK STRING "0"
+// Retrieval info: PRIVATE: RX_PATTERNDETECT STRING "1"
+// Retrieval info: PRIVATE: RX_PPM_SETTING STRING "1000"
+// Retrieval info: PRIVATE: RX_SIGDET STRING "0"
+// Retrieval info: PRIVATE: RX_SYNCSTATUS STRING "1"
+// Retrieval info: PRIVATE: SELF_TEST_MODE NUMERIC "-1"
+// Retrieval info: PRIVATE: SIGNAL_THRESHOLD_SELECT STRING "530"
+// Retrieval info: PRIVATE: TX_BASE_INPUT_TYPE STRING ""
+// Retrieval info: PRIVATE: TX_CLR STRING "1"
+// Retrieval info: PRIVATE: TX_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: TX_FORCE_DISPARITY STRING "0"
+// Retrieval info: PRIVATE: TX_FREQUENCY STRING "125.0000"
+// Retrieval info: PRIVATE: TX_PLL_LOCKED STRING "1"
+// Retrieval info: PRIVATE: TX_TERMINATION STRING "100"
+// Retrieval info: PRIVATE: USE_8B10B_DECODER STRING "0"
+// Retrieval info: PRIVATE: USE_8B10B_ENCODER STRING "0"
+// Retrieval info: PRIVATE: USE_8B_10B_MODE STRING "OFF"
+// Retrieval info: PRIVATE: USE_AUTO_BIT_SLIP NUMERIC "1"
+// Retrieval info: PRIVATE: USE_CRUCLK_FROM_PLL STRING "1"
+// Retrieval info: PRIVATE: USE_DC_COUPLING STRING "0"
+// Retrieval info: PRIVATE: USE_EQUALIZER STRING "0"
+// Retrieval info: PRIVATE: USE_EXTERNAL_TX_TERMINATION STRING "0"
+// Retrieval info: PRIVATE: USE_GENERIC_FIFO STRING "0"
+// Retrieval info: PRIVATE: USE_RATE_MATCH_FIFO STRING "0"
+// Retrieval info: PRIVATE: USE_RLV STRING "0"
+// Retrieval info: PRIVATE: USE_RX_CORECLK STRING "0"
+// Retrieval info: PRIVATE: USE_RX_CRUCLK STRING "1"
+// Retrieval info: PRIVATE: USE_TX_CORECLK STRING "1"
+// Retrieval info: PRIVATE: VERSION STRING "4.0"
+// Retrieval info: PRIVATE: VOD_SETTING STRING "800"
+// Retrieval info: PRIVATE: VOD_SIGNAL STRING "0"
+// Retrieval info: PRIVATE: XGM_RXANALOGRESET STRING "1"
+// Retrieval info: LIBRARY: altgxb altgxb.all
+// Retrieval info: CONSTANT: ALIGN_PATTERN STRING "P0101111100"
+// Retrieval info: CONSTANT: ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: ALLOW_GXB_MERGING STRING "OFF"
+// Retrieval info: CONSTANT: CHANNEL_WIDTH NUMERIC "20"
+// Retrieval info: CONSTANT: CLK_OUT_MODE_REFERENCE STRING "ON"
+// Retrieval info: CONSTANT: CONSIDER_ENABLE_TX_8B_10B_I1I2_GENERATION STRING "ON"
+// Retrieval info: CONSTANT: CONSIDER_INSTANTIATE_TRANSMITTER_PLL_PARAM STRING "ON"
+// Retrieval info: CONSTANT: CRU_INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: DISPARITY_MODE STRING "ON"
+// Retrieval info: CONSTANT: DWIDTH_FACTOR NUMERIC "2"
+// Retrieval info: CONSTANT: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "OFF"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_SETTING NUMERIC "20"
+// Retrieval info: CONSTANT: FLIP_RX_OUT STRING "OFF"
+// Retrieval info: CONSTANT: FLIP_TX_IN STRING "OFF"
+// Retrieval info: CONSTANT: FORCE_DISPARITY_MODE STRING "OFF"
+// Retrieval info: CONSTANT: FOR_ENGINEERING_SAMPLE_DEVICE STRING "OFF"
+// Retrieval info: CONSTANT: INSTANTIATE_TRANSMITTER_PLL STRING "ON"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "NONE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altgxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: NUMBER_OF_QUADS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUPLEX"
+// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: PLL_INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_SETTING NUMERIC "10"
+// Retrieval info: CONSTANT: PROTOCOL STRING "CUSTOM"
+// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RUN_LENGTH_ENABLE STRING "OFF"
+// Retrieval info: CONSTANT: RX_BANDWIDTH_TYPE STRING "NEW_LOW"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_ENABLE_DC_COUPLING STRING "OFF"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "ON"
+// Retrieval info: CONSTANT: RX_PPM_SETTING NUMERIC "1000"
+// Retrieval info: CONSTANT: SIGNAL_THRESHOLD_SELECT NUMERIC "530"
+// Retrieval info: CONSTANT: TX_TERMINATION NUMERIC "2"
+// Retrieval info: CONSTANT: USE_8B_10B_MODE STRING "OFF"
+// Retrieval info: CONSTANT: USE_AUTO_BIT_SLIP STRING "ON"
+// Retrieval info: CONSTANT: USE_CHANNEL_ALIGN STRING "OFF"
+// Retrieval info: CONSTANT: USE_DOUBLE_DATA_MODE STRING "ON"
+// Retrieval info: CONSTANT: USE_EQUALIZER_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: USE_GENERIC_FIFO STRING "OFF"
+// Retrieval info: CONSTANT: USE_PREEMPHASIS_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: USE_RATE_MATCH_FIFO STRING "OFF"
+// Retrieval info: CONSTANT: USE_RX_CLKOUT STRING "ON"
+// Retrieval info: CONSTANT: USE_RX_CORECLK STRING "OFF"
+// Retrieval info: CONSTANT: USE_RX_CRUCLK STRING "ON"
+// Retrieval info: CONSTANT: USE_SELF_TEST_MODE STRING "OFF"
+// Retrieval info: CONSTANT: USE_SYMBOL_ALIGN STRING "ON"
+// Retrieval info: CONSTANT: USE_TX_CORECLK STRING "ON"
+// Retrieval info: CONSTANT: USE_VOD_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "800"
+// Retrieval info: USED_PORT: coreclk_out 0 0 1 0 OUTPUT NODEFVAL "coreclk_out[0..0]"
+// Retrieval info: USED_PORT: inclk 0 0 1 0 INPUT GND "inclk[0..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT GND "pll_areset[0..0]"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: pllenable 0 0 1 0 INPUT VCC "pllenable[0..0]"
+// Retrieval info: USED_PORT: rx_clkout 0 0 1 0 OUTPUT NODEFVAL "rx_clkout[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_enacdet 0 0 1 0 INPUT GND "rx_enacdet[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT GND "rx_in[0..0]"
+// Retrieval info: USED_PORT: rx_locked 0 0 1 0 OUTPUT NODEFVAL "rx_locked[0..0]"
+// Retrieval info: USED_PORT: rx_out 0 0 20 0 OUTPUT NODEFVAL "rx_out[19..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
+// Retrieval info: USED_PORT: rxanalogreset 0 0 1 0 INPUT GND "rxanalogreset[0..0]"
+// Retrieval info: USED_PORT: rxdigitalreset 0 0 1 0 INPUT GND "rxdigitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_coreclk 0 0 1 0 INPUT GND "tx_coreclk[0..0]"
+// Retrieval info: USED_PORT: tx_in 0 0 20 0 INPUT GND "tx_in[19..0]"
+// Retrieval info: USED_PORT: tx_out 0 0 1 0 OUTPUT NODEFVAL "tx_out[0..0]"
+// Retrieval info: USED_PORT: txdigitalreset 0 0 1 0 INPUT GND "txdigitalreset[0..0]"
+// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
+// Retrieval info: CONNECT: @pllenable 0 0 1 0 pllenable 0 0 1 0
+// Retrieval info: CONNECT: rx_locked 0 0 1 0 @rx_locked 0 0 1 0
+// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
+// Retrieval info: CONNECT: @txdigitalreset 0 0 1 0 txdigitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_in 0 0 1 0 rx_in 0 0 1 0
+// Retrieval info: CONNECT: coreclk_out 0 0 1 0 @coreclk_out 0 0 1 0
+// Retrieval info: CONNECT: @tx_coreclk 0 0 1 0 tx_coreclk 0 0 1 0
+// Retrieval info: CONNECT: tx_out 0 0 1 0 @tx_out 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
+// Retrieval info: CONNECT: rx_out 0 0 20 0 @rx_out 0 0 20 0
+// Retrieval info: CONNECT: rx_clkout 0 0 1 0 @rx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rxdigitalreset 0 0 1 0 rxdigitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rxanalogreset 0 0 1 0 rxanalogreset 0 0 1 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: @rx_enacdet 0 0 1 0 rx_enacdet 0 0 1 0
+// Retrieval info: CONNECT: @tx_in 0 0 20 0 tx_in 0 0 20 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_12500.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_12500.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_12500.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_12500.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_12500_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_12500_bb.v FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v b/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v
new file mode 100644
index 0000000000000000000000000000000000000000..ea95b70bc2be910051f6c4dede52bfa7a55a97e5
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v
@@ -0,0 +1,407 @@
+// megafunction wizard: %ALTGXB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altgxb
+
+// ============================================================
+// File Name: altpcie_serdes_1sgx_x1_15625.v
+// Megafunction Name(s):
+// altgxb
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 176 10/26/2005 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_1sgx_x1_15625 (
+ inclk,
+ pll_areset,
+ pllenable,
+ rx_cruclk,
+ rx_enacdet,
+ rx_in,
+ rxanalogreset,
+ rxdigitalreset,
+ tx_coreclk,
+ tx_in,
+ txdigitalreset,
+ coreclk_out,
+ pll_locked,
+ rx_clkout,
+ rx_freqlocked,
+ rx_locked,
+ rx_out,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_out);
+
+ input [0:0] inclk;
+ input [0:0] pll_areset;
+ input [0:0] pllenable;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_enacdet;
+ input [0:0] rx_in;
+ input [0:0] rxanalogreset;
+ input [0:0] rxdigitalreset;
+ input [0:0] tx_coreclk;
+ input [19:0] tx_in;
+ input [0:0] txdigitalreset;
+ output [0:0] coreclk_out;
+ output [0:0] pll_locked;
+ output [0:0] rx_clkout;
+ output [0:0] rx_freqlocked;
+ output [0:0] rx_locked;
+ output [19:0] rx_out;
+ output [1:0] rx_patterndetect;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_out;
+
+ wire [1:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [19:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [1:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [1:0] rx_patterndetect = sub_wire0[1:0];
+ wire [0:0] tx_out = sub_wire1[0:0];
+ wire [19:0] rx_out = sub_wire2[19:0];
+ wire [0:0] coreclk_out = sub_wire3[0:0];
+ wire [0:0] rx_locked = sub_wire4[0:0];
+ wire [0:0] rx_freqlocked = sub_wire5[0:0];
+ wire [0:0] rx_clkout = sub_wire6[0:0];
+ wire [1:0] rx_syncstatus = sub_wire7[1:0];
+ wire [0:0] pll_locked = sub_wire8[0:0];
+
+ altgxb altgxb_component (
+ .pll_areset (pll_areset),
+ .rx_enacdet (rx_enacdet),
+ .rx_cruclk (rx_cruclk),
+ .pllenable (pllenable),
+ .inclk (inclk),
+ .rx_in (rx_in),
+ .tx_in (tx_in),
+ .rxanalogreset (rxanalogreset),
+ .tx_coreclk (tx_coreclk),
+ .rxdigitalreset (rxdigitalreset),
+ .txdigitalreset (txdigitalreset),
+ .rx_patterndetect (sub_wire0),
+ .tx_out (sub_wire1),
+ .rx_out (sub_wire2),
+ .coreclk_out (sub_wire3),
+ .rx_locked (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .rx_clkout (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .pll_locked (sub_wire8)
+ // synopsys translate_off
+ ,
+ .rx_we (),
+ .rx_coreclk (),
+ .rx_channelaligned (),
+ .rx_bisterr (),
+ .rx_slpbk (),
+ .rx_aclr (),
+ .rx_fifoalmostempty (),
+ .tx_aclr (),
+ .rx_bistdone (),
+ .rx_signaldetect (),
+ .tx_forcedisparity (),
+ .tx_vodctrl (),
+ .rx_equalizerctrl (),
+ .rx_a1a2size (),
+ .tx_srlpbk (),
+ .rx_errdetect (),
+ .rx_re (),
+ .rx_disperr (),
+ .rx_locktodata (),
+ .tx_preemphasisctrl (),
+ .rx_rlv (),
+ .rx_fifoalmostfull (),
+ .rx_bitslip (),
+ .rx_a1a2sizeout (),
+ .rx_locktorefclk (),
+ .rx_ctrldetect (),
+ .tx_ctrlenable ()
+ // synopsys translate_on
+ );
+ defparam
+ altgxb_component.align_pattern = "P0101111100",
+ altgxb_component.align_pattern_length = 10,
+ altgxb_component.allow_gxb_merging = "OFF",
+ altgxb_component.channel_width = 20,
+ altgxb_component.clk_out_mode_reference = "ON",
+ altgxb_component.consider_enable_tx_8b_10b_i1i2_generation = "ON",
+ altgxb_component.consider_instantiate_transmitter_pll_param = "ON",
+ altgxb_component.cru_inclock_period = 6400,
+ altgxb_component.data_rate = 2500,
+ altgxb_component.data_rate_remainder = 0,
+ altgxb_component.disparity_mode = "ON",
+ altgxb_component.dwidth_factor = 2,
+ altgxb_component.enable_tx_8b_10b_i1i2_generation = "OFF",
+ altgxb_component.equalizer_ctrl_setting = 20,
+ altgxb_component.flip_rx_out = "OFF",
+ altgxb_component.flip_tx_in = "OFF",
+ altgxb_component.force_disparity_mode = "OFF",
+ altgxb_component.for_engineering_sample_device = "OFF",
+ altgxb_component.instantiate_transmitter_pll = "ON",
+ altgxb_component.intended_device_family = "Stratix GX",
+ altgxb_component.loopback_mode = "NONE",
+ altgxb_component.lpm_type = "altgxb",
+ altgxb_component.number_of_channels = 1,
+ altgxb_component.number_of_quads = 1,
+ altgxb_component.operation_mode = "DUPLEX",
+ altgxb_component.pll_bandwidth_type = "LOW",
+ altgxb_component.pll_inclock_period = 6400,
+ altgxb_component.preemphasis_ctrl_setting = 10,
+ altgxb_component.protocol = "CUSTOM",
+ altgxb_component.reverse_loopback_mode = "NONE",
+ altgxb_component.run_length_enable = "OFF",
+ altgxb_component.rx_bandwidth_type = "NEW_LOW",
+ altgxb_component.rx_data_rate = 2500,
+ altgxb_component.rx_data_rate_remainder = 0,
+ altgxb_component.rx_enable_dc_coupling = "OFF",
+ altgxb_component.rx_force_signal_detect = "ON",
+ altgxb_component.rx_ppm_setting = 1000,
+ altgxb_component.signal_threshold_select = 530,
+ altgxb_component.tx_termination = 2,
+ altgxb_component.use_8b_10b_mode = "OFF",
+ altgxb_component.use_auto_bit_slip = "ON",
+ altgxb_component.use_channel_align = "OFF",
+ altgxb_component.use_double_data_mode = "ON",
+ altgxb_component.use_equalizer_ctrl_signal = "OFF",
+ altgxb_component.use_generic_fifo = "OFF",
+ altgxb_component.use_preemphasis_ctrl_signal = "OFF",
+ altgxb_component.use_rate_match_fifo = "OFF",
+ altgxb_component.use_rx_clkout = "ON",
+ altgxb_component.use_rx_coreclk = "OFF",
+ altgxb_component.use_rx_cruclk = "ON",
+ altgxb_component.use_self_test_mode = "OFF",
+ altgxb_component.use_symbol_align = "ON",
+ altgxb_component.use_tx_coreclk = "ON",
+ altgxb_component.use_vod_ctrl_signal = "OFF",
+ altgxb_component.vod_ctrl_setting = 800;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADD_GENERIC_FIFO_WE_SYNCH_REGISTER STRING "0"
+// Retrieval info: PRIVATE: ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: PRIVATE: ALIGN_PATTERN_LENGTH STRING "10"
+// Retrieval info: PRIVATE: CHANNEL_WIDTH STRING "20"
+// Retrieval info: PRIVATE: CLK_OUT_MODE_REFERENCE STRING "1"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "0"
+// Retrieval info: PRIVATE: EQU_SETTING STRING "2"
+// Retrieval info: PRIVATE: FLIP_ALIGN_PATTERN STRING "0"
+// Retrieval info: PRIVATE: FLIP_RX_OUT STRING "0"
+// Retrieval info: PRIVATE: FLIP_TX_IN STRING "0"
+// Retrieval info: PRIVATE: FOR_ENGINEERING_SAMPLE_DEVICE STRING "0"
+// Retrieval info: PRIVATE: GXB_QUAD_MERGE STRING "0"
+// Retrieval info: PRIVATE: INFINIBAND_INVALID_CODE STRING "0"
+// Retrieval info: PRIVATE: INSTANTIATE_TRANSMITTER_PLL STRING "1"
+// Retrieval info: PRIVATE: LOOPBACK_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;pll_areset;rx_in;rx_coreclk;rx_cruclk"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "rx_aclr;rx_bitslip;rx_enacdet;rx_we;rx_re"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "rx_slpbk;rx_a1a2size;rx_equalizerctrl;rx_locktorefclk;rx_locktodata"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "tx_in;tx_coreclk;tx_aclr;tx_ctrlenable;tx_forcedisparity"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "tx_srlpbk;tx_vodctrl;tx_preemphasisctrl;txdigitalreset;rxdigitalreset"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_5 STRING "rxanalogreset;pllenable;pll_locked;coreclk_out;rx_out"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_6 STRING "rx_clkout;rx_locked;rx_freqlocked;rx_rlv;rx_syncstatus"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_7 STRING "rx_patterndetect;rx_ctrldetect;rx_errdetect;rx_disperr;rx_signaldetect"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_8 STRING "rx_fifoalmostempty;rx_fifoalmostfull;rx_channelaligned;rx_bisterr;rx_bistdone"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_9 STRING "rx_a1a2sizeout;tx_out"
+// Retrieval info: PRIVATE: NUMBER_OF_CHANNELS STRING "1"
+// Retrieval info: PRIVATE: OP_MODE STRING "Duplex"
+// Retrieval info: PRIVATE: PLL_ACLR STRING "1"
+// Retrieval info: PRIVATE: PLL_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: PRIVATE: PLL_DC_COUPLING STRING "1"
+// Retrieval info: PRIVATE: PLL_ENABLE STRING "1"
+// Retrieval info: PRIVATE: PLL_LOCKED STRING "1"
+// Retrieval info: PRIVATE: PREEMPHASIS_SETTING STRING "2"
+// Retrieval info: PRIVATE: PREEMPHASIS_SIGNAL STRING "0"
+// Retrieval info: PRIVATE: PROTOCOL STRING "CUSTOM"
+// Retrieval info: PRIVATE: REVERSE_LOOPBACK_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: RLV STRING "5"
+// Retrieval info: PRIVATE: RX_A1A2 STRING "0"
+// Retrieval info: PRIVATE: RX_A1A2SIZEOUT STRING "0"
+// Retrieval info: PRIVATE: RX_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: PRIVATE: RX_BASE_INPUT_TYPE STRING ""
+// Retrieval info: PRIVATE: RX_BISTDONE STRING "0"
+// Retrieval info: PRIVATE: RX_BISTERR STRING "0"
+// Retrieval info: PRIVATE: RX_BITSLIP STRING "0"
+// Retrieval info: PRIVATE: RX_CLKOUT STRING "1"
+// Retrieval info: PRIVATE: RX_CLR STRING "1"
+// Retrieval info: PRIVATE: RX_CTRLDETECT STRING "0"
+// Retrieval info: PRIVATE: RX_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: RX_DISPERR STRING "0"
+// Retrieval info: PRIVATE: RX_ENACDET STRING "1"
+// Retrieval info: PRIVATE: RX_ERRDETECT STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOALMOSTEMPTY STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOALMOSTFULL STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOEMPTY STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOFULL STRING "0"
+// Retrieval info: PRIVATE: RX_FORCE_SIGNAL_DETECT STRING "1"
+// Retrieval info: PRIVATE: RX_FREQLOCKED STRING "1"
+// Retrieval info: PRIVATE: RX_FREQUENCY STRING "156.25"
+// Retrieval info: PRIVATE: RX_LOCKED STRING "1"
+// Retrieval info: PRIVATE: RX_LOCKTODATA STRING "0"
+// Retrieval info: PRIVATE: RX_LOCKTOREFCLK STRING "0"
+// Retrieval info: PRIVATE: RX_PATTERNDETECT STRING "1"
+// Retrieval info: PRIVATE: RX_PPM_SETTING STRING "1000"
+// Retrieval info: PRIVATE: RX_SIGDET STRING "0"
+// Retrieval info: PRIVATE: RX_SYNCSTATUS STRING "1"
+// Retrieval info: PRIVATE: SELF_TEST_MODE NUMERIC "-1"
+// Retrieval info: PRIVATE: SIGNAL_THRESHOLD_SELECT STRING "530"
+// Retrieval info: PRIVATE: TX_BASE_INPUT_TYPE STRING ""
+// Retrieval info: PRIVATE: TX_CLR STRING "1"
+// Retrieval info: PRIVATE: TX_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: TX_FORCE_DISPARITY STRING "0"
+// Retrieval info: PRIVATE: TX_FREQUENCY STRING "156.25"
+// Retrieval info: PRIVATE: TX_PLL_LOCKED STRING "1"
+// Retrieval info: PRIVATE: TX_TERMINATION STRING "100"
+// Retrieval info: PRIVATE: USE_8B10B_DECODER STRING "0"
+// Retrieval info: PRIVATE: USE_8B10B_ENCODER STRING "0"
+// Retrieval info: PRIVATE: USE_8B_10B_MODE STRING "OFF"
+// Retrieval info: PRIVATE: USE_AUTO_BIT_SLIP NUMERIC "1"
+// Retrieval info: PRIVATE: USE_CRUCLK_FROM_PLL STRING "1"
+// Retrieval info: PRIVATE: USE_DC_COUPLING STRING "0"
+// Retrieval info: PRIVATE: USE_EQUALIZER STRING "0"
+// Retrieval info: PRIVATE: USE_EXTERNAL_TX_TERMINATION STRING "0"
+// Retrieval info: PRIVATE: USE_GENERIC_FIFO STRING "0"
+// Retrieval info: PRIVATE: USE_RATE_MATCH_FIFO STRING "0"
+// Retrieval info: PRIVATE: USE_RLV STRING "0"
+// Retrieval info: PRIVATE: USE_RX_CORECLK STRING "0"
+// Retrieval info: PRIVATE: USE_RX_CRUCLK STRING "1"
+// Retrieval info: PRIVATE: USE_TX_CORECLK STRING "1"
+// Retrieval info: PRIVATE: VERSION STRING "4.0"
+// Retrieval info: PRIVATE: VOD_SETTING STRING "800"
+// Retrieval info: PRIVATE: VOD_SIGNAL STRING "0"
+// Retrieval info: PRIVATE: XGM_RXANALOGRESET STRING "1"
+// Retrieval info: LIBRARY: altgxb altgxb.all
+// Retrieval info: CONSTANT: ALIGN_PATTERN STRING "P0101111100"
+// Retrieval info: CONSTANT: ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: ALLOW_GXB_MERGING STRING "OFF"
+// Retrieval info: CONSTANT: CHANNEL_WIDTH NUMERIC "20"
+// Retrieval info: CONSTANT: CLK_OUT_MODE_REFERENCE STRING "ON"
+// Retrieval info: CONSTANT: CONSIDER_ENABLE_TX_8B_10B_I1I2_GENERATION STRING "ON"
+// Retrieval info: CONSTANT: CONSIDER_INSTANTIATE_TRANSMITTER_PLL_PARAM STRING "ON"
+// Retrieval info: CONSTANT: CRU_INCLOCK_PERIOD NUMERIC "6400"
+// Retrieval info: CONSTANT: DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: DISPARITY_MODE STRING "ON"
+// Retrieval info: CONSTANT: DWIDTH_FACTOR NUMERIC "2"
+// Retrieval info: CONSTANT: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "OFF"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_SETTING NUMERIC "20"
+// Retrieval info: CONSTANT: FLIP_RX_OUT STRING "OFF"
+// Retrieval info: CONSTANT: FLIP_TX_IN STRING "OFF"
+// Retrieval info: CONSTANT: FORCE_DISPARITY_MODE STRING "OFF"
+// Retrieval info: CONSTANT: FOR_ENGINEERING_SAMPLE_DEVICE STRING "OFF"
+// Retrieval info: CONSTANT: INSTANTIATE_TRANSMITTER_PLL STRING "ON"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "NONE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altgxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: NUMBER_OF_QUADS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUPLEX"
+// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: PLL_INCLOCK_PERIOD NUMERIC "6400"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_SETTING NUMERIC "10"
+// Retrieval info: CONSTANT: PROTOCOL STRING "CUSTOM"
+// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RUN_LENGTH_ENABLE STRING "OFF"
+// Retrieval info: CONSTANT: RX_BANDWIDTH_TYPE STRING "NEW_LOW"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_ENABLE_DC_COUPLING STRING "OFF"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "ON"
+// Retrieval info: CONSTANT: RX_PPM_SETTING NUMERIC "1000"
+// Retrieval info: CONSTANT: SIGNAL_THRESHOLD_SELECT NUMERIC "530"
+// Retrieval info: CONSTANT: TX_TERMINATION NUMERIC "2"
+// Retrieval info: CONSTANT: USE_8B_10B_MODE STRING "OFF"
+// Retrieval info: CONSTANT: USE_AUTO_BIT_SLIP STRING "ON"
+// Retrieval info: CONSTANT: USE_CHANNEL_ALIGN STRING "OFF"
+// Retrieval info: CONSTANT: USE_DOUBLE_DATA_MODE STRING "ON"
+// Retrieval info: CONSTANT: USE_EQUALIZER_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: USE_GENERIC_FIFO STRING "OFF"
+// Retrieval info: CONSTANT: USE_PREEMPHASIS_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: USE_RATE_MATCH_FIFO STRING "OFF"
+// Retrieval info: CONSTANT: USE_RX_CLKOUT STRING "ON"
+// Retrieval info: CONSTANT: USE_RX_CORECLK STRING "OFF"
+// Retrieval info: CONSTANT: USE_RX_CRUCLK STRING "ON"
+// Retrieval info: CONSTANT: USE_SELF_TEST_MODE STRING "OFF"
+// Retrieval info: CONSTANT: USE_SYMBOL_ALIGN STRING "ON"
+// Retrieval info: CONSTANT: USE_TX_CORECLK STRING "ON"
+// Retrieval info: CONSTANT: USE_VOD_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "800"
+// Retrieval info: USED_PORT: coreclk_out 0 0 1 0 OUTPUT NODEFVAL "coreclk_out[0..0]"
+// Retrieval info: USED_PORT: inclk 0 0 1 0 INPUT GND "inclk[0..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT GND "pll_areset[0..0]"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: pllenable 0 0 1 0 INPUT VCC "pllenable[0..0]"
+// Retrieval info: USED_PORT: rx_clkout 0 0 1 0 OUTPUT NODEFVAL "rx_clkout[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_enacdet 0 0 1 0 INPUT GND "rx_enacdet[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT GND "rx_in[0..0]"
+// Retrieval info: USED_PORT: rx_locked 0 0 1 0 OUTPUT NODEFVAL "rx_locked[0..0]"
+// Retrieval info: USED_PORT: rx_out 0 0 20 0 OUTPUT NODEFVAL "rx_out[19..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
+// Retrieval info: USED_PORT: rxanalogreset 0 0 1 0 INPUT GND "rxanalogreset[0..0]"
+// Retrieval info: USED_PORT: rxdigitalreset 0 0 1 0 INPUT GND "rxdigitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_coreclk 0 0 1 0 INPUT GND "tx_coreclk[0..0]"
+// Retrieval info: USED_PORT: tx_in 0 0 20 0 INPUT GND "tx_in[19..0]"
+// Retrieval info: USED_PORT: tx_out 0 0 1 0 OUTPUT NODEFVAL "tx_out[0..0]"
+// Retrieval info: USED_PORT: txdigitalreset 0 0 1 0 INPUT GND "txdigitalreset[0..0]"
+// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
+// Retrieval info: CONNECT: @pllenable 0 0 1 0 pllenable 0 0 1 0
+// Retrieval info: CONNECT: rx_locked 0 0 1 0 @rx_locked 0 0 1 0
+// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
+// Retrieval info: CONNECT: @txdigitalreset 0 0 1 0 txdigitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_in 0 0 1 0 rx_in 0 0 1 0
+// Retrieval info: CONNECT: coreclk_out 0 0 1 0 @coreclk_out 0 0 1 0
+// Retrieval info: CONNECT: @tx_coreclk 0 0 1 0 tx_coreclk 0 0 1 0
+// Retrieval info: CONNECT: tx_out 0 0 1 0 @tx_out 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
+// Retrieval info: CONNECT: rx_out 0 0 20 0 @rx_out 0 0 20 0
+// Retrieval info: CONNECT: rx_clkout 0 0 1 0 @rx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rxdigitalreset 0 0 1 0 rxdigitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rxanalogreset 0 0 1 0 rxanalogreset 0 0 1 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: @rx_enacdet 0 0 1 0 rx_enacdet 0 0 1 0
+// Retrieval info: CONNECT: @tx_in 0 0 20 0 tx_in 0 0 20 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x1_15625_bb.v FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v b/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v
new file mode 100644
index 0000000000000000000000000000000000000000..acaedce164125d9f847c278388c2ae75f29c0087
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v
@@ -0,0 +1,407 @@
+// megafunction wizard: %ALTGXB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altgxb
+
+// ============================================================
+// File Name: altpcie_serdes_1sgx_x4_12500.v
+// Megafunction Name(s):
+// altgxb
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 176 10/26/2005 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_1sgx_x4_12500 (
+ inclk,
+ pll_areset,
+ pllenable,
+ rx_cruclk,
+ rx_enacdet,
+ rx_in,
+ rxanalogreset,
+ rxdigitalreset,
+ tx_coreclk,
+ tx_in,
+ txdigitalreset,
+ coreclk_out,
+ pll_locked,
+ rx_clkout,
+ rx_freqlocked,
+ rx_locked,
+ rx_out,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_out);
+
+ input [0:0] inclk;
+ input [0:0] pll_areset;
+ input [0:0] pllenable;
+ input [0:0] rx_cruclk;
+ input [3:0] rx_enacdet;
+ input [3:0] rx_in;
+ input [3:0] rxanalogreset;
+ input [3:0] rxdigitalreset;
+ input [3:0] tx_coreclk;
+ input [79:0] tx_in;
+ input [3:0] txdigitalreset;
+ output [0:0] coreclk_out;
+ output [0:0] pll_locked;
+ output [3:0] rx_clkout;
+ output [3:0] rx_freqlocked;
+ output [3:0] rx_locked;
+ output [79:0] rx_out;
+ output [7:0] rx_patterndetect;
+ output [7:0] rx_syncstatus;
+ output [3:0] tx_out;
+
+ wire [7:0] sub_wire0;
+ wire [3:0] sub_wire1;
+ wire [79:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [3:0] sub_wire4;
+ wire [3:0] sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [7:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [7:0] rx_patterndetect = sub_wire0[7:0];
+ wire [3:0] tx_out = sub_wire1[3:0];
+ wire [79:0] rx_out = sub_wire2[79:0];
+ wire [0:0] coreclk_out = sub_wire3[0:0];
+ wire [3:0] rx_locked = sub_wire4[3:0];
+ wire [3:0] rx_freqlocked = sub_wire5[3:0];
+ wire [3:0] rx_clkout = sub_wire6[3:0];
+ wire [7:0] rx_syncstatus = sub_wire7[7:0];
+ wire [0:0] pll_locked = sub_wire8[0:0];
+
+ altgxb altgxb_component (
+ .pll_areset (pll_areset),
+ .rx_enacdet (rx_enacdet),
+ .rx_cruclk (rx_cruclk),
+ .pllenable (pllenable),
+ .inclk (inclk),
+ .rx_in (rx_in),
+ .tx_in (tx_in),
+ .rxanalogreset (rxanalogreset),
+ .tx_coreclk (tx_coreclk),
+ .rxdigitalreset (rxdigitalreset),
+ .txdigitalreset (txdigitalreset),
+ .rx_patterndetect (sub_wire0),
+ .tx_out (sub_wire1),
+ .rx_out (sub_wire2),
+ .coreclk_out (sub_wire3),
+ .rx_locked (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .rx_clkout (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .pll_locked (sub_wire8)
+ // synopsys translate_off
+ ,
+ .rx_we (),
+ .rx_coreclk (),
+ .rx_channelaligned (),
+ .rx_bisterr (),
+ .rx_slpbk (),
+ .rx_aclr (),
+ .rx_fifoalmostempty (),
+ .tx_aclr (),
+ .rx_bistdone (),
+ .rx_signaldetect (),
+ .tx_forcedisparity (),
+ .tx_vodctrl (),
+ .rx_equalizerctrl (),
+ .rx_a1a2size (),
+ .tx_srlpbk (),
+ .rx_errdetect (),
+ .rx_re (),
+ .rx_disperr (),
+ .rx_locktodata (),
+ .tx_preemphasisctrl (),
+ .rx_rlv (),
+ .rx_fifoalmostfull (),
+ .rx_bitslip (),
+ .rx_a1a2sizeout (),
+ .rx_locktorefclk (),
+ .rx_ctrldetect (),
+ .tx_ctrlenable ()
+ // synopsys translate_on
+ );
+ defparam
+ altgxb_component.align_pattern = "P0101111100",
+ altgxb_component.align_pattern_length = 10,
+ altgxb_component.allow_gxb_merging = "OFF",
+ altgxb_component.channel_width = 20,
+ altgxb_component.clk_out_mode_reference = "ON",
+ altgxb_component.consider_enable_tx_8b_10b_i1i2_generation = "ON",
+ altgxb_component.consider_instantiate_transmitter_pll_param = "ON",
+ altgxb_component.cru_inclock_period = 8000,
+ altgxb_component.data_rate = 2500,
+ altgxb_component.data_rate_remainder = 0,
+ altgxb_component.disparity_mode = "ON",
+ altgxb_component.dwidth_factor = 2,
+ altgxb_component.enable_tx_8b_10b_i1i2_generation = "OFF",
+ altgxb_component.equalizer_ctrl_setting = 20,
+ altgxb_component.flip_rx_out = "OFF",
+ altgxb_component.flip_tx_in = "OFF",
+ altgxb_component.force_disparity_mode = "OFF",
+ altgxb_component.for_engineering_sample_device = "OFF",
+ altgxb_component.instantiate_transmitter_pll = "ON",
+ altgxb_component.intended_device_family = "Stratix GX",
+ altgxb_component.loopback_mode = "NONE",
+ altgxb_component.lpm_type = "altgxb",
+ altgxb_component.number_of_channels = 4,
+ altgxb_component.number_of_quads = 1,
+ altgxb_component.operation_mode = "DUPLEX",
+ altgxb_component.pll_bandwidth_type = "LOW",
+ altgxb_component.pll_inclock_period = 8000,
+ altgxb_component.preemphasis_ctrl_setting = 10,
+ altgxb_component.protocol = "CUSTOM",
+ altgxb_component.reverse_loopback_mode = "NONE",
+ altgxb_component.run_length_enable = "OFF",
+ altgxb_component.rx_bandwidth_type = "NEW_LOW",
+ altgxb_component.rx_data_rate = 2500,
+ altgxb_component.rx_data_rate_remainder = 0,
+ altgxb_component.rx_enable_dc_coupling = "OFF",
+ altgxb_component.rx_force_signal_detect = "ON",
+ altgxb_component.rx_ppm_setting = 1000,
+ altgxb_component.signal_threshold_select = 530,
+ altgxb_component.tx_termination = 2,
+ altgxb_component.use_8b_10b_mode = "OFF",
+ altgxb_component.use_auto_bit_slip = "ON",
+ altgxb_component.use_channel_align = "OFF",
+ altgxb_component.use_double_data_mode = "ON",
+ altgxb_component.use_equalizer_ctrl_signal = "OFF",
+ altgxb_component.use_generic_fifo = "OFF",
+ altgxb_component.use_preemphasis_ctrl_signal = "OFF",
+ altgxb_component.use_rate_match_fifo = "OFF",
+ altgxb_component.use_rx_clkout = "ON",
+ altgxb_component.use_rx_coreclk = "OFF",
+ altgxb_component.use_rx_cruclk = "ON",
+ altgxb_component.use_self_test_mode = "OFF",
+ altgxb_component.use_symbol_align = "ON",
+ altgxb_component.use_tx_coreclk = "ON",
+ altgxb_component.use_vod_ctrl_signal = "OFF",
+ altgxb_component.vod_ctrl_setting = 800;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADD_GENERIC_FIFO_WE_SYNCH_REGISTER STRING "0"
+// Retrieval info: PRIVATE: ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: PRIVATE: ALIGN_PATTERN_LENGTH STRING "10"
+// Retrieval info: PRIVATE: CHANNEL_WIDTH STRING "20"
+// Retrieval info: PRIVATE: CLK_OUT_MODE_REFERENCE STRING "1"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "0"
+// Retrieval info: PRIVATE: EQU_SETTING STRING "2"
+// Retrieval info: PRIVATE: FLIP_ALIGN_PATTERN STRING "0"
+// Retrieval info: PRIVATE: FLIP_RX_OUT STRING "0"
+// Retrieval info: PRIVATE: FLIP_TX_IN STRING "0"
+// Retrieval info: PRIVATE: FOR_ENGINEERING_SAMPLE_DEVICE STRING "0"
+// Retrieval info: PRIVATE: GXB_QUAD_MERGE STRING "0"
+// Retrieval info: PRIVATE: INFINIBAND_INVALID_CODE STRING "0"
+// Retrieval info: PRIVATE: INSTANTIATE_TRANSMITTER_PLL STRING "1"
+// Retrieval info: PRIVATE: LOOPBACK_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;pll_areset;rx_in;rx_coreclk;rx_cruclk"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "rx_aclr;rx_bitslip;rx_enacdet;rx_we;rx_re"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "rx_slpbk;rx_a1a2size;rx_equalizerctrl;rx_locktorefclk;rx_locktodata"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "tx_in;tx_coreclk;tx_aclr;tx_ctrlenable;tx_forcedisparity"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "tx_srlpbk;tx_vodctrl;tx_preemphasisctrl;txdigitalreset;rxdigitalreset"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_5 STRING "rxanalogreset;pllenable;pll_locked;coreclk_out;rx_out"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_6 STRING "rx_clkout;rx_locked;rx_freqlocked;rx_rlv;rx_syncstatus"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_7 STRING "rx_patterndetect;rx_ctrldetect;rx_errdetect;rx_disperr;rx_signaldetect"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_8 STRING "rx_fifoalmostempty;rx_fifoalmostfull;rx_channelaligned;rx_bisterr;rx_bistdone"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_9 STRING "rx_a1a2sizeout;tx_out"
+// Retrieval info: PRIVATE: NUMBER_OF_CHANNELS STRING "4"
+// Retrieval info: PRIVATE: OP_MODE STRING "Duplex"
+// Retrieval info: PRIVATE: PLL_ACLR STRING "1"
+// Retrieval info: PRIVATE: PLL_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: PRIVATE: PLL_DC_COUPLING STRING "1"
+// Retrieval info: PRIVATE: PLL_ENABLE STRING "1"
+// Retrieval info: PRIVATE: PLL_LOCKED STRING "1"
+// Retrieval info: PRIVATE: PREEMPHASIS_SETTING STRING "2"
+// Retrieval info: PRIVATE: PREEMPHASIS_SIGNAL STRING "0"
+// Retrieval info: PRIVATE: PROTOCOL STRING "CUSTOM"
+// Retrieval info: PRIVATE: REVERSE_LOOPBACK_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: RLV STRING "5"
+// Retrieval info: PRIVATE: RX_A1A2 STRING "0"
+// Retrieval info: PRIVATE: RX_A1A2SIZEOUT STRING "0"
+// Retrieval info: PRIVATE: RX_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: PRIVATE: RX_BASE_INPUT_TYPE STRING ""
+// Retrieval info: PRIVATE: RX_BISTDONE STRING "0"
+// Retrieval info: PRIVATE: RX_BISTERR STRING "0"
+// Retrieval info: PRIVATE: RX_BITSLIP STRING "0"
+// Retrieval info: PRIVATE: RX_CLKOUT STRING "1"
+// Retrieval info: PRIVATE: RX_CLR STRING "1"
+// Retrieval info: PRIVATE: RX_CTRLDETECT STRING "0"
+// Retrieval info: PRIVATE: RX_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: RX_DISPERR STRING "0"
+// Retrieval info: PRIVATE: RX_ENACDET STRING "1"
+// Retrieval info: PRIVATE: RX_ERRDETECT STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOALMOSTEMPTY STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOALMOSTFULL STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOEMPTY STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOFULL STRING "0"
+// Retrieval info: PRIVATE: RX_FORCE_SIGNAL_DETECT STRING "1"
+// Retrieval info: PRIVATE: RX_FREQLOCKED STRING "1"
+// Retrieval info: PRIVATE: RX_FREQUENCY STRING "125.0000"
+// Retrieval info: PRIVATE: RX_LOCKED STRING "1"
+// Retrieval info: PRIVATE: RX_LOCKTODATA STRING "0"
+// Retrieval info: PRIVATE: RX_LOCKTOREFCLK STRING "0"
+// Retrieval info: PRIVATE: RX_PATTERNDETECT STRING "1"
+// Retrieval info: PRIVATE: RX_PPM_SETTING STRING "1000"
+// Retrieval info: PRIVATE: RX_SIGDET STRING "0"
+// Retrieval info: PRIVATE: RX_SYNCSTATUS STRING "1"
+// Retrieval info: PRIVATE: SELF_TEST_MODE NUMERIC "-1"
+// Retrieval info: PRIVATE: SIGNAL_THRESHOLD_SELECT STRING "530"
+// Retrieval info: PRIVATE: TX_BASE_INPUT_TYPE STRING ""
+// Retrieval info: PRIVATE: TX_CLR STRING "1"
+// Retrieval info: PRIVATE: TX_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: TX_FORCE_DISPARITY STRING "0"
+// Retrieval info: PRIVATE: TX_FREQUENCY STRING "125.0000"
+// Retrieval info: PRIVATE: TX_PLL_LOCKED STRING "1"
+// Retrieval info: PRIVATE: TX_TERMINATION STRING "100"
+// Retrieval info: PRIVATE: USE_8B10B_DECODER STRING "0"
+// Retrieval info: PRIVATE: USE_8B10B_ENCODER STRING "0"
+// Retrieval info: PRIVATE: USE_8B_10B_MODE STRING "OFF"
+// Retrieval info: PRIVATE: USE_AUTO_BIT_SLIP NUMERIC "1"
+// Retrieval info: PRIVATE: USE_CRUCLK_FROM_PLL STRING "1"
+// Retrieval info: PRIVATE: USE_DC_COUPLING STRING "0"
+// Retrieval info: PRIVATE: USE_EQUALIZER STRING "0"
+// Retrieval info: PRIVATE: USE_EXTERNAL_TX_TERMINATION STRING "0"
+// Retrieval info: PRIVATE: USE_GENERIC_FIFO STRING "0"
+// Retrieval info: PRIVATE: USE_RATE_MATCH_FIFO STRING "0"
+// Retrieval info: PRIVATE: USE_RLV STRING "0"
+// Retrieval info: PRIVATE: USE_RX_CORECLK STRING "0"
+// Retrieval info: PRIVATE: USE_RX_CRUCLK STRING "1"
+// Retrieval info: PRIVATE: USE_TX_CORECLK STRING "1"
+// Retrieval info: PRIVATE: VERSION STRING "4.0"
+// Retrieval info: PRIVATE: VOD_SETTING STRING "800"
+// Retrieval info: PRIVATE: VOD_SIGNAL STRING "0"
+// Retrieval info: PRIVATE: XGM_RXANALOGRESET STRING "1"
+// Retrieval info: LIBRARY: altgxb altgxb.all
+// Retrieval info: CONSTANT: ALIGN_PATTERN STRING "P0101111100"
+// Retrieval info: CONSTANT: ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: ALLOW_GXB_MERGING STRING "OFF"
+// Retrieval info: CONSTANT: CHANNEL_WIDTH NUMERIC "20"
+// Retrieval info: CONSTANT: CLK_OUT_MODE_REFERENCE STRING "ON"
+// Retrieval info: CONSTANT: CONSIDER_ENABLE_TX_8B_10B_I1I2_GENERATION STRING "ON"
+// Retrieval info: CONSTANT: CONSIDER_INSTANTIATE_TRANSMITTER_PLL_PARAM STRING "ON"
+// Retrieval info: CONSTANT: CRU_INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: DISPARITY_MODE STRING "ON"
+// Retrieval info: CONSTANT: DWIDTH_FACTOR NUMERIC "2"
+// Retrieval info: CONSTANT: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "OFF"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_SETTING NUMERIC "20"
+// Retrieval info: CONSTANT: FLIP_RX_OUT STRING "OFF"
+// Retrieval info: CONSTANT: FLIP_TX_IN STRING "OFF"
+// Retrieval info: CONSTANT: FORCE_DISPARITY_MODE STRING "OFF"
+// Retrieval info: CONSTANT: FOR_ENGINEERING_SAMPLE_DEVICE STRING "OFF"
+// Retrieval info: CONSTANT: INSTANTIATE_TRANSMITTER_PLL STRING "ON"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "NONE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altgxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: NUMBER_OF_QUADS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUPLEX"
+// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: PLL_INCLOCK_PERIOD NUMERIC "8000"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_SETTING NUMERIC "10"
+// Retrieval info: CONSTANT: PROTOCOL STRING "CUSTOM"
+// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RUN_LENGTH_ENABLE STRING "OFF"
+// Retrieval info: CONSTANT: RX_BANDWIDTH_TYPE STRING "NEW_LOW"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_ENABLE_DC_COUPLING STRING "OFF"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "ON"
+// Retrieval info: CONSTANT: RX_PPM_SETTING NUMERIC "1000"
+// Retrieval info: CONSTANT: SIGNAL_THRESHOLD_SELECT NUMERIC "530"
+// Retrieval info: CONSTANT: TX_TERMINATION NUMERIC "2"
+// Retrieval info: CONSTANT: USE_8B_10B_MODE STRING "OFF"
+// Retrieval info: CONSTANT: USE_AUTO_BIT_SLIP STRING "ON"
+// Retrieval info: CONSTANT: USE_CHANNEL_ALIGN STRING "OFF"
+// Retrieval info: CONSTANT: USE_DOUBLE_DATA_MODE STRING "ON"
+// Retrieval info: CONSTANT: USE_EQUALIZER_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: USE_GENERIC_FIFO STRING "OFF"
+// Retrieval info: CONSTANT: USE_PREEMPHASIS_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: USE_RATE_MATCH_FIFO STRING "OFF"
+// Retrieval info: CONSTANT: USE_RX_CLKOUT STRING "ON"
+// Retrieval info: CONSTANT: USE_RX_CORECLK STRING "OFF"
+// Retrieval info: CONSTANT: USE_RX_CRUCLK STRING "ON"
+// Retrieval info: CONSTANT: USE_SELF_TEST_MODE STRING "OFF"
+// Retrieval info: CONSTANT: USE_SYMBOL_ALIGN STRING "ON"
+// Retrieval info: CONSTANT: USE_TX_CORECLK STRING "ON"
+// Retrieval info: CONSTANT: USE_VOD_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "800"
+// Retrieval info: USED_PORT: coreclk_out 0 0 1 0 OUTPUT NODEFVAL "coreclk_out[0..0]"
+// Retrieval info: USED_PORT: inclk 0 0 1 0 INPUT GND "inclk[0..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT GND "pll_areset[0..0]"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: pllenable 0 0 1 0 INPUT VCC "pllenable[0..0]"
+// Retrieval info: USED_PORT: rx_clkout 0 0 4 0 OUTPUT NODEFVAL "rx_clkout[3..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_enacdet 0 0 4 0 INPUT GND "rx_enacdet[3..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_in 0 0 4 0 INPUT GND "rx_in[3..0]"
+// Retrieval info: USED_PORT: rx_locked 0 0 4 0 OUTPUT NODEFVAL "rx_locked[3..0]"
+// Retrieval info: USED_PORT: rx_out 0 0 80 0 OUTPUT NODEFVAL "rx_out[79..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: rxanalogreset 0 0 4 0 INPUT GND "rxanalogreset[3..0]"
+// Retrieval info: USED_PORT: rxdigitalreset 0 0 4 0 INPUT GND "rxdigitalreset[3..0]"
+// Retrieval info: USED_PORT: tx_coreclk 0 0 4 0 INPUT GND "tx_coreclk[3..0]"
+// Retrieval info: USED_PORT: tx_in 0 0 80 0 INPUT GND "tx_in[79..0]"
+// Retrieval info: USED_PORT: tx_out 0 0 4 0 OUTPUT NODEFVAL "tx_out[3..0]"
+// Retrieval info: USED_PORT: txdigitalreset 0 0 4 0 INPUT GND "txdigitalreset[3..0]"
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: @pllenable 0 0 1 0 pllenable 0 0 1 0
+// Retrieval info: CONNECT: rx_locked 0 0 4 0 @rx_locked 0 0 4 0
+// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
+// Retrieval info: CONNECT: @txdigitalreset 0 0 4 0 txdigitalreset 0 0 4 0
+// Retrieval info: CONNECT: @rx_in 0 0 4 0 rx_in 0 0 4 0
+// Retrieval info: CONNECT: coreclk_out 0 0 1 0 @coreclk_out 0 0 1 0
+// Retrieval info: CONNECT: @tx_coreclk 0 0 4 0 tx_coreclk 0 0 4 0
+// Retrieval info: CONNECT: tx_out 0 0 4 0 @tx_out 0 0 4 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: rx_out 0 0 80 0 @rx_out 0 0 80 0
+// Retrieval info: CONNECT: rx_clkout 0 0 4 0 @rx_clkout 0 0 4 0
+// Retrieval info: CONNECT: @rxdigitalreset 0 0 4 0 rxdigitalreset 0 0 4 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rxanalogreset 0 0 4 0 rxanalogreset 0 0 4 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: @rx_enacdet 0 0 4 0 rx_enacdet 0 0 4 0
+// Retrieval info: CONNECT: @tx_in 0 0 80 0 tx_in 0 0 80 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_12500.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_12500.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_12500.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_12500.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_12500_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_12500_bb.v FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v b/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v
new file mode 100644
index 0000000000000000000000000000000000000000..666374b04c4c4ec38d87b3841a63c4d3045dc7f2
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v
@@ -0,0 +1,407 @@
+// megafunction wizard: %ALTGXB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altgxb
+
+// ============================================================
+// File Name: altpcie_serdes_1sgx_x4_15625.v
+// Megafunction Name(s):
+// altgxb
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 176 10/26/2005 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_1sgx_x4_15625 (
+ inclk,
+ pll_areset,
+ pllenable,
+ rx_cruclk,
+ rx_enacdet,
+ rx_in,
+ rxanalogreset,
+ rxdigitalreset,
+ tx_coreclk,
+ tx_in,
+ txdigitalreset,
+ coreclk_out,
+ pll_locked,
+ rx_clkout,
+ rx_freqlocked,
+ rx_locked,
+ rx_out,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_out);
+
+ input [0:0] inclk;
+ input [0:0] pll_areset;
+ input [0:0] pllenable;
+ input [0:0] rx_cruclk;
+ input [3:0] rx_enacdet;
+ input [3:0] rx_in;
+ input [3:0] rxanalogreset;
+ input [3:0] rxdigitalreset;
+ input [3:0] tx_coreclk;
+ input [79:0] tx_in;
+ input [3:0] txdigitalreset;
+ output [0:0] coreclk_out;
+ output [0:0] pll_locked;
+ output [3:0] rx_clkout;
+ output [3:0] rx_freqlocked;
+ output [3:0] rx_locked;
+ output [79:0] rx_out;
+ output [7:0] rx_patterndetect;
+ output [7:0] rx_syncstatus;
+ output [3:0] tx_out;
+
+ wire [7:0] sub_wire0;
+ wire [3:0] sub_wire1;
+ wire [79:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [3:0] sub_wire4;
+ wire [3:0] sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [7:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [7:0] rx_patterndetect = sub_wire0[7:0];
+ wire [3:0] tx_out = sub_wire1[3:0];
+ wire [79:0] rx_out = sub_wire2[79:0];
+ wire [0:0] coreclk_out = sub_wire3[0:0];
+ wire [3:0] rx_locked = sub_wire4[3:0];
+ wire [3:0] rx_freqlocked = sub_wire5[3:0];
+ wire [3:0] rx_clkout = sub_wire6[3:0];
+ wire [7:0] rx_syncstatus = sub_wire7[7:0];
+ wire [0:0] pll_locked = sub_wire8[0:0];
+
+ altgxb altgxb_component (
+ .pll_areset (pll_areset),
+ .rx_enacdet (rx_enacdet),
+ .rx_cruclk (rx_cruclk),
+ .pllenable (pllenable),
+ .inclk (inclk),
+ .rx_in (rx_in),
+ .tx_in (tx_in),
+ .rxanalogreset (rxanalogreset),
+ .tx_coreclk (tx_coreclk),
+ .rxdigitalreset (rxdigitalreset),
+ .txdigitalreset (txdigitalreset),
+ .rx_patterndetect (sub_wire0),
+ .tx_out (sub_wire1),
+ .rx_out (sub_wire2),
+ .coreclk_out (sub_wire3),
+ .rx_locked (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .rx_clkout (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .pll_locked (sub_wire8)
+ // synopsys translate_off
+ ,
+ .rx_we (),
+ .rx_coreclk (),
+ .rx_channelaligned (),
+ .rx_bisterr (),
+ .rx_slpbk (),
+ .rx_aclr (),
+ .rx_fifoalmostempty (),
+ .tx_aclr (),
+ .rx_bistdone (),
+ .rx_signaldetect (),
+ .tx_forcedisparity (),
+ .tx_vodctrl (),
+ .rx_equalizerctrl (),
+ .rx_a1a2size (),
+ .tx_srlpbk (),
+ .rx_errdetect (),
+ .rx_re (),
+ .rx_disperr (),
+ .rx_locktodata (),
+ .tx_preemphasisctrl (),
+ .rx_rlv (),
+ .rx_fifoalmostfull (),
+ .rx_bitslip (),
+ .rx_a1a2sizeout (),
+ .rx_locktorefclk (),
+ .rx_ctrldetect (),
+ .tx_ctrlenable ()
+ // synopsys translate_on
+ );
+ defparam
+ altgxb_component.align_pattern = "P0101111100",
+ altgxb_component.align_pattern_length = 10,
+ altgxb_component.allow_gxb_merging = "OFF",
+ altgxb_component.channel_width = 20,
+ altgxb_component.clk_out_mode_reference = "ON",
+ altgxb_component.consider_enable_tx_8b_10b_i1i2_generation = "ON",
+ altgxb_component.consider_instantiate_transmitter_pll_param = "ON",
+ altgxb_component.cru_inclock_period = 6400,
+ altgxb_component.data_rate = 2500,
+ altgxb_component.data_rate_remainder = 0,
+ altgxb_component.disparity_mode = "ON",
+ altgxb_component.dwidth_factor = 2,
+ altgxb_component.enable_tx_8b_10b_i1i2_generation = "OFF",
+ altgxb_component.equalizer_ctrl_setting = 20,
+ altgxb_component.flip_rx_out = "OFF",
+ altgxb_component.flip_tx_in = "OFF",
+ altgxb_component.force_disparity_mode = "OFF",
+ altgxb_component.for_engineering_sample_device = "OFF",
+ altgxb_component.instantiate_transmitter_pll = "ON",
+ altgxb_component.intended_device_family = "Stratix GX",
+ altgxb_component.loopback_mode = "NONE",
+ altgxb_component.lpm_type = "altgxb",
+ altgxb_component.number_of_channels = 4,
+ altgxb_component.number_of_quads = 1,
+ altgxb_component.operation_mode = "DUPLEX",
+ altgxb_component.pll_bandwidth_type = "LOW",
+ altgxb_component.pll_inclock_period = 6400,
+ altgxb_component.preemphasis_ctrl_setting = 10,
+ altgxb_component.protocol = "CUSTOM",
+ altgxb_component.reverse_loopback_mode = "NONE",
+ altgxb_component.run_length_enable = "OFF",
+ altgxb_component.rx_bandwidth_type = "NEW_LOW",
+ altgxb_component.rx_data_rate = 2500,
+ altgxb_component.rx_data_rate_remainder = 0,
+ altgxb_component.rx_enable_dc_coupling = "OFF",
+ altgxb_component.rx_force_signal_detect = "ON",
+ altgxb_component.rx_ppm_setting = 1000,
+ altgxb_component.signal_threshold_select = 530,
+ altgxb_component.tx_termination = 2,
+ altgxb_component.use_8b_10b_mode = "OFF",
+ altgxb_component.use_auto_bit_slip = "ON",
+ altgxb_component.use_channel_align = "OFF",
+ altgxb_component.use_double_data_mode = "ON",
+ altgxb_component.use_equalizer_ctrl_signal = "OFF",
+ altgxb_component.use_generic_fifo = "OFF",
+ altgxb_component.use_preemphasis_ctrl_signal = "OFF",
+ altgxb_component.use_rate_match_fifo = "OFF",
+ altgxb_component.use_rx_clkout = "ON",
+ altgxb_component.use_rx_coreclk = "OFF",
+ altgxb_component.use_rx_cruclk = "ON",
+ altgxb_component.use_self_test_mode = "OFF",
+ altgxb_component.use_symbol_align = "ON",
+ altgxb_component.use_tx_coreclk = "ON",
+ altgxb_component.use_vod_ctrl_signal = "OFF",
+ altgxb_component.vod_ctrl_setting = 800;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADD_GENERIC_FIFO_WE_SYNCH_REGISTER STRING "0"
+// Retrieval info: PRIVATE: ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: PRIVATE: ALIGN_PATTERN_LENGTH STRING "10"
+// Retrieval info: PRIVATE: CHANNEL_WIDTH STRING "20"
+// Retrieval info: PRIVATE: CLK_OUT_MODE_REFERENCE STRING "1"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
+// Retrieval info: PRIVATE: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "0"
+// Retrieval info: PRIVATE: EQU_SETTING STRING "2"
+// Retrieval info: PRIVATE: FLIP_ALIGN_PATTERN STRING "0"
+// Retrieval info: PRIVATE: FLIP_RX_OUT STRING "0"
+// Retrieval info: PRIVATE: FLIP_TX_IN STRING "0"
+// Retrieval info: PRIVATE: FOR_ENGINEERING_SAMPLE_DEVICE STRING "0"
+// Retrieval info: PRIVATE: GXB_QUAD_MERGE STRING "0"
+// Retrieval info: PRIVATE: INFINIBAND_INVALID_CODE STRING "0"
+// Retrieval info: PRIVATE: INSTANTIATE_TRANSMITTER_PLL STRING "1"
+// Retrieval info: PRIVATE: LOOPBACK_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;pll_areset;rx_in;rx_coreclk;rx_cruclk"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "rx_aclr;rx_bitslip;rx_enacdet;rx_we;rx_re"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "rx_slpbk;rx_a1a2size;rx_equalizerctrl;rx_locktorefclk;rx_locktodata"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "tx_in;tx_coreclk;tx_aclr;tx_ctrlenable;tx_forcedisparity"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "tx_srlpbk;tx_vodctrl;tx_preemphasisctrl;txdigitalreset;rxdigitalreset"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_5 STRING "rxanalogreset;pllenable;pll_locked;coreclk_out;rx_out"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_6 STRING "rx_clkout;rx_locked;rx_freqlocked;rx_rlv;rx_syncstatus"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_7 STRING "rx_patterndetect;rx_ctrldetect;rx_errdetect;rx_disperr;rx_signaldetect"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_8 STRING "rx_fifoalmostempty;rx_fifoalmostfull;rx_channelaligned;rx_bisterr;rx_bistdone"
+// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_9 STRING "rx_a1a2sizeout;tx_out"
+// Retrieval info: PRIVATE: NUMBER_OF_CHANNELS STRING "4"
+// Retrieval info: PRIVATE: OP_MODE STRING "Duplex"
+// Retrieval info: PRIVATE: PLL_ACLR STRING "1"
+// Retrieval info: PRIVATE: PLL_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: PRIVATE: PLL_DC_COUPLING STRING "1"
+// Retrieval info: PRIVATE: PLL_ENABLE STRING "1"
+// Retrieval info: PRIVATE: PLL_LOCKED STRING "1"
+// Retrieval info: PRIVATE: PREEMPHASIS_SETTING STRING "2"
+// Retrieval info: PRIVATE: PREEMPHASIS_SIGNAL STRING "0"
+// Retrieval info: PRIVATE: PROTOCOL STRING "CUSTOM"
+// Retrieval info: PRIVATE: REVERSE_LOOPBACK_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: RLV STRING "5"
+// Retrieval info: PRIVATE: RX_A1A2 STRING "0"
+// Retrieval info: PRIVATE: RX_A1A2SIZEOUT STRING "0"
+// Retrieval info: PRIVATE: RX_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: PRIVATE: RX_BASE_INPUT_TYPE STRING ""
+// Retrieval info: PRIVATE: RX_BISTDONE STRING "0"
+// Retrieval info: PRIVATE: RX_BISTERR STRING "0"
+// Retrieval info: PRIVATE: RX_BITSLIP STRING "0"
+// Retrieval info: PRIVATE: RX_CLKOUT STRING "1"
+// Retrieval info: PRIVATE: RX_CLR STRING "1"
+// Retrieval info: PRIVATE: RX_CTRLDETECT STRING "0"
+// Retrieval info: PRIVATE: RX_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: RX_DISPERR STRING "0"
+// Retrieval info: PRIVATE: RX_ENACDET STRING "1"
+// Retrieval info: PRIVATE: RX_ERRDETECT STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOALMOSTEMPTY STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOALMOSTFULL STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOEMPTY STRING "0"
+// Retrieval info: PRIVATE: RX_FIFOFULL STRING "0"
+// Retrieval info: PRIVATE: RX_FORCE_SIGNAL_DETECT STRING "1"
+// Retrieval info: PRIVATE: RX_FREQLOCKED STRING "1"
+// Retrieval info: PRIVATE: RX_FREQUENCY STRING "156.25"
+// Retrieval info: PRIVATE: RX_LOCKED STRING "1"
+// Retrieval info: PRIVATE: RX_LOCKTODATA STRING "0"
+// Retrieval info: PRIVATE: RX_LOCKTOREFCLK STRING "0"
+// Retrieval info: PRIVATE: RX_PATTERNDETECT STRING "1"
+// Retrieval info: PRIVATE: RX_PPM_SETTING STRING "1000"
+// Retrieval info: PRIVATE: RX_SIGDET STRING "0"
+// Retrieval info: PRIVATE: RX_SYNCSTATUS STRING "1"
+// Retrieval info: PRIVATE: SELF_TEST_MODE NUMERIC "-1"
+// Retrieval info: PRIVATE: SIGNAL_THRESHOLD_SELECT STRING "530"
+// Retrieval info: PRIVATE: TX_BASE_INPUT_TYPE STRING ""
+// Retrieval info: PRIVATE: TX_CLR STRING "1"
+// Retrieval info: PRIVATE: TX_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: TX_FORCE_DISPARITY STRING "0"
+// Retrieval info: PRIVATE: TX_FREQUENCY STRING "156.25"
+// Retrieval info: PRIVATE: TX_PLL_LOCKED STRING "1"
+// Retrieval info: PRIVATE: TX_TERMINATION STRING "100"
+// Retrieval info: PRIVATE: USE_8B10B_DECODER STRING "0"
+// Retrieval info: PRIVATE: USE_8B10B_ENCODER STRING "0"
+// Retrieval info: PRIVATE: USE_8B_10B_MODE STRING "OFF"
+// Retrieval info: PRIVATE: USE_AUTO_BIT_SLIP NUMERIC "1"
+// Retrieval info: PRIVATE: USE_CRUCLK_FROM_PLL STRING "1"
+// Retrieval info: PRIVATE: USE_DC_COUPLING STRING "0"
+// Retrieval info: PRIVATE: USE_EQUALIZER STRING "0"
+// Retrieval info: PRIVATE: USE_EXTERNAL_TX_TERMINATION STRING "0"
+// Retrieval info: PRIVATE: USE_GENERIC_FIFO STRING "0"
+// Retrieval info: PRIVATE: USE_RATE_MATCH_FIFO STRING "0"
+// Retrieval info: PRIVATE: USE_RLV STRING "0"
+// Retrieval info: PRIVATE: USE_RX_CORECLK STRING "0"
+// Retrieval info: PRIVATE: USE_RX_CRUCLK STRING "1"
+// Retrieval info: PRIVATE: USE_TX_CORECLK STRING "1"
+// Retrieval info: PRIVATE: VERSION STRING "4.0"
+// Retrieval info: PRIVATE: VOD_SETTING STRING "800"
+// Retrieval info: PRIVATE: VOD_SIGNAL STRING "0"
+// Retrieval info: PRIVATE: XGM_RXANALOGRESET STRING "1"
+// Retrieval info: LIBRARY: altgxb altgxb.all
+// Retrieval info: CONSTANT: ALIGN_PATTERN STRING "P0101111100"
+// Retrieval info: CONSTANT: ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: ALLOW_GXB_MERGING STRING "OFF"
+// Retrieval info: CONSTANT: CHANNEL_WIDTH NUMERIC "20"
+// Retrieval info: CONSTANT: CLK_OUT_MODE_REFERENCE STRING "ON"
+// Retrieval info: CONSTANT: CONSIDER_ENABLE_TX_8B_10B_I1I2_GENERATION STRING "ON"
+// Retrieval info: CONSTANT: CONSIDER_INSTANTIATE_TRANSMITTER_PLL_PARAM STRING "ON"
+// Retrieval info: CONSTANT: CRU_INCLOCK_PERIOD NUMERIC "6400"
+// Retrieval info: CONSTANT: DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: DISPARITY_MODE STRING "ON"
+// Retrieval info: CONSTANT: DWIDTH_FACTOR NUMERIC "2"
+// Retrieval info: CONSTANT: ENABLE_TX_8B_10B_I1I2_GENERATION STRING "OFF"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_SETTING NUMERIC "20"
+// Retrieval info: CONSTANT: FLIP_RX_OUT STRING "OFF"
+// Retrieval info: CONSTANT: FLIP_TX_IN STRING "OFF"
+// Retrieval info: CONSTANT: FORCE_DISPARITY_MODE STRING "OFF"
+// Retrieval info: CONSTANT: FOR_ENGINEERING_SAMPLE_DEVICE STRING "OFF"
+// Retrieval info: CONSTANT: INSTANTIATE_TRANSMITTER_PLL STRING "ON"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "NONE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altgxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: NUMBER_OF_QUADS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUPLEX"
+// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: PLL_INCLOCK_PERIOD NUMERIC "6400"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_SETTING NUMERIC "10"
+// Retrieval info: CONSTANT: PROTOCOL STRING "CUSTOM"
+// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RUN_LENGTH_ENABLE STRING "OFF"
+// Retrieval info: CONSTANT: RX_BANDWIDTH_TYPE STRING "NEW_LOW"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_ENABLE_DC_COUPLING STRING "OFF"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "ON"
+// Retrieval info: CONSTANT: RX_PPM_SETTING NUMERIC "1000"
+// Retrieval info: CONSTANT: SIGNAL_THRESHOLD_SELECT NUMERIC "530"
+// Retrieval info: CONSTANT: TX_TERMINATION NUMERIC "2"
+// Retrieval info: CONSTANT: USE_8B_10B_MODE STRING "OFF"
+// Retrieval info: CONSTANT: USE_AUTO_BIT_SLIP STRING "ON"
+// Retrieval info: CONSTANT: USE_CHANNEL_ALIGN STRING "OFF"
+// Retrieval info: CONSTANT: USE_DOUBLE_DATA_MODE STRING "ON"
+// Retrieval info: CONSTANT: USE_EQUALIZER_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: USE_GENERIC_FIFO STRING "OFF"
+// Retrieval info: CONSTANT: USE_PREEMPHASIS_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: USE_RATE_MATCH_FIFO STRING "OFF"
+// Retrieval info: CONSTANT: USE_RX_CLKOUT STRING "ON"
+// Retrieval info: CONSTANT: USE_RX_CORECLK STRING "OFF"
+// Retrieval info: CONSTANT: USE_RX_CRUCLK STRING "ON"
+// Retrieval info: CONSTANT: USE_SELF_TEST_MODE STRING "OFF"
+// Retrieval info: CONSTANT: USE_SYMBOL_ALIGN STRING "ON"
+// Retrieval info: CONSTANT: USE_TX_CORECLK STRING "ON"
+// Retrieval info: CONSTANT: USE_VOD_CTRL_SIGNAL STRING "OFF"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "800"
+// Retrieval info: USED_PORT: coreclk_out 0 0 1 0 OUTPUT NODEFVAL "coreclk_out[0..0]"
+// Retrieval info: USED_PORT: inclk 0 0 1 0 INPUT GND "inclk[0..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT GND "pll_areset[0..0]"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: pllenable 0 0 1 0 INPUT VCC "pllenable[0..0]"
+// Retrieval info: USED_PORT: rx_clkout 0 0 4 0 OUTPUT NODEFVAL "rx_clkout[3..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_enacdet 0 0 4 0 INPUT GND "rx_enacdet[3..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_in 0 0 4 0 INPUT GND "rx_in[3..0]"
+// Retrieval info: USED_PORT: rx_locked 0 0 4 0 OUTPUT NODEFVAL "rx_locked[3..0]"
+// Retrieval info: USED_PORT: rx_out 0 0 80 0 OUTPUT NODEFVAL "rx_out[79..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: rxanalogreset 0 0 4 0 INPUT GND "rxanalogreset[3..0]"
+// Retrieval info: USED_PORT: rxdigitalreset 0 0 4 0 INPUT GND "rxdigitalreset[3..0]"
+// Retrieval info: USED_PORT: tx_coreclk 0 0 4 0 INPUT GND "tx_coreclk[3..0]"
+// Retrieval info: USED_PORT: tx_in 0 0 80 0 INPUT GND "tx_in[79..0]"
+// Retrieval info: USED_PORT: tx_out 0 0 4 0 OUTPUT NODEFVAL "tx_out[3..0]"
+// Retrieval info: USED_PORT: txdigitalreset 0 0 4 0 INPUT GND "txdigitalreset[3..0]"
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: @pllenable 0 0 1 0 pllenable 0 0 1 0
+// Retrieval info: CONNECT: rx_locked 0 0 4 0 @rx_locked 0 0 4 0
+// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
+// Retrieval info: CONNECT: @txdigitalreset 0 0 4 0 txdigitalreset 0 0 4 0
+// Retrieval info: CONNECT: @rx_in 0 0 4 0 rx_in 0 0 4 0
+// Retrieval info: CONNECT: coreclk_out 0 0 1 0 @coreclk_out 0 0 1 0
+// Retrieval info: CONNECT: @tx_coreclk 0 0 4 0 tx_coreclk 0 0 4 0
+// Retrieval info: CONNECT: tx_out 0 0 4 0 @tx_out 0 0 4 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: rx_out 0 0 80 0 @rx_out 0 0 80 0
+// Retrieval info: CONNECT: rx_clkout 0 0 4 0 @rx_clkout 0 0 4 0
+// Retrieval info: CONNECT: @rxdigitalreset 0 0 4 0 rxdigitalreset 0 0 4 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rxanalogreset 0 0 4 0 rxanalogreset 0 0 4 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: @rx_enacdet 0 0 4 0 rx_enacdet 0 0 4 0
+// Retrieval info: CONNECT: @tx_in 0 0 80 0 tx_in 0 0 80 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_15625.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_15625.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_15625.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_15625.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_15625_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_1sgx_x4_15625_bb.v FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..cfe8e8975cd4eb579151edefb165ad72e57a07a0
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v
@@ -0,0 +1,1559 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_2agx_x1d_gen1_08p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// arriaii_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Internal Build 106 07/20/2008 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Arria II" elec_idle_infer_enable="false" enable_0ppm="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=1 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gxb_analog_power="2.5v" gxb_powerdown_width=1 intended_device_speed_grade=4 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_dprio_mode=0 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=0 rx_cru_divide_by=0 rx_cru_inclock0_period=10000 rx_cru_m_divider=1 rx_cru_multiply_by=0 rx_cru_n_divider=1 rx_cru_pfd_clk_select=0 rx_cru_vco_post_scale_divider=1 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.5v" tx_channel_bonding="indv" tx_channel_width=8 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=0 tx_pll_divide_by=0 tx_pll_inclk0_period=10000 tx_pll_m_divider=1 tx_pll_multiply_by=0 tx_pll_n_divider=1 tx_pll_pfd_clk_select=0 tx_pll_vco_post_scale_divider=1 tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 8.1 cbx_alt4gxb 2008:07:18:07:31:37:SJ cbx_mgl 2008:07:11:15:23:48:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = arriaii_hssi_calibration_block 1 arriaii_hssi_clock_divider 1 arriaii_hssi_cmu 1 arriaii_hssi_pll 2 arriaii_hssi_rx_pcs 1 arriaii_hssi_rx_pma 1 arriaii_hssi_tx_pcs 1 arriaii_hssi_tx_pma 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_2agx_x1d_gen1_08p_alt4gxb_sp59
+ (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) /* synthesis synthesis_clearbox=1 */;
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [1:0] powerdn;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ output [0:0] rx_ctrldetect;
+ input [0:0] rx_datain;
+ output [7:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [0:0] rx_freqlocked;
+ output [0:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [0:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ input [0:0] tx_ctrlenable;
+ input [7:0] tx_datain;
+ output [0:0] tx_dataout;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_ch_clk_div0_analogrefclkout;
+ wire wire_ch_clk_div0_analogrefclkpulse;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxadcepowerdown;
+ wire [3:0] wire_cent_unit0_rxadceresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire [1:0] analogfastrefclkout;
+ wire [1:0] analogrefclkout;
+ wire [0:0] analogrefclkpulse;
+ wire cal_blk_powerdown;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire fixedclk;
+ wire [5:0] fixedclk_in;
+ wire [0:0] nonusertocmu_out;
+ wire [0:0] pipedatavalid_out;
+ wire [0:0] pipeelecidle_out;
+ wire [9:0] pll0_clkin;
+ wire [3:0] pll0_out;
+ wire [1:0] pll_ch_dataout_wire;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire reconfig_clk;
+ wire [3:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [0:0] rx_bitslip;
+ wire [0:0] rx_coreclk_in;
+ wire [8:0] rx_cruclk_in;
+ wire [3:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [2:0] rx_elecidleinfersel;
+ wire [0:0] rx_enapatternalign;
+ wire [0:0] rx_freqlocked_wire;
+ wire [0:0] rx_locktodata;
+ wire [0:0] rx_locktodata_wire;
+ wire [0:0] rx_locktorefclk_wire;
+ wire [7:0] rx_out_wire;
+ wire [1:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [0:0] rx_phfifordenable;
+ wire [0:0] rx_phfiforeset;
+ wire [0:0] rx_phfifowrdisable;
+ wire [0:0] rx_pipestatetransdoneout;
+ wire [0:0] rx_pldcruclk_in;
+ wire [3:0] rx_pll_clkout;
+ wire [0:0] rx_pll_pfdrefclkout_wire;
+ wire [0:0] rx_plllocked_wire;
+ wire [0:0] rx_pma_clockout;
+ wire [0:0] rx_pma_dataout;
+ wire [0:0] rx_pma_locktorefout;
+ wire [19:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [0:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [0:0] rx_prbscidenable;
+ wire [19:0] rx_revparallelfdbkdata;
+ wire [0:0] rx_rmfiforeset;
+ wire [5:0] rx_rxcruresetout;
+ wire [0:0] rx_signaldetect_wire;
+ wire [5:0] tx_analogreset_out;
+ wire [0:0] tx_clkout_int_wire;
+ wire [0:0] tx_core_clkout_wire;
+ wire [0:0] tx_coreclk_in;
+ wire [7:0] tx_datain_wire;
+ wire [43:0] tx_datainfull;
+ wire [19:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [0:0] tx_forcedisp_wire;
+ wire [0:0] tx_invpolarity;
+ wire [0:0] tx_localrefclk;
+ wire [0:0] tx_phfiforeset;
+ wire [0:0] tx_pipedeemph;
+ wire [2:0] tx_pipemargin;
+ wire [1:0] tx_pipepowerdownout;
+ wire [3:0] tx_pipepowerstateout;
+ wire [0:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [0:0] tx_revparallellpbken;
+ wire [0:0] tx_rxdetectvalidout;
+ wire [0:0] tx_rxfoundout;
+ wire [0:0] txdetectrxout;
+
+ arriaii_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ arriaii_hssi_clock_divider ch_clk_div0
+ (
+ .analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_ch_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(pll0_out[3:0]),
+ .coreclkout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(),
+ .rateswitchout(),
+ .refclkout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .dprioin({100{1'b0}}),
+ .powerdn(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
+ ch_clk_div0.data_rate = 0,
+ ch_clk_div0.divide_by = 5,
+ ch_clk_div0.divider_type = "CHANNEL_REGULAR",
+ ch_clk_div0.dprio_config_mode = 6'h00,
+ ch_clk_div0.enable_dynamic_divider = "false",
+ ch_clk_div0.enable_refclk_out = "false",
+ ch_clk_div0.inclk_select = 0,
+ ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
+ ch_clk_div0.pre_divide_by = 1,
+ ch_clk_div0.refclk_divide_by = 0,
+ ch_clk_div0.refclk_multiply_by = 0,
+ ch_clk_div0.select_local_rate_switch_done = "false",
+ ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_coreclkout_phase_shift = 0,
+ ch_clk_div0.sim_refclkout_phase_shift = 0,
+ ch_clk_div0.use_coreclk_out_post_divider = "false",
+ ch_clk_div0.use_refclk_post_divider = "false",
+ ch_clk_div0.use_vco_bypass = "false",
+ ch_clk_div0.lpm_type = "arriaii_hssi_clock_divider";
+ arriaii_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(),
+ .cmudividerdprioin({600{1'b0}}),
+ .cmudividerdprioout(),
+ .cmuplldprioin({1800{1'b0}}),
+ .cmuplldprioout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(1'b1),
+ .dpriodisableout(),
+ .dprioin(1'b0),
+ .dprioload(1'b0),
+ .dpriooe(),
+ .dprioout(),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk(fixedclk_in[5:0]),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(wire_cent_unit0_rxadcepowerdown),
+ .rxadceresetout(wire_cent_unit0_rxadceresetout),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxdprioout(),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({1600{1'b0}}),
+ .rxpcsdprioout(),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpmadprioin({1800{1'b0}}),
+ .rxpmadprioout(),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txdprioout(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({600{1'b0}}),
+ .txpcsdprioout(),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout(),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({1800{1'b0}}),
+ .txpmadprioout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .rateswitch(1'b0),
+ .rateswitchdonein(1'b0),
+ .rxclk(1'b0),
+ .rxcoreclk(1'b0),
+ .rxdprioin({1200{1'b0}}),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({6000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txdprioin({600{1'b0}}),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 250000,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "none",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "local reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "false",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "none",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "false",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "2.5V",
+ cent_unit0.lpm_type = "arriaii_hssi_cmu";
+ arriaii_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.charge_pump_current_bits = 0,
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.inclk1_input_period = 5000,
+ rx_cdr_pll0.inclk2_input_period = 5000,
+ rx_cdr_pll0.inclk3_input_period = 5000,
+ rx_cdr_pll0.inclk4_input_period = 5000,
+ rx_cdr_pll0.inclk5_input_period = 5000,
+ rx_cdr_pll0.inclk6_input_period = 5000,
+ rx_cdr_pll0.inclk7_input_period = 5000,
+ rx_cdr_pll0.inclk8_input_period = 5000,
+ rx_cdr_pll0.inclk9_input_period = 5000,
+ rx_cdr_pll0.loop_filter_c_bits = 0,
+ rx_cdr_pll0.loop_filter_r_bits = 0,
+ rx_cdr_pll0.m = 1,
+ rx_cdr_pll0.n = 1,
+ rx_cdr_pll0.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll0.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.protocol_hint = "pcie",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_data_rate = 0,
+ rx_cdr_pll0.vco_divide_by = 0,
+ rx_cdr_pll0.vco_multiply_by = 0,
+ rx_cdr_pll0.vco_post_scale = 1,
+ rx_cdr_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.channel_num = 4,
+ tx_pll0.charge_pump_current_bits = 0,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.inclk1_input_period = 5000,
+ tx_pll0.inclk2_input_period = 5000,
+ tx_pll0.inclk3_input_period = 5000,
+ tx_pll0.inclk4_input_period = 5000,
+ tx_pll0.inclk5_input_period = 5000,
+ tx_pll0.inclk6_input_period = 5000,
+ tx_pll0.inclk7_input_period = 5000,
+ tx_pll0.inclk8_input_period = 5000,
+ tx_pll0.inclk9_input_period = 5000,
+ tx_pll0.loop_filter_c_bits = 0,
+ tx_pll0.loop_filter_r_bits = 0,
+ tx_pll0.m = 1,
+ tx_pll0.n = 1,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.protocol_hint = "pcie",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_data_rate = 0,
+ tx_pll0.vco_divide_by = 0,
+ tx_pll0.vco_multiply_by = 0,
+ tx_pll0.vco_post_scale = 1,
+ tx_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[0]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(),
+ .phfifooverflow(),
+ .phfifoptrsresetout(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(),
+ .phfifowrenableout(),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxnwrclk({3{1'b0}}),
+ .phfifoxnwrenable({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "none",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 8,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "local reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h00,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "none",
+ receive_pcs0.ph_fifo_xn_select = 1,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 250000,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "false",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h00,
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 1,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 0,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 4,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
+ .datain({{32{1'b0}}, tx_datain_wire[7:0]}),
+ .datainfull(tx_datainfull[43:0]),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifooverflow(),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifobyteserdisable(1'b0),
+ .phfifoptrsreset(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdclk({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .phfifoxnwrenable({3{1'b0}}),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.channel_bonding = "none",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 8,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h00,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs0.ph_fifo_xn_select = 1,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "local",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "false",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .fastrefclk0in(analogfastrefclkout[1:0]),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({analogrefclkout[1:0]}),
+ .refclk0inpulse(analogrefclkpulse[0]),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "1.5V",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 0,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h00,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "arriaii_hssi_tx_pma";
+ assign
+ analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
+ analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
+ analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
+ cal_blk_powerdown = 1'b1,
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ fixedclk = 1'b0,
+ fixedclk_in = {5'b00000, fixedclk},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[0]},
+ pipedatavalid_out = {wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[0]},
+ pipeelecidle_out = {wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs0_pipestatus},
+ pll0_clkin = {9'b000000000, pll_inclk_wire[0]},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_clk = 1'b0,
+ rx_analogreset_in = {3'b000, rx_analogreset[0]},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_bitslip = 1'b0,
+ rx_coreclk_in = {tx_core_clkout_wire[0]},
+ rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
+ rx_dataout = {rx_out_wire[7:0]},
+ rx_deserclock_in = {rx_pll_clkout[3:0]},
+ rx_digitalreset_in = {3'b000, rx_digitalreset[0]},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
+ rx_elecidleinfersel = {3{1'b0}},
+ rx_enapatternalign = 1'b0,
+ rx_freqlocked = {rx_freqlocked_wire[0]},
+ rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = 1'b0,
+ rx_locktodata_wire = {rx_locktodata[0]},
+ rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
+ rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {1200'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ rx_phfifordenable = 1'b1,
+ rx_phfiforeset = 1'b0,
+ rx_phfifowrdisable = 1'b0,
+ rx_pipestatetransdoneout = {wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[0]},
+ rx_pll_clkout = {wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {rx_plllocked_wire[0]},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
+ rx_pma_clockout = {wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ rx_powerdown = 1'b0,
+ rx_powerdown_in = {3'b000, rx_powerdown[0]},
+ rx_prbscidenable = 1'b0,
+ rx_revparallelfdbkdata = {wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = 1'b0,
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout = {tx_core_clkout_wire[0]},
+ tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
+ tx_core_clkout_wire = {tx_clkout_int_wire[0]},
+ tx_coreclk_in = {tx_core_clkout_wire[0]},
+ tx_datain_wire = {tx_datain[7:0]},
+ tx_datainfull = {44{1'b0}},
+ tx_dataout = {wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {3'b000, tx_digitalreset[0]},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
+ tx_dprioin_wire = {1050'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 150'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ tx_forcedisp_wire = {tx_forcedispcompliance[0]},
+ tx_invpolarity = 1'b0,
+ tx_localrefclk = {wire_transmit_pma0_clockout},
+ tx_phfiforeset = 1'b0,
+ tx_pipedeemph = 1'b0,
+ tx_pipemargin = {3{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = 1'b0,
+ tx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ tx_revparallellpbken = 1'b0,
+ tx_rxdetectvalidout = {wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma0_rxfoundout},
+ txdetectrxout = {wire_transmit_pcs0_txdetectrx};
+endmodule //altpcie_serdes_2agx_x1d_gen1_08p_alt4gxb_sp59
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_2agx_x1d_gen1_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout)/* synthesis synthesis_clearbox = 1 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [1:0] powerdn;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [0:0] tx_ctrlenable;
+ input [7:0] tx_datain;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ output [0:0] pll_locked;
+ output [0:0] rx_ctrldetect;
+ output [7:0] rx_dataout;
+ output [0:0] rx_freqlocked;
+ output [0:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [0:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [0:0] sub_wire7;
+ wire [2:0] sub_wire8;
+ wire [0:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [7:0] sub_wire12;
+ wire [0:0] rx_patterndetect = sub_wire0[0:0];
+ wire [0:0] rx_ctrldetect = sub_wire1[0:0];
+ wire [0:0] pipedatavalid = sub_wire2[0:0];
+ wire [0:0] pipephydonestatus = sub_wire3[0:0];
+ wire [0:0] rx_pll_locked = sub_wire4[0:0];
+ wire [0:0] rx_freqlocked = sub_wire5[0:0];
+ wire [0:0] tx_dataout = sub_wire6[0:0];
+ wire [0:0] pipeelecidle = sub_wire7[0:0];
+ wire [2:0] pipestatus = sub_wire8[2:0];
+ wire [0:0] rx_syncstatus = sub_wire9[0:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [0:0] pll_locked = sub_wire11[0:0];
+ wire [7:0] rx_dataout = sub_wire12[7:0];
+
+ altpcie_serdes_2agx_x1d_gen1_08p_alt4gxb_sp59 altpcie_serdes_2agx_x1d_gen1_08p_alt4gxb_sp59_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .rx_datain (rx_datain),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .rx_ctrldetect (sub_wire1),
+ .pipedatavalid (sub_wire2),
+ .pipephydonestatus (sub_wire3),
+ .rx_pll_locked (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .tx_dataout (sub_wire6),
+ .pipeelecidle (sub_wire7),
+ .pipestatus (sub_wire8),
+ .rx_syncstatus (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .pll_locked (sub_wire11),
+ .rx_dataout (sub_wire12));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.82"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.65"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.5"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE NUMERIC "4"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_analog_power STRING "2.5v"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_divide_by NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_multiply_by NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_divide_by NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_multiply_by NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 1 0 OUTPUT NODEFVAL "rx_pll_locked[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 1 0 @rx_pll_locked 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_08p.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_08p.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_08p.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_08p.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_08p.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_08p_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_08p_bb.v TRUE FALSE
+// Retrieval info: LIB_FILE: arriaii_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v
new file mode 100644
index 0000000000000000000000000000000000000000..496e41080c69e1d7de4c9463c11c8866c7cc0784
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v
@@ -0,0 +1,1600 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_2agx_x1d_gen1_16p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Internal Build 85 12/04/2008 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="true" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=1 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gxb_analog_power="2.5v" gxb_powerdown_width=1 input_clock_frequency="100 MHz" intended_device_speed_grade="4" intended_device_variant="ANY" loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 preemphasis_ctrl_1stposttap_setting=9 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=800 rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_n_divider=2 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.5v" tx_channel_bonding="indv" tx_channel_width=16 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=800 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_n_divider=2 tx_pll_vco_data_rate=800 tx_pll_vco_post_scale_divider=2 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=2 cal_blk_clk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 9.0 cbx_alt4gxb 2008:12:03:02:19:40:SJ cbx_mgl 2008:11:20:17:03:51:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = arriaii_hssi_calibration_block 1 arriaii_hssi_clock_divider 1 arriaii_hssi_cmu 1 arriaii_hssi_pll 2 arriaii_hssi_rx_pcs 1 arriaii_hssi_rx_pma 1 arriaii_hssi_tx_pcs 1 arriaii_hssi_tx_pma 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a
+ (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) ;
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [1:0] powerdn;
+ input reconfig_clk;
+ output [16:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ output [1:0] rx_ctrldetect;
+ input [0:0] rx_datain;
+ output [15:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ output [0:0] tx_dataout;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [0:0] pipe8b10binvpolarity;
+ tri0 pll_inclk;
+ tri0 [1:0] powerdn;
+ tri0 reconfig_clk;
+ tri0 [3:0] reconfig_togxb;
+ tri0 [0:0] rx_analogreset;
+ tri0 [0:0] rx_cruclk;
+ tri0 [0:0] rx_datain;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [1:0] tx_ctrlenable;
+ tri0 [15:0] tx_datain;
+ tri0 [0:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [0:0] tx_forcedispcompliance;
+ tri0 [0:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_ch_clk_div0_analogrefclkout;
+ wire wire_ch_clk_div0_analogrefclkpulse;
+ wire wire_cent_unit0_dprioout;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire wire_receive_pcs0_signaldetect;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire [1:0] analogfastrefclkout;
+ wire [1:0] analogrefclkout;
+ wire [0:0] analogrefclkpulse;
+ wire cal_blk_powerdown;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [5:0] cent_unit_txdetectrxpowerdn;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [5:0] fixedclk_to_cmu;
+ wire [2:0] grayelecidleinfersel_from_tx;
+ wire [0:0] nonusertocmu_out;
+ wire [0:0] pipedatavalid_out;
+ wire [0:0] pipeelecidle_out;
+ wire [9:0] pll0_clkin;
+ wire [3:0] pll0_out;
+ wire [1:0] pll_ch_dataout_wire;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire [0:0] reconfig_togxb_busy;
+ wire [5:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [0:0] rx_coreclk_in;
+ wire [8:0] rx_cruclk_in;
+ wire [3:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [2:0] rx_elecidleinfersel;
+ wire [0:0] rx_enapatternalign;
+ wire [0:0] rx_freqlocked_wire;
+ wire [0:0] rx_locktodata;
+ wire [0:0] rx_locktodata_wire;
+ wire [0:0] rx_locktorefclk_wire;
+ wire [15:0] rx_out_wire;
+ wire [1:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [0:0] rx_phfifordenable;
+ wire [0:0] rx_phfiforeset;
+ wire [0:0] rx_phfifowrdisable;
+ wire [0:0] rx_pipestatetransdoneout;
+ wire [0:0] rx_pldcruclk_in;
+ wire [3:0] rx_pll_clkout;
+ wire [0:0] rx_pll_pfdrefclkout_wire;
+ wire [0:0] rx_plllocked_wire;
+ wire [16:0] rx_pma_analogtestbus;
+ wire [0:0] rx_pma_clockout;
+ wire [0:0] rx_pma_dataout;
+ wire [0:0] rx_pma_locktorefout;
+ wire [19:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [0:0] rx_powerdown;
+ wire [5:0] rx_powerdown_in;
+ wire [0:0] rx_prbscidenable;
+ wire [19:0] rx_revparallelfdbkdata;
+ wire [0:0] rx_rmfiforeset;
+ wire [5:0] rx_rxcruresetout;
+ wire [0:0] rx_signaldetect_wire;
+ wire [5:0] tx_analogreset_out;
+ wire [0:0] tx_clkout_int_wire;
+ wire [0:0] tx_core_clkout_wire;
+ wire [0:0] tx_coreclk_in;
+ wire [15:0] tx_datain_wire;
+ wire [43:0] tx_datainfull;
+ wire [19:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [1:0] tx_forcedisp_wire;
+ wire [0:0] tx_invpolarity;
+ wire [0:0] tx_localrefclk;
+ wire [0:0] tx_pcs_forceelecidleout;
+ wire [0:0] tx_phfiforeset;
+ wire [0:0] tx_pipedeemph;
+ wire [2:0] tx_pipemargin;
+ wire [1:0] tx_pipepowerdownout;
+ wire [3:0] tx_pipepowerstateout;
+ wire [0:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [0:0] tx_revparallellpbken;
+ wire [0:0] tx_rxdetectvalidout;
+ wire [0:0] tx_rxfoundout;
+ wire [0:0] txdetectrxout;
+
+ arriaii_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ arriaii_hssi_clock_divider ch_clk_div0
+ (
+ .analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_ch_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(pll0_out[3:0]),
+ .coreclkout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(),
+ .rateswitchout(),
+ .refclkout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .dprioin({100{1'b0}}),
+ .powerdn(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
+ ch_clk_div0.data_rate = 800,
+ ch_clk_div0.divide_by = 5,
+ ch_clk_div0.divider_type = "CHANNEL_REGULAR",
+ ch_clk_div0.dprio_config_mode = 6'h00,
+ ch_clk_div0.effective_data_rate = "2500 Mbps",
+ ch_clk_div0.enable_dynamic_divider = "false",
+ ch_clk_div0.enable_refclk_out = "false",
+ ch_clk_div0.inclk_select = 0,
+ ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
+ ch_clk_div0.pre_divide_by = 1,
+ ch_clk_div0.select_local_rate_switch_done = "false",
+ ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_coreclkout_phase_shift = 0,
+ ch_clk_div0.sim_refclkout_phase_shift = 0,
+ ch_clk_div0.use_coreclk_out_post_divider = "true",
+ ch_clk_div0.use_refclk_post_divider = "false",
+ ch_clk_div0.use_vco_bypass = "false",
+ ch_clk_div0.lpm_type = "arriaii_hssi_clock_divider";
+ arriaii_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(),
+ .cmudividerdprioin({600{1'b0}}),
+ .cmudividerdprioout(),
+ .cmuplldprioin({1800{1'b0}}),
+ .cmuplldprioout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(1'b1),
+ .dpriodisableout(),
+ .dprioin(1'b0),
+ .dprioload(1'b0),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .fixedclk({{5{1'b0}}, fixedclk_to_cmu[0]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({1600{1'b0}}),
+ .rxpcsdprioout(),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpmadprioin({1800{1'b0}}),
+ .rxpmadprioout(),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({600{1'b0}}),
+ .txpcsdprioout(),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout(),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({1800{1'b0}}),
+ .txpmadprioout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchdonein(1'b0),
+ .rxclk(1'b0),
+ .rxcoreclk(1'b0),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 250000,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "none",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "local reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "none",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "2.5V",
+ cent_unit0.lpm_type = "arriaii_hssi_cmu";
+ arriaii_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.bandwidth_type = "Medium",
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.input_clock_frequency = "100 MHz",
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 2,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.protocol_hint = "pcie",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_data_rate = 800,
+ rx_cdr_pll0.vco_post_scale = 2,
+ rx_cdr_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.bandwidth_type = "High",
+ tx_pll0.channel_num = 4,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.input_clock_frequency = "100 MHz",
+ tx_pll0.m = 25,
+ tx_pll0.n = 2,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pfd_fb_select = "internal",
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.protocol_hint = "pcie",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_data_rate = 800,
+ tx_pll0.vco_post_scale = 2,
+ tx_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(),
+ .phfifooverflow(),
+ .phfifoptrsresetout(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(),
+ .phfifowrenableout(),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(wire_receive_pcs0_signaldetect),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxnwrclk({3{1'b0}}),
+ .phfifoxnwrenable({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "none",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "local reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h00,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "none",
+ receive_pcs0.ph_fifo_xn_select = 1,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 250000,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 6,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 0,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 0,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h00,
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "false",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 1,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 4,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
+ .datain({{24{1'b0}}, tx_datain_wire[15:0]}),
+ .datainfull({tx_datainfull[43:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifooverflow(),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifobyteserdisable(1'b0),
+ .phfifoptrsreset(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdclk({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .phfifoxnwrenable({3{1'b0}}),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.channel_bonding = "none",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h00,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs0.ph_fifo_xn_select = 1,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "local",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .fastrefclk0in(analogfastrefclkout[1:0]),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({analogrefclkout[1:0]}),
+ .refclk0inpulse(analogrefclkpulse[0]),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .pclk({5{1'b0}}),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "1.5V",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 0,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h00,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.physical_clkin0_mapping = "x1",
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 9,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 2,
+ transmit_pma0.lpm_type = "arriaii_hssi_tx_pma";
+ assign
+ analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
+ analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
+ analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
+ cal_blk_powerdown = 1'b1,
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ fixedclk_to_cmu = {6{reconfig_clk}},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs0_grayelecidleinferselout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[0]},
+ pipedatavalid_out = {wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[0]},
+ pipeelecidle_out = {wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs0_pipestatus},
+ pll0_clkin = {9'b000000000, pll_inclk_wire[0]},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ rx_analogreset_in = {5'b00000, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_coreclk_in = {tx_core_clkout_wire[0]},
+ rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[15:0]},
+ rx_deserclock_in = {rx_pll_clkout[3:0]},
+ rx_digitalreset_in = {3'b000, rx_digitalreset[0]},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
+ rx_elecidleinfersel = {3{1'b0}},
+ rx_enapatternalign = 1'b0,
+ rx_freqlocked = {rx_freqlocked_wire[0]},
+ rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = 1'b0,
+ rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[0])},
+ rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {1200'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ rx_phfifordenable = 1'b1,
+ rx_phfiforeset = 1'b0,
+ rx_phfifowrdisable = 1'b0,
+ rx_pipestatetransdoneout = {wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[0]},
+ rx_pll_clkout = {wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {rx_plllocked_wire[0]},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
+ rx_pma_analogtestbus = {12'b000000000000, wire_receive_pma0_analogtestbus[5:2], 1'b0},
+ rx_pma_clockout = {wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ rx_powerdown = 1'b0,
+ rx_powerdown_in = {5'b00000, rx_powerdown[0]},
+ rx_prbscidenable = 1'b0,
+ rx_revparallelfdbkdata = {wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = 1'b0,
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs0_syncstatus[1:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout = {tx_core_clkout_wire[0]},
+ tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
+ tx_core_clkout_wire = {tx_clkout_int_wire[0]},
+ tx_coreclk_in = {tx_core_clkout_wire[0]},
+ tx_datain_wire = {tx_datain[15:0]},
+ tx_datainfull = {44{1'b0}},
+ tx_dataout = {wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {3'b000, tx_digitalreset[0]},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
+ tx_dprioin_wire = {1050'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 150'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = 1'b0,
+ tx_localrefclk = {wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = 1'b0,
+ tx_pipedeemph = 1'b0,
+ tx_pipemargin = {3{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = 1'b0,
+ tx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ tx_revparallellpbken = 1'b0,
+ tx_rxdetectvalidout = {wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma0_rxfoundout},
+ txdetectrxout = {wire_transmit_pcs0_txdetectrx};
+endmodule //altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_2agx_x1d_gen1_16p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [1:0] powerdn;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ output [0:0] pll_locked;
+ output [16:0] reconfig_fromgxb;
+ output [1:0] rx_ctrldetect;
+ output [15:0] rx_dataout;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [0:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+
+
+ wire [1:0] sub_wire0;
+ wire [1:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [0:0] sub_wire7;
+ wire [2:0] sub_wire8;
+ wire [1:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [16:0] sub_wire11;
+ wire [0:0] sub_wire12;
+ wire [15:0] sub_wire13;
+ wire [1:0] rx_patterndetect = sub_wire0[1:0];
+ wire [1:0] rx_ctrldetect = sub_wire1[1:0];
+ wire [0:0] pipedatavalid = sub_wire2[0:0];
+ wire [0:0] pipephydonestatus = sub_wire3[0:0];
+ wire [0:0] rx_pll_locked = sub_wire4[0:0];
+ wire [0:0] rx_freqlocked = sub_wire5[0:0];
+ wire [0:0] tx_dataout = sub_wire6[0:0];
+ wire [0:0] pipeelecidle = sub_wire7[0:0];
+ wire [2:0] pipestatus = sub_wire8[2:0];
+ wire [1:0] rx_syncstatus = sub_wire9[1:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [16:0] reconfig_fromgxb = sub_wire11[16:0];
+ wire [0:0] pll_locked = sub_wire12[0:0];
+ wire [15:0] rx_dataout = sub_wire13[15:0];
+
+ altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .reconfig_clk (reconfig_clk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .rx_ctrldetect (sub_wire1),
+ .pipedatavalid (sub_wire2),
+ .pipephydonestatus (sub_wire3),
+ .rx_pll_locked (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .tx_dataout (sub_wire6),
+ .pipeelecidle (sub_wire7),
+ .pipestatus (sub_wire8),
+ .rx_syncstatus (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .pll_locked (sub_wire12),
+ .rx_dataout (sub_wire13));
+ defparam
+ altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "2.5v"
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "4"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "9"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "2"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "true"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_vco_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_slew_rate STRING "off"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 2 0 OUTPUT NODEFVAL "rx_ctrldetect[1..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 16 0 OUTPUT NODEFVAL "rx_dataout[15..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 1 0 OUTPUT NODEFVAL "rx_pll_locked[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 2 0 INPUT NODEFVAL "tx_ctrlenable[1..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 16 0 INPUT NODEFVAL "tx_datain[15..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 2 0 @rx_ctrldetect 0 0 2 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 16 0 @rx_dataout 0 0 16 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 1 0 @rx_pll_locked 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 2 0 tx_ctrlenable 0 0 2 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: CONNECT: @tx_datain 0 0 16 0 tx_datain 0 0 16 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p_bb.v TRUE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..8675cff38c8198aeb62165e5dda131945478b772
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v
@@ -0,0 +1,3582 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_2agx_x4d_gen1_08p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// arriaii_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Internal Build 106 07/20/2008 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Arria II" elec_idle_infer_enable="false" enable_0ppm="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=1 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gxb_analog_power="2.5v" gxb_powerdown_width=1 intended_device_speed_grade=4 loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_dprio_mode=0 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=0 rx_cru_divide_by=0 rx_cru_inclock0_period=10000 rx_cru_m_divider=1 rx_cru_multiply_by=0 rx_cru_n_divider=1 rx_cru_pfd_clk_select=0 rx_cru_vco_post_scale_divider=1 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.5v" tx_channel_bonding="x4" tx_channel_width=8 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=0 tx_pll_divide_by=0 tx_pll_inclk0_period=10000 tx_pll_m_divider=1 tx_pll_multiply_by=0 tx_pll_n_divider=1 tx_pll_pfd_clk_select=0 tx_pll_vco_post_scale_divider=1 tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 8.1 cbx_alt4gxb 2008:07:18:07:31:37:SJ cbx_mgl 2008:07:11:15:23:48:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = arriaii_hssi_calibration_block 1 arriaii_hssi_clock_divider 1 arriaii_hssi_cmu 1 arriaii_hssi_pll 5 arriaii_hssi_rx_pcs 4 arriaii_hssi_rx_pma 4 arriaii_hssi_tx_pcs 4 arriaii_hssi_tx_pma 4
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_2agx_x4d_gen1_08p_alt4gxb_jc59
+ (
+ cal_blk_clk,
+ coreclkout,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) /* synthesis synthesis_clearbox=1 */;
+ input cal_blk_clk;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [7:0] powerdn;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ output [3:0] rx_ctrldetect;
+ input [3:0] rx_datain;
+ output [31:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [3:0] rx_freqlocked;
+ output [3:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [3:0] rx_syncstatus;
+ input [3:0] tx_ctrlenable;
+ input [31:0] tx_datain;
+ output [3:0] tx_dataout;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_central_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div0_analogrefclkout;
+ wire wire_central_clk_div0_analogrefclkpulse;
+ wire wire_central_clk_div0_coreclkout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_refclkout;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxadcepowerdown;
+ wire [3:0] wire_cent_unit0_rxadceresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire wire_receive_pcs0_rateswitchout;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire wire_receive_pcs1_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire wire_receive_pcs1_rateswitchout;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_pipedatavalid;
+ wire wire_receive_pcs2_pipeelecidle;
+ wire wire_receive_pcs2_pipephydonestatus;
+ wire wire_receive_pcs2_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs2_pipestatus;
+ wire wire_receive_pcs2_rateswitchout;
+ wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_pipedatavalid;
+ wire wire_receive_pcs3_pipeelecidle;
+ wire wire_receive_pcs3_pipephydonestatus;
+ wire wire_receive_pcs3_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs3_pipestatus;
+ wire wire_receive_pcs3_rateswitchout;
+ wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_clkout;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs2_clkout;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs2_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs2_pipepowerstateout;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs3_clkout;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs3_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs3_pipepowerstateout;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire wire_transmit_pma2_rxdetectvalidout;
+ wire wire_transmit_pma2_rxfoundout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire wire_transmit_pma3_rxdetectvalidout;
+ wire wire_transmit_pma3_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [0:0] cent_unit_clkdivpowerdn;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [3:0] clk_div_clk0in;
+ wire [0:0] clk_div_pclkin;
+ wire [1:0] cmu_analogfastrefclkout;
+ wire [1:0] cmu_analogrefclkout;
+ wire [0:0] cmu_analogrefclkpulse;
+ wire [0:0] coreclkout_wire;
+ wire fixedclk;
+ wire [5:0] fixedclk_in;
+ wire [0:0] int_hiprateswtichdone;
+ wire [3:0] int_rx_coreclkout;
+ wire [3:0] int_rx_phfifobyteserdisable;
+ wire [3:0] int_rx_phfifoptrsresetout;
+ wire [3:0] int_rx_phfifordenableout;
+ wire [3:0] int_rx_phfiforesetout;
+ wire [3:0] int_rx_phfifowrdisableout;
+ wire [11:0] int_rx_phfifoxnbytesel;
+ wire [11:0] int_rx_phfifoxnrdenable;
+ wire [11:0] int_rx_phfifoxnwrclk;
+ wire [11:0] int_rx_phfifoxnwrenable;
+ wire [0:0] int_rxcoreclk;
+ wire [0:0] int_rxphfifordenable;
+ wire [0:0] int_rxphfiforeset;
+ wire [0:0] int_rxphfifox4byteselout;
+ wire [0:0] int_rxphfifox4rdenableout;
+ wire [0:0] int_rxphfifox4wrclkout;
+ wire [0:0] int_rxphfifox4wrenableout;
+ wire [3:0] int_tx_coreclkout;
+ wire [3:0] int_tx_phfiforddisableout;
+ wire [3:0] int_tx_phfiforesetout;
+ wire [3:0] int_tx_phfifowrenableout;
+ wire [11:0] int_tx_phfifoxnbytesel;
+ wire [11:0] int_tx_phfifoxnrdclk;
+ wire [11:0] int_tx_phfifoxnrdenable;
+ wire [11:0] int_tx_phfifoxnwrenable;
+ wire [0:0] int_txcoreclk;
+ wire [0:0] int_txphfiforddisable;
+ wire [0:0] int_txphfiforeset;
+ wire [0:0] int_txphfifowrenable;
+ wire [0:0] int_txphfifox4byteselout;
+ wire [0:0] int_txphfifox4rdclkout;
+ wire [0:0] int_txphfifox4rdenableout;
+ wire [0:0] int_txphfifox4wrenableout;
+ wire [0:0] nonusertocmu_out;
+ wire [3:0] pipedatavalid_out;
+ wire [3:0] pipeelecidle_out;
+ wire [9:0] pll0_clkin;
+ wire [3:0] pll0_out;
+ wire [3:0] pll1_out;
+ wire [7:0] pll_ch_dataout_wire;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire reconfig_clk;
+ wire [0:0] refclk_pma;
+ wire [3:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [3:0] rx_bitslip;
+ wire [3:0] rx_coreclk_in;
+ wire [35:0] rx_cruclk_in;
+ wire [15:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [11:0] rx_elecidleinfersel;
+ wire [3:0] rx_enapatternalign;
+ wire [3:0] rx_freqlocked_wire;
+ wire [3:0] rx_locktodata;
+ wire [3:0] rx_locktodata_wire;
+ wire [3:0] rx_locktorefclk_wire;
+ wire [31:0] rx_out_wire;
+ wire [7:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [3:0] rx_phfifordenable;
+ wire [3:0] rx_phfiforeset;
+ wire [3:0] rx_phfifowrdisable;
+ wire [3:0] rx_pipestatetransdoneout;
+ wire [3:0] rx_pldcruclk_in;
+ wire [15:0] rx_pll_clkout;
+ wire [3:0] rx_pll_pfdrefclkout_wire;
+ wire [3:0] rx_plllocked_wire;
+ wire [3:0] rx_pma_clockout;
+ wire [3:0] rx_pma_dataout;
+ wire [3:0] rx_pma_locktorefout;
+ wire [79:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [3:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [3:0] rx_prbscidenable;
+ wire [79:0] rx_revparallelfdbkdata;
+ wire [3:0] rx_rmfiforeset;
+ wire [5:0] rx_rxcruresetout;
+ wire [3:0] rx_signaldetect_wire;
+ wire [0:0] rxphfifowrdisable;
+ wire [5:0] tx_analogreset_out;
+ wire [3:0] tx_clkout_int_wire;
+ wire [3:0] tx_coreclk_in;
+ wire [31:0] tx_datain_wire;
+ wire [175:0] tx_datainfull;
+ wire [79:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [3:0] tx_forcedisp_wire;
+ wire [3:0] tx_invpolarity;
+ wire [3:0] tx_localrefclk;
+ wire [3:0] tx_phfiforeset;
+ wire [3:0] tx_pipedeemph;
+ wire [11:0] tx_pipemargin;
+ wire [7:0] tx_pipepowerdownout;
+ wire [15:0] tx_pipepowerstateout;
+ wire [3:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [3:0] tx_revparallellpbken;
+ wire [3:0] tx_rxdetectvalidout;
+ wire [3:0] tx_rxfoundout;
+ wire [3:0] txdetectrxout;
+
+ arriaii_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ arriaii_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[3:0]),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkin({2{clk_div_pclkin[0]}}),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .dprioin({100{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .vcobypassin(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.data_rate = 0,
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.enable_dynamic_divider = "false",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclk_divide_by = 0,
+ central_clk_div0.refclk_multiply_by = 0,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_rate_switch_base_clock = "true",
+ central_clk_div0.select_local_refclk = "true",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "false",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "arriaii_hssi_clock_divider";
+ arriaii_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin({600{1'b0}}),
+ .cmudividerdprioout(),
+ .cmuplldprioin({1800{1'b0}}),
+ .cmuplldprioout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(1'b1),
+ .dpriodisableout(),
+ .dprioin(1'b0),
+ .dprioload(1'b0),
+ .dpriooe(),
+ .dprioout(),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk(fixedclk_in[5:0]),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(wire_cent_unit0_rxadcepowerdown),
+ .rxadceresetout(wire_cent_unit0_rxadceresetout),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxdprioout(),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({1600{1'b0}}),
+ .rxpcsdprioout(),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({1800{1'b0}}),
+ .rxpmadprioout(),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txdprioout(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({600{1'b0}}),
+ .txpcsdprioout(),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({1800{1'b0}}),
+ .txpmadprioout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .rateswitch(1'b0),
+ .rxdprioin({1200{1'b0}}),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({6000{1'b0}}),
+ .txdprioin({600{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.dprio_config_mode = 6'h00,
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 250000,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "x4",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "false",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "x4",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "false",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "2.5V",
+ cent_unit0.lpm_type = "arriaii_hssi_cmu";
+ arriaii_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.charge_pump_current_bits = 0,
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.inclk1_input_period = 5000,
+ rx_cdr_pll0.inclk2_input_period = 5000,
+ rx_cdr_pll0.inclk3_input_period = 5000,
+ rx_cdr_pll0.inclk4_input_period = 5000,
+ rx_cdr_pll0.inclk5_input_period = 5000,
+ rx_cdr_pll0.inclk6_input_period = 5000,
+ rx_cdr_pll0.inclk7_input_period = 5000,
+ rx_cdr_pll0.inclk8_input_period = 5000,
+ rx_cdr_pll0.inclk9_input_period = 5000,
+ rx_cdr_pll0.loop_filter_c_bits = 0,
+ rx_cdr_pll0.loop_filter_r_bits = 0,
+ rx_cdr_pll0.m = 1,
+ rx_cdr_pll0.n = 1,
+ rx_cdr_pll0.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll0.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.protocol_hint = "pcie",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_data_rate = 0,
+ rx_cdr_pll0.vco_divide_by = 0,
+ rx_cdr_pll0.vco_multiply_by = 0,
+ rx_cdr_pll0.vco_post_scale = 1,
+ rx_cdr_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[17:9]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.charge_pump_current_bits = 0,
+ rx_cdr_pll1.dprio_config_mode = 6'h00,
+ rx_cdr_pll1.inclk0_input_period = 10000,
+ rx_cdr_pll1.inclk1_input_period = 5000,
+ rx_cdr_pll1.inclk2_input_period = 5000,
+ rx_cdr_pll1.inclk3_input_period = 5000,
+ rx_cdr_pll1.inclk4_input_period = 5000,
+ rx_cdr_pll1.inclk5_input_period = 5000,
+ rx_cdr_pll1.inclk6_input_period = 5000,
+ rx_cdr_pll1.inclk7_input_period = 5000,
+ rx_cdr_pll1.inclk8_input_period = 5000,
+ rx_cdr_pll1.inclk9_input_period = 5000,
+ rx_cdr_pll1.loop_filter_c_bits = 0,
+ rx_cdr_pll1.loop_filter_r_bits = 0,
+ rx_cdr_pll1.m = 1,
+ rx_cdr_pll1.n = 1,
+ rx_cdr_pll1.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll1.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll1.pfd_clk_select = 0,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.protocol_hint = "pcie",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_data_rate = 0,
+ rx_cdr_pll1.vco_divide_by = 0,
+ rx_cdr_pll1.vco_multiply_by = 0,
+ rx_cdr_pll1.vco_post_scale = 1,
+ rx_cdr_pll1.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[26:18]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.charge_pump_current_bits = 0,
+ rx_cdr_pll2.dprio_config_mode = 6'h00,
+ rx_cdr_pll2.inclk0_input_period = 10000,
+ rx_cdr_pll2.inclk1_input_period = 5000,
+ rx_cdr_pll2.inclk2_input_period = 5000,
+ rx_cdr_pll2.inclk3_input_period = 5000,
+ rx_cdr_pll2.inclk4_input_period = 5000,
+ rx_cdr_pll2.inclk5_input_period = 5000,
+ rx_cdr_pll2.inclk6_input_period = 5000,
+ rx_cdr_pll2.inclk7_input_period = 5000,
+ rx_cdr_pll2.inclk8_input_period = 5000,
+ rx_cdr_pll2.inclk9_input_period = 5000,
+ rx_cdr_pll2.loop_filter_c_bits = 0,
+ rx_cdr_pll2.loop_filter_r_bits = 0,
+ rx_cdr_pll2.m = 1,
+ rx_cdr_pll2.n = 1,
+ rx_cdr_pll2.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll2.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll2.pfd_clk_select = 0,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.protocol_hint = "pcie",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_data_rate = 0,
+ rx_cdr_pll2.vco_divide_by = 0,
+ rx_cdr_pll2.vco_multiply_by = 0,
+ rx_cdr_pll2.vco_post_scale = 1,
+ rx_cdr_pll2.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[35:27]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.charge_pump_current_bits = 0,
+ rx_cdr_pll3.dprio_config_mode = 6'h00,
+ rx_cdr_pll3.inclk0_input_period = 10000,
+ rx_cdr_pll3.inclk1_input_period = 5000,
+ rx_cdr_pll3.inclk2_input_period = 5000,
+ rx_cdr_pll3.inclk3_input_period = 5000,
+ rx_cdr_pll3.inclk4_input_period = 5000,
+ rx_cdr_pll3.inclk5_input_period = 5000,
+ rx_cdr_pll3.inclk6_input_period = 5000,
+ rx_cdr_pll3.inclk7_input_period = 5000,
+ rx_cdr_pll3.inclk8_input_period = 5000,
+ rx_cdr_pll3.inclk9_input_period = 5000,
+ rx_cdr_pll3.loop_filter_c_bits = 0,
+ rx_cdr_pll3.loop_filter_r_bits = 0,
+ rx_cdr_pll3.m = 1,
+ rx_cdr_pll3.n = 1,
+ rx_cdr_pll3.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll3.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll3.pfd_clk_select = 0,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.protocol_hint = "pcie",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_data_rate = 0,
+ rx_cdr_pll3.vco_divide_by = 0,
+ rx_cdr_pll3.vco_multiply_by = 0,
+ rx_cdr_pll3.vco_post_scale = 1,
+ rx_cdr_pll3.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.channel_num = 4,
+ tx_pll0.charge_pump_current_bits = 0,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.inclk1_input_period = 5000,
+ tx_pll0.inclk2_input_period = 5000,
+ tx_pll0.inclk3_input_period = 5000,
+ tx_pll0.inclk4_input_period = 5000,
+ tx_pll0.inclk5_input_period = 5000,
+ tx_pll0.inclk6_input_period = 5000,
+ tx_pll0.inclk7_input_period = 5000,
+ tx_pll0.inclk8_input_period = 5000,
+ tx_pll0.inclk9_input_period = 5000,
+ tx_pll0.loop_filter_c_bits = 0,
+ tx_pll0.loop_filter_r_bits = 0,
+ tx_pll0.m = 1,
+ tx_pll0.n = 1,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.protocol_hint = "pcie",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_data_rate = 0,
+ tx_pll0.vco_divide_by = 0,
+ tx_pll0.vco_multiply_by = 0,
+ tx_pll0.vco_post_scale = 1,
+ tx_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[0]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x4",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 8,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h00,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 250000,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "false",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[1]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.auto_spd_self_switch_enable = "false",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_mask_cycle = 800,
+ receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x4",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 8,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h00,
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "false",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 250000,
+ receive_pcs1.protocol_hint = "pcie",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rxstatus_error_report_mode = 0,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "false",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[2]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[8:6]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs2_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs2_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[5:4]),
+ .pipepowerstate(tx_pipepowerstateout[11:8]),
+ .pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs2_pipestatus),
+ .powerdn(powerdn[5:4]),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[2]),
+ .rxfound(rx_pcs_rxfound_wire[5:4]),
+ .signaldetected(rx_signaldetect_wire[2]),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "false",
+ receive_pcs2.allow_pipe_polarity_inversion = "true",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 14,
+ receive_pcs2.auto_spd_self_switch_enable = "false",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_enable = "true",
+ receive_pcs2.cdrctrl_mask_cycle = 800,
+ receive_pcs2.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs2.cdrctrl_rxvalid_mask = "true",
+ receive_pcs2.channel_bonding = "x4",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 8,
+ receive_pcs2.clk1_mux_select = "recovered clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "false",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "pipe",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs2.deskew_pattern = "0",
+ receive_pcs2.disable_auto_idle_insertion = "false",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h00,
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 16,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 17,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "false",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 250000,
+ receive_pcs2.protocol_hint = "pcie",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "false",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs2.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs2.rate_match_pattern_size = 20,
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "true",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rxstatus_error_report_mode = 0,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "false",
+ receive_pcs2.use_double_data_mode = "false",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[3]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[11:9]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs3_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs3_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[7:6]),
+ .pipepowerstate(tx_pipepowerstateout[15:12]),
+ .pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs3_pipestatus),
+ .powerdn(powerdn[7:6]),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[3]),
+ .rxfound(rx_pcs_rxfound_wire[7:6]),
+ .signaldetected(rx_signaldetect_wire[3]),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "false",
+ receive_pcs3.allow_pipe_polarity_inversion = "true",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 14,
+ receive_pcs3.auto_spd_self_switch_enable = "false",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_enable = "true",
+ receive_pcs3.cdrctrl_mask_cycle = 800,
+ receive_pcs3.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs3.cdrctrl_rxvalid_mask = "true",
+ receive_pcs3.channel_bonding = "x4",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 8,
+ receive_pcs3.clk1_mux_select = "recovered clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "false",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "pipe",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs3.deskew_pattern = "0",
+ receive_pcs3.disable_auto_idle_insertion = "false",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h00,
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 16,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 17,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "false",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 250000,
+ receive_pcs3.protocol_hint = "pcie",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "false",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs3.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs3.rate_match_pattern_size = 20,
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "true",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rxstatus_error_report_mode = 0,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "false",
+ receive_pcs3.use_double_data_mode = "false",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h00,
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 1,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 0,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 4,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h00,
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eqa_ctrl = 0,
+ receive_pma1.eqb_ctrl = 0,
+ receive_pma1.eqc_ctrl = 0,
+ receive_pma1.eqd_ctrl = 1,
+ receive_pma1.eqv_ctrl = 0,
+ receive_pma1.force_signal_detect = "true",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 0,
+ receive_pma1.protocol_hint = "pcie",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma1.signal_detect_loss_threshold = 4,
+ receive_pma1.termination = "OCT 100 Ohms",
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma2_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.allow_serial_loopback = "false",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = "0.82V",
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h00,
+ receive_pma2.eq_dc_gain = 3,
+ receive_pma2.eqa_ctrl = 0,
+ receive_pma2.eqb_ctrl = 0,
+ receive_pma2.eqc_ctrl = 0,
+ receive_pma2.eqd_ctrl = 1,
+ receive_pma2.eqv_ctrl = 0,
+ receive_pma2.force_signal_detect = "true",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 0,
+ receive_pma2.protocol_hint = "pcie",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma2.signal_detect_loss_threshold = 4,
+ receive_pma2.termination = "OCT 100 Ohms",
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma3_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.allow_serial_loopback = "false",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = "0.82V",
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h00,
+ receive_pma3.eq_dc_gain = 3,
+ receive_pma3.eqa_ctrl = 0,
+ receive_pma3.eqb_ctrl = 0,
+ receive_pma3.eqc_ctrl = 0,
+ receive_pma3.eqd_ctrl = 1,
+ receive_pma3.eqv_ctrl = 0,
+ receive_pma3.force_signal_detect = "true",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 0,
+ receive_pma3.protocol_hint = "pcie",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma3.signal_detect_loss_threshold = 4,
+ receive_pma3.termination = "OCT 100 Ohms",
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
+ .datain({{32{1'b0}}, tx_datain_wire[7:0]}),
+ .datainfull(tx_datainfull[43:0]),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.channel_bonding = "x4",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 8,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h00,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "false",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(wire_transmit_pcs1_clkout),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[1]}),
+ .datain({{32{1'b0}}, tx_datain_wire[15:8]}),
+ .datainfull(tx_datainfull[87:44]),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[1]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[1]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[1]),
+ .pipetxdeemph(tx_pipedeemph[1]),
+ .pipetxmargin(tx_pipemargin[5:3]),
+ .pipetxswing(tx_pipeswing[1]),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.auto_spd_self_switch_enable = "false",
+ transmit_pcs1.channel_bonding = "x4",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 8,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h00,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "false",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(wire_transmit_pcs2_clkout),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[2]}),
+ .datain({{32{1'b0}}, tx_datain_wire[23:16]}),
+ .datainfull(tx_datainfull[131:88]),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(tx_detectrxloop[2]),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[2]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[2]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[2]),
+ .pipetxdeemph(tx_pipedeemph[2]),
+ .pipetxmargin(tx_pipemargin[8:6]),
+ .pipetxswing(tx_pipeswing[2]),
+ .powerdn(powerdn[5:4]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[59:40]),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "false",
+ transmit_pcs2.auto_spd_self_switch_enable = "false",
+ transmit_pcs2.channel_bonding = "x4",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 8,
+ transmit_pcs2.core_clock_0ppm = "false",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "pipe",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "new",
+ transmit_pcs2.dprio_config_mode = 6'h00,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "true",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "pcie",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "false",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(wire_transmit_pcs3_clkout),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[3]}),
+ .datain({{32{1'b0}}, tx_datain_wire[31:24]}),
+ .datainfull(tx_datainfull[175:132]),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(tx_detectrxloop[3]),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[3]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[3]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[3]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[3]),
+ .pipetxdeemph(tx_pipedeemph[3]),
+ .pipetxmargin(tx_pipemargin[11:9]),
+ .pipetxswing(tx_pipeswing[3]),
+ .powerdn(powerdn[7:6]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[79:60]),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "false",
+ transmit_pcs3.auto_spd_self_switch_enable = "false",
+ transmit_pcs3.channel_bonding = "x4",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 8,
+ transmit_pcs3.core_clock_0ppm = "false",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "pipe",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "new",
+ transmit_pcs3.dprio_config_mode = 6'h00,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "true",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "pcie",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "false",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "1.5V",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h00,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "1.5V",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h00,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.preemp_pretap = 0,
+ transmit_pma1.preemp_pretap_inv = "false",
+ transmit_pma1.preemp_tap_1 = 0,
+ transmit_pma1.preemp_tap_2 = 0,
+ transmit_pma1.preemp_tap_2_inv = "false",
+ transmit_pma1.protocol_hint = "pcie",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "off",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = 4,
+ transmit_pma1.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma2_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[2])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "1.5V",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h00,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.preemp_pretap = 0,
+ transmit_pma2.preemp_pretap_inv = "false",
+ transmit_pma2.preemp_tap_1 = 0,
+ transmit_pma2.preemp_tap_2 = 0,
+ transmit_pma2.preemp_tap_2_inv = "false",
+ transmit_pma2.protocol_hint = "pcie",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "off",
+ transmit_pma2.termination = "OCT 100 Ohms",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = 4,
+ transmit_pma2.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma3_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[3])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "1.5V",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h00,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.preemp_pretap = 0,
+ transmit_pma3.preemp_pretap_inv = "false",
+ transmit_pma3.preemp_tap_1 = 0,
+ transmit_pma3.preemp_tap_2 = 0,
+ transmit_pma3.preemp_tap_2_inv = "false",
+ transmit_pma3.protocol_hint = "pcie",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "off",
+ transmit_pma3.termination = "OCT 100 Ohms",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = 4,
+ transmit_pma3.lpm_type = "arriaii_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b1,
+ cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ clk_div_clk0in = {pll0_out[3:0]},
+ clk_div_pclkin = {1'b0},
+ cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
+ cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
+ cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div0_coreclkout},
+ fixedclk = 1'b0,
+ fixedclk_in = {{2{1'b0}}, {4{fixedclk}}},
+ int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
+ int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
+ int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
+ int_rxcoreclk = {int_rx_coreclkout[0]},
+ int_rxphfifordenable = {int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
+ int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
+ int_txcoreclk = {int_tx_coreclkout[0]},
+ int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[3:0]},
+ pipedatavalid_out = {wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[3:0]},
+ pipeelecidle_out = {wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll0_clkin = {9'b000000000, pll_inclk_wire[0]},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_clk = 1'b0,
+ refclk_pma = {wire_central_clk_div0_refclkout},
+ rx_analogreset_in = {4{rx_analogreset[0]}},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_bitslip = {4{1'b0}},
+ rx_coreclk_in = {4{coreclkout_wire[0]}},
+ rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[3], 8'b00000000, rx_pldcruclk_in[2], 8'b00000000, rx_pldcruclk_in[1], 8'b00000000, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs3_ctrldetect[0], wire_receive_pcs2_ctrldetect[0], wire_receive_pcs1_ctrldetect[0], wire_receive_pcs0_ctrldetect[0]},
+ rx_dataout = {rx_out_wire[31:0]},
+ rx_deserclock_in = {rx_pll_clkout[15:0]},
+ rx_digitalreset_in = {4{rx_digitalreset[0]}},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
+ rx_elecidleinfersel = {12{1'b0}},
+ rx_enapatternalign = {4{1'b0}},
+ rx_freqlocked = {rx_freqlocked_wire[3:0]},
+ rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = {4{1'b0}},
+ rx_locktodata_wire = {rx_locktodata[3:0]},
+ rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs3_dataout[7:0], wire_receive_pcs2_dataout[7:0], wire_receive_pcs1_dataout[7:0], wire_receive_pcs0_dataout[7:0]},
+ rx_patterndetect = {wire_receive_pcs3_patterndetect[0], wire_receive_pcs2_patterndetect[0], wire_receive_pcs1_patterndetect[0], wire_receive_pcs0_patterndetect[0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {4{400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}},
+ rx_phfifordenable = {4{1'b1}},
+ rx_phfiforeset = {4{1'b0}},
+ rx_phfifowrdisable = {4{1'b0}},
+ rx_pipestatetransdoneout = {wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[3:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {rx_plllocked_wire[3:0]},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {6{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}},
+ rx_powerdown = {4{1'b0}},
+ rx_powerdown_in = {rx_powerdown[3:0]},
+ rx_prbscidenable = {4{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {4{1'b0}},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs3_syncstatus[0], wire_receive_pcs2_syncstatus[0], wire_receive_pcs1_syncstatus[0], wire_receive_pcs0_syncstatus[0]},
+ rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout_int_wire = {wire_transmit_pcs3_clkout, wire_transmit_pcs2_clkout, wire_transmit_pcs1_clkout, wire_transmit_pcs0_clkout},
+ tx_coreclk_in = {4{coreclkout_wire[0]}},
+ tx_datain_wire = {tx_datain[31:0]},
+ tx_datainfull = {176{1'b0}},
+ tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {4{tx_digitalreset[0]}},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
+ tx_dprioin_wire = {600'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, {4{150'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}},
+ tx_forcedisp_wire = {tx_forcedispcompliance[3:0]},
+ tx_invpolarity = {4{1'b0}},
+ tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_phfiforeset = {4{1'b0}},
+ tx_pipedeemph = {4{1'b0}},
+ tx_pipemargin = {12{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = {4{1'b0}},
+ tx_pmadprioin_wire = {6{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}},
+ tx_revparallellpbken = {4{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx};
+endmodule //altpcie_serdes_2agx_x4d_gen1_08p_alt4gxb_jc59
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_2agx_x4d_gen1_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout)/* synthesis synthesis_clearbox = 1 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [7:0] powerdn;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ input [3:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [3:0] tx_ctrlenable;
+ input [31:0] tx_datain;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+ output [0:0] coreclkout;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ output [0:0] pll_locked;
+ output [3:0] rx_ctrldetect;
+ output [31:0] rx_dataout;
+ output [3:0] rx_freqlocked;
+ output [3:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [3:0] rx_syncstatus;
+ output [3:0] tx_dataout;
+
+ wire [3:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [3:0] sub_wire2;
+ wire [3:0] sub_wire3;
+ wire [3:0] sub_wire4;
+ wire [3:0] sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [3:0] sub_wire7;
+ wire [3:0] sub_wire8;
+ wire [11:0] sub_wire9;
+ wire [3:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [31:0] sub_wire12;
+ wire [3:0] rx_patterndetect = sub_wire0[3:0];
+ wire [0:0] coreclkout = sub_wire1[0:0];
+ wire [3:0] rx_ctrldetect = sub_wire2[3:0];
+ wire [3:0] pipedatavalid = sub_wire3[3:0];
+ wire [3:0] pipephydonestatus = sub_wire4[3:0];
+ wire [3:0] rx_pll_locked = sub_wire5[3:0];
+ wire [3:0] rx_freqlocked = sub_wire6[3:0];
+ wire [3:0] tx_dataout = sub_wire7[3:0];
+ wire [3:0] pipeelecidle = sub_wire8[3:0];
+ wire [11:0] pipestatus = sub_wire9[11:0];
+ wire [3:0] rx_syncstatus = sub_wire10[3:0];
+ wire [0:0] pll_locked = sub_wire11[0:0];
+ wire [31:0] rx_dataout = sub_wire12[31:0];
+
+ altpcie_serdes_2agx_x4d_gen1_08p_alt4gxb_jc59 altpcie_serdes_2agx_x4d_gen1_08p_alt4gxb_jc59_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .rx_datain (rx_datain),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .coreclkout (sub_wire1),
+ .rx_ctrldetect (sub_wire2),
+ .pipedatavalid (sub_wire3),
+ .pipephydonestatus (sub_wire4),
+ .rx_pll_locked (sub_wire5),
+ .rx_freqlocked (sub_wire6),
+ .tx_dataout (sub_wire7),
+ .pipeelecidle (sub_wire8),
+ .pipestatus (sub_wire9),
+ .rx_syncstatus (sub_wire10),
+ .pll_locked (sub_wire11),
+ .rx_dataout (sub_wire12));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.82"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x4"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.65"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.5"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE NUMERIC "4"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_analog_power STRING "2.5v"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_divide_by NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_multiply_by NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_divide_by NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_multiply_by NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 4 0 OUTPUT NODEFVAL "rx_ctrldetect[3..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 32 0 OUTPUT NODEFVAL "rx_dataout[31..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 4 0 OUTPUT NODEFVAL "rx_patterndetect[3..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 4 0 OUTPUT NODEFVAL "rx_syncstatus[3..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 4 0 INPUT NODEFVAL "tx_ctrlenable[3..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 32 0 INPUT NODEFVAL "tx_datain[31..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 4 0 @rx_ctrldetect 0 0 4 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 32 0 @rx_dataout 0 0 32 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 4 0 @rx_syncstatus 0 0 4 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 4 0 tx_ctrlenable 0 0 4 0
+// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
+// Retrieval info: CONNECT: @tx_datain 0 0 32 0 tx_datain 0 0 32 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_08p.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_08p.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_08p.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_08p.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_08p.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_08p_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_08p_bb.v TRUE FALSE
+// Retrieval info: LIB_FILE: arriaii_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v
new file mode 100644
index 0000000000000000000000000000000000000000..fb6e36cc40887cd4671ffac6be0945431a045a45
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v
@@ -0,0 +1,3600 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_2agx_x4d_gen1_16p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.0 Internal Build 85 12/04/2008 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="true" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=1 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gxb_analog_power="2.5v" gxb_powerdown_width=1 input_clock_frequency="100 MHz" intended_device_speed_grade="4" intended_device_variant="ANY" loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_control_width=1 preemphasis_ctrl_1stposttap_setting=9 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=800 rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_n_divider=2 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.5v" tx_channel_bonding="x4" tx_channel_width=16 tx_clkout_width=4 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=800 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_n_divider=2 tx_pll_vco_data_rate=800 tx_pll_vco_post_scale_divider=2 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=2 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 9.0 cbx_alt4gxb 2008:12:03:02:19:40:SJ cbx_mgl 2008:11:20:17:03:51:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = arriaii_hssi_calibration_block 1 arriaii_hssi_clock_divider 1 arriaii_hssi_cmu 1 arriaii_hssi_pll 5 arriaii_hssi_rx_pcs 4 arriaii_hssi_rx_pma 4 arriaii_hssi_tx_pcs 4 arriaii_hssi_tx_pma 4
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_2agx_x4d_gen1_16p_alt4gxb_hu3a
+ (
+ cal_blk_clk,
+ coreclkout,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) ;
+ input cal_blk_clk;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [7:0] powerdn;
+ input reconfig_clk;
+ output [16:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ output [7:0] rx_ctrldetect;
+ input [3:0] rx_datain;
+ output [63:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [3:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ output [3:0] tx_dataout;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [3:0] pipe8b10binvpolarity;
+ tri0 pll_inclk;
+ tri0 [7:0] powerdn;
+ tri0 reconfig_clk;
+ tri0 [3:0] reconfig_togxb;
+ tri0 [0:0] rx_analogreset;
+ tri0 [3:0] rx_cruclk;
+ tri0 [3:0] rx_datain;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [7:0] tx_ctrlenable;
+ tri0 [63:0] tx_datain;
+ tri0 [3:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [3:0] tx_forcedispcompliance;
+ tri0 [3:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_central_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div0_analogrefclkout;
+ wire wire_central_clk_div0_analogrefclkpulse;
+ wire wire_central_clk_div0_coreclkout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_refclkout;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire wire_cent_unit0_dprioout;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire wire_receive_pcs0_rateswitchout;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire wire_receive_pcs0_signaldetect;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire wire_receive_pcs1_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire wire_receive_pcs1_rateswitchout;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire wire_receive_pcs1_signaldetect;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_pipedatavalid;
+ wire wire_receive_pcs2_pipeelecidle;
+ wire wire_receive_pcs2_pipephydonestatus;
+ wire wire_receive_pcs2_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs2_pipestatus;
+ wire wire_receive_pcs2_rateswitchout;
+ wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
+ wire wire_receive_pcs2_signaldetect;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_pipedatavalid;
+ wire wire_receive_pcs3_pipeelecidle;
+ wire wire_receive_pcs3_pipephydonestatus;
+ wire wire_receive_pcs3_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs3_pipestatus;
+ wire wire_receive_pcs3_rateswitchout;
+ wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
+ wire wire_receive_pcs3_signaldetect;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire [7:0] wire_receive_pma1_analogtestbus;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire [7:0] wire_receive_pma2_analogtestbus;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire [7:0] wire_receive_pma3_analogtestbus;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_clkout;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire wire_transmit_pcs1_forceelecidleout;
+ wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs2_clkout;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire wire_transmit_pcs2_forceelecidleout;
+ wire [2:0] wire_transmit_pcs2_grayelecidleinferselout;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs2_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs2_pipepowerstateout;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs3_clkout;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire wire_transmit_pcs3_forceelecidleout;
+ wire [2:0] wire_transmit_pcs3_grayelecidleinferselout;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs3_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs3_pipepowerstateout;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire wire_transmit_pma2_rxdetectvalidout;
+ wire wire_transmit_pma2_rxfoundout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire wire_transmit_pma3_rxdetectvalidout;
+ wire wire_transmit_pma3_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [3:0] cent_unit_clkdivpowerdn;
+ wire [7:0] cent_unit_pllpowerdn;
+ wire [7:0] cent_unit_pllresetout;
+ wire [3:0] cent_unit_quadresetout;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [5:0] cent_unit_txdetectrxpowerdn;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [3:0] clk_div_clk0in;
+ wire [1:0] cmu_analogfastrefclkout;
+ wire [1:0] cmu_analogrefclkout;
+ wire [0:0] cmu_analogrefclkpulse;
+ wire [0:0] coreclkout_wire;
+ wire [5:0] fixedclk_to_cmu;
+ wire [11:0] grayelecidleinfersel_from_tx;
+ wire [0:0] int_hiprateswtichdone;
+ wire [3:0] int_rx_coreclkout;
+ wire [3:0] int_rx_phfifobyteserdisable;
+ wire [3:0] int_rx_phfifoptrsresetout;
+ wire [3:0] int_rx_phfifordenableout;
+ wire [3:0] int_rx_phfiforesetout;
+ wire [3:0] int_rx_phfifowrdisableout;
+ wire [11:0] int_rx_phfifoxnbytesel;
+ wire [11:0] int_rx_phfifoxnrdenable;
+ wire [11:0] int_rx_phfifoxnwrclk;
+ wire [11:0] int_rx_phfifoxnwrenable;
+ wire [0:0] int_rxcoreclk;
+ wire [0:0] int_rxphfifordenable;
+ wire [0:0] int_rxphfiforeset;
+ wire [0:0] int_rxphfifox4byteselout;
+ wire [0:0] int_rxphfifox4rdenableout;
+ wire [0:0] int_rxphfifox4wrclkout;
+ wire [0:0] int_rxphfifox4wrenableout;
+ wire [3:0] int_tx_coreclkout;
+ wire [3:0] int_tx_phfiforddisableout;
+ wire [3:0] int_tx_phfiforesetout;
+ wire [3:0] int_tx_phfifowrenableout;
+ wire [11:0] int_tx_phfifoxnbytesel;
+ wire [11:0] int_tx_phfifoxnrdclk;
+ wire [11:0] int_tx_phfifoxnrdenable;
+ wire [11:0] int_tx_phfifoxnwrenable;
+ wire [0:0] int_txcoreclk;
+ wire [0:0] int_txphfiforddisable;
+ wire [0:0] int_txphfiforeset;
+ wire [0:0] int_txphfifowrenable;
+ wire [0:0] int_txphfifox4byteselout;
+ wire [0:0] int_txphfifox4rdclkout;
+ wire [0:0] int_txphfifox4rdenableout;
+ wire [0:0] int_txphfifox4wrenableout;
+ wire [3:0] nonusertocmu_out;
+ wire [3:0] pipedatavalid_out;
+ wire [3:0] pipeelecidle_out;
+ wire [39:0] pll0_clkin;
+ wire [15:0] pll0_out;
+ wire [7:0] pll_ch_dataout_wire;
+ wire [0:0] pll_inclk_wire;
+ wire [3:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [7:0] pllpowerdn_in;
+ wire [7:0] pllreset_in;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] refclk_pma;
+ wire [5:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [3:0] rx_coreclk_in;
+ wire [35:0] rx_cruclk_in;
+ wire [15:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [11:0] rx_elecidleinfersel;
+ wire [3:0] rx_enapatternalign;
+ wire [3:0] rx_freqlocked_wire;
+ wire [3:0] rx_locktodata;
+ wire [3:0] rx_locktodata_wire;
+ wire [3:0] rx_locktorefclk_wire;
+ wire [63:0] rx_out_wire;
+ wire [7:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [3:0] rx_phfifordenable;
+ wire [3:0] rx_phfiforeset;
+ wire [3:0] rx_phfifowrdisable;
+ wire [3:0] rx_pipestatetransdoneout;
+ wire [3:0] rx_pldcruclk_in;
+ wire [15:0] rx_pll_clkout;
+ wire [3:0] rx_pll_pfdrefclkout_wire;
+ wire [3:0] rx_plllocked_wire;
+ wire [67:0] rx_pma_analogtestbus;
+ wire [3:0] rx_pma_clockout;
+ wire [3:0] rx_pma_dataout;
+ wire [3:0] rx_pma_locktorefout;
+ wire [79:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [3:0] rx_powerdown;
+ wire [5:0] rx_powerdown_in;
+ wire [3:0] rx_prbscidenable;
+ wire [79:0] rx_revparallelfdbkdata;
+ wire [3:0] rx_rmfiforeset;
+ wire [5:0] rx_rxcruresetout;
+ wire [3:0] rx_signaldetect_wire;
+ wire [0:0] rxphfifowrdisable;
+ wire [5:0] tx_analogreset_out;
+ wire [3:0] tx_clkout_int_wire;
+ wire [3:0] tx_coreclk_in;
+ wire [63:0] tx_datain_wire;
+ wire [175:0] tx_datainfull;
+ wire [79:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [7:0] tx_forcedisp_wire;
+ wire [3:0] tx_invpolarity;
+ wire [3:0] tx_localrefclk;
+ wire [3:0] tx_pcs_forceelecidleout;
+ wire [3:0] tx_phfiforeset;
+ wire [3:0] tx_pipedeemph;
+ wire [11:0] tx_pipemargin;
+ wire [7:0] tx_pipepowerdownout;
+ wire [15:0] tx_pipepowerstateout;
+ wire [3:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [3:0] tx_revparallellpbken;
+ wire [3:0] tx_rxdetectvalidout;
+ wire [3:0] tx_rxfoundout;
+ wire [3:0] txdetectrxout;
+
+ arriaii_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ arriaii_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[3:0]),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .dprioin({100{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.data_rate = 800,
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.dprio_config_mode = 6'h00,
+ central_clk_div0.effective_data_rate = "2500 Mbps",
+ central_clk_div0.enable_dynamic_divider = "false",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_rate_switch_base_clock = "true",
+ central_clk_div0.select_local_refclk = "true",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "true",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "arriaii_hssi_clock_divider";
+ arriaii_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin({600{1'b0}}),
+ .cmudividerdprioout(),
+ .cmuplldprioin({1800{1'b0}}),
+ .cmuplldprioout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(1'b1),
+ .dpriodisableout(),
+ .dprioin(1'b0),
+ .dprioload(1'b0),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({1600{1'b0}}),
+ .rxpcsdprioout(),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({1800{1'b0}}),
+ .rxpmadprioout(),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({600{1'b0}}),
+ .txpcsdprioout(),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({1800{1'b0}}),
+ .txpmadprioout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .rateswitch(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.dprio_config_mode = 6'h00,
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 250000,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "x4",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "x4",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "2.5V",
+ cent_unit0.lpm_type = "arriaii_hssi_cmu";
+ arriaii_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.bandwidth_type = "Medium",
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.input_clock_frequency = "100 MHz",
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 2,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.protocol_hint = "pcie",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_data_rate = 800,
+ rx_cdr_pll0.vco_post_scale = 2,
+ rx_cdr_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[17:9]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.bandwidth_type = "Medium",
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.dprio_config_mode = 6'h00,
+ rx_cdr_pll1.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll1.inclk0_input_period = 10000,
+ rx_cdr_pll1.input_clock_frequency = "100 MHz",
+ rx_cdr_pll1.m = 25,
+ rx_cdr_pll1.n = 2,
+ rx_cdr_pll1.pfd_clk_select = 0,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.protocol_hint = "pcie",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_data_rate = 800,
+ rx_cdr_pll1.vco_post_scale = 2,
+ rx_cdr_pll1.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[26:18]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.bandwidth_type = "Medium",
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.dprio_config_mode = 6'h00,
+ rx_cdr_pll2.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll2.inclk0_input_period = 10000,
+ rx_cdr_pll2.input_clock_frequency = "100 MHz",
+ rx_cdr_pll2.m = 25,
+ rx_cdr_pll2.n = 2,
+ rx_cdr_pll2.pfd_clk_select = 0,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.protocol_hint = "pcie",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_data_rate = 800,
+ rx_cdr_pll2.vco_post_scale = 2,
+ rx_cdr_pll2.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[35:27]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.bandwidth_type = "Medium",
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.dprio_config_mode = 6'h00,
+ rx_cdr_pll3.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll3.inclk0_input_period = 10000,
+ rx_cdr_pll3.input_clock_frequency = "100 MHz",
+ rx_cdr_pll3.m = 25,
+ rx_cdr_pll3.n = 2,
+ rx_cdr_pll3.pfd_clk_select = 0,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.protocol_hint = "pcie",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_data_rate = 800,
+ rx_cdr_pll3.vco_post_scale = 2,
+ rx_cdr_pll3.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.bandwidth_type = "High",
+ tx_pll0.channel_num = 4,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.input_clock_frequency = "100 MHz",
+ tx_pll0.m = 25,
+ tx_pll0.n = 2,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pfd_fb_select = "internal",
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.protocol_hint = "pcie",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_data_rate = 800,
+ tx_pll0.vco_post_scale = 2,
+ tx_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(wire_receive_pcs0_signaldetect),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x4",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h00,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 250000,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 6,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 0,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 0,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetect(wire_receive_pcs1_signaldetect),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.auto_spd_self_switch_enable = "false",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_mask_cycle = 800,
+ receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x4",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 16,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h00,
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "false",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 250000,
+ receive_pcs1.protocol_hint = "pcie",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 6,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 0,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 0,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rxstatus_error_report_mode = 0,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "true",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[8:6]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs2_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs2_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[5:4]),
+ .pipepowerstate(tx_pipepowerstateout[11:8]),
+ .pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs2_pipestatus),
+ .powerdn(powerdn[5:4]),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[2]),
+ .rxfound(rx_pcs_rxfound_wire[5:4]),
+ .signaldetect(wire_receive_pcs2_signaldetect),
+ .signaldetected(rx_signaldetect_wire[2]),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "false",
+ receive_pcs2.allow_pipe_polarity_inversion = "true",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 14,
+ receive_pcs2.auto_spd_self_switch_enable = "false",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_enable = "true",
+ receive_pcs2.cdrctrl_mask_cycle = 800,
+ receive_pcs2.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs2.cdrctrl_rxvalid_mask = "true",
+ receive_pcs2.channel_bonding = "x4",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 16,
+ receive_pcs2.clk1_mux_select = "recovered clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "false",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "pipe",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs2.deskew_pattern = "0",
+ receive_pcs2.disable_auto_idle_insertion = "false",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h00,
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 16,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 17,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "false",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 250000,
+ receive_pcs2.protocol_hint = "pcie",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "false",
+ receive_pcs2.rate_match_delete_threshold = 6,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 0,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs2.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs2.rate_match_pattern_size = 20,
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "true",
+ receive_pcs2.rate_match_start_threshold = 0,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rxstatus_error_report_mode = 0,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "false",
+ receive_pcs2.use_double_data_mode = "true",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[11:9]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs3_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs3_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[7:6]),
+ .pipepowerstate(tx_pipepowerstateout[15:12]),
+ .pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs3_pipestatus),
+ .powerdn(powerdn[7:6]),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[3]),
+ .rxfound(rx_pcs_rxfound_wire[7:6]),
+ .signaldetect(wire_receive_pcs3_signaldetect),
+ .signaldetected(rx_signaldetect_wire[3]),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "false",
+ receive_pcs3.allow_pipe_polarity_inversion = "true",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 14,
+ receive_pcs3.auto_spd_self_switch_enable = "false",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_enable = "true",
+ receive_pcs3.cdrctrl_mask_cycle = 800,
+ receive_pcs3.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs3.cdrctrl_rxvalid_mask = "true",
+ receive_pcs3.channel_bonding = "x4",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 16,
+ receive_pcs3.clk1_mux_select = "recovered clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "false",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "pipe",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs3.deskew_pattern = "0",
+ receive_pcs3.disable_auto_idle_insertion = "false",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h00,
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 16,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 17,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "false",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 250000,
+ receive_pcs3.protocol_hint = "pcie",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "false",
+ receive_pcs3.rate_match_delete_threshold = 6,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 0,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs3.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs3.rate_match_pattern_size = 20,
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "true",
+ receive_pcs3.rate_match_start_threshold = 0,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rxstatus_error_report_mode = 0,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "false",
+ receive_pcs3.use_double_data_mode = "true",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h00,
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "false",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 1,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 4,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma1_analogtestbus),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h00,
+ receive_pma1.enable_ltd = "false",
+ receive_pma1.enable_ltr = "false",
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eqa_ctrl = 0,
+ receive_pma1.eqb_ctrl = 0,
+ receive_pma1.eqc_ctrl = 0,
+ receive_pma1.eqd_ctrl = 0,
+ receive_pma1.eqv_ctrl = 1,
+ receive_pma1.force_signal_detect = "true",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 1,
+ receive_pma1.ppmselect = 32,
+ receive_pma1.protocol_hint = "pcie",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma1.signal_detect_loss_threshold = 4,
+ receive_pma1.termination = "OCT 100 Ohms",
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma2_analogtestbus),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma2_signaldetect)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.allow_serial_loopback = "false",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = "0.82V",
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h00,
+ receive_pma2.enable_ltd = "false",
+ receive_pma2.enable_ltr = "false",
+ receive_pma2.eq_dc_gain = 3,
+ receive_pma2.eqa_ctrl = 0,
+ receive_pma2.eqb_ctrl = 0,
+ receive_pma2.eqc_ctrl = 0,
+ receive_pma2.eqd_ctrl = 0,
+ receive_pma2.eqv_ctrl = 1,
+ receive_pma2.force_signal_detect = "true",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 1,
+ receive_pma2.ppmselect = 32,
+ receive_pma2.protocol_hint = "pcie",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma2.signal_detect_loss_threshold = 4,
+ receive_pma2.termination = "OCT 100 Ohms",
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma3_analogtestbus),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma3_signaldetect)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.allow_serial_loopback = "false",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = "0.82V",
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h00,
+ receive_pma3.enable_ltd = "false",
+ receive_pma3.enable_ltr = "false",
+ receive_pma3.eq_dc_gain = 3,
+ receive_pma3.eqa_ctrl = 0,
+ receive_pma3.eqb_ctrl = 0,
+ receive_pma3.eqc_ctrl = 0,
+ receive_pma3.eqd_ctrl = 0,
+ receive_pma3.eqv_ctrl = 1,
+ receive_pma3.force_signal_detect = "true",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 1,
+ receive_pma3.ppmselect = 32,
+ receive_pma3.protocol_hint = "pcie",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma3.signal_detect_loss_threshold = 4,
+ receive_pma3.termination = "OCT 100 Ohms",
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
+ .datain({{24{1'b0}}, tx_datain_wire[15:0]}),
+ .datainfull({tx_datainfull[43:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.channel_bonding = "x4",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h00,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(wire_transmit_pcs1_clkout),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
+ .datain({{24{1'b0}}, tx_datain_wire[31:16]}),
+ .datainfull({tx_datainfull[87:44]}),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[1]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .forceelecidleout(wire_transmit_pcs1_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[1]),
+ .pipetxdeemph(tx_pipedeemph[1]),
+ .pipetxmargin(tx_pipemargin[5:3]),
+ .pipetxswing(tx_pipeswing[1]),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.auto_spd_self_switch_enable = "false",
+ transmit_pcs1.channel_bonding = "x4",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 16,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h00,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "true",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(wire_transmit_pcs2_clkout),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[5:4]}),
+ .datain({{24{1'b0}}, tx_datain_wire[47:32]}),
+ .datainfull({tx_datainfull[131:88]}),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(tx_detectrxloop[2]),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[2]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[8:6]),
+ .enrevparallellpbk(tx_revparallellpbken[2]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[5:4]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .forceelecidleout(wire_transmit_pcs2_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[2]),
+ .pipetxdeemph(tx_pipedeemph[2]),
+ .pipetxmargin(tx_pipemargin[8:6]),
+ .pipetxswing(tx_pipeswing[2]),
+ .powerdn(powerdn[5:4]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[59:40]),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "false",
+ transmit_pcs2.auto_spd_self_switch_enable = "false",
+ transmit_pcs2.channel_bonding = "x4",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 16,
+ transmit_pcs2.core_clock_0ppm = "false",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "pipe",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "new",
+ transmit_pcs2.dprio_config_mode = 6'h00,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "true",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "pcie",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "true",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(wire_transmit_pcs3_clkout),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[7:6]}),
+ .datain({{24{1'b0}}, tx_datain_wire[63:48]}),
+ .datainfull({tx_datainfull[175:132]}),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(tx_detectrxloop[3]),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[3]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[11:9]),
+ .enrevparallellpbk(tx_revparallellpbken[3]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[7:6]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .forceelecidleout(wire_transmit_pcs3_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[3]),
+ .pipetxdeemph(tx_pipedeemph[3]),
+ .pipetxmargin(tx_pipemargin[11:9]),
+ .pipetxswing(tx_pipeswing[3]),
+ .powerdn(powerdn[7:6]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[79:60]),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "false",
+ transmit_pcs3.auto_spd_self_switch_enable = "false",
+ transmit_pcs3.channel_bonding = "x4",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 16,
+ transmit_pcs3.core_clock_0ppm = "false",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "pipe",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "new",
+ transmit_pcs3.dprio_config_mode = 6'h00,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "true",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "pcie",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "true",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .pclk({5{1'b0}}),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "1.5V",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h00,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.physical_clkin1_mapping = "x4",
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 9,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 2,
+ transmit_pma0.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .pclk({5{1'b0}}),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "1.5V",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h00,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.physical_clkin1_mapping = "x4",
+ transmit_pma1.preemp_pretap = 0,
+ transmit_pma1.preemp_pretap_inv = "false",
+ transmit_pma1.preemp_tap_1 = 9,
+ transmit_pma1.preemp_tap_2 = 0,
+ transmit_pma1.preemp_tap_2_inv = "false",
+ transmit_pma1.protocol_hint = "pcie",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "off",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = 2,
+ transmit_pma1.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[2]),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma2_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[2])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .pclk({5{1'b0}}),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "1.5V",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h00,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.physical_clkin1_mapping = "x4",
+ transmit_pma2.preemp_pretap = 0,
+ transmit_pma2.preemp_pretap_inv = "false",
+ transmit_pma2.preemp_tap_1 = 9,
+ transmit_pma2.preemp_tap_2 = 0,
+ transmit_pma2.preemp_tap_2_inv = "false",
+ transmit_pma2.protocol_hint = "pcie",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "off",
+ transmit_pma2.termination = "OCT 100 Ohms",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = 2,
+ transmit_pma2.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[3]),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma3_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[3])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .pclk({5{1'b0}}),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "1.5V",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h00,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.physical_clkin1_mapping = "x4",
+ transmit_pma3.preemp_pretap = 0,
+ transmit_pma3.preemp_pretap_inv = "false",
+ transmit_pma3.preemp_tap_1 = 9,
+ transmit_pma3.preemp_tap_2 = 0,
+ transmit_pma3.preemp_tap_2_inv = "false",
+ transmit_pma3.protocol_hint = "pcie",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "off",
+ transmit_pma3.termination = "OCT 100 Ohms",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = 2,
+ transmit_pma3.lpm_type = "arriaii_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b1,
+ cent_unit_clkdivpowerdn = {3'b000, wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_pllpowerdn = {6'b000000, wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {6'b000000, wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {3'b000, wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ clk_div_clk0in = {pll0_out[3:0]},
+ cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
+ cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
+ cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div0_coreclkout},
+ fixedclk_to_cmu = {6{reconfig_clk}},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs3_grayelecidleinferselout, wire_transmit_pcs2_grayelecidleinferselout, wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
+ int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
+ int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
+ int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
+ int_rxcoreclk = {int_rx_coreclkout[0]},
+ int_rxphfifordenable = {int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
+ int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
+ int_txcoreclk = {int_tx_coreclkout[0]},
+ int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {3'b000, wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[3:0]},
+ pipedatavalid_out = {wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[3:0]},
+ pipeelecidle_out = {wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll0_clkin = {30'b000000000000000000000000000000, 9'b000000000, pll_inclk_wire[0]},
+ pll0_out = {12'b000000000000, wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {3'b000, wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {6'b000000, 1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {6'b000000, 1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ refclk_pma = {wire_central_clk_div0_refclkout},
+ rx_analogreset_in = {2'b00, {4{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_coreclk_in = {4{coreclkout_wire[0]}},
+ rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[3], 8'b00000000, rx_pldcruclk_in[2], 8'b00000000, rx_pldcruclk_in[1], 8'b00000000, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[63:0]},
+ rx_deserclock_in = {rx_pll_clkout[15:0]},
+ rx_digitalreset_in = {4{rx_digitalreset[0]}},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
+ rx_elecidleinfersel = {12{1'b0}},
+ rx_enapatternalign = {4{1'b0}},
+ rx_freqlocked = {rx_freqlocked_wire[3:0]},
+ rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = {4{1'b0}},
+ rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
+ rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {4{400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}},
+ rx_phfifordenable = {4{1'b1}},
+ rx_phfiforeset = {4{1'b0}},
+ rx_phfifowrdisable = {4{1'b0}},
+ rx_pipestatetransdoneout = {wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[3:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {rx_plllocked_wire[3:0]},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_analogtestbus = {51'b000000000000000000000000000000000000000000000000000, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
+ rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {6{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}},
+ rx_powerdown = {4{1'b0}},
+ rx_powerdown_in = {2'b00, rx_powerdown[3:0]},
+ rx_prbscidenable = {4{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {4{1'b0}},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
+ rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout_int_wire = {wire_transmit_pcs3_clkout, wire_transmit_pcs2_clkout, wire_transmit_pcs1_clkout, wire_transmit_pcs0_clkout},
+ tx_coreclk_in = {4{coreclkout_wire[0]}},
+ tx_datain_wire = {tx_datain[63:0]},
+ tx_datainfull = {176{1'b0}},
+ tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {4{tx_digitalreset[0]}},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
+ tx_dprioin_wire = {600'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, {4{150'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[3], 1'b0, tx_forcedispcompliance[2], 1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = {4{1'b0}},
+ tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = {4{1'b0}},
+ tx_pipedeemph = {4{1'b0}},
+ tx_pipemargin = {12{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = {4{1'b0}},
+ tx_pmadprioin_wire = {6{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}},
+ tx_revparallellpbken = {4{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx};
+endmodule //altpcie_serdes_2agx_x4d_gen1_16p_alt4gxb_hu3a
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_2agx_x4d_gen1_16p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [7:0] powerdn;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ input [3:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+ output [0:0] coreclkout;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ output [0:0] pll_locked;
+ output [16:0] reconfig_fromgxb;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [3:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ output [3:0] tx_dataout;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [3:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+
+
+ wire [7:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [7:0] sub_wire2;
+ wire [3:0] sub_wire3;
+ wire [3:0] sub_wire4;
+ wire [3:0] sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [3:0] sub_wire7;
+ wire [3:0] sub_wire8;
+ wire [11:0] sub_wire9;
+ wire [7:0] sub_wire10;
+ wire [16:0] sub_wire11;
+ wire [0:0] sub_wire12;
+ wire [63:0] sub_wire13;
+ wire [7:0] rx_patterndetect = sub_wire0[7:0];
+ wire [0:0] coreclkout = sub_wire1[0:0];
+ wire [7:0] rx_ctrldetect = sub_wire2[7:0];
+ wire [3:0] pipedatavalid = sub_wire3[3:0];
+ wire [3:0] pipephydonestatus = sub_wire4[3:0];
+ wire [3:0] rx_pll_locked = sub_wire5[3:0];
+ wire [3:0] rx_freqlocked = sub_wire6[3:0];
+ wire [3:0] tx_dataout = sub_wire7[3:0];
+ wire [3:0] pipeelecidle = sub_wire8[3:0];
+ wire [11:0] pipestatus = sub_wire9[11:0];
+ wire [7:0] rx_syncstatus = sub_wire10[7:0];
+ wire [16:0] reconfig_fromgxb = sub_wire11[16:0];
+ wire [0:0] pll_locked = sub_wire12[0:0];
+ wire [63:0] rx_dataout = sub_wire13[63:0];
+
+ altpcie_serdes_2agx_x4d_gen1_16p_alt4gxb_hu3a altpcie_serdes_2agx_x4d_gen1_16p_alt4gxb_hu3a_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .reconfig_clk (reconfig_clk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .coreclkout (sub_wire1),
+ .rx_ctrldetect (sub_wire2),
+ .pipedatavalid (sub_wire3),
+ .pipephydonestatus (sub_wire4),
+ .rx_pll_locked (sub_wire5),
+ .rx_freqlocked (sub_wire6),
+ .tx_dataout (sub_wire7),
+ .pipeelecidle (sub_wire8),
+ .pipestatus (sub_wire9),
+ .rx_syncstatus (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .pll_locked (sub_wire12),
+ .rx_dataout (sub_wire13));
+ defparam
+ altpcie_serdes_2agx_x4d_gen1_16p_alt4gxb_hu3a_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x4"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "2.5v"
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "4"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "9"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "2"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "true"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_vco_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_slew_rate STRING "off"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_16p.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_16p.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_16p.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_16p.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_16p.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_16p_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x4d_gen1_16p_bb.v TRUE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..5a2fecf0441bfb3b66b2cd0a9c8b10264ad594a3
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v
@@ -0,0 +1,6489 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_2agx_x8d_gen1_08p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// arriaii_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Internal Build 106 07/20/2008 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Arria II" elec_idle_infer_enable="false" enable_0ppm="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=1 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gxb_analog_power="2.5v" gxb_powerdown_width=1 intended_device_speed_grade=4 loopback_mode="none" number_of_channels=8 number_of_quads=2 operation_mode="duplex" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_dprio_mode=0 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x8" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=0 rx_cru_divide_by=0 rx_cru_inclock0_period=10000 rx_cru_m_divider=1 rx_cru_multiply_by=0 rx_cru_n_divider=1 rx_cru_pfd_clk_select=0 rx_cru_vco_post_scale_divider=1 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.5v" tx_channel_bonding="x8" tx_channel_width=8 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=0 tx_pll_divide_by=0 tx_pll_inclk0_period=10000 tx_pll_m_divider=1 tx_pll_multiply_by=0 tx_pll_n_divider=1 tx_pll_pfd_clk_select=0 tx_pll_vco_post_scale_divider=1 tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 8.1 cbx_alt4gxb 2008:07:18:07:31:37:SJ cbx_mgl 2008:07:11:15:23:48:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = arriaii_hssi_calibration_block 2 arriaii_hssi_clock_divider 2 arriaii_hssi_cmu 2 arriaii_hssi_pll 9 arriaii_hssi_rx_pcs 8 arriaii_hssi_rx_pma 8 arriaii_hssi_tx_pcs 8 arriaii_hssi_tx_pma 8
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_2agx_x8d_gen1_08p_alt4gxb_0d59
+ (
+ cal_blk_clk,
+ coreclkout,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) /* synthesis synthesis_clearbox=1 */;
+ input cal_blk_clk;
+ output [1:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input [7:0] pipe8b10binvpolarity;
+ output [7:0] pipedatavalid;
+ output [7:0] pipeelecidle;
+ output [7:0] pipephydonestatus;
+ output [23:0] pipestatus;
+ input pll_inclk;
+ output [1:0] pll_locked;
+ input [15:0] powerdn;
+ input [0:0] rx_analogreset;
+ input [7:0] rx_cruclk;
+ output [7:0] rx_ctrldetect;
+ input [7:0] rx_datain;
+ output [63:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [7:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [7:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ output [7:0] tx_dataout;
+ input [7:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [7:0] tx_forcedispcompliance;
+ input [7:0] tx_forceelecidle;
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire wire_cal_blk0_nonusertocmu;
+ wire wire_cal_blk1_nonusertocmu;
+ wire [1:0] wire_central_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div0_analogrefclkout;
+ wire wire_central_clk_div0_analogrefclkpulse;
+ wire wire_central_clk_div0_coreclkout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_refclkout;
+ wire [1:0] wire_central_clk_div1_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div1_analogrefclkout;
+ wire wire_central_clk_div1_analogrefclkpulse;
+ wire wire_central_clk_div1_coreclkout;
+ wire wire_central_clk_div1_rateswitchdone;
+ wire wire_central_clk_div1_refclkout;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxadcepowerdown;
+ wire [3:0] wire_cent_unit0_rxadceresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1:0] wire_cent_unit1_clkdivpowerdn;
+ wire [1:0] wire_cent_unit1_pllpowerdn;
+ wire [1:0] wire_cent_unit1_pllresetout;
+ wire wire_cent_unit1_quadresetout;
+ wire [3:0] wire_cent_unit1_rxadcepowerdown;
+ wire [3:0] wire_cent_unit1_rxadceresetout;
+ wire [5:0] wire_cent_unit1_rxanalogresetout;
+ wire [5:0] wire_cent_unit1_rxcrupowerdown;
+ wire [5:0] wire_cent_unit1_rxcruresetout;
+ wire [3:0] wire_cent_unit1_rxdigitalresetout;
+ wire [5:0] wire_cent_unit1_rxibpowerdown;
+ wire wire_cent_unit1_rxphfifox4byteselout;
+ wire wire_cent_unit1_rxphfifox4rdenableout;
+ wire wire_cent_unit1_rxphfifox4wrclkout;
+ wire wire_cent_unit1_rxphfifox4wrenableout;
+ wire [5:0] wire_cent_unit1_txanalogresetout;
+ wire [3:0] wire_cent_unit1_txctrlout;
+ wire [31:0] wire_cent_unit1_txdataout;
+ wire [5:0] wire_cent_unit1_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit1_txdigitalresetout;
+ wire [5:0] wire_cent_unit1_txobpowerdown;
+ wire wire_cent_unit1_txphfifox4byteselout;
+ wire wire_cent_unit1_txphfifox4rdclkout;
+ wire wire_cent_unit1_txphfifox4rdenableout;
+ wire wire_cent_unit1_txphfifox4wrenableout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll4_clk;
+ wire [1:0] wire_rx_cdr_pll4_dataout;
+ wire wire_rx_cdr_pll4_freqlocked;
+ wire wire_rx_cdr_pll4_locked;
+ wire wire_rx_cdr_pll4_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll5_clk;
+ wire [1:0] wire_rx_cdr_pll5_dataout;
+ wire wire_rx_cdr_pll5_freqlocked;
+ wire wire_rx_cdr_pll5_locked;
+ wire wire_rx_cdr_pll5_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll6_clk;
+ wire [1:0] wire_rx_cdr_pll6_dataout;
+ wire wire_rx_cdr_pll6_freqlocked;
+ wire wire_rx_cdr_pll6_locked;
+ wire wire_rx_cdr_pll6_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll7_clk;
+ wire [1:0] wire_rx_cdr_pll7_dataout;
+ wire wire_rx_cdr_pll7_freqlocked;
+ wire wire_rx_cdr_pll7_locked;
+ wire wire_rx_cdr_pll7_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire wire_receive_pcs0_iqpphfifobyteselout;
+ wire wire_receive_pcs0_iqpphfifordenableout;
+ wire wire_receive_pcs0_iqpphfifowrclkout;
+ wire wire_receive_pcs0_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire wire_receive_pcs0_rateswitchout;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire wire_receive_pcs1_iqpphfifobyteselout;
+ wire wire_receive_pcs1_iqpphfifordenableout;
+ wire wire_receive_pcs1_iqpphfifowrclkout;
+ wire wire_receive_pcs1_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire wire_receive_pcs1_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire wire_receive_pcs1_rateswitchout;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire wire_receive_pcs2_iqpphfifobyteselout;
+ wire wire_receive_pcs2_iqpphfifordenableout;
+ wire wire_receive_pcs2_iqpphfifowrclkout;
+ wire wire_receive_pcs2_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_pipedatavalid;
+ wire wire_receive_pcs2_pipeelecidle;
+ wire wire_receive_pcs2_pipephydonestatus;
+ wire wire_receive_pcs2_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs2_pipestatus;
+ wire wire_receive_pcs2_rateswitchout;
+ wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire wire_receive_pcs3_iqpphfifobyteselout;
+ wire wire_receive_pcs3_iqpphfifordenableout;
+ wire wire_receive_pcs3_iqpphfifowrclkout;
+ wire wire_receive_pcs3_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_pipedatavalid;
+ wire wire_receive_pcs3_pipeelecidle;
+ wire wire_receive_pcs3_pipephydonestatus;
+ wire wire_receive_pcs3_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs3_pipestatus;
+ wire wire_receive_pcs3_rateswitchout;
+ wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire wire_receive_pcs4_cdrctrllocktorefclkout;
+ wire wire_receive_pcs4_coreclkout;
+ wire [3:0] wire_receive_pcs4_ctrldetect;
+ wire [39:0] wire_receive_pcs4_dataout;
+ wire wire_receive_pcs4_iqpphfifobyteselout;
+ wire wire_receive_pcs4_iqpphfifordenableout;
+ wire wire_receive_pcs4_iqpphfifowrclkout;
+ wire wire_receive_pcs4_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs4_patterndetect;
+ wire wire_receive_pcs4_phfifobyteserdisableout;
+ wire wire_receive_pcs4_phfifoptrsresetout;
+ wire wire_receive_pcs4_phfifordenableout;
+ wire wire_receive_pcs4_phfiforesetout;
+ wire wire_receive_pcs4_phfifowrdisableout;
+ wire wire_receive_pcs4_pipedatavalid;
+ wire wire_receive_pcs4_pipeelecidle;
+ wire wire_receive_pcs4_pipephydonestatus;
+ wire wire_receive_pcs4_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs4_pipestatus;
+ wire wire_receive_pcs4_rateswitchout;
+ wire [19:0] wire_receive_pcs4_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs4_syncstatus;
+ wire wire_receive_pcs5_cdrctrllocktorefclkout;
+ wire wire_receive_pcs5_coreclkout;
+ wire [3:0] wire_receive_pcs5_ctrldetect;
+ wire [39:0] wire_receive_pcs5_dataout;
+ wire wire_receive_pcs5_iqpphfifobyteselout;
+ wire wire_receive_pcs5_iqpphfifordenableout;
+ wire wire_receive_pcs5_iqpphfifowrclkout;
+ wire wire_receive_pcs5_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs5_patterndetect;
+ wire wire_receive_pcs5_phfifobyteserdisableout;
+ wire wire_receive_pcs5_phfifoptrsresetout;
+ wire wire_receive_pcs5_phfifordenableout;
+ wire wire_receive_pcs5_phfiforesetout;
+ wire wire_receive_pcs5_phfifowrdisableout;
+ wire wire_receive_pcs5_pipedatavalid;
+ wire wire_receive_pcs5_pipeelecidle;
+ wire wire_receive_pcs5_pipephydonestatus;
+ wire wire_receive_pcs5_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs5_pipestatus;
+ wire wire_receive_pcs5_rateswitchout;
+ wire [19:0] wire_receive_pcs5_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs5_syncstatus;
+ wire wire_receive_pcs6_cdrctrllocktorefclkout;
+ wire wire_receive_pcs6_coreclkout;
+ wire [3:0] wire_receive_pcs6_ctrldetect;
+ wire [39:0] wire_receive_pcs6_dataout;
+ wire wire_receive_pcs6_iqpphfifobyteselout;
+ wire wire_receive_pcs6_iqpphfifordenableout;
+ wire wire_receive_pcs6_iqpphfifowrclkout;
+ wire wire_receive_pcs6_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs6_patterndetect;
+ wire wire_receive_pcs6_phfifobyteserdisableout;
+ wire wire_receive_pcs6_phfifoptrsresetout;
+ wire wire_receive_pcs6_phfifordenableout;
+ wire wire_receive_pcs6_phfiforesetout;
+ wire wire_receive_pcs6_phfifowrdisableout;
+ wire wire_receive_pcs6_pipedatavalid;
+ wire wire_receive_pcs6_pipeelecidle;
+ wire wire_receive_pcs6_pipephydonestatus;
+ wire wire_receive_pcs6_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs6_pipestatus;
+ wire wire_receive_pcs6_rateswitchout;
+ wire [19:0] wire_receive_pcs6_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs6_syncstatus;
+ wire wire_receive_pcs7_cdrctrllocktorefclkout;
+ wire wire_receive_pcs7_coreclkout;
+ wire [3:0] wire_receive_pcs7_ctrldetect;
+ wire [39:0] wire_receive_pcs7_dataout;
+ wire wire_receive_pcs7_iqpphfifobyteselout;
+ wire wire_receive_pcs7_iqpphfifordenableout;
+ wire wire_receive_pcs7_iqpphfifowrclkout;
+ wire wire_receive_pcs7_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs7_patterndetect;
+ wire wire_receive_pcs7_phfifobyteserdisableout;
+ wire wire_receive_pcs7_phfifoptrsresetout;
+ wire wire_receive_pcs7_phfifordenableout;
+ wire wire_receive_pcs7_phfiforesetout;
+ wire wire_receive_pcs7_phfifowrdisableout;
+ wire wire_receive_pcs7_pipedatavalid;
+ wire wire_receive_pcs7_pipeelecidle;
+ wire wire_receive_pcs7_pipephydonestatus;
+ wire wire_receive_pcs7_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs7_pipestatus;
+ wire wire_receive_pcs7_rateswitchout;
+ wire [19:0] wire_receive_pcs7_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs7_syncstatus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire wire_receive_pma4_clockout;
+ wire wire_receive_pma4_dataout;
+ wire wire_receive_pma4_locktorefout;
+ wire [63:0] wire_receive_pma4_recoverdataout;
+ wire wire_receive_pma4_signaldetect;
+ wire wire_receive_pma5_clockout;
+ wire wire_receive_pma5_dataout;
+ wire wire_receive_pma5_locktorefout;
+ wire [63:0] wire_receive_pma5_recoverdataout;
+ wire wire_receive_pma5_signaldetect;
+ wire wire_receive_pma6_clockout;
+ wire wire_receive_pma6_dataout;
+ wire wire_receive_pma6_locktorefout;
+ wire [63:0] wire_receive_pma6_recoverdataout;
+ wire wire_receive_pma6_signaldetect;
+ wire wire_receive_pma7_clockout;
+ wire wire_receive_pma7_dataout;
+ wire wire_receive_pma7_locktorefout;
+ wire [63:0] wire_receive_pma7_recoverdataout;
+ wire wire_receive_pma7_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire wire_transmit_pcs0_iqpphfifobyteselout;
+ wire wire_transmit_pcs0_iqpphfifordclkout;
+ wire wire_transmit_pcs0_iqpphfifordenableout;
+ wire wire_transmit_pcs0_iqpphfifowrenableout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_clkout;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire wire_transmit_pcs1_iqpphfifobyteselout;
+ wire wire_transmit_pcs1_iqpphfifordclkout;
+ wire wire_transmit_pcs1_iqpphfifordenableout;
+ wire wire_transmit_pcs1_iqpphfifowrenableout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs2_clkout;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire wire_transmit_pcs2_iqpphfifobyteselout;
+ wire wire_transmit_pcs2_iqpphfifordclkout;
+ wire wire_transmit_pcs2_iqpphfifordenableout;
+ wire wire_transmit_pcs2_iqpphfifowrenableout;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs2_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs2_pipepowerstateout;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs3_clkout;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire wire_transmit_pcs3_iqpphfifobyteselout;
+ wire wire_transmit_pcs3_iqpphfifordclkout;
+ wire wire_transmit_pcs3_iqpphfifordenableout;
+ wire wire_transmit_pcs3_iqpphfifowrenableout;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs3_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs3_pipepowerstateout;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pcs4_clkout;
+ wire wire_transmit_pcs4_coreclkout;
+ wire [19:0] wire_transmit_pcs4_dataout;
+ wire wire_transmit_pcs4_iqpphfifobyteselout;
+ wire wire_transmit_pcs4_iqpphfifordclkout;
+ wire wire_transmit_pcs4_iqpphfifordenableout;
+ wire wire_transmit_pcs4_iqpphfifowrenableout;
+ wire wire_transmit_pcs4_phfiforddisableout;
+ wire wire_transmit_pcs4_phfiforesetout;
+ wire wire_transmit_pcs4_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs4_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs4_pipepowerstateout;
+ wire wire_transmit_pcs4_txdetectrx;
+ wire wire_transmit_pcs5_clkout;
+ wire wire_transmit_pcs5_coreclkout;
+ wire [19:0] wire_transmit_pcs5_dataout;
+ wire wire_transmit_pcs5_iqpphfifobyteselout;
+ wire wire_transmit_pcs5_iqpphfifordclkout;
+ wire wire_transmit_pcs5_iqpphfifordenableout;
+ wire wire_transmit_pcs5_iqpphfifowrenableout;
+ wire wire_transmit_pcs5_phfiforddisableout;
+ wire wire_transmit_pcs5_phfiforesetout;
+ wire wire_transmit_pcs5_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs5_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs5_pipepowerstateout;
+ wire wire_transmit_pcs5_txdetectrx;
+ wire wire_transmit_pcs6_clkout;
+ wire wire_transmit_pcs6_coreclkout;
+ wire [19:0] wire_transmit_pcs6_dataout;
+ wire wire_transmit_pcs6_iqpphfifobyteselout;
+ wire wire_transmit_pcs6_iqpphfifordclkout;
+ wire wire_transmit_pcs6_iqpphfifordenableout;
+ wire wire_transmit_pcs6_iqpphfifowrenableout;
+ wire wire_transmit_pcs6_phfiforddisableout;
+ wire wire_transmit_pcs6_phfiforesetout;
+ wire wire_transmit_pcs6_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs6_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs6_pipepowerstateout;
+ wire wire_transmit_pcs6_txdetectrx;
+ wire wire_transmit_pcs7_clkout;
+ wire wire_transmit_pcs7_coreclkout;
+ wire [19:0] wire_transmit_pcs7_dataout;
+ wire wire_transmit_pcs7_iqpphfifobyteselout;
+ wire wire_transmit_pcs7_iqpphfifordclkout;
+ wire wire_transmit_pcs7_iqpphfifordenableout;
+ wire wire_transmit_pcs7_iqpphfifowrenableout;
+ wire wire_transmit_pcs7_phfiforddisableout;
+ wire wire_transmit_pcs7_phfiforesetout;
+ wire wire_transmit_pcs7_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs7_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs7_pipepowerstateout;
+ wire wire_transmit_pcs7_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire wire_transmit_pma2_rxdetectvalidout;
+ wire wire_transmit_pma2_rxfoundout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire wire_transmit_pma3_rxdetectvalidout;
+ wire wire_transmit_pma3_rxfoundout;
+ wire wire_transmit_pma4_clockout;
+ wire wire_transmit_pma4_dataout;
+ wire wire_transmit_pma4_rxdetectvalidout;
+ wire wire_transmit_pma4_rxfoundout;
+ wire wire_transmit_pma5_clockout;
+ wire wire_transmit_pma5_dataout;
+ wire wire_transmit_pma5_rxdetectvalidout;
+ wire wire_transmit_pma5_rxfoundout;
+ wire wire_transmit_pma6_clockout;
+ wire wire_transmit_pma6_dataout;
+ wire wire_transmit_pma6_rxdetectvalidout;
+ wire wire_transmit_pma6_rxfoundout;
+ wire wire_transmit_pma7_clockout;
+ wire wire_transmit_pma7_dataout;
+ wire wire_transmit_pma7_rxdetectvalidout;
+ wire wire_transmit_pma7_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [1:0] cent_unit_clkdivpowerdn;
+ wire [3:0] cent_unit_pllpowerdn;
+ wire [3:0] cent_unit_pllresetout;
+ wire [1:0] cent_unit_quadresetout;
+ wire [11:0] cent_unit_rxcrupowerdn;
+ wire [11:0] cent_unit_rxibpowerdn;
+ wire [63:0] cent_unit_tx_xgmdataout;
+ wire [7:0] cent_unit_txctrlout;
+ wire [7:0] cent_unit_txdetectrxpowerdn;
+ wire [11:0] cent_unit_txobpowerdn;
+ wire [7:0] clk_div_clk0in;
+ wire [1:0] clk_div_pclkin;
+ wire [3:0] cmu_analogfastrefclkout;
+ wire [3:0] cmu_analogrefclkout;
+ wire [1:0] cmu_analogrefclkpulse;
+ wire [0:0] coreclkout_bi_quad_wire;
+ wire [1:0] coreclkout_wire;
+ wire fixedclk;
+ wire [11:0] fixedclk_in;
+ wire [1:0] int_hiprateswtichdone;
+ wire [7:0] int_rx_coreclkout;
+ wire [7:0] int_rx_iqpphfifobyteselout;
+ wire [7:0] int_rx_iqpphfifordenableout;
+ wire [7:0] int_rx_iqpphfifowrclkout;
+ wire [7:0] int_rx_iqpphfifowrenableout;
+ wire [15:0] int_rx_iqpphfifoxnbytesel;
+ wire [15:0] int_rx_iqpphfifoxnrdenable;
+ wire [15:0] int_rx_iqpphfifoxnwrclk;
+ wire [15:0] int_rx_iqpphfifoxnwrenable;
+ wire [7:0] int_rx_phfifobyteserdisable;
+ wire [7:0] int_rx_phfifoptrsresetout;
+ wire [7:0] int_rx_phfifordenableout;
+ wire [7:0] int_rx_phfiforesetout;
+ wire [7:0] int_rx_phfifowrdisableout;
+ wire [23:0] int_rx_phfifoxnbytesel;
+ wire [23:0] int_rx_phfifoxnrdenable;
+ wire [23:0] int_rx_phfifoxnwrclk;
+ wire [23:0] int_rx_phfifoxnwrenable;
+ wire [1:0] int_rxcoreclk;
+ wire [1:0] int_rxphfifordenable;
+ wire [1:0] int_rxphfiforeset;
+ wire [1:0] int_rxphfifox4byteselout;
+ wire [1:0] int_rxphfifox4rdenableout;
+ wire [1:0] int_rxphfifox4wrclkout;
+ wire [1:0] int_rxphfifox4wrenableout;
+ wire [7:0] int_tx_coreclkout;
+ wire [7:0] int_tx_iqpphfifobyteselout;
+ wire [7:0] int_tx_iqpphfifordclkout;
+ wire [7:0] int_tx_iqpphfifordenableout;
+ wire [7:0] int_tx_iqpphfifowrenableout;
+ wire [15:0] int_tx_iqpphfifoxnbytesel;
+ wire [15:0] int_tx_iqpphfifoxnrdclk;
+ wire [15:0] int_tx_iqpphfifoxnrdenable;
+ wire [15:0] int_tx_iqpphfifoxnwrenable;
+ wire [7:0] int_tx_phfiforddisableout;
+ wire [7:0] int_tx_phfiforesetout;
+ wire [7:0] int_tx_phfifowrenableout;
+ wire [23:0] int_tx_phfifoxnbytesel;
+ wire [23:0] int_tx_phfifoxnrdclk;
+ wire [23:0] int_tx_phfifoxnrdenable;
+ wire [23:0] int_tx_phfifoxnwrenable;
+ wire [1:0] int_txcoreclk;
+ wire [1:0] int_txphfiforddisable;
+ wire [1:0] int_txphfiforeset;
+ wire [1:0] int_txphfifowrenable;
+ wire [1:0] int_txphfifox4byteselout;
+ wire [1:0] int_txphfifox4rdclkout;
+ wire [1:0] int_txphfifox4rdenableout;
+ wire [1:0] int_txphfifox4wrenableout;
+ wire [1:0] nonusertocmu_out;
+ wire [7:0] pipedatavalid_out;
+ wire [7:0] pipeelecidle_out;
+ wire [19:0] pll0_clkin;
+ wire [7:0] pll0_out;
+ wire [7:0] pll1_out;
+ wire [15:0] pll_ch_dataout_wire;
+ wire [0:0] pll_inclk_wire;
+ wire [1:0] pll_locked_out;
+ wire [1:0] pll_powerdown;
+ wire [3:0] pllpowerdn_in;
+ wire [3:0] pllreset_in;
+ wire reconfig_clk;
+ wire [1:0] refclk_pma;
+ wire [7:0] rx_analogreset_in;
+ wire [11:0] rx_analogreset_out;
+ wire [7:0] rx_bitslip;
+ wire [7:0] rx_coreclk_in;
+ wire [71:0] rx_cruclk_in;
+ wire [31:0] rx_deserclock_in;
+ wire [7:0] rx_digitalreset_in;
+ wire [7:0] rx_digitalreset_out;
+ wire [23:0] rx_elecidleinfersel;
+ wire [7:0] rx_enapatternalign;
+ wire [7:0] rx_freqlocked_wire;
+ wire [7:0] rx_locktodata;
+ wire [7:0] rx_locktodata_wire;
+ wire [7:0] rx_locktorefclk_wire;
+ wire [63:0] rx_out_wire;
+ wire [15:0] rx_pcs_rxfound_wire;
+ wire [3199:0] rx_pcsdprioin_wire;
+ wire [7:0] rx_phfifordenable;
+ wire [7:0] rx_phfiforeset;
+ wire [7:0] rx_phfifowrdisable;
+ wire [7:0] rx_pipestatetransdoneout;
+ wire [7:0] rx_pldcruclk_in;
+ wire [31:0] rx_pll_clkout;
+ wire [7:0] rx_pll_pfdrefclkout_wire;
+ wire [7:0] rx_plllocked_wire;
+ wire [7:0] rx_pma_clockout;
+ wire [7:0] rx_pma_dataout;
+ wire [7:0] rx_pma_locktorefout;
+ wire [159:0] rx_pma_recoverdataout_wire;
+ wire [3599:0] rx_pmadprioin_wire;
+ wire [7:0] rx_powerdown;
+ wire [7:0] rx_powerdown_in;
+ wire [7:0] rx_prbscidenable;
+ wire [159:0] rx_revparallelfdbkdata;
+ wire [7:0] rx_rmfiforeset;
+ wire [11:0] rx_rxcruresetout;
+ wire [7:0] rx_signaldetect_wire;
+ wire [1:0] rxphfifowrdisable;
+ wire [11:0] tx_analogreset_out;
+ wire [7:0] tx_clkout_int_wire;
+ wire [7:0] tx_coreclk_in;
+ wire [63:0] tx_datain_wire;
+ wire [351:0] tx_datainfull;
+ wire [159:0] tx_dataout_pcs_to_pma;
+ wire [7:0] tx_digitalreset_in;
+ wire [7:0] tx_digitalreset_out;
+ wire [2399:0] tx_dprioin_wire;
+ wire [7:0] tx_forcedisp_wire;
+ wire [7:0] tx_invpolarity;
+ wire [7:0] tx_localrefclk;
+ wire [7:0] tx_phfiforeset;
+ wire [7:0] tx_pipedeemph;
+ wire [23:0] tx_pipemargin;
+ wire [15:0] tx_pipepowerdownout;
+ wire [31:0] tx_pipepowerstateout;
+ wire [7:0] tx_pipeswing;
+ wire [3599:0] tx_pmadprioin_wire;
+ wire [7:0] tx_revparallellpbken;
+ wire [7:0] tx_rxdetectvalidout;
+ wire [7:0] tx_rxfoundout;
+ wire [7:0] txdetectrxout;
+
+ arriaii_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ arriaii_hssi_calibration_block cal_blk1
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk1_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ arriaii_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[3:0]),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkin({2{clk_div_pclkin[0]}}),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .dprioin({100{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .vcobypassin(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.data_rate = 0,
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.enable_dynamic_divider = "false",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclk_divide_by = 0,
+ central_clk_div0.refclk_multiply_by = 0,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_rate_switch_base_clock = "true",
+ central_clk_div0.select_local_refclk = "true",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "false",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "arriaii_hssi_clock_divider";
+ arriaii_hssi_clock_divider central_clk_div1
+ (
+ .analogfastrefclkout(wire_central_clk_div1_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div1_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div1_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[7:4]),
+ .coreclkout(wire_central_clk_div1_coreclkout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .powerdn(cent_unit_clkdivpowerdn[1]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div1_rateswitchdone),
+ .rateswitchout(),
+ .refclkin({2{clk_div_pclkin[1]}}),
+ .refclkout(wire_central_clk_div1_refclkout)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .dprioin({100{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .vcobypassin(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div1.data_rate = 0,
+ central_clk_div1.divide_by = 5,
+ central_clk_div1.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div1.enable_dynamic_divider = "false",
+ central_clk_div1.enable_refclk_out = "true",
+ central_clk_div1.inclk_select = 0,
+ central_clk_div1.logical_channel_address = 0,
+ central_clk_div1.pre_divide_by = 1,
+ central_clk_div1.refclk_divide_by = 0,
+ central_clk_div1.refclk_multiply_by = 0,
+ central_clk_div1.refclkin_select = 0,
+ central_clk_div1.select_local_rate_switch_base_clock = "true",
+ central_clk_div1.select_local_refclk = "false",
+ central_clk_div1.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div1.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div1.sim_coreclkout_phase_shift = 0,
+ central_clk_div1.sim_refclkout_phase_shift = 0,
+ central_clk_div1.use_coreclk_out_post_divider = "false",
+ central_clk_div1.use_refclk_post_divider = "false",
+ central_clk_div1.use_vco_bypass = "false",
+ central_clk_div1.lpm_type = "arriaii_hssi_clock_divider";
+ arriaii_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin({600{1'b0}}),
+ .cmudividerdprioout(),
+ .cmuplldprioin({1800{1'b0}}),
+ .cmuplldprioout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(1'b1),
+ .dpriodisableout(),
+ .dprioin(1'b0),
+ .dprioload(1'b0),
+ .dpriooe(),
+ .dprioout(),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk(fixedclk_in[5:0]),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(wire_cent_unit0_rxadcepowerdown),
+ .rxadceresetout(wire_cent_unit0_rxadceresetout),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxdprioout(),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({1600{1'b0}}),
+ .rxpcsdprioout(),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({1800{1'b0}}),
+ .rxpmadprioout(),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txdprioout(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({600{1'b0}}),
+ .txpcsdprioout(),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({1800{1'b0}}),
+ .txpmadprioout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .rateswitch(1'b0),
+ .rxdprioin({1200{1'b0}}),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({6000{1'b0}}),
+ .txdprioin({600{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "driver",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.dprio_config_mode = 6'h00,
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 250000,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "x8",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "false",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "x8",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "false",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "2.5V",
+ cent_unit0.lpm_type = "arriaii_hssi_cmu";
+ arriaii_hssi_cmu cent_unit1
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit1_clkdivpowerdn),
+ .cmudividerdprioin({600{1'b0}}),
+ .cmudividerdprioout(),
+ .cmuplldprioin({1800{1'b0}}),
+ .cmuplldprioout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(1'b1),
+ .dpriodisableout(),
+ .dprioin(1'b0),
+ .dprioload(1'b0),
+ .dpriooe(),
+ .dprioout(),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk(fixedclk_in[11:6]),
+ .nonuserfromcal(nonusertocmu_out[1]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit1_pllpowerdn),
+ .pllresetout(wire_cent_unit1_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit1_quadresetout),
+ .rateswitchdonein(int_hiprateswtichdone[1]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(wire_cent_unit1_rxadcepowerdown),
+ .rxadceresetout(wire_cent_unit1_rxadceresetout),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[7:4]}),
+ .rxanalogresetout(wire_cent_unit1_rxanalogresetout),
+ .rxclk(refclk_pma[1]),
+ .rxcoreclk(int_rxcoreclk[1]),
+ .rxcrupowerdown(wire_cent_unit1_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit1_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[7:4]),
+ .rxdigitalresetout(wire_cent_unit1_rxdigitalresetout),
+ .rxdprioout(),
+ .rxibpowerdown(wire_cent_unit1_rxibpowerdown),
+ .rxpcsdprioin({1600{1'b0}}),
+ .rxpcsdprioout(),
+ .rxphfifordenable(int_rxphfifordenable[1]),
+ .rxphfiforeset(int_rxphfiforeset[1]),
+ .rxphfifowrdisable(rxphfifowrdisable[1]),
+ .rxphfifox4byteselout(wire_cent_unit1_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit1_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit1_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit1_rxphfifox4wrenableout),
+ .rxpmadprioin({1800{1'b0}}),
+ .rxpmadprioout(),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[7:4]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit1_txanalogresetout),
+ .txclk(refclk_pma[1]),
+ .txcoreclk(int_txcoreclk[1]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit1_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit1_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit1_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[7:4]),
+ .txdigitalresetout(wire_cent_unit1_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txdprioout(),
+ .txobpowerdown(wire_cent_unit1_txobpowerdown),
+ .txpcsdprioin({600{1'b0}}),
+ .txpcsdprioout(),
+ .txphfiforddisable(int_txphfiforddisable[1]),
+ .txphfiforeset(int_txphfiforeset[1]),
+ .txphfifowrenable(int_txphfifowrenable[1]),
+ .txphfifox4byteselout(wire_cent_unit1_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit1_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit1_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit1_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[1]}),
+ .txpmadprioin({1800{1'b0}}),
+ .txpmadprioout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .rateswitch(1'b0),
+ .rxdprioin({1200{1'b0}}),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({6000{1'b0}}),
+ .txdprioin({600{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit1.auto_spd_phystatus_notify_count = 14,
+ cent_unit1.bonded_quad_mode = "receiver",
+ cent_unit1.devaddr = ((((starting_channel_number / 4) + 1) % 32) + 1),
+ cent_unit1.dprio_config_mode = 6'h00,
+ cent_unit1.in_xaui_mode = "false",
+ cent_unit1.offset_all_errors_align = "false",
+ cent_unit1.pipe_auto_speed_nego_enable = "false",
+ cent_unit1.pipe_freq_scale_mode = "Frequency",
+ cent_unit1.pma_done_count = 250000,
+ cent_unit1.portaddr = (((starting_channel_number + 4) / 128) + 1),
+ cent_unit1.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit1.rx0_channel_bonding = "x8",
+ cent_unit1.rx0_clk1_mux_select = "recovered clock",
+ cent_unit1.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit1.rx0_ph_fifo_reg_mode = "false",
+ cent_unit1.rx0_rd_clk_mux_select = "core clock",
+ cent_unit1.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit1.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit1.rx0_use_double_data_mode = "false",
+ cent_unit1.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit1.tx0_channel_bonding = "x8",
+ cent_unit1.tx0_ph_fifo_reg_mode = "false",
+ cent_unit1.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit1.tx0_use_double_data_mode = "false",
+ cent_unit1.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit1.use_deskew_fifo = "false",
+ cent_unit1.vcceh_voltage = "2.5V",
+ cent_unit1.lpm_type = "arriaii_hssi_cmu";
+ arriaii_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.charge_pump_current_bits = 0,
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.inclk1_input_period = 5000,
+ rx_cdr_pll0.inclk2_input_period = 5000,
+ rx_cdr_pll0.inclk3_input_period = 5000,
+ rx_cdr_pll0.inclk4_input_period = 5000,
+ rx_cdr_pll0.inclk5_input_period = 5000,
+ rx_cdr_pll0.inclk6_input_period = 5000,
+ rx_cdr_pll0.inclk7_input_period = 5000,
+ rx_cdr_pll0.inclk8_input_period = 5000,
+ rx_cdr_pll0.inclk9_input_period = 5000,
+ rx_cdr_pll0.loop_filter_c_bits = 0,
+ rx_cdr_pll0.loop_filter_r_bits = 0,
+ rx_cdr_pll0.m = 1,
+ rx_cdr_pll0.n = 1,
+ rx_cdr_pll0.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll0.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.protocol_hint = "pcie",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_data_rate = 0,
+ rx_cdr_pll0.vco_divide_by = 0,
+ rx_cdr_pll0.vco_multiply_by = 0,
+ rx_cdr_pll0.vco_post_scale = 1,
+ rx_cdr_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[17:9]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.charge_pump_current_bits = 0,
+ rx_cdr_pll1.dprio_config_mode = 6'h00,
+ rx_cdr_pll1.inclk0_input_period = 10000,
+ rx_cdr_pll1.inclk1_input_period = 5000,
+ rx_cdr_pll1.inclk2_input_period = 5000,
+ rx_cdr_pll1.inclk3_input_period = 5000,
+ rx_cdr_pll1.inclk4_input_period = 5000,
+ rx_cdr_pll1.inclk5_input_period = 5000,
+ rx_cdr_pll1.inclk6_input_period = 5000,
+ rx_cdr_pll1.inclk7_input_period = 5000,
+ rx_cdr_pll1.inclk8_input_period = 5000,
+ rx_cdr_pll1.inclk9_input_period = 5000,
+ rx_cdr_pll1.loop_filter_c_bits = 0,
+ rx_cdr_pll1.loop_filter_r_bits = 0,
+ rx_cdr_pll1.m = 1,
+ rx_cdr_pll1.n = 1,
+ rx_cdr_pll1.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll1.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll1.pfd_clk_select = 0,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.protocol_hint = "pcie",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_data_rate = 0,
+ rx_cdr_pll1.vco_divide_by = 0,
+ rx_cdr_pll1.vco_multiply_by = 0,
+ rx_cdr_pll1.vco_post_scale = 1,
+ rx_cdr_pll1.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[26:18]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.charge_pump_current_bits = 0,
+ rx_cdr_pll2.dprio_config_mode = 6'h00,
+ rx_cdr_pll2.inclk0_input_period = 10000,
+ rx_cdr_pll2.inclk1_input_period = 5000,
+ rx_cdr_pll2.inclk2_input_period = 5000,
+ rx_cdr_pll2.inclk3_input_period = 5000,
+ rx_cdr_pll2.inclk4_input_period = 5000,
+ rx_cdr_pll2.inclk5_input_period = 5000,
+ rx_cdr_pll2.inclk6_input_period = 5000,
+ rx_cdr_pll2.inclk7_input_period = 5000,
+ rx_cdr_pll2.inclk8_input_period = 5000,
+ rx_cdr_pll2.inclk9_input_period = 5000,
+ rx_cdr_pll2.loop_filter_c_bits = 0,
+ rx_cdr_pll2.loop_filter_r_bits = 0,
+ rx_cdr_pll2.m = 1,
+ rx_cdr_pll2.n = 1,
+ rx_cdr_pll2.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll2.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll2.pfd_clk_select = 0,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.protocol_hint = "pcie",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_data_rate = 0,
+ rx_cdr_pll2.vco_divide_by = 0,
+ rx_cdr_pll2.vco_multiply_by = 0,
+ rx_cdr_pll2.vco_post_scale = 1,
+ rx_cdr_pll2.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[35:27]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.charge_pump_current_bits = 0,
+ rx_cdr_pll3.dprio_config_mode = 6'h00,
+ rx_cdr_pll3.inclk0_input_period = 10000,
+ rx_cdr_pll3.inclk1_input_period = 5000,
+ rx_cdr_pll3.inclk2_input_period = 5000,
+ rx_cdr_pll3.inclk3_input_period = 5000,
+ rx_cdr_pll3.inclk4_input_period = 5000,
+ rx_cdr_pll3.inclk5_input_period = 5000,
+ rx_cdr_pll3.inclk6_input_period = 5000,
+ rx_cdr_pll3.inclk7_input_period = 5000,
+ rx_cdr_pll3.inclk8_input_period = 5000,
+ rx_cdr_pll3.inclk9_input_period = 5000,
+ rx_cdr_pll3.loop_filter_c_bits = 0,
+ rx_cdr_pll3.loop_filter_r_bits = 0,
+ rx_cdr_pll3.m = 1,
+ rx_cdr_pll3.n = 1,
+ rx_cdr_pll3.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll3.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll3.pfd_clk_select = 0,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.protocol_hint = "pcie",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_data_rate = 0,
+ rx_cdr_pll3.vco_divide_by = 0,
+ rx_cdr_pll3.vco_multiply_by = 0,
+ rx_cdr_pll3.vco_post_scale = 1,
+ rx_cdr_pll3.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll4
+ (
+ .areset(rx_rxcruresetout[6]),
+ .clk(wire_rx_cdr_pll4_clk),
+ .datain(rx_pma_dataout[4]),
+ .dataout(wire_rx_cdr_pll4_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll4_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[44:36]}),
+ .locked(wire_rx_cdr_pll4_locked),
+ .locktorefclk(rx_pma_locktorefout[4]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll4_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[6]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll4.channel_num = ((starting_channel_number + 4) % 4),
+ rx_cdr_pll4.charge_pump_current_bits = 0,
+ rx_cdr_pll4.dprio_config_mode = 6'h00,
+ rx_cdr_pll4.inclk0_input_period = 10000,
+ rx_cdr_pll4.inclk1_input_period = 5000,
+ rx_cdr_pll4.inclk2_input_period = 5000,
+ rx_cdr_pll4.inclk3_input_period = 5000,
+ rx_cdr_pll4.inclk4_input_period = 5000,
+ rx_cdr_pll4.inclk5_input_period = 5000,
+ rx_cdr_pll4.inclk6_input_period = 5000,
+ rx_cdr_pll4.inclk7_input_period = 5000,
+ rx_cdr_pll4.inclk8_input_period = 5000,
+ rx_cdr_pll4.inclk9_input_period = 5000,
+ rx_cdr_pll4.loop_filter_c_bits = 0,
+ rx_cdr_pll4.loop_filter_r_bits = 0,
+ rx_cdr_pll4.m = 1,
+ rx_cdr_pll4.n = 1,
+ rx_cdr_pll4.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll4.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll4.pfd_clk_select = 0,
+ rx_cdr_pll4.pll_type = "RX CDR",
+ rx_cdr_pll4.protocol_hint = "pcie",
+ rx_cdr_pll4.use_refclk_pin = "false",
+ rx_cdr_pll4.vco_data_rate = 0,
+ rx_cdr_pll4.vco_divide_by = 0,
+ rx_cdr_pll4.vco_multiply_by = 0,
+ rx_cdr_pll4.vco_post_scale = 1,
+ rx_cdr_pll4.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll5
+ (
+ .areset(rx_rxcruresetout[7]),
+ .clk(wire_rx_cdr_pll5_clk),
+ .datain(rx_pma_dataout[5]),
+ .dataout(wire_rx_cdr_pll5_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll5_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[53:45]}),
+ .locked(wire_rx_cdr_pll5_locked),
+ .locktorefclk(rx_pma_locktorefout[5]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll5_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[7]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll5.channel_num = ((starting_channel_number + 5) % 4),
+ rx_cdr_pll5.charge_pump_current_bits = 0,
+ rx_cdr_pll5.dprio_config_mode = 6'h00,
+ rx_cdr_pll5.inclk0_input_period = 10000,
+ rx_cdr_pll5.inclk1_input_period = 5000,
+ rx_cdr_pll5.inclk2_input_period = 5000,
+ rx_cdr_pll5.inclk3_input_period = 5000,
+ rx_cdr_pll5.inclk4_input_period = 5000,
+ rx_cdr_pll5.inclk5_input_period = 5000,
+ rx_cdr_pll5.inclk6_input_period = 5000,
+ rx_cdr_pll5.inclk7_input_period = 5000,
+ rx_cdr_pll5.inclk8_input_period = 5000,
+ rx_cdr_pll5.inclk9_input_period = 5000,
+ rx_cdr_pll5.loop_filter_c_bits = 0,
+ rx_cdr_pll5.loop_filter_r_bits = 0,
+ rx_cdr_pll5.m = 1,
+ rx_cdr_pll5.n = 1,
+ rx_cdr_pll5.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll5.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll5.pfd_clk_select = 0,
+ rx_cdr_pll5.pll_type = "RX CDR",
+ rx_cdr_pll5.protocol_hint = "pcie",
+ rx_cdr_pll5.use_refclk_pin = "false",
+ rx_cdr_pll5.vco_data_rate = 0,
+ rx_cdr_pll5.vco_divide_by = 0,
+ rx_cdr_pll5.vco_multiply_by = 0,
+ rx_cdr_pll5.vco_post_scale = 1,
+ rx_cdr_pll5.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll6
+ (
+ .areset(rx_rxcruresetout[8]),
+ .clk(wire_rx_cdr_pll6_clk),
+ .datain(rx_pma_dataout[6]),
+ .dataout(wire_rx_cdr_pll6_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll6_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[62:54]}),
+ .locked(wire_rx_cdr_pll6_locked),
+ .locktorefclk(rx_pma_locktorefout[6]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll6_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[8]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll6.channel_num = ((starting_channel_number + 6) % 4),
+ rx_cdr_pll6.charge_pump_current_bits = 0,
+ rx_cdr_pll6.dprio_config_mode = 6'h00,
+ rx_cdr_pll6.inclk0_input_period = 10000,
+ rx_cdr_pll6.inclk1_input_period = 5000,
+ rx_cdr_pll6.inclk2_input_period = 5000,
+ rx_cdr_pll6.inclk3_input_period = 5000,
+ rx_cdr_pll6.inclk4_input_period = 5000,
+ rx_cdr_pll6.inclk5_input_period = 5000,
+ rx_cdr_pll6.inclk6_input_period = 5000,
+ rx_cdr_pll6.inclk7_input_period = 5000,
+ rx_cdr_pll6.inclk8_input_period = 5000,
+ rx_cdr_pll6.inclk9_input_period = 5000,
+ rx_cdr_pll6.loop_filter_c_bits = 0,
+ rx_cdr_pll6.loop_filter_r_bits = 0,
+ rx_cdr_pll6.m = 1,
+ rx_cdr_pll6.n = 1,
+ rx_cdr_pll6.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll6.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll6.pfd_clk_select = 0,
+ rx_cdr_pll6.pll_type = "RX CDR",
+ rx_cdr_pll6.protocol_hint = "pcie",
+ rx_cdr_pll6.use_refclk_pin = "false",
+ rx_cdr_pll6.vco_data_rate = 0,
+ rx_cdr_pll6.vco_divide_by = 0,
+ rx_cdr_pll6.vco_multiply_by = 0,
+ rx_cdr_pll6.vco_post_scale = 1,
+ rx_cdr_pll6.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll rx_cdr_pll7
+ (
+ .areset(rx_rxcruresetout[9]),
+ .clk(wire_rx_cdr_pll7_clk),
+ .datain(rx_pma_dataout[7]),
+ .dataout(wire_rx_cdr_pll7_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll7_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[71:63]}),
+ .locked(wire_rx_cdr_pll7_locked),
+ .locktorefclk(rx_pma_locktorefout[7]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll7_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[9]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll7.channel_num = ((starting_channel_number + 7) % 4),
+ rx_cdr_pll7.charge_pump_current_bits = 0,
+ rx_cdr_pll7.dprio_config_mode = 6'h00,
+ rx_cdr_pll7.inclk0_input_period = 10000,
+ rx_cdr_pll7.inclk1_input_period = 5000,
+ rx_cdr_pll7.inclk2_input_period = 5000,
+ rx_cdr_pll7.inclk3_input_period = 5000,
+ rx_cdr_pll7.inclk4_input_period = 5000,
+ rx_cdr_pll7.inclk5_input_period = 5000,
+ rx_cdr_pll7.inclk6_input_period = 5000,
+ rx_cdr_pll7.inclk7_input_period = 5000,
+ rx_cdr_pll7.inclk8_input_period = 5000,
+ rx_cdr_pll7.inclk9_input_period = 5000,
+ rx_cdr_pll7.loop_filter_c_bits = 0,
+ rx_cdr_pll7.loop_filter_r_bits = 0,
+ rx_cdr_pll7.m = 1,
+ rx_cdr_pll7.n = 1,
+ rx_cdr_pll7.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll7.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll7.pfd_clk_select = 0,
+ rx_cdr_pll7.pll_type = "RX CDR",
+ rx_cdr_pll7.protocol_hint = "pcie",
+ rx_cdr_pll7.use_refclk_pin = "false",
+ rx_cdr_pll7.vco_data_rate = 0,
+ rx_cdr_pll7.vco_divide_by = 0,
+ rx_cdr_pll7.vco_multiply_by = 0,
+ rx_cdr_pll7.vco_post_scale = 1,
+ rx_cdr_pll7.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.channel_num = 4,
+ tx_pll0.charge_pump_current_bits = 0,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.inclk1_input_period = 5000,
+ tx_pll0.inclk2_input_period = 5000,
+ tx_pll0.inclk3_input_period = 5000,
+ tx_pll0.inclk4_input_period = 5000,
+ tx_pll0.inclk5_input_period = 5000,
+ tx_pll0.inclk6_input_period = 5000,
+ tx_pll0.inclk7_input_period = 5000,
+ tx_pll0.inclk8_input_period = 5000,
+ tx_pll0.inclk9_input_period = 5000,
+ tx_pll0.loop_filter_c_bits = 0,
+ tx_pll0.loop_filter_r_bits = 0,
+ tx_pll0.m = 1,
+ tx_pll0.n = 1,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.protocol_hint = "pcie",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_data_rate = 0,
+ tx_pll0.vco_divide_by = 0,
+ tx_pll0.vco_multiply_by = 0,
+ tx_pll0.vco_post_scale = 1,
+ tx_pll0.lpm_type = "arriaii_hssi_pll";
+ arriaii_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[0]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs0_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs0_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs0_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs0_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[1:0]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[1:0]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[1:0]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[1:0]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x8",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 8,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h00,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 250000,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "false",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[1]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs1_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs1_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs1_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs1_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[3:2]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[3:2]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[3:2]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[3:2]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.auto_spd_self_switch_enable = "false",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_mask_cycle = 800,
+ receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x8",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 8,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h00,
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "false",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 250000,
+ receive_pcs1.protocol_hint = "pcie",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rxstatus_error_report_mode = 0,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "false",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[2]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[8:6]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs2_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs2_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs2_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs2_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[5:4]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[5:4]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[5:4]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[5:4]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs2_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs2_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[5:4]),
+ .pipepowerstate(tx_pipepowerstateout[11:8]),
+ .pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs2_pipestatus),
+ .powerdn(powerdn[5:4]),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[2]),
+ .rxfound(rx_pcs_rxfound_wire[5:4]),
+ .signaldetected(rx_signaldetect_wire[2]),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "false",
+ receive_pcs2.allow_pipe_polarity_inversion = "true",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 14,
+ receive_pcs2.auto_spd_self_switch_enable = "false",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_enable = "true",
+ receive_pcs2.cdrctrl_mask_cycle = 800,
+ receive_pcs2.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs2.cdrctrl_rxvalid_mask = "true",
+ receive_pcs2.channel_bonding = "x8",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 8,
+ receive_pcs2.clk1_mux_select = "recovered clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "false",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "pipe",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs2.deskew_pattern = "0",
+ receive_pcs2.disable_auto_idle_insertion = "false",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h00,
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 16,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 17,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "false",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 250000,
+ receive_pcs2.protocol_hint = "pcie",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "false",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs2.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs2.rate_match_pattern_size = 20,
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "true",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rxstatus_error_report_mode = 0,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "false",
+ receive_pcs2.use_double_data_mode = "false",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[3]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[11:9]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs3_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs3_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs3_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs3_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[7:6]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[7:6]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[7:6]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[7:6]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs3_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs3_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[7:6]),
+ .pipepowerstate(tx_pipepowerstateout[15:12]),
+ .pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs3_pipestatus),
+ .powerdn(powerdn[7:6]),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[3]),
+ .rxfound(rx_pcs_rxfound_wire[7:6]),
+ .signaldetected(rx_signaldetect_wire[3]),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "false",
+ receive_pcs3.allow_pipe_polarity_inversion = "true",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 14,
+ receive_pcs3.auto_spd_self_switch_enable = "false",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_enable = "true",
+ receive_pcs3.cdrctrl_mask_cycle = 800,
+ receive_pcs3.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs3.cdrctrl_rxvalid_mask = "true",
+ receive_pcs3.channel_bonding = "x8",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 8,
+ receive_pcs3.clk1_mux_select = "recovered clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "false",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "pipe",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs3.deskew_pattern = "0",
+ receive_pcs3.disable_auto_idle_insertion = "false",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h00,
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 16,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 17,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "false",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 250000,
+ receive_pcs3.protocol_hint = "pcie",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "false",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs3.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs3.rate_match_pattern_size = 20,
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "true",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rxstatus_error_report_mode = 0,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "false",
+ receive_pcs3.use_double_data_mode = "false",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs4
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[4]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs4_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[4]),
+ .coreclkout(wire_receive_pcs4_coreclkout),
+ .ctrldetect(wire_receive_pcs4_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[99:80]),
+ .dataout(wire_receive_pcs4_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[4]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[1999:1600]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[14:12]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[4]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs4_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs4_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs4_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs4_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[9:8]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[9:8]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[9:8]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[9:8]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs4_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs4_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs4_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[4]),
+ .phfifordenableout(wire_receive_pcs4_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[4]),
+ .phfiforesetout(wire_receive_pcs4_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[4]),
+ .phfifowrdisableout(wire_receive_pcs4_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[14:12]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[14:12]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[14:12]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[14:12]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[4]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs4_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs4_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs4_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[9:8]),
+ .pipepowerstate(tx_pipepowerstateout[19:16]),
+ .pipestatetransdoneout(wire_receive_pcs4_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs4_pipestatus),
+ .powerdn(powerdn[9:8]),
+ .prbscidenable(rx_prbscidenable[4]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(wire_receive_pcs4_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[4]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs4_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[4]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[4]),
+ .rxfound(rx_pcs_rxfound_wire[9:8]),
+ .signaldetected(rx_signaldetect_wire[4]),
+ .syncstatus(wire_receive_pcs4_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs4.align_pattern = "0101111100",
+ receive_pcs4.align_pattern_length = 10,
+ receive_pcs4.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs4.allow_align_polarity_inversion = "false",
+ receive_pcs4.allow_pipe_polarity_inversion = "true",
+ receive_pcs4.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs4.auto_spd_phystatus_notify_count = 14,
+ receive_pcs4.auto_spd_self_switch_enable = "false",
+ receive_pcs4.bit_slip_enable = "false",
+ receive_pcs4.byte_order_mode = "none",
+ receive_pcs4.byte_order_pad_pattern = "0",
+ receive_pcs4.byte_order_pattern = "0",
+ receive_pcs4.byte_order_pld_ctrl_enable = "false",
+ receive_pcs4.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs4.cdrctrl_enable = "true",
+ receive_pcs4.cdrctrl_mask_cycle = 800,
+ receive_pcs4.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs4.cdrctrl_rxvalid_mask = "true",
+ receive_pcs4.channel_bonding = "x8",
+ receive_pcs4.channel_number = ((starting_channel_number + 4) % 4),
+ receive_pcs4.channel_width = 8,
+ receive_pcs4.clk1_mux_select = "recovered clock",
+ receive_pcs4.clk2_mux_select = "digital reference clock",
+ receive_pcs4.core_clock_0ppm = "false",
+ receive_pcs4.datapath_low_latency_mode = "false",
+ receive_pcs4.datapath_protocol = "pipe",
+ receive_pcs4.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs4.dec_8b_10b_mode = "normal",
+ receive_pcs4.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs4.deskew_pattern = "0",
+ receive_pcs4.disable_auto_idle_insertion = "false",
+ receive_pcs4.disable_running_disp_in_word_align = "false",
+ receive_pcs4.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs4.dprio_config_mode = 6'h00,
+ receive_pcs4.elec_idle_infer_enable = "false",
+ receive_pcs4.elec_idle_num_com_detect = 3,
+ receive_pcs4.enable_bit_reversal = "false",
+ receive_pcs4.enable_deep_align = "false",
+ receive_pcs4.enable_deep_align_byte_swap = "false",
+ receive_pcs4.enable_self_test_mode = "false",
+ receive_pcs4.enable_true_complement_match_in_word_align = "false",
+ receive_pcs4.force_signal_detect_dig = "true",
+ receive_pcs4.hip_enable = "false",
+ receive_pcs4.infiniband_invalid_code = 0,
+ receive_pcs4.insert_pad_on_underflow = "false",
+ receive_pcs4.logical_channel_address = (starting_channel_number + 4),
+ receive_pcs4.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs4.num_align_cons_good_data = 16,
+ receive_pcs4.num_align_cons_pat = 4,
+ receive_pcs4.num_align_loss_sync_error = 17,
+ receive_pcs4.ph_fifo_low_latency_enable = "true",
+ receive_pcs4.ph_fifo_reg_mode = "false",
+ receive_pcs4.ph_fifo_xn_mapping0 = "none",
+ receive_pcs4.ph_fifo_xn_mapping1 = "up",
+ receive_pcs4.ph_fifo_xn_mapping2 = "none",
+ receive_pcs4.ph_fifo_xn_select = 1,
+ receive_pcs4.pipe_auto_speed_nego_enable = "false",
+ receive_pcs4.pipe_freq_scale_mode = "Frequency",
+ receive_pcs4.pma_done_count = 250000,
+ receive_pcs4.protocol_hint = "pcie",
+ receive_pcs4.rate_match_almost_empty_threshold = 11,
+ receive_pcs4.rate_match_almost_full_threshold = 13,
+ receive_pcs4.rate_match_back_to_back = "false",
+ receive_pcs4.rate_match_delete_threshold = 13,
+ receive_pcs4.rate_match_empty_threshold = 5,
+ receive_pcs4.rate_match_fifo_mode = "true",
+ receive_pcs4.rate_match_full_threshold = 20,
+ receive_pcs4.rate_match_insert_threshold = 11,
+ receive_pcs4.rate_match_ordered_set_based = "false",
+ receive_pcs4.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs4.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs4.rate_match_pattern_size = 20,
+ receive_pcs4.rate_match_reset_enable = "false",
+ receive_pcs4.rate_match_skip_set_based = "true",
+ receive_pcs4.rate_match_start_threshold = 7,
+ receive_pcs4.rd_clk_mux_select = "core clock",
+ receive_pcs4.recovered_clk_mux_select = "recovered clock",
+ receive_pcs4.run_length = 40,
+ receive_pcs4.run_length_enable = "true",
+ receive_pcs4.rx_detect_bypass = "false",
+ receive_pcs4.rxstatus_error_report_mode = 0,
+ receive_pcs4.self_test_mode = "incremental",
+ receive_pcs4.use_alignment_state_machine = "true",
+ receive_pcs4.use_deserializer_double_data_mode = "false",
+ receive_pcs4.use_deskew_fifo = "false",
+ receive_pcs4.use_double_data_mode = "false",
+ receive_pcs4.use_parallel_loopback = "false",
+ receive_pcs4.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs4.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs5
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[5]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs5_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[5]),
+ .coreclkout(wire_receive_pcs5_coreclkout),
+ .ctrldetect(wire_receive_pcs5_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[119:100]),
+ .dataout(wire_receive_pcs5_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[5]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[2399:2000]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[17:15]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[5]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs5_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs5_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs5_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs5_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[11:10]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[11:10]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[11:10]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[11:10]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs5_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs5_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs5_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[5]),
+ .phfifordenableout(wire_receive_pcs5_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[5]),
+ .phfiforesetout(wire_receive_pcs5_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[5]),
+ .phfifowrdisableout(wire_receive_pcs5_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[17:15]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[17:15]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[17:15]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[17:15]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[5]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs5_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs5_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs5_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[11:10]),
+ .pipepowerstate(tx_pipepowerstateout[23:20]),
+ .pipestatetransdoneout(wire_receive_pcs5_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs5_pipestatus),
+ .powerdn(powerdn[11:10]),
+ .prbscidenable(rx_prbscidenable[5]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(wire_receive_pcs5_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[5]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs5_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[5]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[5]),
+ .rxfound(rx_pcs_rxfound_wire[11:10]),
+ .signaldetected(rx_signaldetect_wire[5]),
+ .syncstatus(wire_receive_pcs5_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs5.align_pattern = "0101111100",
+ receive_pcs5.align_pattern_length = 10,
+ receive_pcs5.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs5.allow_align_polarity_inversion = "false",
+ receive_pcs5.allow_pipe_polarity_inversion = "true",
+ receive_pcs5.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs5.auto_spd_phystatus_notify_count = 14,
+ receive_pcs5.auto_spd_self_switch_enable = "false",
+ receive_pcs5.bit_slip_enable = "false",
+ receive_pcs5.byte_order_mode = "none",
+ receive_pcs5.byte_order_pad_pattern = "0",
+ receive_pcs5.byte_order_pattern = "0",
+ receive_pcs5.byte_order_pld_ctrl_enable = "false",
+ receive_pcs5.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs5.cdrctrl_enable = "true",
+ receive_pcs5.cdrctrl_mask_cycle = 800,
+ receive_pcs5.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs5.cdrctrl_rxvalid_mask = "true",
+ receive_pcs5.channel_bonding = "x8",
+ receive_pcs5.channel_number = ((starting_channel_number + 5) % 4),
+ receive_pcs5.channel_width = 8,
+ receive_pcs5.clk1_mux_select = "recovered clock",
+ receive_pcs5.clk2_mux_select = "digital reference clock",
+ receive_pcs5.core_clock_0ppm = "false",
+ receive_pcs5.datapath_low_latency_mode = "false",
+ receive_pcs5.datapath_protocol = "pipe",
+ receive_pcs5.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs5.dec_8b_10b_mode = "normal",
+ receive_pcs5.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs5.deskew_pattern = "0",
+ receive_pcs5.disable_auto_idle_insertion = "false",
+ receive_pcs5.disable_running_disp_in_word_align = "false",
+ receive_pcs5.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs5.dprio_config_mode = 6'h00,
+ receive_pcs5.elec_idle_infer_enable = "false",
+ receive_pcs5.elec_idle_num_com_detect = 3,
+ receive_pcs5.enable_bit_reversal = "false",
+ receive_pcs5.enable_deep_align = "false",
+ receive_pcs5.enable_deep_align_byte_swap = "false",
+ receive_pcs5.enable_self_test_mode = "false",
+ receive_pcs5.enable_true_complement_match_in_word_align = "false",
+ receive_pcs5.force_signal_detect_dig = "true",
+ receive_pcs5.hip_enable = "false",
+ receive_pcs5.infiniband_invalid_code = 0,
+ receive_pcs5.insert_pad_on_underflow = "false",
+ receive_pcs5.logical_channel_address = (starting_channel_number + 5),
+ receive_pcs5.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs5.num_align_cons_good_data = 16,
+ receive_pcs5.num_align_cons_pat = 4,
+ receive_pcs5.num_align_loss_sync_error = 17,
+ receive_pcs5.ph_fifo_low_latency_enable = "true",
+ receive_pcs5.ph_fifo_reg_mode = "false",
+ receive_pcs5.ph_fifo_xn_mapping0 = "none",
+ receive_pcs5.ph_fifo_xn_mapping1 = "up",
+ receive_pcs5.ph_fifo_xn_mapping2 = "none",
+ receive_pcs5.ph_fifo_xn_select = 1,
+ receive_pcs5.pipe_auto_speed_nego_enable = "false",
+ receive_pcs5.pipe_freq_scale_mode = "Frequency",
+ receive_pcs5.pma_done_count = 250000,
+ receive_pcs5.protocol_hint = "pcie",
+ receive_pcs5.rate_match_almost_empty_threshold = 11,
+ receive_pcs5.rate_match_almost_full_threshold = 13,
+ receive_pcs5.rate_match_back_to_back = "false",
+ receive_pcs5.rate_match_delete_threshold = 13,
+ receive_pcs5.rate_match_empty_threshold = 5,
+ receive_pcs5.rate_match_fifo_mode = "true",
+ receive_pcs5.rate_match_full_threshold = 20,
+ receive_pcs5.rate_match_insert_threshold = 11,
+ receive_pcs5.rate_match_ordered_set_based = "false",
+ receive_pcs5.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs5.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs5.rate_match_pattern_size = 20,
+ receive_pcs5.rate_match_reset_enable = "false",
+ receive_pcs5.rate_match_skip_set_based = "true",
+ receive_pcs5.rate_match_start_threshold = 7,
+ receive_pcs5.rd_clk_mux_select = "core clock",
+ receive_pcs5.recovered_clk_mux_select = "recovered clock",
+ receive_pcs5.run_length = 40,
+ receive_pcs5.run_length_enable = "true",
+ receive_pcs5.rx_detect_bypass = "false",
+ receive_pcs5.rxstatus_error_report_mode = 0,
+ receive_pcs5.self_test_mode = "incremental",
+ receive_pcs5.use_alignment_state_machine = "true",
+ receive_pcs5.use_deserializer_double_data_mode = "false",
+ receive_pcs5.use_deskew_fifo = "false",
+ receive_pcs5.use_double_data_mode = "false",
+ receive_pcs5.use_parallel_loopback = "false",
+ receive_pcs5.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs5.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs6
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[6]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs6_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[6]),
+ .coreclkout(wire_receive_pcs6_coreclkout),
+ .ctrldetect(wire_receive_pcs6_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[139:120]),
+ .dataout(wire_receive_pcs6_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[6]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[2799:2400]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[20:18]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[6]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs6_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs6_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs6_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs6_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[13:12]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[13:12]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[13:12]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[13:12]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs6_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs6_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs6_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[6]),
+ .phfifordenableout(wire_receive_pcs6_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[6]),
+ .phfiforesetout(wire_receive_pcs6_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[6]),
+ .phfifowrdisableout(wire_receive_pcs6_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[20:18]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[20:18]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[20:18]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[20:18]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[6]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs6_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs6_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs6_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[13:12]),
+ .pipepowerstate(tx_pipepowerstateout[27:24]),
+ .pipestatetransdoneout(wire_receive_pcs6_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs6_pipestatus),
+ .powerdn(powerdn[13:12]),
+ .prbscidenable(rx_prbscidenable[6]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(wire_receive_pcs6_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[6]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs6_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[6]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[6]),
+ .rxfound(rx_pcs_rxfound_wire[13:12]),
+ .signaldetected(rx_signaldetect_wire[6]),
+ .syncstatus(wire_receive_pcs6_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs6.align_pattern = "0101111100",
+ receive_pcs6.align_pattern_length = 10,
+ receive_pcs6.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs6.allow_align_polarity_inversion = "false",
+ receive_pcs6.allow_pipe_polarity_inversion = "true",
+ receive_pcs6.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs6.auto_spd_phystatus_notify_count = 14,
+ receive_pcs6.auto_spd_self_switch_enable = "false",
+ receive_pcs6.bit_slip_enable = "false",
+ receive_pcs6.byte_order_mode = "none",
+ receive_pcs6.byte_order_pad_pattern = "0",
+ receive_pcs6.byte_order_pattern = "0",
+ receive_pcs6.byte_order_pld_ctrl_enable = "false",
+ receive_pcs6.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs6.cdrctrl_enable = "true",
+ receive_pcs6.cdrctrl_mask_cycle = 800,
+ receive_pcs6.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs6.cdrctrl_rxvalid_mask = "true",
+ receive_pcs6.channel_bonding = "x8",
+ receive_pcs6.channel_number = ((starting_channel_number + 6) % 4),
+ receive_pcs6.channel_width = 8,
+ receive_pcs6.clk1_mux_select = "recovered clock",
+ receive_pcs6.clk2_mux_select = "digital reference clock",
+ receive_pcs6.core_clock_0ppm = "false",
+ receive_pcs6.datapath_low_latency_mode = "false",
+ receive_pcs6.datapath_protocol = "pipe",
+ receive_pcs6.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs6.dec_8b_10b_mode = "normal",
+ receive_pcs6.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs6.deskew_pattern = "0",
+ receive_pcs6.disable_auto_idle_insertion = "false",
+ receive_pcs6.disable_running_disp_in_word_align = "false",
+ receive_pcs6.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs6.dprio_config_mode = 6'h00,
+ receive_pcs6.elec_idle_infer_enable = "false",
+ receive_pcs6.elec_idle_num_com_detect = 3,
+ receive_pcs6.enable_bit_reversal = "false",
+ receive_pcs6.enable_deep_align = "false",
+ receive_pcs6.enable_deep_align_byte_swap = "false",
+ receive_pcs6.enable_self_test_mode = "false",
+ receive_pcs6.enable_true_complement_match_in_word_align = "false",
+ receive_pcs6.force_signal_detect_dig = "true",
+ receive_pcs6.hip_enable = "false",
+ receive_pcs6.infiniband_invalid_code = 0,
+ receive_pcs6.insert_pad_on_underflow = "false",
+ receive_pcs6.logical_channel_address = (starting_channel_number + 6),
+ receive_pcs6.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs6.num_align_cons_good_data = 16,
+ receive_pcs6.num_align_cons_pat = 4,
+ receive_pcs6.num_align_loss_sync_error = 17,
+ receive_pcs6.ph_fifo_low_latency_enable = "true",
+ receive_pcs6.ph_fifo_reg_mode = "false",
+ receive_pcs6.ph_fifo_xn_mapping0 = "none",
+ receive_pcs6.ph_fifo_xn_mapping1 = "up",
+ receive_pcs6.ph_fifo_xn_mapping2 = "none",
+ receive_pcs6.ph_fifo_xn_select = 1,
+ receive_pcs6.pipe_auto_speed_nego_enable = "false",
+ receive_pcs6.pipe_freq_scale_mode = "Frequency",
+ receive_pcs6.pma_done_count = 250000,
+ receive_pcs6.protocol_hint = "pcie",
+ receive_pcs6.rate_match_almost_empty_threshold = 11,
+ receive_pcs6.rate_match_almost_full_threshold = 13,
+ receive_pcs6.rate_match_back_to_back = "false",
+ receive_pcs6.rate_match_delete_threshold = 13,
+ receive_pcs6.rate_match_empty_threshold = 5,
+ receive_pcs6.rate_match_fifo_mode = "true",
+ receive_pcs6.rate_match_full_threshold = 20,
+ receive_pcs6.rate_match_insert_threshold = 11,
+ receive_pcs6.rate_match_ordered_set_based = "false",
+ receive_pcs6.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs6.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs6.rate_match_pattern_size = 20,
+ receive_pcs6.rate_match_reset_enable = "false",
+ receive_pcs6.rate_match_skip_set_based = "true",
+ receive_pcs6.rate_match_start_threshold = 7,
+ receive_pcs6.rd_clk_mux_select = "core clock",
+ receive_pcs6.recovered_clk_mux_select = "recovered clock",
+ receive_pcs6.run_length = 40,
+ receive_pcs6.run_length_enable = "true",
+ receive_pcs6.rx_detect_bypass = "false",
+ receive_pcs6.rxstatus_error_report_mode = 0,
+ receive_pcs6.self_test_mode = "incremental",
+ receive_pcs6.use_alignment_state_machine = "true",
+ receive_pcs6.use_deserializer_double_data_mode = "false",
+ receive_pcs6.use_deskew_fifo = "false",
+ receive_pcs6.use_double_data_mode = "false",
+ receive_pcs6.use_parallel_loopback = "false",
+ receive_pcs6.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs6.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pcs receive_pcs7
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[7]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs7_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[7]),
+ .coreclkout(wire_receive_pcs7_coreclkout),
+ .ctrldetect(wire_receive_pcs7_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[159:140]),
+ .dataout(wire_receive_pcs7_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[7]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[3199:2800]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[23:21]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[7]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs7_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs7_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs7_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs7_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[15:14]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[15:14]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[15:14]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[15:14]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs7_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs7_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs7_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[7]),
+ .phfifordenableout(wire_receive_pcs7_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[7]),
+ .phfiforesetout(wire_receive_pcs7_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[7]),
+ .phfifowrdisableout(wire_receive_pcs7_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[23:21]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[23:21]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[23:21]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[23:21]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[7]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs7_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs7_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs7_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[15:14]),
+ .pipepowerstate(tx_pipepowerstateout[31:28]),
+ .pipestatetransdoneout(wire_receive_pcs7_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs7_pipestatus),
+ .powerdn(powerdn[15:14]),
+ .prbscidenable(rx_prbscidenable[7]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(wire_receive_pcs7_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[7]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs7_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[7]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[7]),
+ .rxfound(rx_pcs_rxfound_wire[15:14]),
+ .signaldetected(rx_signaldetect_wire[7]),
+ .syncstatus(wire_receive_pcs7_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs7.align_pattern = "0101111100",
+ receive_pcs7.align_pattern_length = 10,
+ receive_pcs7.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs7.allow_align_polarity_inversion = "false",
+ receive_pcs7.allow_pipe_polarity_inversion = "true",
+ receive_pcs7.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs7.auto_spd_phystatus_notify_count = 14,
+ receive_pcs7.auto_spd_self_switch_enable = "false",
+ receive_pcs7.bit_slip_enable = "false",
+ receive_pcs7.byte_order_mode = "none",
+ receive_pcs7.byte_order_pad_pattern = "0",
+ receive_pcs7.byte_order_pattern = "0",
+ receive_pcs7.byte_order_pld_ctrl_enable = "false",
+ receive_pcs7.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs7.cdrctrl_enable = "true",
+ receive_pcs7.cdrctrl_mask_cycle = 800,
+ receive_pcs7.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs7.cdrctrl_rxvalid_mask = "true",
+ receive_pcs7.channel_bonding = "x8",
+ receive_pcs7.channel_number = ((starting_channel_number + 7) % 4),
+ receive_pcs7.channel_width = 8,
+ receive_pcs7.clk1_mux_select = "recovered clock",
+ receive_pcs7.clk2_mux_select = "digital reference clock",
+ receive_pcs7.core_clock_0ppm = "false",
+ receive_pcs7.datapath_low_latency_mode = "false",
+ receive_pcs7.datapath_protocol = "pipe",
+ receive_pcs7.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs7.dec_8b_10b_mode = "normal",
+ receive_pcs7.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs7.deskew_pattern = "0",
+ receive_pcs7.disable_auto_idle_insertion = "false",
+ receive_pcs7.disable_running_disp_in_word_align = "false",
+ receive_pcs7.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs7.dprio_config_mode = 6'h00,
+ receive_pcs7.elec_idle_infer_enable = "false",
+ receive_pcs7.elec_idle_num_com_detect = 3,
+ receive_pcs7.enable_bit_reversal = "false",
+ receive_pcs7.enable_deep_align = "false",
+ receive_pcs7.enable_deep_align_byte_swap = "false",
+ receive_pcs7.enable_self_test_mode = "false",
+ receive_pcs7.enable_true_complement_match_in_word_align = "false",
+ receive_pcs7.force_signal_detect_dig = "true",
+ receive_pcs7.hip_enable = "false",
+ receive_pcs7.infiniband_invalid_code = 0,
+ receive_pcs7.insert_pad_on_underflow = "false",
+ receive_pcs7.logical_channel_address = (starting_channel_number + 7),
+ receive_pcs7.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs7.num_align_cons_good_data = 16,
+ receive_pcs7.num_align_cons_pat = 4,
+ receive_pcs7.num_align_loss_sync_error = 17,
+ receive_pcs7.ph_fifo_low_latency_enable = "true",
+ receive_pcs7.ph_fifo_reg_mode = "false",
+ receive_pcs7.ph_fifo_xn_mapping0 = "none",
+ receive_pcs7.ph_fifo_xn_mapping1 = "up",
+ receive_pcs7.ph_fifo_xn_mapping2 = "none",
+ receive_pcs7.ph_fifo_xn_select = 1,
+ receive_pcs7.pipe_auto_speed_nego_enable = "false",
+ receive_pcs7.pipe_freq_scale_mode = "Frequency",
+ receive_pcs7.pma_done_count = 250000,
+ receive_pcs7.protocol_hint = "pcie",
+ receive_pcs7.rate_match_almost_empty_threshold = 11,
+ receive_pcs7.rate_match_almost_full_threshold = 13,
+ receive_pcs7.rate_match_back_to_back = "false",
+ receive_pcs7.rate_match_delete_threshold = 13,
+ receive_pcs7.rate_match_empty_threshold = 5,
+ receive_pcs7.rate_match_fifo_mode = "true",
+ receive_pcs7.rate_match_full_threshold = 20,
+ receive_pcs7.rate_match_insert_threshold = 11,
+ receive_pcs7.rate_match_ordered_set_based = "false",
+ receive_pcs7.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs7.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs7.rate_match_pattern_size = 20,
+ receive_pcs7.rate_match_reset_enable = "false",
+ receive_pcs7.rate_match_skip_set_based = "true",
+ receive_pcs7.rate_match_start_threshold = 7,
+ receive_pcs7.rd_clk_mux_select = "core clock",
+ receive_pcs7.recovered_clk_mux_select = "recovered clock",
+ receive_pcs7.run_length = 40,
+ receive_pcs7.run_length_enable = "true",
+ receive_pcs7.rx_detect_bypass = "false",
+ receive_pcs7.rxstatus_error_report_mode = 0,
+ receive_pcs7.self_test_mode = "incremental",
+ receive_pcs7.use_alignment_state_machine = "true",
+ receive_pcs7.use_deserializer_double_data_mode = "false",
+ receive_pcs7.use_deskew_fifo = "false",
+ receive_pcs7.use_double_data_mode = "false",
+ receive_pcs7.use_parallel_loopback = "false",
+ receive_pcs7.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs7.lpm_type = "arriaii_hssi_rx_pcs";
+ arriaii_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h00,
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 1,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 0,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 4,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h00,
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eqa_ctrl = 0,
+ receive_pma1.eqb_ctrl = 0,
+ receive_pma1.eqc_ctrl = 0,
+ receive_pma1.eqd_ctrl = 1,
+ receive_pma1.eqv_ctrl = 0,
+ receive_pma1.force_signal_detect = "true",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 0,
+ receive_pma1.protocol_hint = "pcie",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma1.signal_detect_loss_threshold = 4,
+ receive_pma1.termination = "OCT 100 Ohms",
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma2_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.allow_serial_loopback = "false",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = "0.82V",
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h00,
+ receive_pma2.eq_dc_gain = 3,
+ receive_pma2.eqa_ctrl = 0,
+ receive_pma2.eqb_ctrl = 0,
+ receive_pma2.eqc_ctrl = 0,
+ receive_pma2.eqd_ctrl = 1,
+ receive_pma2.eqv_ctrl = 0,
+ receive_pma2.force_signal_detect = "true",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 0,
+ receive_pma2.protocol_hint = "pcie",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma2.signal_detect_loss_threshold = 4,
+ receive_pma2.termination = "OCT 100 Ohms",
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma3_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.allow_serial_loopback = "false",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = "0.82V",
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h00,
+ receive_pma3.eq_dc_gain = 3,
+ receive_pma3.eqa_ctrl = 0,
+ receive_pma3.eqb_ctrl = 0,
+ receive_pma3.eqc_ctrl = 0,
+ receive_pma3.eqd_ctrl = 1,
+ receive_pma3.eqv_ctrl = 0,
+ receive_pma3.force_signal_detect = "true",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 0,
+ receive_pma3.protocol_hint = "pcie",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma3.signal_detect_loss_threshold = 4,
+ receive_pma3.termination = "OCT 100 Ohms",
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma4
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma4_clockout),
+ .datain(rx_datain[4]),
+ .dataout(wire_receive_pma4_dataout),
+ .deserclock(rx_deserclock_in[19:16]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[2099:1800]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[4]),
+ .locktoref(rx_locktorefclk_wire[4]),
+ .locktorefout(wire_receive_pma4_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[4]),
+ .powerdn(cent_unit_rxibpowerdn[6]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[4]),
+ .recoverdatain(pll_ch_dataout_wire[9:8]),
+ .recoverdataout(wire_receive_pma4_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[6]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma4_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma4.allow_serial_loopback = "false",
+ receive_pma4.channel_number = ((starting_channel_number + 4) % 4),
+ receive_pma4.channel_type = "auto",
+ receive_pma4.common_mode = "0.82V",
+ receive_pma4.deserialization_factor = 10,
+ receive_pma4.dprio_config_mode = 6'h00,
+ receive_pma4.eq_dc_gain = 3,
+ receive_pma4.eqa_ctrl = 0,
+ receive_pma4.eqb_ctrl = 0,
+ receive_pma4.eqc_ctrl = 0,
+ receive_pma4.eqd_ctrl = 1,
+ receive_pma4.eqv_ctrl = 0,
+ receive_pma4.force_signal_detect = "true",
+ receive_pma4.logical_channel_address = (starting_channel_number + 4),
+ receive_pma4.low_speed_test_select = 0,
+ receive_pma4.offset_cancellation = 0,
+ receive_pma4.protocol_hint = "pcie",
+ receive_pma4.send_direct_reverse_serial_loopback = "None",
+ receive_pma4.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma4.signal_detect_loss_threshold = 4,
+ receive_pma4.termination = "OCT 100 Ohms",
+ receive_pma4.use_deser_double_data_width = "false",
+ receive_pma4.use_pma_direct = "false",
+ receive_pma4.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma5
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma5_clockout),
+ .datain(rx_datain[5]),
+ .dataout(wire_receive_pma5_dataout),
+ .deserclock(rx_deserclock_in[23:20]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[2399:2100]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[5]),
+ .locktoref(rx_locktorefclk_wire[5]),
+ .locktorefout(wire_receive_pma5_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[5]),
+ .powerdn(cent_unit_rxibpowerdn[7]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[5]),
+ .recoverdatain(pll_ch_dataout_wire[11:10]),
+ .recoverdataout(wire_receive_pma5_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[7]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma5_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma5.allow_serial_loopback = "false",
+ receive_pma5.channel_number = ((starting_channel_number + 5) % 4),
+ receive_pma5.channel_type = "auto",
+ receive_pma5.common_mode = "0.82V",
+ receive_pma5.deserialization_factor = 10,
+ receive_pma5.dprio_config_mode = 6'h00,
+ receive_pma5.eq_dc_gain = 3,
+ receive_pma5.eqa_ctrl = 0,
+ receive_pma5.eqb_ctrl = 0,
+ receive_pma5.eqc_ctrl = 0,
+ receive_pma5.eqd_ctrl = 1,
+ receive_pma5.eqv_ctrl = 0,
+ receive_pma5.force_signal_detect = "true",
+ receive_pma5.logical_channel_address = (starting_channel_number + 5),
+ receive_pma5.low_speed_test_select = 0,
+ receive_pma5.offset_cancellation = 0,
+ receive_pma5.protocol_hint = "pcie",
+ receive_pma5.send_direct_reverse_serial_loopback = "None",
+ receive_pma5.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma5.signal_detect_loss_threshold = 4,
+ receive_pma5.termination = "OCT 100 Ohms",
+ receive_pma5.use_deser_double_data_width = "false",
+ receive_pma5.use_pma_direct = "false",
+ receive_pma5.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma6
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma6_clockout),
+ .datain(rx_datain[6]),
+ .dataout(wire_receive_pma6_dataout),
+ .deserclock(rx_deserclock_in[27:24]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[2699:2400]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[6]),
+ .locktoref(rx_locktorefclk_wire[6]),
+ .locktorefout(wire_receive_pma6_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[6]),
+ .powerdn(cent_unit_rxibpowerdn[8]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[6]),
+ .recoverdatain(pll_ch_dataout_wire[13:12]),
+ .recoverdataout(wire_receive_pma6_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[8]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma6_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma6.allow_serial_loopback = "false",
+ receive_pma6.channel_number = ((starting_channel_number + 6) % 4),
+ receive_pma6.channel_type = "auto",
+ receive_pma6.common_mode = "0.82V",
+ receive_pma6.deserialization_factor = 10,
+ receive_pma6.dprio_config_mode = 6'h00,
+ receive_pma6.eq_dc_gain = 3,
+ receive_pma6.eqa_ctrl = 0,
+ receive_pma6.eqb_ctrl = 0,
+ receive_pma6.eqc_ctrl = 0,
+ receive_pma6.eqd_ctrl = 1,
+ receive_pma6.eqv_ctrl = 0,
+ receive_pma6.force_signal_detect = "true",
+ receive_pma6.logical_channel_address = (starting_channel_number + 6),
+ receive_pma6.low_speed_test_select = 0,
+ receive_pma6.offset_cancellation = 0,
+ receive_pma6.protocol_hint = "pcie",
+ receive_pma6.send_direct_reverse_serial_loopback = "None",
+ receive_pma6.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma6.signal_detect_loss_threshold = 4,
+ receive_pma6.termination = "OCT 100 Ohms",
+ receive_pma6.use_deser_double_data_width = "false",
+ receive_pma6.use_pma_direct = "false",
+ receive_pma6.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_rx_pma receive_pma7
+ (
+ .adaptdone(),
+ .analogtestbus(),
+ .clockout(wire_receive_pma7_clockout),
+ .datain(rx_datain[7]),
+ .dataout(wire_receive_pma7_dataout),
+ .deserclock(rx_deserclock_in[31:28]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[2999:2700]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[7]),
+ .locktoref(rx_locktorefclk_wire[7]),
+ .locktorefout(wire_receive_pma7_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[7]),
+ .powerdn(cent_unit_rxibpowerdn[9]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[7]),
+ .recoverdatain(pll_ch_dataout_wire[15:14]),
+ .recoverdataout(wire_receive_pma7_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[9]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma7_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma7.allow_serial_loopback = "false",
+ receive_pma7.channel_number = ((starting_channel_number + 7) % 4),
+ receive_pma7.channel_type = "auto",
+ receive_pma7.common_mode = "0.82V",
+ receive_pma7.deserialization_factor = 10,
+ receive_pma7.dprio_config_mode = 6'h00,
+ receive_pma7.eq_dc_gain = 3,
+ receive_pma7.eqa_ctrl = 0,
+ receive_pma7.eqb_ctrl = 0,
+ receive_pma7.eqc_ctrl = 0,
+ receive_pma7.eqd_ctrl = 1,
+ receive_pma7.eqv_ctrl = 0,
+ receive_pma7.force_signal_detect = "true",
+ receive_pma7.logical_channel_address = (starting_channel_number + 7),
+ receive_pma7.low_speed_test_select = 0,
+ receive_pma7.offset_cancellation = 0,
+ receive_pma7.protocol_hint = "pcie",
+ receive_pma7.send_direct_reverse_serial_loopback = "None",
+ receive_pma7.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma7.signal_detect_loss_threshold = 4,
+ receive_pma7.termination = "OCT 100 Ohms",
+ receive_pma7.use_deser_double_data_width = "false",
+ receive_pma7.use_pma_direct = "false",
+ receive_pma7.lpm_type = "arriaii_hssi_rx_pma";
+ arriaii_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
+ .datain({{32{1'b0}}, tx_datain_wire[7:0]}),
+ .datainfull(tx_datainfull[43:0]),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(wire_transmit_pcs0_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs0_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs0_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs0_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[1:0]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[1:0]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[1:0]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[1:0]),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.channel_bonding = "x8",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 8,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h00,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "false",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(wire_transmit_pcs1_clkout),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[1]}),
+ .datain({{32{1'b0}}, tx_datain_wire[15:8]}),
+ .datainfull(tx_datainfull[87:44]),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[1]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[1]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(wire_transmit_pcs1_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs1_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs1_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs1_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[3:2]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[3:2]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[3:2]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[3:2]),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[1]),
+ .pipetxdeemph(tx_pipedeemph[1]),
+ .pipetxmargin(tx_pipemargin[5:3]),
+ .pipetxswing(tx_pipeswing[1]),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.auto_spd_self_switch_enable = "false",
+ transmit_pcs1.channel_bonding = "x8",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 8,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h00,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "false",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(wire_transmit_pcs2_clkout),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[2]}),
+ .datain({{32{1'b0}}, tx_datain_wire[23:16]}),
+ .datainfull(tx_datainfull[131:88]),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(tx_detectrxloop[2]),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[2]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[2]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(wire_transmit_pcs2_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs2_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs2_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs2_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[5:4]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[5:4]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[5:4]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[5:4]),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[2]),
+ .pipetxdeemph(tx_pipedeemph[2]),
+ .pipetxmargin(tx_pipemargin[8:6]),
+ .pipetxswing(tx_pipeswing[2]),
+ .powerdn(powerdn[5:4]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[59:40]),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "false",
+ transmit_pcs2.auto_spd_self_switch_enable = "false",
+ transmit_pcs2.channel_bonding = "x8",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 8,
+ transmit_pcs2.core_clock_0ppm = "false",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "pipe",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "new",
+ transmit_pcs2.dprio_config_mode = 6'h00,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "true",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "pcie",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "false",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(wire_transmit_pcs3_clkout),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[3]}),
+ .datain({{32{1'b0}}, tx_datain_wire[31:24]}),
+ .datainfull(tx_datainfull[175:132]),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(tx_detectrxloop[3]),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[3]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[3]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[3]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(wire_transmit_pcs3_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs3_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs3_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs3_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[7:6]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[7:6]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[7:6]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[7:6]),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[3]),
+ .pipetxdeemph(tx_pipedeemph[3]),
+ .pipetxmargin(tx_pipemargin[11:9]),
+ .pipetxswing(tx_pipeswing[3]),
+ .powerdn(powerdn[7:6]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[79:60]),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "false",
+ transmit_pcs3.auto_spd_self_switch_enable = "false",
+ transmit_pcs3.channel_bonding = "x8",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 8,
+ transmit_pcs3.core_clock_0ppm = "false",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "pipe",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "new",
+ transmit_pcs3.dprio_config_mode = 6'h00,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "true",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "pcie",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "false",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs4
+ (
+ .clkout(wire_transmit_pcs4_clkout),
+ .coreclk(tx_coreclk_in[4]),
+ .coreclkout(wire_transmit_pcs4_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[4]}),
+ .datain({{32{1'b0}}, tx_datain_wire[39:32]}),
+ .datainfull(tx_datainfull[219:176]),
+ .dataout(wire_transmit_pcs4_dataout),
+ .detectrxloop(tx_detectrxloop[4]),
+ .digitalreset(tx_digitalreset_out[4]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[4]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[749:600]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[4]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[4]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[4]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[4]),
+ .iqpphfifobyteselout(wire_transmit_pcs4_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs4_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs4_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs4_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[9:8]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[9:8]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[9:8]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[9:8]),
+ .localrefclk(tx_localrefclk[4]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[4]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[4]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs4_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[4]),
+ .phfiforesetout(wire_transmit_pcs4_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs4_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[14:12]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[14:12]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[14:12]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[14:12]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs4_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs4_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[4]),
+ .pipetxdeemph(tx_pipedeemph[4]),
+ .pipetxmargin(tx_pipemargin[14:12]),
+ .pipetxswing(tx_pipeswing[4]),
+ .powerdn(powerdn[9:8]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[99:80]),
+ .txdetectrx(wire_transmit_pcs4_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[4]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[39:32]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs4.allow_polarity_inversion = "false",
+ transmit_pcs4.auto_spd_self_switch_enable = "false",
+ transmit_pcs4.channel_bonding = "x8",
+ transmit_pcs4.channel_number = ((starting_channel_number + 4) % 4),
+ transmit_pcs4.channel_width = 8,
+ transmit_pcs4.core_clock_0ppm = "false",
+ transmit_pcs4.datapath_low_latency_mode = "false",
+ transmit_pcs4.datapath_protocol = "pipe",
+ transmit_pcs4.disable_ph_low_latency_mode = "false",
+ transmit_pcs4.disparity_mode = "new",
+ transmit_pcs4.dprio_config_mode = 6'h00,
+ transmit_pcs4.elec_idle_delay = 6,
+ transmit_pcs4.enable_bit_reversal = "false",
+ transmit_pcs4.enable_idle_selection = "false",
+ transmit_pcs4.enable_reverse_parallel_loopback = "true",
+ transmit_pcs4.enable_self_test_mode = "false",
+ transmit_pcs4.enable_symbol_swap = "false",
+ transmit_pcs4.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs4.enc_8b_10b_mode = "normal",
+ transmit_pcs4.force_echar = "false",
+ transmit_pcs4.force_kchar = "false",
+ transmit_pcs4.hip_enable = "false",
+ transmit_pcs4.logical_channel_address = (starting_channel_number + 4),
+ transmit_pcs4.ph_fifo_reg_mode = "false",
+ transmit_pcs4.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs4.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs4.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs4.ph_fifo_xn_select = 1,
+ transmit_pcs4.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs4.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs4.prbs_cid_pattern = "false",
+ transmit_pcs4.protocol_hint = "pcie",
+ transmit_pcs4.refclk_select = "cmu_clock_divider",
+ transmit_pcs4.self_test_mode = "incremental",
+ transmit_pcs4.use_double_data_mode = "false",
+ transmit_pcs4.use_serializer_double_data_mode = "false",
+ transmit_pcs4.wr_clk_mux_select = "core_clk",
+ transmit_pcs4.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs5
+ (
+ .clkout(wire_transmit_pcs5_clkout),
+ .coreclk(tx_coreclk_in[5]),
+ .coreclkout(wire_transmit_pcs5_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[5]}),
+ .datain({{32{1'b0}}, tx_datain_wire[47:40]}),
+ .datainfull(tx_datainfull[263:220]),
+ .dataout(wire_transmit_pcs5_dataout),
+ .detectrxloop(tx_detectrxloop[5]),
+ .digitalreset(tx_digitalreset_out[5]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[5]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[899:750]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[5]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[5]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[5]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[5]),
+ .iqpphfifobyteselout(wire_transmit_pcs5_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs5_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs5_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs5_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[11:10]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[11:10]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[11:10]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[11:10]),
+ .localrefclk(tx_localrefclk[5]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[5]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[5]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs5_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[5]),
+ .phfiforesetout(wire_transmit_pcs5_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs5_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[17:15]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[17:15]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[17:15]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[17:15]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs5_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs5_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[5]),
+ .pipetxdeemph(tx_pipedeemph[5]),
+ .pipetxmargin(tx_pipemargin[17:15]),
+ .pipetxswing(tx_pipeswing[5]),
+ .powerdn(powerdn[11:10]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[119:100]),
+ .txdetectrx(wire_transmit_pcs5_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[5]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[47:40]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs5.allow_polarity_inversion = "false",
+ transmit_pcs5.auto_spd_self_switch_enable = "false",
+ transmit_pcs5.channel_bonding = "x8",
+ transmit_pcs5.channel_number = ((starting_channel_number + 5) % 4),
+ transmit_pcs5.channel_width = 8,
+ transmit_pcs5.core_clock_0ppm = "false",
+ transmit_pcs5.datapath_low_latency_mode = "false",
+ transmit_pcs5.datapath_protocol = "pipe",
+ transmit_pcs5.disable_ph_low_latency_mode = "false",
+ transmit_pcs5.disparity_mode = "new",
+ transmit_pcs5.dprio_config_mode = 6'h00,
+ transmit_pcs5.elec_idle_delay = 6,
+ transmit_pcs5.enable_bit_reversal = "false",
+ transmit_pcs5.enable_idle_selection = "false",
+ transmit_pcs5.enable_reverse_parallel_loopback = "true",
+ transmit_pcs5.enable_self_test_mode = "false",
+ transmit_pcs5.enable_symbol_swap = "false",
+ transmit_pcs5.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs5.enc_8b_10b_mode = "normal",
+ transmit_pcs5.force_echar = "false",
+ transmit_pcs5.force_kchar = "false",
+ transmit_pcs5.hip_enable = "false",
+ transmit_pcs5.logical_channel_address = (starting_channel_number + 5),
+ transmit_pcs5.ph_fifo_reg_mode = "false",
+ transmit_pcs5.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs5.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs5.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs5.ph_fifo_xn_select = 1,
+ transmit_pcs5.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs5.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs5.prbs_cid_pattern = "false",
+ transmit_pcs5.protocol_hint = "pcie",
+ transmit_pcs5.refclk_select = "cmu_clock_divider",
+ transmit_pcs5.self_test_mode = "incremental",
+ transmit_pcs5.use_double_data_mode = "false",
+ transmit_pcs5.use_serializer_double_data_mode = "false",
+ transmit_pcs5.wr_clk_mux_select = "core_clk",
+ transmit_pcs5.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs6
+ (
+ .clkout(wire_transmit_pcs6_clkout),
+ .coreclk(tx_coreclk_in[6]),
+ .coreclkout(wire_transmit_pcs6_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[6]}),
+ .datain({{32{1'b0}}, tx_datain_wire[55:48]}),
+ .datainfull(tx_datainfull[307:264]),
+ .dataout(wire_transmit_pcs6_dataout),
+ .detectrxloop(tx_detectrxloop[6]),
+ .digitalreset(tx_digitalreset_out[6]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[6]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[1049:900]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[6]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[6]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[6]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[6]),
+ .iqpphfifobyteselout(wire_transmit_pcs6_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs6_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs6_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs6_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[13:12]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[13:12]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[13:12]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[13:12]),
+ .localrefclk(tx_localrefclk[6]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[6]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[6]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs6_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[6]),
+ .phfiforesetout(wire_transmit_pcs6_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs6_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[20:18]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[20:18]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[20:18]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[20:18]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs6_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs6_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[6]),
+ .pipetxdeemph(tx_pipedeemph[6]),
+ .pipetxmargin(tx_pipemargin[20:18]),
+ .pipetxswing(tx_pipeswing[6]),
+ .powerdn(powerdn[13:12]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[139:120]),
+ .txdetectrx(wire_transmit_pcs6_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[6]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[55:48]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs6.allow_polarity_inversion = "false",
+ transmit_pcs6.auto_spd_self_switch_enable = "false",
+ transmit_pcs6.channel_bonding = "x8",
+ transmit_pcs6.channel_number = ((starting_channel_number + 6) % 4),
+ transmit_pcs6.channel_width = 8,
+ transmit_pcs6.core_clock_0ppm = "false",
+ transmit_pcs6.datapath_low_latency_mode = "false",
+ transmit_pcs6.datapath_protocol = "pipe",
+ transmit_pcs6.disable_ph_low_latency_mode = "false",
+ transmit_pcs6.disparity_mode = "new",
+ transmit_pcs6.dprio_config_mode = 6'h00,
+ transmit_pcs6.elec_idle_delay = 6,
+ transmit_pcs6.enable_bit_reversal = "false",
+ transmit_pcs6.enable_idle_selection = "false",
+ transmit_pcs6.enable_reverse_parallel_loopback = "true",
+ transmit_pcs6.enable_self_test_mode = "false",
+ transmit_pcs6.enable_symbol_swap = "false",
+ transmit_pcs6.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs6.enc_8b_10b_mode = "normal",
+ transmit_pcs6.force_echar = "false",
+ transmit_pcs6.force_kchar = "false",
+ transmit_pcs6.hip_enable = "false",
+ transmit_pcs6.logical_channel_address = (starting_channel_number + 6),
+ transmit_pcs6.ph_fifo_reg_mode = "false",
+ transmit_pcs6.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs6.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs6.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs6.ph_fifo_xn_select = 1,
+ transmit_pcs6.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs6.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs6.prbs_cid_pattern = "false",
+ transmit_pcs6.protocol_hint = "pcie",
+ transmit_pcs6.refclk_select = "cmu_clock_divider",
+ transmit_pcs6.self_test_mode = "incremental",
+ transmit_pcs6.use_double_data_mode = "false",
+ transmit_pcs6.use_serializer_double_data_mode = "false",
+ transmit_pcs6.wr_clk_mux_select = "core_clk",
+ transmit_pcs6.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pcs transmit_pcs7
+ (
+ .clkout(wire_transmit_pcs7_clkout),
+ .coreclk(tx_coreclk_in[7]),
+ .coreclkout(wire_transmit_pcs7_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[7]}),
+ .datain({{32{1'b0}}, tx_datain_wire[63:56]}),
+ .datainfull(tx_datainfull[351:308]),
+ .dataout(wire_transmit_pcs7_dataout),
+ .detectrxloop(tx_detectrxloop[7]),
+ .digitalreset(tx_digitalreset_out[7]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[7]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[1199:1050]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[7]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[7]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[7]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[7]),
+ .iqpphfifobyteselout(wire_transmit_pcs7_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs7_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs7_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs7_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[15:14]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[15:14]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[15:14]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[15:14]),
+ .localrefclk(tx_localrefclk[7]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[7]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[7]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs7_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[7]),
+ .phfiforesetout(wire_transmit_pcs7_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs7_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[23:21]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[23:21]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[23:21]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[23:21]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs7_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs7_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[7]),
+ .pipetxdeemph(tx_pipedeemph[7]),
+ .pipetxmargin(tx_pipemargin[23:21]),
+ .pipetxswing(tx_pipeswing[7]),
+ .powerdn(powerdn[15:14]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[159:140]),
+ .txdetectrx(wire_transmit_pcs7_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[7]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[63:56]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs7.allow_polarity_inversion = "false",
+ transmit_pcs7.auto_spd_self_switch_enable = "false",
+ transmit_pcs7.channel_bonding = "x8",
+ transmit_pcs7.channel_number = ((starting_channel_number + 7) % 4),
+ transmit_pcs7.channel_width = 8,
+ transmit_pcs7.core_clock_0ppm = "false",
+ transmit_pcs7.datapath_low_latency_mode = "false",
+ transmit_pcs7.datapath_protocol = "pipe",
+ transmit_pcs7.disable_ph_low_latency_mode = "false",
+ transmit_pcs7.disparity_mode = "new",
+ transmit_pcs7.dprio_config_mode = 6'h00,
+ transmit_pcs7.elec_idle_delay = 6,
+ transmit_pcs7.enable_bit_reversal = "false",
+ transmit_pcs7.enable_idle_selection = "false",
+ transmit_pcs7.enable_reverse_parallel_loopback = "true",
+ transmit_pcs7.enable_self_test_mode = "false",
+ transmit_pcs7.enable_symbol_swap = "false",
+ transmit_pcs7.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs7.enc_8b_10b_mode = "normal",
+ transmit_pcs7.force_echar = "false",
+ transmit_pcs7.force_kchar = "false",
+ transmit_pcs7.hip_enable = "false",
+ transmit_pcs7.logical_channel_address = (starting_channel_number + 7),
+ transmit_pcs7.ph_fifo_reg_mode = "false",
+ transmit_pcs7.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs7.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs7.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs7.ph_fifo_xn_select = 1,
+ transmit_pcs7.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs7.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs7.prbs_cid_pattern = "false",
+ transmit_pcs7.protocol_hint = "pcie",
+ transmit_pcs7.refclk_select = "cmu_clock_divider",
+ transmit_pcs7.self_test_mode = "incremental",
+ transmit_pcs7.use_double_data_mode = "false",
+ transmit_pcs7.use_serializer_double_data_mode = "false",
+ transmit_pcs7.wr_clk_mux_select = "core_clk",
+ transmit_pcs7.lpm_type = "arriaii_hssi_tx_pcs";
+ arriaii_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "1.5V",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h00,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "1.5V",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h00,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.preemp_pretap = 0,
+ transmit_pma1.preemp_pretap_inv = "false",
+ transmit_pma1.preemp_tap_1 = 0,
+ transmit_pma1.preemp_tap_2 = 0,
+ transmit_pma1.preemp_tap_2_inv = "false",
+ transmit_pma1.protocol_hint = "pcie",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "off",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = 4,
+ transmit_pma1.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma2_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[2])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "1.5V",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h00,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.preemp_pretap = 0,
+ transmit_pma2.preemp_pretap_inv = "false",
+ transmit_pma2.preemp_tap_1 = 0,
+ transmit_pma2.preemp_tap_2 = 0,
+ transmit_pma2.preemp_tap_2_inv = "false",
+ transmit_pma2.protocol_hint = "pcie",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "off",
+ transmit_pma2.termination = "OCT 100 Ohms",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = 4,
+ transmit_pma2.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma3_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[3])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "1.5V",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h00,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.preemp_pretap = 0,
+ transmit_pma3.preemp_pretap_inv = "false",
+ transmit_pma3.preemp_tap_1 = 0,
+ transmit_pma3.preemp_tap_2 = 0,
+ transmit_pma3.preemp_tap_2_inv = "false",
+ transmit_pma3.protocol_hint = "pcie",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "off",
+ transmit_pma3.termination = "OCT 100 Ohms",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = 4,
+ transmit_pma3.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma4
+ (
+ .clockout(wire_transmit_pma4_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[99:80]}),
+ .dataout(wire_transmit_pma4_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[4]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[2099:1800]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[4]),
+ .powerdn(cent_unit_txobpowerdn[6]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(cmu_analogrefclkout[1:0]),
+ .refclk2inpulse(cmu_analogrefclkpulse[0]),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[4]),
+ .rxdetectvalidout(wire_transmit_pma4_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma4_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[6])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma4.analog_power = "1.5V",
+ transmit_pma4.channel_number = ((starting_channel_number + 4) % 4),
+ transmit_pma4.channel_type = "auto",
+ transmit_pma4.clkin_select = 2,
+ transmit_pma4.clkmux_delay = "false",
+ transmit_pma4.common_mode = "0.65V",
+ transmit_pma4.dprio_config_mode = 6'h00,
+ transmit_pma4.enable_reverse_serial_loopback = "false",
+ transmit_pma4.logical_channel_address = (starting_channel_number + 4),
+ transmit_pma4.low_speed_test_select = 0,
+ transmit_pma4.preemp_pretap = 0,
+ transmit_pma4.preemp_pretap_inv = "false",
+ transmit_pma4.preemp_tap_1 = 0,
+ transmit_pma4.preemp_tap_2 = 0,
+ transmit_pma4.preemp_tap_2_inv = "false",
+ transmit_pma4.protocol_hint = "pcie",
+ transmit_pma4.rx_detect = 0,
+ transmit_pma4.serialization_factor = 10,
+ transmit_pma4.slew_rate = "off",
+ transmit_pma4.termination = "OCT 100 Ohms",
+ transmit_pma4.use_pma_direct = "false",
+ transmit_pma4.use_ser_double_data_mode = "false",
+ transmit_pma4.vod_selection = 4,
+ transmit_pma4.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma5
+ (
+ .clockout(wire_transmit_pma5_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[119:100]}),
+ .dataout(wire_transmit_pma5_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[5]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[2399:2100]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[5]),
+ .powerdn(cent_unit_txobpowerdn[7]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(cmu_analogrefclkout[1:0]),
+ .refclk2inpulse(cmu_analogrefclkpulse[0]),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[5]),
+ .rxdetectvalidout(wire_transmit_pma5_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma5_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[7])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma5.analog_power = "1.5V",
+ transmit_pma5.channel_number = ((starting_channel_number + 5) % 4),
+ transmit_pma5.channel_type = "auto",
+ transmit_pma5.clkin_select = 2,
+ transmit_pma5.clkmux_delay = "false",
+ transmit_pma5.common_mode = "0.65V",
+ transmit_pma5.dprio_config_mode = 6'h00,
+ transmit_pma5.enable_reverse_serial_loopback = "false",
+ transmit_pma5.logical_channel_address = (starting_channel_number + 5),
+ transmit_pma5.low_speed_test_select = 0,
+ transmit_pma5.preemp_pretap = 0,
+ transmit_pma5.preemp_pretap_inv = "false",
+ transmit_pma5.preemp_tap_1 = 0,
+ transmit_pma5.preemp_tap_2 = 0,
+ transmit_pma5.preemp_tap_2_inv = "false",
+ transmit_pma5.protocol_hint = "pcie",
+ transmit_pma5.rx_detect = 0,
+ transmit_pma5.serialization_factor = 10,
+ transmit_pma5.slew_rate = "off",
+ transmit_pma5.termination = "OCT 100 Ohms",
+ transmit_pma5.use_pma_direct = "false",
+ transmit_pma5.use_ser_double_data_mode = "false",
+ transmit_pma5.vod_selection = 4,
+ transmit_pma5.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma6
+ (
+ .clockout(wire_transmit_pma6_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[139:120]}),
+ .dataout(wire_transmit_pma6_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[6]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[2699:2400]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[6]),
+ .powerdn(cent_unit_txobpowerdn[8]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(cmu_analogrefclkout[1:0]),
+ .refclk2inpulse(cmu_analogrefclkpulse[0]),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[6]),
+ .rxdetectvalidout(wire_transmit_pma6_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma6_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[8])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma6.analog_power = "1.5V",
+ transmit_pma6.channel_number = ((starting_channel_number + 6) % 4),
+ transmit_pma6.channel_type = "auto",
+ transmit_pma6.clkin_select = 2,
+ transmit_pma6.clkmux_delay = "false",
+ transmit_pma6.common_mode = "0.65V",
+ transmit_pma6.dprio_config_mode = 6'h00,
+ transmit_pma6.enable_reverse_serial_loopback = "false",
+ transmit_pma6.logical_channel_address = (starting_channel_number + 6),
+ transmit_pma6.low_speed_test_select = 0,
+ transmit_pma6.preemp_pretap = 0,
+ transmit_pma6.preemp_pretap_inv = "false",
+ transmit_pma6.preemp_tap_1 = 0,
+ transmit_pma6.preemp_tap_2 = 0,
+ transmit_pma6.preemp_tap_2_inv = "false",
+ transmit_pma6.protocol_hint = "pcie",
+ transmit_pma6.rx_detect = 0,
+ transmit_pma6.serialization_factor = 10,
+ transmit_pma6.slew_rate = "off",
+ transmit_pma6.termination = "OCT 100 Ohms",
+ transmit_pma6.use_pma_direct = "false",
+ transmit_pma6.use_ser_double_data_mode = "false",
+ transmit_pma6.vod_selection = 4,
+ transmit_pma6.lpm_type = "arriaii_hssi_tx_pma";
+ arriaii_hssi_tx_pma transmit_pma7
+ (
+ .clockout(wire_transmit_pma7_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[159:140]}),
+ .dataout(wire_transmit_pma7_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[7]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[2999:2700]),
+ .dprioout(),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[7]),
+ .powerdn(cent_unit_txobpowerdn[9]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(cmu_analogrefclkout[1:0]),
+ .refclk2inpulse(cmu_analogrefclkpulse[0]),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[7]),
+ .rxdetectvalidout(wire_transmit_pma7_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma7_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[9])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma7.analog_power = "1.5V",
+ transmit_pma7.channel_number = ((starting_channel_number + 7) % 4),
+ transmit_pma7.channel_type = "auto",
+ transmit_pma7.clkin_select = 2,
+ transmit_pma7.clkmux_delay = "false",
+ transmit_pma7.common_mode = "0.65V",
+ transmit_pma7.dprio_config_mode = 6'h00,
+ transmit_pma7.enable_reverse_serial_loopback = "false",
+ transmit_pma7.logical_channel_address = (starting_channel_number + 7),
+ transmit_pma7.low_speed_test_select = 0,
+ transmit_pma7.preemp_pretap = 0,
+ transmit_pma7.preemp_pretap_inv = "false",
+ transmit_pma7.preemp_tap_1 = 0,
+ transmit_pma7.preemp_tap_2 = 0,
+ transmit_pma7.preemp_tap_2_inv = "false",
+ transmit_pma7.protocol_hint = "pcie",
+ transmit_pma7.rx_detect = 0,
+ transmit_pma7.serialization_factor = 10,
+ transmit_pma7.slew_rate = "off",
+ transmit_pma7.termination = "OCT 100 Ohms",
+ transmit_pma7.use_pma_direct = "false",
+ transmit_pma7.use_ser_double_data_mode = "false",
+ transmit_pma7.vod_selection = 4,
+ transmit_pma7.lpm_type = "arriaii_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b1,
+ cent_unit_clkdivpowerdn = {wire_cent_unit1_clkdivpowerdn[0], wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_pllpowerdn = {wire_cent_unit1_pllpowerdn[1:0], wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit1_pllresetout[1:0], wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit1_quadresetout, wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit1_rxcrupowerdown[5:0], wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit1_rxibpowerdown[5:0], wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit1_txdataout, wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit1_txctrlout, wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit1_txdetectrxpowerdown[3:0], wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit1_txobpowerdown[5:0], wire_cent_unit0_txobpowerdown[5:0]},
+ clk_div_clk0in = {pll0_out[7:0]},
+ clk_div_pclkin = {refclk_pma[0], 1'b0},
+ cmu_analogfastrefclkout = {wire_central_clk_div1_analogfastrefclkout, wire_central_clk_div0_analogfastrefclkout},
+ cmu_analogrefclkout = {wire_central_clk_div1_analogrefclkout, wire_central_clk_div0_analogrefclkout},
+ cmu_analogrefclkpulse = {wire_central_clk_div1_analogrefclkpulse, wire_central_clk_div0_analogrefclkpulse},
+ coreclkout = {2{coreclkout_wire[0]}},
+ coreclkout_bi_quad_wire = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div1_coreclkout, wire_central_clk_div0_coreclkout},
+ fixedclk = 1'b0,
+ fixedclk_in = {{2{1'b0}}, {4{fixedclk}}, {2{1'b0}}, {4{fixedclk}}},
+ int_hiprateswtichdone = {wire_central_clk_div1_rateswitchdone, wire_central_clk_div0_rateswitchdone},
+ int_rx_coreclkout = {wire_receive_pcs7_coreclkout, wire_receive_pcs6_coreclkout, wire_receive_pcs5_coreclkout, wire_receive_pcs4_coreclkout, wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_iqpphfifobyteselout = {wire_receive_pcs7_iqpphfifobyteselout, wire_receive_pcs6_iqpphfifobyteselout, wire_receive_pcs5_iqpphfifobyteselout, wire_receive_pcs4_iqpphfifobyteselout, wire_receive_pcs3_iqpphfifobyteselout, wire_receive_pcs2_iqpphfifobyteselout, wire_receive_pcs1_iqpphfifobyteselout, wire_receive_pcs0_iqpphfifobyteselout},
+ int_rx_iqpphfifordenableout = {wire_receive_pcs7_iqpphfifordenableout, wire_receive_pcs6_iqpphfifordenableout, wire_receive_pcs5_iqpphfifordenableout, wire_receive_pcs4_iqpphfifordenableout, wire_receive_pcs3_iqpphfifordenableout, wire_receive_pcs2_iqpphfifordenableout, wire_receive_pcs1_iqpphfifordenableout, wire_receive_pcs0_iqpphfifordenableout},
+ int_rx_iqpphfifowrclkout = {wire_receive_pcs7_iqpphfifowrclkout, wire_receive_pcs6_iqpphfifowrclkout, wire_receive_pcs5_iqpphfifowrclkout, wire_receive_pcs4_iqpphfifowrclkout, wire_receive_pcs3_iqpphfifowrclkout, wire_receive_pcs2_iqpphfifowrclkout, wire_receive_pcs1_iqpphfifowrclkout, wire_receive_pcs0_iqpphfifowrclkout},
+ int_rx_iqpphfifowrenableout = {wire_receive_pcs7_iqpphfifowrenableout, wire_receive_pcs6_iqpphfifowrenableout, wire_receive_pcs5_iqpphfifowrenableout, wire_receive_pcs4_iqpphfifowrenableout, wire_receive_pcs3_iqpphfifowrenableout, wire_receive_pcs2_iqpphfifowrenableout, wire_receive_pcs1_iqpphfifowrenableout, wire_receive_pcs0_iqpphfifowrenableout},
+ int_rx_iqpphfifoxnbytesel = {{3{2'b00}}, int_rx_iqpphfifobyteselout[3], 1'b0, {4{2'b00}}},
+ int_rx_iqpphfifoxnrdenable = {{3{2'b00}}, int_rx_iqpphfifordenableout[3], 1'b0, {4{2'b00}}},
+ int_rx_iqpphfifoxnwrclk = {{3{2'b00}}, int_rx_iqpphfifowrclkout[3], 1'b0, {4{2'b00}}},
+ int_rx_iqpphfifoxnwrenable = {{3{2'b00}}, int_rx_iqpphfifowrenableout[3], 1'b0, {4{2'b00}}},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs7_phfifobyteserdisableout, wire_receive_pcs6_phfifobyteserdisableout, wire_receive_pcs5_phfifobyteserdisableout, wire_receive_pcs4_phfifobyteserdisableout, wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs7_phfifoptrsresetout, wire_receive_pcs6_phfifoptrsresetout, wire_receive_pcs5_phfifoptrsresetout, wire_receive_pcs4_phfifoptrsresetout, wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs7_phfifordenableout, wire_receive_pcs6_phfifordenableout, wire_receive_pcs5_phfifordenableout, wire_receive_pcs4_phfifordenableout, wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs7_phfiforesetout, wire_receive_pcs6_phfiforesetout, wire_receive_pcs5_phfiforesetout, wire_receive_pcs4_phfiforesetout, wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs7_phfifowrdisableout, wire_receive_pcs6_phfifowrdisableout, wire_receive_pcs5_phfifowrdisableout, wire_receive_pcs4_phfifowrdisableout, wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {1'b0, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], 1'b0, int_rxphfifox4byteselout[0], 2'b00, int_rxphfifox4byteselout[0], 2'b00, int_rxphfifox4byteselout[0], 2'b00, int_rxphfifox4byteselout[0], 2'b00},
+ int_rx_phfifoxnrdenable = {1'b0, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], 1'b0, int_rxphfifox4rdenableout[0], 2'b00, int_rxphfifox4rdenableout[0], 2'b00, int_rxphfifox4rdenableout[0], 2'b00, int_rxphfifox4rdenableout[0], 2'b00},
+ int_rx_phfifoxnwrclk = {1'b0, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], 1'b0, int_rxphfifox4wrclkout[0], 2'b00, int_rxphfifox4wrclkout[0], 2'b00, int_rxphfifox4wrclkout[0], 2'b00, int_rxphfifox4wrclkout[0], 2'b00},
+ int_rx_phfifoxnwrenable = {1'b0, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], 1'b0, int_rxphfifox4wrenableout[0], 2'b00, int_rxphfifox4wrenableout[0], 2'b00, int_rxphfifox4wrenableout[0], 2'b00, int_rxphfifox4wrenableout[0], 2'b00},
+ int_rxcoreclk = {1'b0, int_rx_coreclkout[0]},
+ int_rxphfifordenable = {1'b0, int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {1'b0, int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit1_rxphfifox4byteselout, wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit1_rxphfifox4rdenableout, wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit1_rxphfifox4wrclkout, wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit1_rxphfifox4wrenableout, wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs7_coreclkout, wire_transmit_pcs6_coreclkout, wire_transmit_pcs5_coreclkout, wire_transmit_pcs4_coreclkout, wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_iqpphfifobyteselout = {wire_transmit_pcs7_iqpphfifobyteselout, wire_transmit_pcs6_iqpphfifobyteselout, wire_transmit_pcs5_iqpphfifobyteselout, wire_transmit_pcs4_iqpphfifobyteselout, wire_transmit_pcs3_iqpphfifobyteselout, wire_transmit_pcs2_iqpphfifobyteselout, wire_transmit_pcs1_iqpphfifobyteselout, wire_transmit_pcs0_iqpphfifobyteselout},
+ int_tx_iqpphfifordclkout = {wire_transmit_pcs7_iqpphfifordclkout, wire_transmit_pcs6_iqpphfifordclkout, wire_transmit_pcs5_iqpphfifordclkout, wire_transmit_pcs4_iqpphfifordclkout, wire_transmit_pcs3_iqpphfifordclkout, wire_transmit_pcs2_iqpphfifordclkout, wire_transmit_pcs1_iqpphfifordclkout, wire_transmit_pcs0_iqpphfifordclkout},
+ int_tx_iqpphfifordenableout = {wire_transmit_pcs7_iqpphfifordenableout, wire_transmit_pcs6_iqpphfifordenableout, wire_transmit_pcs5_iqpphfifordenableout, wire_transmit_pcs4_iqpphfifordenableout, wire_transmit_pcs3_iqpphfifordenableout, wire_transmit_pcs2_iqpphfifordenableout, wire_transmit_pcs1_iqpphfifordenableout, wire_transmit_pcs0_iqpphfifordenableout},
+ int_tx_iqpphfifowrenableout = {wire_transmit_pcs7_iqpphfifowrenableout, wire_transmit_pcs6_iqpphfifowrenableout, wire_transmit_pcs5_iqpphfifowrenableout, wire_transmit_pcs4_iqpphfifowrenableout, wire_transmit_pcs3_iqpphfifowrenableout, wire_transmit_pcs2_iqpphfifowrenableout, wire_transmit_pcs1_iqpphfifowrenableout, wire_transmit_pcs0_iqpphfifowrenableout},
+ int_tx_iqpphfifoxnbytesel = {{3{2'b00}}, int_tx_iqpphfifobyteselout[3], 1'b0, {4{2'b00}}},
+ int_tx_iqpphfifoxnrdclk = {{3{2'b00}}, int_tx_iqpphfifordclkout[3], 1'b0, {4{2'b00}}},
+ int_tx_iqpphfifoxnrdenable = {{3{2'b00}}, int_tx_iqpphfifordenableout[3], 1'b0, {4{2'b00}}},
+ int_tx_iqpphfifoxnwrenable = {{3{2'b00}}, int_tx_iqpphfifowrenableout[3], 1'b0, {4{2'b00}}},
+ int_tx_phfiforddisableout = {wire_transmit_pcs7_phfiforddisableout, wire_transmit_pcs6_phfiforddisableout, wire_transmit_pcs5_phfiforddisableout, wire_transmit_pcs4_phfiforddisableout, wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs7_phfiforesetout, wire_transmit_pcs6_phfiforesetout, wire_transmit_pcs5_phfiforesetout, wire_transmit_pcs4_phfiforesetout, wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs7_phfifowrenableout, wire_transmit_pcs6_phfifowrenableout, wire_transmit_pcs5_phfifowrenableout, wire_transmit_pcs4_phfifowrenableout, wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {1'b0, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], 1'b0, int_txphfifox4byteselout[0], 2'b00, int_txphfifox4byteselout[0], 2'b00, int_txphfifox4byteselout[0], 2'b00, int_txphfifox4byteselout[0], 2'b00},
+ int_tx_phfifoxnrdclk = {1'b0, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], 1'b0, int_txphfifox4rdclkout[0], 2'b00, int_txphfifox4rdclkout[0], 2'b00, int_txphfifox4rdclkout[0], 2'b00, int_txphfifox4rdclkout[0], 2'b00},
+ int_tx_phfifoxnrdenable = {1'b0, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], 1'b0, int_txphfifox4rdenableout[0], 2'b00, int_txphfifox4rdenableout[0], 2'b00, int_txphfifox4rdenableout[0], 2'b00, int_txphfifox4rdenableout[0], 2'b00},
+ int_tx_phfifoxnwrenable = {1'b0, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], 1'b0, int_txphfifox4wrenableout[0], 2'b00, int_txphfifox4wrenableout[0], 2'b00, int_txphfifox4wrenableout[0], 2'b00, int_txphfifox4wrenableout[0], 2'b00},
+ int_txcoreclk = {1'b0, int_tx_coreclkout[0]},
+ int_txphfiforddisable = {1'b0, int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {1'b0, int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {1'b0, int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit1_txphfifox4byteselout, wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit1_txphfifox4rdclkout, wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit1_txphfifox4rdenableout, wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit1_txphfifox4wrenableout, wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk1_nonusertocmu, wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[7:0]},
+ pipedatavalid_out = {wire_receive_pcs7_pipedatavalid, wire_receive_pcs6_pipedatavalid, wire_receive_pcs5_pipedatavalid, wire_receive_pcs4_pipedatavalid, wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[7:0]},
+ pipeelecidle_out = {wire_receive_pcs7_pipeelecidle, wire_receive_pcs6_pipeelecidle, wire_receive_pcs5_pipeelecidle, wire_receive_pcs4_pipeelecidle, wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs7_pipephydonestatus, wire_receive_pcs6_pipephydonestatus, wire_receive_pcs5_pipephydonestatus, wire_receive_pcs4_pipephydonestatus, wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs7_pipestatus, wire_receive_pcs6_pipestatus, wire_receive_pcs5_pipestatus, wire_receive_pcs4_pipestatus, wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll0_clkin = {10'b0000000000, 9'b000000000, pll_inclk_wire[0]},
+ pll0_out = {4'b0000, wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll7_dataout, wire_rx_cdr_pll6_dataout, wire_rx_cdr_pll5_dataout, wire_rx_cdr_pll4_dataout, wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {2{pll_locked_out[0]}},
+ pll_locked_out = {1'b0, wire_tx_pll0_locked},
+ pll_powerdown = {2{1'b0}},
+ pllpowerdn_in = {2'b00, 1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {2'b00, 1'b0, cent_unit_pllresetout[0]},
+ reconfig_clk = 1'b0,
+ refclk_pma = {wire_central_clk_div1_refclkout, wire_central_clk_div0_refclkout},
+ rx_analogreset_in = {8{rx_analogreset[0]}},
+ rx_analogreset_out = {wire_cent_unit1_rxanalogresetout[5:0], wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_bitslip = {8{1'b0}},
+ rx_coreclk_in = {8{coreclkout_bi_quad_wire[0]}},
+ rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[7], 8'b00000000, rx_pldcruclk_in[6], 8'b00000000, rx_pldcruclk_in[5], 8'b00000000, rx_pldcruclk_in[4], 8'b00000000, rx_pldcruclk_in[3], 8'b00000000, rx_pldcruclk_in[2], 8'b00000000, rx_pldcruclk_in[1], 8'b00000000, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs7_ctrldetect[0], wire_receive_pcs6_ctrldetect[0], wire_receive_pcs5_ctrldetect[0], wire_receive_pcs4_ctrldetect[0], wire_receive_pcs3_ctrldetect[0], wire_receive_pcs2_ctrldetect[0], wire_receive_pcs1_ctrldetect[0], wire_receive_pcs0_ctrldetect[0]},
+ rx_dataout = {rx_out_wire[63:0]},
+ rx_deserclock_in = {rx_pll_clkout[31:0]},
+ rx_digitalreset_in = {8{rx_digitalreset[0]}},
+ rx_digitalreset_out = {wire_cent_unit1_rxdigitalresetout, wire_cent_unit0_rxdigitalresetout},
+ rx_elecidleinfersel = {24{1'b0}},
+ rx_enapatternalign = {8{1'b0}},
+ rx_freqlocked = {rx_freqlocked_wire[7:0]},
+ rx_freqlocked_wire = {wire_rx_cdr_pll7_freqlocked, wire_rx_cdr_pll6_freqlocked, wire_rx_cdr_pll5_freqlocked, wire_rx_cdr_pll4_freqlocked, wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = {8{1'b0}},
+ rx_locktodata_wire = {rx_locktodata[7:0]},
+ rx_locktorefclk_wire = {wire_receive_pcs7_cdrctrllocktorefclkout, wire_receive_pcs6_cdrctrllocktorefclkout, wire_receive_pcs5_cdrctrllocktorefclkout, wire_receive_pcs4_cdrctrllocktorefclkout, wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs7_dataout[7:0], wire_receive_pcs6_dataout[7:0], wire_receive_pcs5_dataout[7:0], wire_receive_pcs4_dataout[7:0], wire_receive_pcs3_dataout[7:0], wire_receive_pcs2_dataout[7:0], wire_receive_pcs1_dataout[7:0], wire_receive_pcs0_dataout[7:0]},
+ rx_patterndetect = {wire_receive_pcs7_patterndetect[0], wire_receive_pcs6_patterndetect[0], wire_receive_pcs5_patterndetect[0], wire_receive_pcs4_patterndetect[0], wire_receive_pcs3_patterndetect[0], wire_receive_pcs2_patterndetect[0], wire_receive_pcs1_patterndetect[0], wire_receive_pcs0_patterndetect[0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[7], tx_rxfoundout[7], txdetectrxout[6], tx_rxfoundout[6], txdetectrxout[5], tx_rxfoundout[5], txdetectrxout[4], tx_rxfoundout[4], txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {8{400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}},
+ rx_phfifordenable = {8{1'b1}},
+ rx_phfiforeset = {8{1'b0}},
+ rx_phfifowrdisable = {8{1'b0}},
+ rx_pipestatetransdoneout = {wire_receive_pcs7_pipestatetransdoneout, wire_receive_pcs6_pipestatetransdoneout, wire_receive_pcs5_pipestatetransdoneout, wire_receive_pcs4_pipestatetransdoneout, wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[7:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll7_clk, wire_rx_cdr_pll6_clk, wire_rx_cdr_pll5_clk, wire_rx_cdr_pll4_clk, wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {rx_plllocked_wire[7:0]},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll7_pfdrefclkout, wire_rx_cdr_pll6_pfdrefclkout, wire_rx_cdr_pll5_pfdrefclkout, wire_rx_cdr_pll4_pfdrefclkout, wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll7_locked, wire_rx_cdr_pll6_locked, wire_rx_cdr_pll5_locked, wire_rx_cdr_pll4_locked, wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_clockout = {wire_receive_pma7_clockout, wire_receive_pma6_clockout, wire_receive_pma5_clockout, wire_receive_pma4_clockout, wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma7_dataout, wire_receive_pma6_dataout, wire_receive_pma5_dataout, wire_receive_pma4_dataout, wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma7_locktorefout, wire_receive_pma6_locktorefout, wire_receive_pma5_locktorefout, wire_receive_pma4_locktorefout, wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma7_recoverdataout[19:0], wire_receive_pma6_recoverdataout[19:0], wire_receive_pma5_recoverdataout[19:0], wire_receive_pma4_recoverdataout[19:0], wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {12{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}},
+ rx_powerdown = {8{1'b0}},
+ rx_powerdown_in = {rx_powerdown[7:0]},
+ rx_prbscidenable = {8{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs7_revparallelfdbkdata, wire_receive_pcs6_revparallelfdbkdata, wire_receive_pcs5_revparallelfdbkdata, wire_receive_pcs4_revparallelfdbkdata, wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {8{1'b0}},
+ rx_rxcruresetout = {wire_cent_unit1_rxcruresetout[5:0], wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma7_signaldetect, wire_receive_pma6_signaldetect, wire_receive_pma5_signaldetect, wire_receive_pma4_signaldetect, wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs7_syncstatus[0], wire_receive_pcs6_syncstatus[0], wire_receive_pcs5_syncstatus[0], wire_receive_pcs4_syncstatus[0], wire_receive_pcs3_syncstatus[0], wire_receive_pcs2_syncstatus[0], wire_receive_pcs1_syncstatus[0], wire_receive_pcs0_syncstatus[0]},
+ rxphfifowrdisable = {1'b0, int_rx_phfifowrdisableout[0]},
+ tx_analogreset_out = {wire_cent_unit1_txanalogresetout[5:0], wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout_int_wire = {wire_transmit_pcs7_clkout, wire_transmit_pcs6_clkout, wire_transmit_pcs5_clkout, wire_transmit_pcs4_clkout, wire_transmit_pcs3_clkout, wire_transmit_pcs2_clkout, wire_transmit_pcs1_clkout, wire_transmit_pcs0_clkout},
+ tx_coreclk_in = {8{coreclkout_bi_quad_wire[0]}},
+ tx_datain_wire = {tx_datain[63:0]},
+ tx_datainfull = {352{1'b0}},
+ tx_dataout = {wire_transmit_pma7_dataout, wire_transmit_pma6_dataout, wire_transmit_pma5_dataout, wire_transmit_pma4_dataout, wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs7_dataout, wire_transmit_pcs6_dataout, wire_transmit_pcs5_dataout, wire_transmit_pcs4_dataout, wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {8{tx_digitalreset[0]}},
+ tx_digitalreset_out = {wire_cent_unit1_txdigitalresetout, wire_cent_unit0_txdigitalresetout},
+ tx_dprioin_wire = {1200'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, {8{150'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}},
+ tx_forcedisp_wire = {tx_forcedispcompliance[7:0]},
+ tx_invpolarity = {8{1'b0}},
+ tx_localrefclk = {wire_transmit_pma7_clockout, wire_transmit_pma6_clockout, wire_transmit_pma5_clockout, wire_transmit_pma4_clockout, wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_phfiforeset = {8{1'b0}},
+ tx_pipedeemph = {8{1'b0}},
+ tx_pipemargin = {24{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs7_pipepowerdownout, wire_transmit_pcs6_pipepowerdownout, wire_transmit_pcs5_pipepowerdownout, wire_transmit_pcs4_pipepowerdownout, wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs7_pipepowerstateout, wire_transmit_pcs6_pipepowerstateout, wire_transmit_pcs5_pipepowerstateout, wire_transmit_pcs4_pipepowerstateout, wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = {8{1'b0}},
+ tx_pmadprioin_wire = {12{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}},
+ tx_revparallellpbken = {8{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma7_rxdetectvalidout, wire_transmit_pma6_rxdetectvalidout, wire_transmit_pma5_rxdetectvalidout, wire_transmit_pma4_rxdetectvalidout, wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma7_rxfoundout, wire_transmit_pma6_rxfoundout, wire_transmit_pma5_rxfoundout, wire_transmit_pma4_rxfoundout, wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ txdetectrxout = {wire_transmit_pcs7_txdetectrx, wire_transmit_pcs6_txdetectrx, wire_transmit_pcs5_txdetectrx, wire_transmit_pcs4_txdetectrx, wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx};
+endmodule //altpcie_serdes_2agx_x8d_gen1_08p_alt4gxb_0d59
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_2agx_x8d_gen1_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout)/* synthesis synthesis_clearbox = 1 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [7:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [15:0] powerdn;
+ input [0:0] rx_analogreset;
+ input [7:0] rx_cruclk;
+ input [7:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [7:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [7:0] tx_forcedispcompliance;
+ input [7:0] tx_forceelecidle;
+ output [1:0] coreclkout;
+ output [7:0] pipedatavalid;
+ output [7:0] pipeelecidle;
+ output [7:0] pipephydonestatus;
+ output [23:0] pipestatus;
+ output [1:0] pll_locked;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [7:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [7:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ output [7:0] tx_dataout;
+
+ wire [7:0] sub_wire0;
+ wire [1:0] sub_wire1;
+ wire [7:0] sub_wire2;
+ wire [7:0] sub_wire3;
+ wire [7:0] sub_wire4;
+ wire [7:0] sub_wire5;
+ wire [7:0] sub_wire6;
+ wire [7:0] sub_wire7;
+ wire [7:0] sub_wire8;
+ wire [23:0] sub_wire9;
+ wire [7:0] sub_wire10;
+ wire [1:0] sub_wire11;
+ wire [63:0] sub_wire12;
+ wire [7:0] rx_patterndetect = sub_wire0[7:0];
+ wire [1:0] coreclkout = sub_wire1[1:0];
+ wire [7:0] rx_ctrldetect = sub_wire2[7:0];
+ wire [7:0] pipedatavalid = sub_wire3[7:0];
+ wire [7:0] pipephydonestatus = sub_wire4[7:0];
+ wire [7:0] rx_pll_locked = sub_wire5[7:0];
+ wire [7:0] rx_freqlocked = sub_wire6[7:0];
+ wire [7:0] tx_dataout = sub_wire7[7:0];
+ wire [7:0] pipeelecidle = sub_wire8[7:0];
+ wire [23:0] pipestatus = sub_wire9[23:0];
+ wire [7:0] rx_syncstatus = sub_wire10[7:0];
+ wire [1:0] pll_locked = sub_wire11[1:0];
+ wire [63:0] rx_dataout = sub_wire12[63:0];
+
+ altpcie_serdes_2agx_x8d_gen1_08p_alt4gxb_0d59 altpcie_serdes_2agx_x8d_gen1_08p_alt4gxb_0d59_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .rx_datain (rx_datain),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .coreclkout (sub_wire1),
+ .rx_ctrldetect (sub_wire2),
+ .pipedatavalid (sub_wire3),
+ .pipephydonestatus (sub_wire4),
+ .rx_pll_locked (sub_wire5),
+ .rx_freqlocked (sub_wire6),
+ .tx_dataout (sub_wire7),
+ .pipeelecidle (sub_wire8),
+ .pipestatus (sub_wire9),
+ .rx_syncstatus (sub_wire10),
+ .pll_locked (sub_wire11),
+ .rx_dataout (sub_wire12));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "1"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.82"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x8"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.65"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.5"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE NUMERIC "4"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x8"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x8"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_analog_power STRING "2.5v"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_divide_by NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_multiply_by NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_divide_by NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_multiply_by NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 2 0 OUTPUT NODEFVAL "coreclkout[1..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 8 0 INPUT NODEFVAL "pipe8b10binvpolarity[7..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 8 0 OUTPUT NODEFVAL "pipedatavalid[7..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 8 0 OUTPUT NODEFVAL "pipeelecidle[7..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 8 0 OUTPUT NODEFVAL "pipephydonestatus[7..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 24 0 OUTPUT NODEFVAL "pipestatus[23..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 2 0 OUTPUT NODEFVAL "pll_locked[1..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 16 0 INPUT NODEFVAL "powerdn[15..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 8 0 INPUT GND "rx_cruclk[7..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 8 0 INPUT NODEFVAL "rx_datain[7..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 8 0 OUTPUT NODEFVAL "rx_freqlocked[7..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 8 0 OUTPUT NODEFVAL "rx_pll_locked[7..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 8 0 OUTPUT NODEFVAL "tx_dataout[7..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 8 0 INPUT NODEFVAL "tx_detectrxloop[7..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 8 0 INPUT NODEFVAL "tx_forcedispcompliance[7..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 8 0 INPUT NODEFVAL "tx_forceelecidle[7..0]"
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 8 0 tx_detectrxloop 0 0 8 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 8 0 tx_forcedispcompliance 0 0 8 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 8 0 @pipedatavalid 0 0 8 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 16 0 powerdn 0 0 16 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 8 0 @pipeelecidle 0 0 8 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 24 0 @pipestatus 0 0 24 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 8 0 @rx_pll_locked 0 0 8 0
+// Retrieval info: CONNECT: coreclkout 0 0 2 0 @coreclkout 0 0 2 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 8 0 pipe8b10binvpolarity 0 0 8 0
+// Retrieval info: CONNECT: pll_locked 0 0 2 0 @pll_locked 0 0 2 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 8 0 rx_cruclk 0 0 8 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 8 0 @tx_dataout 0 0 8 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 8 0 @rx_freqlocked 0 0 8 0
+// Retrieval info: CONNECT: @rx_datain 0 0 8 0 rx_datain 0 0 8 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 8 0 @pipephydonestatus 0 0 8 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 8 0 tx_forceelecidle 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x8d_gen1_08p.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x8d_gen1_08p.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x8d_gen1_08p.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x8d_gen1_08p.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x8d_gen1_08p.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x8d_gen1_08p_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x8d_gen1_08p_bb.v TRUE FALSE
+// Retrieval info: LIB_FILE: arriaii_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v b/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v
new file mode 100644
index 0000000000000000000000000000000000000000..594313df90f091fa1e81c063c37ae90607ef3cae
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v
@@ -0,0 +1,530 @@
+// megafunction wizard: %ALT2GXB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt2gxb
+
+// ============================================================
+// File Name: altpcie_serdes_2sgx_x1d_10000.v
+// Megafunction Name(s):
+// alt2gxb
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.1 Build 198 11/07/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_2sgx_x1d_10000 (
+ cal_blk_clk,
+ fixedclk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input fixedclk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [1:0] powerdn;
+ input reconfig_clk;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ output [0:0] pll_locked;
+ output [0:0] reconfig_fromgxb;
+ output [1:0] rx_ctrldetect;
+ output [15:0] rx_dataout;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [1:0] sub_wire0;
+ wire [1:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [0:0] sub_wire7;
+ wire [2:0] sub_wire8;
+ wire [1:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [0:0] sub_wire12;
+ wire [15:0] sub_wire13;
+ wire [1:0] rx_patterndetect = sub_wire0[1:0];
+ wire [1:0] rx_ctrldetect = sub_wire1[1:0];
+ wire [0:0] pipedatavalid = sub_wire2[0:0];
+ wire [0:0] pipephydonestatus = sub_wire3[0:0];
+ wire [0:0] rx_pll_locked = sub_wire4[0:0];
+ wire [0:0] rx_freqlocked = sub_wire5[0:0];
+ wire [0:0] tx_dataout = sub_wire6[0:0];
+ wire [0:0] pipeelecidle = sub_wire7[0:0];
+ wire [2:0] pipestatus = sub_wire8[2:0];
+ wire [1:0] rx_syncstatus = sub_wire9[1:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [0:0] reconfig_fromgxb = sub_wire11[0:0];
+ wire [0:0] pll_locked = sub_wire12[0:0];
+ wire [15:0] rx_dataout = sub_wire13[15:0];
+
+ alt2gxb alt2gxb_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .reconfig_clk (reconfig_clk),
+ .fixedclk (fixedclk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .rx_ctrldetect (sub_wire1),
+ .pipedatavalid (sub_wire2),
+ .pipephydonestatus (sub_wire3),
+ .rx_pll_locked (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .tx_dataout (sub_wire6),
+ .pipeelecidle (sub_wire7),
+ .pipestatus (sub_wire8),
+ .rx_syncstatus (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .pll_locked (sub_wire12),
+ .rx_dataout (sub_wire13)
+ // synopsys translate_off
+ ,
+ .cal_blk_calibrationstatus (),
+ .cal_blk_powerdown (),
+ .coreclkout (),
+ .debug_rx_phase_comp_fifo_error (),
+ .debug_tx_phase_comp_fifo_error (),
+ .gxb_enable (),
+ .pll_inclk_alt (),
+ .pll_locked_alt (),
+ .reconfig_fromgxb_oe (),
+ .rx_a1a2size (),
+ .rx_a1a2sizeout (),
+ .rx_a1detect (),
+ .rx_a2detect (),
+ .rx_bistdone (),
+ .rx_bisterr (),
+ .rx_bitslip (),
+ .rx_byteorderalignstatus (),
+ .rx_channelaligned (),
+ .rx_clkout (),
+ .rx_coreclk (),
+ .rx_cruclk_alt (),
+ .rx_dataoutfull (),
+ .rx_disperr (),
+ .rx_enabyteord (),
+ .rx_enapatternalign (),
+ .rx_errdetect (),
+ .rx_invpolarity (),
+ .rx_k1detect (),
+ .rx_k2detect (),
+ .rx_locktodata (),
+ .rx_locktorefclk (),
+ .rx_phfifooverflow (),
+ .rx_phfifordenable (),
+ .rx_phfiforeset (),
+ .rx_phfifounderflow (),
+ .rx_phfifowrdisable (),
+ .rx_powerdown (),
+ .rx_recovclkout (),
+ .rx_revbitorderwa (),
+ .rx_revbyteorderwa (),
+ .rx_rlv (),
+ .rx_rmfifoalmostempty (),
+ .rx_rmfifoalmostfull (),
+ .rx_rmfifodatadeleted (),
+ .rx_rmfifodatainserted (),
+ .rx_rmfifoempty (),
+ .rx_rmfifofull (),
+ .rx_rmfifordena (),
+ .rx_rmfiforeset (),
+ .rx_rmfifowrena (),
+ .rx_runningdisp (),
+ .rx_seriallpbken (),
+ .rx_signaldetect (),
+ .tx_coreclk (),
+ .tx_datainfull (),
+ .tx_dispval (),
+ .tx_forcedisp (),
+ .tx_invpolarity (),
+ .tx_phfifooverflow (),
+ .tx_phfiforeset (),
+ .tx_phfifounderflow (),
+ .tx_revparallellpbken ()
+ // synopsys translate_on
+ );
+ defparam
+ alt2gxb_component.starting_channel_number = starting_channel_number,
+ alt2gxb_component.cmu_pll_inclock_period = 10000,
+ alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
+ alt2gxb_component.digitalreset_port_width = 1,
+ alt2gxb_component.enable_fast_recovery_pci_mode = "true",
+ alt2gxb_component.en_local_clk_div_ctrl = "true",
+ alt2gxb_component.equalizer_ctrl_a_setting = 0,
+ alt2gxb_component.equalizer_ctrl_b_setting = 0,
+ alt2gxb_component.equalizer_ctrl_c_setting = 0,
+ alt2gxb_component.equalizer_ctrl_d_setting = 0,
+ alt2gxb_component.equalizer_ctrl_v_setting = 0,
+ alt2gxb_component.equalizer_dcgain_setting = 1,
+ alt2gxb_component.gen_reconfig_pll = "false",
+ alt2gxb_component.loopback_mode = "none",
+ alt2gxb_component.lpm_type = "alt2gxb",
+ alt2gxb_component.number_of_channels = 1,
+ alt2gxb_component.operation_mode = "duplex",
+ alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 5,
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
+ alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
+ alt2gxb_component.protocol = "pipe",
+ alt2gxb_component.receiver_termination = "oct_100_ohms",
+ alt2gxb_component.reconfig_dprio_mode = 1,
+ alt2gxb_component.reverse_loopback_mode = "rplb",
+ alt2gxb_component.rx_8b_10b_compatibility_mode = "true",
+ alt2gxb_component.rx_8b_10b_mode = "normal",
+ alt2gxb_component.rx_align_pattern = "0101111100",
+ alt2gxb_component.rx_align_pattern_length = 10,
+ alt2gxb_component.rx_allow_align_polarity_inversion = "false",
+ alt2gxb_component.rx_allow_pipe_polarity_inversion = "true",
+ alt2gxb_component.rx_bandwidth_mode = 1,
+ alt2gxb_component.rx_bitslip_enable = "false",
+ alt2gxb_component.rx_byte_ordering_mode = "none",
+ alt2gxb_component.rx_channel_bonding = "indv",
+ alt2gxb_component.rx_channel_width = 16,
+ alt2gxb_component.rx_common_mode = "0.9v",
+ alt2gxb_component.rx_cru_inclock_period = 10000,
+ alt2gxb_component.rx_cru_pre_divide_by = 1,
+ alt2gxb_component.rx_datapath_protocol = "pipe",
+ alt2gxb_component.rx_data_rate = 2500,
+ alt2gxb_component.rx_data_rate_remainder = 0,
+ alt2gxb_component.rx_disable_auto_idle_insertion = "false",
+ alt2gxb_component.rx_enable_bit_reversal = "false",
+ alt2gxb_component.rx_enable_lock_to_data_sig = "false",
+ alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
+ alt2gxb_component.rx_enable_self_test_mode = "false",
+ alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
+ alt2gxb_component.rx_force_signal_detect = "false",
+ alt2gxb_component.rx_ppmselect = 8,
+ alt2gxb_component.rx_rate_match_back_to_back = "false",
+ alt2gxb_component.rx_rate_match_fifo_mode = "normal",
+ alt2gxb_component.rx_rate_match_ordered_set_based = "false",
+ alt2gxb_component.rx_rate_match_pattern1 = "11010000111010000011",
+ alt2gxb_component.rx_rate_match_pattern2 = "00101111000101111100",
+ alt2gxb_component.rx_rate_match_pattern_size = 20,
+ alt2gxb_component.rx_rate_match_skip_set_based = "false",
+ alt2gxb_component.rx_run_length_enable = "false",
+ alt2gxb_component.rx_signal_detect_threshold = 1,
+ alt2gxb_component.rx_use_align_state_machine = "true",
+ alt2gxb_component.rx_use_clkout = "false",
+ alt2gxb_component.rx_use_coreclk = "false",
+ alt2gxb_component.rx_use_cruclk = "true",
+ alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
+ alt2gxb_component.rx_use_deskew_fifo = "false",
+ alt2gxb_component.rx_use_double_data_mode = "true",
+ alt2gxb_component.rx_use_pipe8b10binvpolarity = "true",
+ alt2gxb_component.rx_use_rate_match_pattern1_only = "false",
+ alt2gxb_component.transmitter_termination = "oct_100_ohms",
+ alt2gxb_component.tx_8b_10b_compatibility_mode = "true",
+ alt2gxb_component.tx_8b_10b_mode = "normal",
+ alt2gxb_component.tx_allow_polarity_inversion = "false",
+ alt2gxb_component.tx_analog_power = "1.2v",
+ alt2gxb_component.tx_channel_bonding = "indv",
+ alt2gxb_component.tx_channel_width = 16,
+ alt2gxb_component.tx_common_mode = "0.6v",
+ alt2gxb_component.tx_data_rate = 2500,
+ alt2gxb_component.tx_data_rate_remainder = 0,
+ alt2gxb_component.tx_enable_bit_reversal = "false",
+ alt2gxb_component.tx_enable_idle_selection = "false",
+ alt2gxb_component.tx_enable_self_test_mode = "false",
+ alt2gxb_component.tx_refclk_divide_by = 1,
+ alt2gxb_component.tx_transmit_protocol = "pipe",
+ alt2gxb_component.tx_use_coreclk = "false",
+ alt2gxb_component.tx_use_double_data_mode = "true",
+ alt2gxb_component.tx_use_serializer_double_data_mode = "false",
+ alt2gxb_component.use_calibration_block = "true",
+ alt2gxb_component.vod_ctrl_setting = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ALT_SIMLIB_GEN STRING "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: PRIVATE: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "1"
+// Retrieval info: PRIVATE: VOD_CTRL_SETTING NUMERIC "800"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500.0000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "62.2"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "62.2"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "1"
+// Retrieval info: PRIVATE: WIZ_EXTERNAL_RX_TERMINATION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EXTERNAL_TX_TERMINATION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500.0000"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "5"
+// Retrieval info: PRIVATE: WIZ_PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_TERMINATION NUMERIC "100"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.85"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "x1"
+// Retrieval info: PRIVATE: WIZ_TCL_KEY STRING "STRATIXIIGX_CONFIG_MODE_PIPE_1X"
+// Retrieval info: PRIVATE: WIZ_TX_TERMINATION NUMERIC "100"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.6"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.2"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: CMU_PLL_INCLOCK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL NUMERIC "3"
+// Retrieval info: CONSTANT: DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: ENABLE_FAST_RECOVERY_PCI_MODE STRING "true"
+// Retrieval info: CONSTANT: EN_LOCAL_CLK_DIV_CTRL STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt2gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "5"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "rplb"
+// Retrieval info: CONSTANT: RX_8B_10B_COMPATIBILITY_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BANDWIDTH_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "none"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.9v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_CRU_PRE_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DISABLE_AUTO_IDLE_INSERTION STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_BACK_TO_BACK STRING "false"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_ORDERED_SET_BASED STRING "false"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_SKIP_SET_BASED STRING "false"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "1"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_COMPATIBILITY_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.2v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.6v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_IDLE_SELECTION STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_REFCLK_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 2 0 OUTPUT NODEFVAL "rx_ctrldetect[1..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 16 0 OUTPUT NODEFVAL "rx_dataout[15..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 1 0 OUTPUT NODEFVAL "rx_pll_locked[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 2 0 INPUT NODEFVAL "tx_ctrlenable[1..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 16 0 INPUT NODEFVAL "tx_datain[15..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
+// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 2 0 @rx_ctrldetect 0 0 2 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 16 0 @rx_dataout 0 0 16 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 1 0 @rx_pll_locked 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 2 0 tx_ctrlenable 0 0 2 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: CONNECT: @tx_datain 0 0 16 0 tx_datain 0 0 16 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x1d_10000.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x1d_10000.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x1d_10000.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x1d_10000.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x1d_10000_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x1d_10000_bb.v FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v b/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v
new file mode 100644
index 0000000000000000000000000000000000000000..8c63637f9604846857c29f07ec71fada73825edb
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v
@@ -0,0 +1,530 @@
+// megafunction wizard: %ALT2GXB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt2gxb
+
+// ============================================================
+// File Name: altpcie_serdes_2sgx_x4d_10000.v
+// Megafunction Name(s):
+// alt2gxb
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.1 Build 198 11/07/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_2sgx_x4d_10000 (
+ cal_blk_clk,
+ fixedclk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input fixedclk;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [7:0] powerdn;
+ input reconfig_clk;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ input [3:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+ output [0:0] coreclkout;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ output [0:0] pll_locked;
+ output [0:0] reconfig_fromgxb;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [3:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ output [3:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [7:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [7:0] sub_wire2;
+ wire [3:0] sub_wire3;
+ wire [3:0] sub_wire4;
+ wire [3:0] sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [3:0] sub_wire7;
+ wire [3:0] sub_wire8;
+ wire [11:0] sub_wire9;
+ wire [7:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [0:0] sub_wire12;
+ wire [63:0] sub_wire13;
+ wire [7:0] rx_patterndetect = sub_wire0[7:0];
+ wire [0:0] coreclkout = sub_wire1[0:0];
+ wire [7:0] rx_ctrldetect = sub_wire2[7:0];
+ wire [3:0] pipedatavalid = sub_wire3[3:0];
+ wire [3:0] pipephydonestatus = sub_wire4[3:0];
+ wire [3:0] rx_pll_locked = sub_wire5[3:0];
+ wire [3:0] rx_freqlocked = sub_wire6[3:0];
+ wire [3:0] tx_dataout = sub_wire7[3:0];
+ wire [3:0] pipeelecidle = sub_wire8[3:0];
+ wire [11:0] pipestatus = sub_wire9[11:0];
+ wire [7:0] rx_syncstatus = sub_wire10[7:0];
+ wire [0:0] reconfig_fromgxb = sub_wire11[0:0];
+ wire [0:0] pll_locked = sub_wire12[0:0];
+ wire [63:0] rx_dataout = sub_wire13[63:0];
+
+ alt2gxb alt2gxb_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .reconfig_clk (reconfig_clk),
+ .fixedclk (fixedclk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .coreclkout (sub_wire1),
+ .rx_ctrldetect (sub_wire2),
+ .pipedatavalid (sub_wire3),
+ .pipephydonestatus (sub_wire4),
+ .rx_pll_locked (sub_wire5),
+ .rx_freqlocked (sub_wire6),
+ .tx_dataout (sub_wire7),
+ .pipeelecidle (sub_wire8),
+ .pipestatus (sub_wire9),
+ .rx_syncstatus (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .pll_locked (sub_wire12),
+ .rx_dataout (sub_wire13)
+ // synopsys translate_off
+ ,
+ .cal_blk_calibrationstatus (),
+ .cal_blk_powerdown (),
+ .debug_rx_phase_comp_fifo_error (),
+ .debug_tx_phase_comp_fifo_error (),
+ .gxb_enable (),
+ .pll_inclk_alt (),
+ .pll_locked_alt (),
+ .reconfig_fromgxb_oe (),
+ .rx_a1a2size (),
+ .rx_a1a2sizeout (),
+ .rx_a1detect (),
+ .rx_a2detect (),
+ .rx_bistdone (),
+ .rx_bisterr (),
+ .rx_bitslip (),
+ .rx_byteorderalignstatus (),
+ .rx_channelaligned (),
+ .rx_clkout (),
+ .rx_coreclk (),
+ .rx_cruclk_alt (),
+ .rx_dataoutfull (),
+ .rx_disperr (),
+ .rx_enabyteord (),
+ .rx_enapatternalign (),
+ .rx_errdetect (),
+ .rx_invpolarity (),
+ .rx_k1detect (),
+ .rx_k2detect (),
+ .rx_locktodata (),
+ .rx_locktorefclk (),
+ .rx_phfifooverflow (),
+ .rx_phfifordenable (),
+ .rx_phfiforeset (),
+ .rx_phfifounderflow (),
+ .rx_phfifowrdisable (),
+ .rx_powerdown (),
+ .rx_recovclkout (),
+ .rx_revbitorderwa (),
+ .rx_revbyteorderwa (),
+ .rx_rlv (),
+ .rx_rmfifoalmostempty (),
+ .rx_rmfifoalmostfull (),
+ .rx_rmfifodatadeleted (),
+ .rx_rmfifodatainserted (),
+ .rx_rmfifoempty (),
+ .rx_rmfifofull (),
+ .rx_rmfifordena (),
+ .rx_rmfiforeset (),
+ .rx_rmfifowrena (),
+ .rx_runningdisp (),
+ .rx_seriallpbken (),
+ .rx_signaldetect (),
+ .tx_clkout (),
+ .tx_coreclk (),
+ .tx_datainfull (),
+ .tx_dispval (),
+ .tx_forcedisp (),
+ .tx_invpolarity (),
+ .tx_phfifooverflow (),
+ .tx_phfiforeset (),
+ .tx_phfifounderflow (),
+ .tx_revparallellpbken ()
+ // synopsys translate_on
+ );
+ defparam
+ alt2gxb_component.starting_channel_number = starting_channel_number,
+ alt2gxb_component.cmu_pll_inclock_period = 10000,
+ alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
+ alt2gxb_component.digitalreset_port_width = 1,
+ alt2gxb_component.enable_fast_recovery_pci_mode = "true",
+ alt2gxb_component.en_local_clk_div_ctrl = "true",
+ alt2gxb_component.equalizer_ctrl_a_setting = 0,
+ alt2gxb_component.equalizer_ctrl_b_setting = 0,
+ alt2gxb_component.equalizer_ctrl_c_setting = 0,
+ alt2gxb_component.equalizer_ctrl_d_setting = 0,
+ alt2gxb_component.equalizer_ctrl_v_setting = 0,
+ alt2gxb_component.equalizer_dcgain_setting = 1,
+ alt2gxb_component.gen_reconfig_pll = "false",
+ alt2gxb_component.loopback_mode = "none",
+ alt2gxb_component.lpm_type = "alt2gxb",
+ alt2gxb_component.number_of_channels = 4,
+ alt2gxb_component.operation_mode = "duplex",
+ alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 5,
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
+ alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
+ alt2gxb_component.protocol = "pipe",
+ alt2gxb_component.receiver_termination = "oct_100_ohms",
+ alt2gxb_component.reconfig_dprio_mode = 1,
+ alt2gxb_component.reverse_loopback_mode = "rplb",
+ alt2gxb_component.rx_8b_10b_compatibility_mode = "true",
+ alt2gxb_component.rx_8b_10b_mode = "normal",
+ alt2gxb_component.rx_align_pattern = "0101111100",
+ alt2gxb_component.rx_align_pattern_length = 10,
+ alt2gxb_component.rx_allow_align_polarity_inversion = "false",
+ alt2gxb_component.rx_allow_pipe_polarity_inversion = "true",
+ alt2gxb_component.rx_bandwidth_mode = 1,
+ alt2gxb_component.rx_bitslip_enable = "false",
+ alt2gxb_component.rx_byte_ordering_mode = "none",
+ alt2gxb_component.rx_channel_bonding = "x4",
+ alt2gxb_component.rx_channel_width = 16,
+ alt2gxb_component.rx_common_mode = "0.9v",
+ alt2gxb_component.rx_cru_inclock_period = 10000,
+ alt2gxb_component.rx_cru_pre_divide_by = 1,
+ alt2gxb_component.rx_datapath_protocol = "pipe",
+ alt2gxb_component.rx_data_rate = 2500,
+ alt2gxb_component.rx_data_rate_remainder = 0,
+ alt2gxb_component.rx_disable_auto_idle_insertion = "false",
+ alt2gxb_component.rx_enable_bit_reversal = "false",
+ alt2gxb_component.rx_enable_lock_to_data_sig = "false",
+ alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
+ alt2gxb_component.rx_enable_self_test_mode = "false",
+ alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
+ alt2gxb_component.rx_force_signal_detect = "false",
+ alt2gxb_component.rx_ppmselect = 8,
+ alt2gxb_component.rx_rate_match_back_to_back = "false",
+ alt2gxb_component.rx_rate_match_fifo_mode = "normal",
+ alt2gxb_component.rx_rate_match_ordered_set_based = "false",
+ alt2gxb_component.rx_rate_match_pattern1 = "11010000111010000011",
+ alt2gxb_component.rx_rate_match_pattern2 = "00101111000101111100",
+ alt2gxb_component.rx_rate_match_pattern_size = 20,
+ alt2gxb_component.rx_rate_match_skip_set_based = "false",
+ alt2gxb_component.rx_run_length_enable = "false",
+ alt2gxb_component.rx_signal_detect_threshold = 1,
+ alt2gxb_component.rx_use_align_state_machine = "true",
+ alt2gxb_component.rx_use_clkout = "false",
+ alt2gxb_component.rx_use_coreclk = "false",
+ alt2gxb_component.rx_use_cruclk = "true",
+ alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
+ alt2gxb_component.rx_use_deskew_fifo = "false",
+ alt2gxb_component.rx_use_double_data_mode = "true",
+ alt2gxb_component.rx_use_pipe8b10binvpolarity = "true",
+ alt2gxb_component.rx_use_rate_match_pattern1_only = "false",
+ alt2gxb_component.transmitter_termination = "oct_100_ohms",
+ alt2gxb_component.tx_8b_10b_compatibility_mode = "true",
+ alt2gxb_component.tx_8b_10b_mode = "normal",
+ alt2gxb_component.tx_allow_polarity_inversion = "false",
+ alt2gxb_component.tx_analog_power = "1.2v",
+ alt2gxb_component.tx_channel_bonding = "x4",
+ alt2gxb_component.tx_channel_width = 16,
+ alt2gxb_component.tx_common_mode = "0.6v",
+ alt2gxb_component.tx_data_rate = 2500,
+ alt2gxb_component.tx_data_rate_remainder = 0,
+ alt2gxb_component.tx_enable_bit_reversal = "false",
+ alt2gxb_component.tx_enable_idle_selection = "false",
+ alt2gxb_component.tx_enable_self_test_mode = "false",
+ alt2gxb_component.tx_refclk_divide_by = 1,
+ alt2gxb_component.tx_transmit_protocol = "pipe",
+ alt2gxb_component.tx_use_coreclk = "false",
+ alt2gxb_component.tx_use_double_data_mode = "true",
+ alt2gxb_component.tx_use_serializer_double_data_mode = "false",
+ alt2gxb_component.use_calibration_block = "true",
+ alt2gxb_component.vod_ctrl_setting = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ALT_SIMLIB_GEN STRING "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: PRIVATE: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "1"
+// Retrieval info: PRIVATE: VOD_CTRL_SETTING NUMERIC "800"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500.0000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "62.2"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "62.2"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "1"
+// Retrieval info: PRIVATE: WIZ_EXTERNAL_RX_TERMINATION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EXTERNAL_TX_TERMINATION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500.0000"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "5"
+// Retrieval info: PRIVATE: WIZ_PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_TERMINATION NUMERIC "100"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.85"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "x4"
+// Retrieval info: PRIVATE: WIZ_TCL_KEY STRING "STRATIXIIGX_CONFIG_MODE_PIPE_4X"
+// Retrieval info: PRIVATE: WIZ_TX_TERMINATION NUMERIC "100"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.6"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.2"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: CMU_PLL_INCLOCK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL NUMERIC "3"
+// Retrieval info: CONSTANT: DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: ENABLE_FAST_RECOVERY_PCI_MODE STRING "true"
+// Retrieval info: CONSTANT: EN_LOCAL_CLK_DIV_CTRL STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt2gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "5"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "rplb"
+// Retrieval info: CONSTANT: RX_8B_10B_COMPATIBILITY_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BANDWIDTH_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "none"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.9v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_CRU_PRE_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DISABLE_AUTO_IDLE_INSERTION STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_BACK_TO_BACK STRING "false"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_ORDERED_SET_BASED STRING "false"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_SKIP_SET_BASED STRING "false"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "1"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_COMPATIBILITY_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.2v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.6v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_IDLE_SELECTION STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_REFCLK_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
+// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x4d_10000.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x4d_10000.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x4d_10000.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x4d_10000.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x4d_10000_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x4d_10000_bb.v FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v b/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v
new file mode 100644
index 0000000000000000000000000000000000000000..1f7b0275ff003c370e70a69e0a74ee7a44f251f4
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v
@@ -0,0 +1,542 @@
+// megafunction wizard: %ALT2GXB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt2gxb
+
+// ============================================================
+// File Name: altpcie_serdes_2sgx_x8d_10000.v
+// Megafunction Name(s):
+// alt2gxb
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.1 Build 198 11/07/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_2sgx_x8d_10000 (
+ cal_blk_clk,
+ fixedclk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_disperr,
+ rx_errdetect,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input fixedclk;
+ input [0:0] gxb_powerdown;
+ input [7:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [15:0] powerdn;
+ input reconfig_clk;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [7:0] rx_cruclk;
+ input [7:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [7:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [7:0] tx_forcedispcompliance;
+ input [7:0] tx_forceelecidle;
+ output [1:0] coreclkout;
+ output [7:0] pipedatavalid;
+ output [7:0] pipeelecidle;
+ output [7:0] pipephydonestatus;
+ output [23:0] pipestatus;
+ output [1:0] pll_locked;
+ output [1:0] reconfig_fromgxb;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [7:0] rx_disperr;
+ output [7:0] rx_errdetect;
+ output [7:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [7:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ output [7:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [7:0] sub_wire0;
+ wire [7:0] sub_wire1;
+ wire [1:0] sub_wire2;
+ wire [7:0] sub_wire3;
+ wire [7:0] sub_wire4;
+ wire [7:0] sub_wire5;
+ wire [7:0] sub_wire6;
+ wire [7:0] sub_wire7;
+ wire [7:0] sub_wire8;
+ wire [7:0] sub_wire9;
+ wire [7:0] sub_wire10;
+ wire [23:0] sub_wire11;
+ wire [7:0] sub_wire12;
+ wire [1:0] sub_wire13;
+ wire [1:0] sub_wire14;
+ wire [63:0] sub_wire15;
+ wire [7:0] rx_disperr = sub_wire0[7:0];
+ wire [7:0] rx_patterndetect = sub_wire1[7:0];
+ wire [1:0] coreclkout = sub_wire2[1:0];
+ wire [7:0] rx_ctrldetect = sub_wire3[7:0];
+ wire [7:0] pipedatavalid = sub_wire4[7:0];
+ wire [7:0] rx_errdetect = sub_wire5[7:0];
+ wire [7:0] pipephydonestatus = sub_wire6[7:0];
+ wire [7:0] rx_pll_locked = sub_wire7[7:0];
+ wire [7:0] rx_freqlocked = sub_wire8[7:0];
+ wire [7:0] tx_dataout = sub_wire9[7:0];
+ wire [7:0] pipeelecidle = sub_wire10[7:0];
+ wire [23:0] pipestatus = sub_wire11[23:0];
+ wire [7:0] rx_syncstatus = sub_wire12[7:0];
+ wire [1:0] reconfig_fromgxb = sub_wire13[1:0];
+ wire [1:0] pll_locked = sub_wire14[1:0];
+ wire [63:0] rx_dataout = sub_wire15[63:0];
+
+ alt2gxb alt2gxb_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .reconfig_clk (reconfig_clk),
+ .fixedclk (fixedclk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_disperr (sub_wire0),
+ .rx_patterndetect (sub_wire1),
+ .coreclkout (sub_wire2),
+ .rx_ctrldetect (sub_wire3),
+ .pipedatavalid (sub_wire4),
+ .rx_errdetect (sub_wire5),
+ .pipephydonestatus (sub_wire6),
+ .rx_pll_locked (sub_wire7),
+ .rx_freqlocked (sub_wire8),
+ .tx_dataout (sub_wire9),
+ .pipeelecidle (sub_wire10),
+ .pipestatus (sub_wire11),
+ .rx_syncstatus (sub_wire12),
+ .reconfig_fromgxb (sub_wire13),
+ .pll_locked (sub_wire14),
+ .rx_dataout (sub_wire15)
+ // synopsys translate_off
+ ,
+ .cal_blk_calibrationstatus (),
+ .cal_blk_powerdown (),
+ .debug_rx_phase_comp_fifo_error (),
+ .debug_tx_phase_comp_fifo_error (),
+ .gxb_enable (),
+ .pll_inclk_alt (),
+ .pll_locked_alt (),
+ .reconfig_fromgxb_oe (),
+ .rx_a1a2size (),
+ .rx_a1a2sizeout (),
+ .rx_a1detect (),
+ .rx_a2detect (),
+ .rx_bistdone (),
+ .rx_bisterr (),
+ .rx_bitslip (),
+ .rx_byteorderalignstatus (),
+ .rx_channelaligned (),
+ .rx_clkout (),
+ .rx_coreclk (),
+ .rx_cruclk_alt (),
+ .rx_dataoutfull (),
+ .rx_enabyteord (),
+ .rx_enapatternalign (),
+ .rx_invpolarity (),
+ .rx_k1detect (),
+ .rx_k2detect (),
+ .rx_locktodata (),
+ .rx_locktorefclk (),
+ .rx_phfifooverflow (),
+ .rx_phfifordenable (),
+ .rx_phfiforeset (),
+ .rx_phfifounderflow (),
+ .rx_phfifowrdisable (),
+ .rx_powerdown (),
+ .rx_recovclkout (),
+ .rx_revbitorderwa (),
+ .rx_revbyteorderwa (),
+ .rx_rlv (),
+ .rx_rmfifoalmostempty (),
+ .rx_rmfifoalmostfull (),
+ .rx_rmfifodatadeleted (),
+ .rx_rmfifodatainserted (),
+ .rx_rmfifoempty (),
+ .rx_rmfifofull (),
+ .rx_rmfifordena (),
+ .rx_rmfiforeset (),
+ .rx_rmfifowrena (),
+ .rx_runningdisp (),
+ .rx_seriallpbken (),
+ .rx_signaldetect (),
+ .tx_clkout (),
+ .tx_coreclk (),
+ .tx_datainfull (),
+ .tx_dispval (),
+ .tx_forcedisp (),
+ .tx_invpolarity (),
+ .tx_phfifooverflow (),
+ .tx_phfiforeset (),
+ .tx_phfifounderflow (),
+ .tx_revparallellpbken ()
+ // synopsys translate_on
+ );
+ defparam
+ alt2gxb_component.starting_channel_number = starting_channel_number,
+ alt2gxb_component.cmu_pll_inclock_period = 10000,
+ alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
+ alt2gxb_component.digitalreset_port_width = 1,
+ alt2gxb_component.enable_fast_recovery_pci_mode = "true",
+ alt2gxb_component.en_local_clk_div_ctrl = "true",
+ alt2gxb_component.equalizer_ctrl_a_setting = 0,
+ alt2gxb_component.equalizer_ctrl_b_setting = 0,
+ alt2gxb_component.equalizer_ctrl_c_setting = 0,
+ alt2gxb_component.equalizer_ctrl_d_setting = 0,
+ alt2gxb_component.equalizer_ctrl_v_setting = 0,
+ alt2gxb_component.equalizer_dcgain_setting = 1,
+ alt2gxb_component.gen_reconfig_pll = "false",
+ alt2gxb_component.loopback_mode = "none",
+ alt2gxb_component.lpm_type = "alt2gxb",
+ alt2gxb_component.number_of_channels = 8,
+ alt2gxb_component.operation_mode = "duplex",
+ alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 5,
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
+ alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
+ alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
+ alt2gxb_component.protocol = "pipe",
+ alt2gxb_component.receiver_termination = "oct_100_ohms",
+ alt2gxb_component.reconfig_dprio_mode = 1,
+ alt2gxb_component.reverse_loopback_mode = "rplb",
+ alt2gxb_component.rx_8b_10b_compatibility_mode = "true",
+ alt2gxb_component.rx_8b_10b_mode = "normal",
+ alt2gxb_component.rx_align_pattern = "0101111100",
+ alt2gxb_component.rx_align_pattern_length = 10,
+ alt2gxb_component.rx_allow_align_polarity_inversion = "false",
+ alt2gxb_component.rx_allow_pipe_polarity_inversion = "true",
+ alt2gxb_component.rx_bandwidth_mode = 1,
+ alt2gxb_component.rx_bitslip_enable = "false",
+ alt2gxb_component.rx_byte_ordering_mode = "none",
+ alt2gxb_component.rx_channel_bonding = "x8",
+ alt2gxb_component.rx_channel_width = 8,
+ alt2gxb_component.rx_common_mode = "0.9v",
+ alt2gxb_component.rx_cru_inclock_period = 10000,
+ alt2gxb_component.rx_cru_pre_divide_by = 1,
+ alt2gxb_component.rx_datapath_protocol = "pipe",
+ alt2gxb_component.rx_data_rate = 2500,
+ alt2gxb_component.rx_data_rate_remainder = 0,
+ alt2gxb_component.rx_disable_auto_idle_insertion = "false",
+ alt2gxb_component.rx_enable_bit_reversal = "false",
+ alt2gxb_component.rx_enable_lock_to_data_sig = "false",
+ alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
+ alt2gxb_component.rx_enable_self_test_mode = "false",
+ alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
+ alt2gxb_component.rx_force_signal_detect = "false",
+ alt2gxb_component.rx_ppmselect = 8,
+ alt2gxb_component.rx_rate_match_back_to_back = "false",
+ alt2gxb_component.rx_rate_match_fifo_mode = "normal",
+ alt2gxb_component.rx_rate_match_ordered_set_based = "false",
+ alt2gxb_component.rx_rate_match_pattern1 = "11010000111010000011",
+ alt2gxb_component.rx_rate_match_pattern2 = "00101111000101111100",
+ alt2gxb_component.rx_rate_match_pattern_size = 20,
+ alt2gxb_component.rx_rate_match_skip_set_based = "false",
+ alt2gxb_component.rx_run_length_enable = "false",
+ alt2gxb_component.rx_signal_detect_threshold = 1,
+ alt2gxb_component.rx_use_align_state_machine = "true",
+ alt2gxb_component.rx_use_clkout = "false",
+ alt2gxb_component.rx_use_coreclk = "false",
+ alt2gxb_component.rx_use_cruclk = "true",
+ alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
+ alt2gxb_component.rx_use_deskew_fifo = "false",
+ alt2gxb_component.rx_use_double_data_mode = "false",
+ alt2gxb_component.rx_use_pipe8b10binvpolarity = "true",
+ alt2gxb_component.rx_use_rate_match_pattern1_only = "false",
+ alt2gxb_component.transmitter_termination = "oct_100_ohms",
+ alt2gxb_component.tx_8b_10b_compatibility_mode = "true",
+ alt2gxb_component.tx_8b_10b_mode = "normal",
+ alt2gxb_component.tx_allow_polarity_inversion = "false",
+ alt2gxb_component.tx_analog_power = "1.2v",
+ alt2gxb_component.tx_channel_bonding = "x8",
+ alt2gxb_component.tx_channel_width = 8,
+ alt2gxb_component.tx_common_mode = "0.6v",
+ alt2gxb_component.tx_data_rate = 2500,
+ alt2gxb_component.tx_data_rate_remainder = 0,
+ alt2gxb_component.tx_enable_bit_reversal = "false",
+ alt2gxb_component.tx_enable_idle_selection = "false",
+ alt2gxb_component.tx_enable_self_test_mode = "false",
+ alt2gxb_component.tx_refclk_divide_by = 1,
+ alt2gxb_component.tx_transmit_protocol = "pipe",
+ alt2gxb_component.tx_use_coreclk = "false",
+ alt2gxb_component.tx_use_double_data_mode = "false",
+ alt2gxb_component.tx_use_serializer_double_data_mode = "false",
+ alt2gxb_component.use_calibration_block = "true",
+ alt2gxb_component.vod_ctrl_setting = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ALT_SIMLIB_GEN STRING "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: PRIVATE: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "1"
+// Retrieval info: PRIVATE: VOD_CTRL_SETTING NUMERIC "800"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500.0000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "62.2"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "62.2"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "1"
+// Retrieval info: PRIVATE: WIZ_EXTERNAL_RX_TERMINATION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EXTERNAL_TX_TERMINATION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500.0000"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "5"
+// Retrieval info: PRIVATE: WIZ_PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_TERMINATION NUMERIC "100"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.85"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "x8"
+// Retrieval info: PRIVATE: WIZ_TCL_KEY STRING "STRATIXIIGX_CONFIG_MODE_PIPE_8X_SINGLE_WIDTH"
+// Retrieval info: PRIVATE: WIZ_TX_TERMINATION NUMERIC "100"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.6"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.2"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: CMU_PLL_INCLOCK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL NUMERIC "3"
+// Retrieval info: CONSTANT: DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: ENABLE_FAST_RECOVERY_PCI_MODE STRING "true"
+// Retrieval info: CONSTANT: EN_LOCAL_CLK_DIV_CTRL STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt2gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "5"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "rplb"
+// Retrieval info: CONSTANT: RX_8B_10B_COMPATIBILITY_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BANDWIDTH_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "none"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x8"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.9v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_CRU_PRE_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DISABLE_AUTO_IDLE_INSERTION STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_BACK_TO_BACK STRING "false"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_ORDERED_SET_BASED STRING "false"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_SKIP_SET_BASED STRING "false"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "1"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_COMPATIBILITY_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.2v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x8"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.6v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_IDLE_SELECTION STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_REFCLK_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 2 0 OUTPUT NODEFVAL "coreclkout[1..0]"
+// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 8 0 INPUT NODEFVAL "pipe8b10binvpolarity[7..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 8 0 OUTPUT NODEFVAL "pipedatavalid[7..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 8 0 OUTPUT NODEFVAL "pipeelecidle[7..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 8 0 OUTPUT NODEFVAL "pipephydonestatus[7..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 24 0 OUTPUT NODEFVAL "pipestatus[23..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 2 0 OUTPUT NODEFVAL "pll_locked[1..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 16 0 INPUT NODEFVAL "powerdn[15..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 2 0 OUTPUT NODEFVAL "reconfig_fromgxb[1..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 8 0 INPUT GND "rx_cruclk[7..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 8 0 INPUT NODEFVAL "rx_datain[7..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_disperr 0 0 8 0 OUTPUT NODEFVAL "rx_disperr[7..0]"
+// Retrieval info: USED_PORT: rx_errdetect 0 0 8 0 OUTPUT NODEFVAL "rx_errdetect[7..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 8 0 OUTPUT NODEFVAL "rx_freqlocked[7..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 8 0 OUTPUT NODEFVAL "rx_pll_locked[7..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 8 0 OUTPUT NODEFVAL "tx_dataout[7..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 8 0 INPUT NODEFVAL "tx_detectrxloop[7..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 8 0 INPUT NODEFVAL "tx_forcedispcompliance[7..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 8 0 INPUT NODEFVAL "tx_forceelecidle[7..0]"
+// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 8 0 tx_detectrxloop 0 0 8 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 8 0 tx_forcedispcompliance 0 0 8 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 8 0 @pipedatavalid 0 0 8 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 16 0 powerdn 0 0 16 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 8 0 @pipeelecidle 0 0 8 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 24 0 @pipestatus 0 0 24 0
+// Retrieval info: CONNECT: rx_errdetect 0 0 8 0 @rx_errdetect 0 0 8 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 8 0 @rx_pll_locked 0 0 8 0
+// Retrieval info: CONNECT: coreclkout 0 0 2 0 @coreclkout 0 0 2 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 8 0 pipe8b10binvpolarity 0 0 8 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
+// Retrieval info: CONNECT: pll_locked 0 0 2 0 @pll_locked 0 0 2 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 8 0 rx_cruclk 0 0 8 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 8 0 @tx_dataout 0 0 8 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 2 0 @reconfig_fromgxb 0 0 2 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 8 0 @rx_freqlocked 0 0 8 0
+// Retrieval info: CONNECT: @rx_datain 0 0 8 0 rx_datain 0 0 8 0
+// Retrieval info: CONNECT: rx_disperr 0 0 8 0 @rx_disperr 0 0 8 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 8 0 @pipephydonestatus 0 0 8 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 8 0 tx_forceelecidle 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x8d_10000.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x8d_10000.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x8d_10000.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x8d_10000.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x8d_10000_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2sgx_x8d_10000_bb.v FALSE FALSE
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..ef8db0b8e57b5216afd8a204649ffbde9cd4abc0
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v
@@ -0,0 +1,1319 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt_c3gxb
+
+// ============================================================
+// File Name: altpcie_serdes_3cgx_x1d_gen1_08p.v
+// Megafunction Name(s):
+// alt_c3gxb
+//
+// Simulation Library Files(s):
+// altera_mf;cycloneiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" equalization_setting=1 equalizer_dcgain_setting=1 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="2" pll_inclk_period=10000 pll_multiply_by="25" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="pcie" receiver_termination="oct_100_ohms" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=16 rx_common_mode="0.82v" rx_datapath_protocol="pipe" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altpcie_serdes_3cgx_x1d_gen1_08p" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_bonding="indv" tx_channel_width=16 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="low" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_areset pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle intended_device_family="Cyclone IV GX"
+//VERSION_BEGIN 10.0SP1 cbx_alt_c3gxb 2010:08:18:21:06:53:SJ cbx_altclkbuf 2010:08:18:21:06:53:SJ cbx_altiobuf_bidir 2010:08:18:21:06:53:SJ cbx_altiobuf_in 2010:08:18:21:06:53:SJ cbx_altiobuf_out 2010:08:18:21:06:53:SJ cbx_altpll 2010:08:18:21:06:53:SJ cbx_cycloneii 2010:08:18:21:06:53:SJ cbx_lpm_add_sub 2010:08:18:21:06:53:SJ cbx_lpm_compare 2010:08:18:21:06:53:SJ cbx_lpm_decode 2010:08:18:21:06:53:SJ cbx_lpm_mux 2010:08:18:21:06:53:SJ cbx_mgl 2010:08:18:21:24:06:SJ cbx_stingray 2010:08:18:21:06:53:SJ cbx_stratix 2010:08:18:21:06:53:SJ cbx_stratixii 2010:08:18:21:06:54:SJ cbx_stratixiii 2010:08:18:21:06:54:SJ cbx_stratixv 2010:08:18:21:06:54:SJ cbx_util_mgl 2010:08:18:21:06:53:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_3cgx_x1d_gen1_08p_alt_c3gxb_lq48
+ (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_areset,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_clkout,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) ;
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ input [0:0] pll_areset;
+ input [0:0] pll_inclk;
+ output [0:0] pll_locked;
+ input [1:0] powerdn;
+ input reconfig_clk;
+ output [4:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ output [1:0] rx_ctrldetect;
+ input [0:0] rx_datain;
+ output [15:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ output [0:0] tx_dataout;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [0:0] pipe8b10binvpolarity;
+ tri0 [0:0] pll_areset;
+ tri0 [1:0] powerdn;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [1:0] tx_ctrlenable;
+ tri0 [15:0] tx_datain;
+ tri0 [0:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [0:0] tx_forcedispcompliance;
+ tri0 [0:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire [5:0] wire_pll0_clk;
+ wire wire_pll0_fref;
+ wire wire_pll0_icdrclk;
+ wire wire_pll0_locked;
+ wire wire_cal_blk0_nonusertocmu;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxanalogresetout;
+ wire [3:0] wire_cent_unit0_rxcrupowerdown;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [3:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire [1199:0] wire_cent_unit0_rxpmadprioout;
+ wire [3:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [3:0] wire_cent_unit0_txdividerpowerdown;
+ wire [3:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire [1199:0] wire_cent_unit0_txpmadprioout;
+ wire wire_receive_pcs0_cdrctrlearlyeios;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire [1:0] wire_receive_pcs0_ctrldetect;
+ wire [19:0] wire_receive_pcs0_dataout;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [1:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [1:0] wire_receive_pcs0_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_freqlocked;
+ wire wire_receive_pma0_locktorefout;
+ wire [9:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire [9:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire wire_transmit_pcs0_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [0:0] cent_unit_quadresetout;
+ wire [3:0] cent_unit_rxcrupowerdn;
+ wire [3:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1199:0] cent_unit_rxpmadprioin;
+ wire [1199:0] cent_unit_rxpmadprioout;
+ wire [599:0] cent_unit_tx_dprioin;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [3:0] cent_unit_txdividerpowerdown;
+ wire [599:0] cent_unit_txdprioout;
+ wire [3:0] cent_unit_txobpowerdn;
+ wire [1199:0] cent_unit_txpmadprioin;
+ wire [1199:0] cent_unit_txpmadprioout;
+ wire [3:0] fixedclk_to_cmu;
+ wire [2:0] grayelecidleinfersel_from_tx;
+ wire [0:0] int_pipeenrevparallellpbkfromtx;
+ wire [0:0] nonusertocmu_out;
+ wire [0:0] pipedatavalid_out;
+ wire [0:0] pipeelecidle_out;
+ wire [0:0] pll_powerdown;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [3:0] rx_analogreset_in;
+ wire [3:0] rx_analogreset_out;
+ wire [0:0] rx_coreclk_in;
+ wire [0:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [2:0] rx_elecidleinfersel;
+ wire [0:0] rx_enapatternalign;
+ wire [0:0] rx_locktodata;
+ wire [0:0] rx_locktorefclk_wire;
+ wire [15:0] rx_out_wire;
+ wire [1:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [0:0] rx_phfifordenable;
+ wire [0:0] rx_phfiforeset;
+ wire [0:0] rx_phfifowrdisable;
+ wire [0:0] rx_pll_pfdrefclkout_wire;
+ wire [4:0] rx_pma_analogtestbus;
+ wire [0:0] rx_pma_clockout;
+ wire [9:0] rx_pma_recoverdataout_wire;
+ wire [1199:0] rx_pmadprioin_wire;
+ wire [1199:0] rx_pmadprioout;
+ wire [0:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [0:0] rx_prbscidenable;
+ wire [19:0] rx_revparallelfdbkdata;
+ wire [0:0] rx_rmfiforeset;
+ wire [0:0] rx_signaldetect_wire;
+ wire [3:0] tx_analogreset_out;
+ wire [0:0] tx_clkout_int_wire;
+ wire [0:0] tx_core_clkout_wire;
+ wire [0:0] tx_coreclk_in;
+ wire [15:0] tx_datain_wire;
+ wire [9:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [599:0] tx_dprioin_wire;
+ wire [1:0] tx_forcedisp_wire;
+ wire [0:0] tx_invpolarity;
+ wire [0:0] tx_localrefclk;
+ wire [0:0] tx_pcs_forceelecidleout;
+ wire [0:0] tx_phfiforeset;
+ wire [1:0] tx_pipepowerdownout;
+ wire [3:0] tx_pipepowerstateout;
+ wire [0:0] tx_pma_fastrefclk0in;
+ wire [0:0] tx_pma_refclk0in;
+ wire [0:0] tx_pma_refclk0inpulse;
+ wire [1199:0] tx_pmadprioin_wire;
+ wire [1199:0] tx_pmadprioout;
+ wire [0:0] tx_revparallellpbken;
+ wire [0:0] tx_rxdetectvalidout;
+ wire [0:0] tx_rxfoundout;
+ wire [599:0] tx_txdprioout;
+ wire [0:0] txdataout;
+ wire [0:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ altpll pll0
+ (
+ .activeclock(),
+ .areset(pll_powerdown[0]),
+ .clk(wire_pll0_clk),
+ .clkbad(),
+ .clkloss(),
+ .enable0(),
+ .enable1(),
+ .extclk(),
+ .fbout(),
+ .fref(wire_pll0_fref),
+ .icdrclk(wire_pll0_icdrclk),
+ .inclk({{1{1'b0}}, pll_inclk[0]}),
+ .locked(wire_pll0_locked),
+ .phasedone(),
+ .scandataout(),
+ .scandone(),
+ .sclkout0(),
+ .sclkout1(),
+ .vcooverrange(),
+ .vcounderrange()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clkena({6{1'b1}}),
+ .clkswitch(1'b0),
+ .configupdate(1'b0),
+ .extclkena({4{1'b1}}),
+ .fbin(1'b1),
+ .pfdena(1'b1),
+ .phasecounterselect({4{1'b1}}),
+ .phasestep(1'b1),
+ .phaseupdown(1'b1),
+ .pllena(1'b1),
+ .scanaclr(1'b0),
+ .scanclk(1'b0),
+ .scanclkena(1'b1),
+ .scandata(1'b0),
+ .scanread(1'b0),
+ .scanwrite(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ pll0.bandwidth_type = "AUTO",
+ pll0.clk0_divide_by = 2,
+ pll0.clk0_multiply_by = 25,
+ pll0.clk1_divide_by = 10,
+ pll0.clk1_multiply_by = 25,
+ pll0.clk2_divide_by = 10,
+ pll0.clk2_duty_cycle = 20,
+ pll0.clk2_multiply_by = 25,
+ pll0.dpa_divide_by = 2,
+ pll0.dpa_multiply_by = 25,
+ pll0.inclk0_input_frequency = 10000,
+ pll0.operation_mode = "no_compensation",
+ pll0.intended_device_family = "Cyclone IV GX",
+ pll0.lpm_type = "altpll";
+ cycloneiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ cycloneiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .coreclkout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkout(),
+ .rxanalogreset({rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpmadprioin({cent_unit_rxpmadprioin[1199:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txctrl({4{1'b0}}),
+ .txctrlout(),
+ .txdatain({32{1'b0}}),
+ .txdataout(),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout(),
+ .txpmadprioin({cent_unit_txpmadprioin[1199:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .pmacramtest(1'b0),
+ .refclkdig(1'b0),
+ .rxcoreclk(1'b0),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .scanclk(1'b0),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({2000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.dprio_config_mode = 6'h01,
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_channel_bonding = "none",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "local reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_channel_bonding = "none",
+ cent_unit0.tx0_rd_clk_mux_select = "central",
+ cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_coreclk_out_post_divider = "false",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
+ cycloneiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[9:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifooverflow(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .revbitorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .refclk(1'b0),
+ .revbyteorderwa(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_cid_mode_enable = "true",
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "none",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "local reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_pipe_enable = "true",
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 32,
+ receive_pcs0.rxstatus_error_report_mode = 1,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
+ cycloneiv_hssi_rx_pma receive_pma0
+ (
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .crupowerdn(cent_unit_rxcrupowerdn[0]),
+ .datain(rx_datain[0]),
+ .datastrobeout(),
+ .deserclock(rx_deserclock_in[0]),
+ .diagnosticlpbkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlocked(wire_receive_pma0_freqlocked),
+ .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dpashift(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.effective_data_rate = "2500 Mbps",
+ receive_pma0.enable_local_divider = "false",
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "false",
+ receive_pma0.enable_pd2_deadzone_detection = "true",
+ receive_pma0.enable_second_order_loop = "false",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eq_setting = 1,
+ receive_pma0.force_signal_detect = "false",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.loop_1_digital_filter = 8,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.power_down_pd2_clocks = "false",
+ receive_pma0.ppm_gen1_2_xcnt_en = 1,
+ receive_pma0.ppm_post_eidle = 0,
+ receive_pma0.ppmselect = 8,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.signal_detect_hysteresis = 4,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma0.signal_detect_loss_threshold = 3,
+ receive_pma0.termination = "OCT 85 Ohms",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
+ cycloneiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrlenable({tx_ctrlenable[1:0]}),
+ .datain({{4{1'b0}}, tx_datain_wire[15:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({2{tx_forceelecidle[0]}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({tx_forcedisp_wire[1:0]}),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifooverflow(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(),
+ .pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(1'b0),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdenablesync(),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrlenable(),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({22{1'b0}}),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .refclk(1'b0),
+ .xgmctrl(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "none",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 4,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "local",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
+ cycloneiv_hssi_tx_pma transmit_pma0
+ (
+ .cgbpowerdn(cent_unit_txdividerpowerdown[0]),
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({tx_dataout_pcs_to_pma[9:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in(tx_pma_fastrefclk0in[0]),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in(tx_pma_refclk0in[0]),
+ .refclk0inpulse(tx_pma_refclk0inpulse[0]),
+ .reverselpbkin(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .diagnosticlpbkin(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.effective_data_rate = "2500 Mbps",
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.preemp_tap_1 = 1,
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "low",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_rx_detect = "true",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b0,
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]},
+ cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
+ cent_unit_rxpmadprioin = {{900{1'b0}}, rx_pmadprioout[299:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1199:0]},
+ cent_unit_tx_dprioin = {{450{1'b0}}, tx_txdprioout[149:0]},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]},
+ cent_unit_txpmadprioin = {{900{1'b0}}, tx_pmadprioout[299:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1199:0]},
+ fixedclk_to_cmu = {4{reconfig_clk}},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs0_grayelecidleinferselout},
+ int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs0_pipeenrevparallellpbkout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[0]},
+ pipedatavalid_out = {wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[0]},
+ pipeelecidle_out = {wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs0_pipestatus},
+ pll_locked = {wire_pll0_locked},
+ pll_powerdown = 1'b0,
+ reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ rx_analogreset_in = {{3{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]},
+ rx_coreclk_in = {tx_core_clkout_wire[0]},
+ rx_ctrldetect = {wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[15:0]},
+ rx_deserclock_in = {wire_pll0_icdrclk},
+ rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_elecidleinfersel = {3{1'b0}},
+ rx_enapatternalign = 1'b0,
+ rx_freqlocked = {(wire_receive_pma0_freqlocked & (~ rx_analogreset[0]))},
+ rx_locktodata = 1'b0,
+ rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
+ rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = 1'b1,
+ rx_phfiforeset = 1'b0,
+ rx_phfifowrdisable = 1'b0,
+ rx_pll_pfdrefclkout_wire = {wire_pll0_fref},
+ rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]},
+ rx_pma_clockout = {wire_receive_pma0_clockout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]},
+ rx_pmadprioin_wire = {{900{1'b0}}, cent_unit_rxpmadprioout[299:0]},
+ rx_pmadprioout = {{900{1'b0}}, wire_receive_pma0_dprioout},
+ rx_powerdown = 1'b0,
+ rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]},
+ rx_prbscidenable = 1'b0,
+ rx_revparallelfdbkdata = {wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = 1'b0,
+ rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs0_syncstatus[1:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]},
+ tx_clkout = {tx_core_clkout_wire[0]},
+ tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
+ tx_core_clkout_wire = {tx_clkout_int_wire[0]},
+ tx_coreclk_in = {tx_clkout_int_wire[0]},
+ tx_datain_wire = {tx_datain[15:0]},
+ tx_dataout = {txdataout[0]},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]},
+ tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_dprioin_wire = {{450{1'b0}}, cent_unit_txdprioout[149:0]},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = 1'b0,
+ tx_localrefclk = {wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = 1'b0,
+ tx_pipepowerdownout = {wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs0_pipepowerstateout},
+ tx_pma_fastrefclk0in = {wire_pll0_clk[0]},
+ tx_pma_refclk0in = {wire_pll0_clk[1]},
+ tx_pma_refclk0inpulse = {wire_pll0_clk[2]},
+ tx_pmadprioin_wire = {{900{1'b0}}, cent_unit_txpmadprioout[299:0]},
+ tx_pmadprioout = {{900{1'b0}}, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = 1'b0,
+ tx_rxdetectvalidout = {wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
+ txdataout = {wire_transmit_pma0_dataout},
+ txdetectrxout = {wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+ initial/*synthesis enable_verilog_initial_construct*/
+ begin
+ $display("Warning: MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) alt_c3gxb|receiver_termination The value assigned is oct_100_ohms and the valid value list is OCT_85_OHMS|OCT_150_OHMS");
+ end
+endmodule //altpcie_serdes_3cgx_x1d_gen1_08p_alt_c3gxb_lq48
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_3cgx_x1d_gen1_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_areset,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ input [0:0] pll_areset;
+ input [0:0] pll_inclk;
+ input [1:0] powerdn;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ output [0:0] pll_locked;
+ output [4:0] reconfig_fromgxb;
+ output [1:0] rx_ctrldetect;
+ output [15:0] rx_dataout;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [0:0] sub_wire0;
+ wire [1:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [4:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [2:0] sub_wire6;
+ wire [1:0] sub_wire7;
+ wire [15:0] sub_wire8;
+ wire [0:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [1:0] sub_wire12;
+ wire [0:0] pipedatavalid = sub_wire0[0:0];
+ wire [1:0] rx_patterndetect = sub_wire1[1:0];
+ wire [0:0] pipephydonestatus = sub_wire2[0:0];
+ wire [0:0] pll_locked = sub_wire3[0:0];
+ wire [4:0] reconfig_fromgxb = sub_wire4[4:0];
+ wire [0:0] rx_freqlocked = sub_wire5[0:0];
+ wire [2:0] pipestatus = sub_wire6[2:0];
+ wire [1:0] rx_syncstatus = sub_wire7[1:0];
+ wire [15:0] rx_dataout = sub_wire8[15:0];
+ wire [0:0] pipeelecidle = sub_wire9[0:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [0:0] tx_dataout = sub_wire11[0:0];
+ wire [1:0] rx_ctrldetect = sub_wire12[1:0];
+
+ altpcie_serdes_3cgx_x1d_gen1_08p_alt_c3gxb_lq48 altpcie_serdes_3cgx_x1d_gen1_08p_alt_c3gxb_lq48_component (
+ .pll_inclk (pll_inclk),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_detectrxloop (tx_detectrxloop),
+ .cal_blk_clk (cal_blk_clk),
+ .tx_forceelecidle (tx_forceelecidle),
+ .rx_datain (rx_datain),
+ .rx_digitalreset (rx_digitalreset),
+ .pll_areset (pll_areset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .tx_datain (tx_datain),
+ .tx_digitalreset (tx_digitalreset),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .reconfig_clk (reconfig_clk),
+ .rx_analogreset (rx_analogreset),
+ .powerdn (powerdn),
+ .tx_ctrlenable (tx_ctrlenable),
+ .pipedatavalid (sub_wire0),
+ .rx_patterndetect (sub_wire1),
+ .pipephydonestatus (sub_wire2),
+ .pll_locked (sub_wire3),
+ .reconfig_fromgxb (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .pipestatus (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .rx_dataout (sub_wire8),
+ .pipeelecidle (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .tx_dataout (sub_wire11),
+ .rx_ctrldetect (sub_wire12));
+ defparam
+ altpcie_serdes_3cgx_x1d_gen1_08p_alt_c3gxb_lq48_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: pll_divide_by STRING "2"
+// Retrieval info: CONSTANT: pll_multiply_by STRING "25"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
+// Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: top_module_name STRING "altpcie_serdes_3cgx_x1d_gen1_08p"
+// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 2 0 OUTPUT NODEFVAL "rx_ctrldetect[1..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 16 0 OUTPUT NODEFVAL "rx_dataout[15..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 2 0 INPUT NODEFVAL "tx_ctrlenable[1..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 16 0 INPUT NODEFVAL "tx_datain[15..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
+// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 2 0 tx_ctrlenable 0 0 2 0
+// Retrieval info: CONNECT: @tx_datain 0 0 16 0 tx_datain 0 0 16 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
+// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 2 0 @rx_ctrldetect 0 0 2 0
+// Retrieval info: CONNECT: rx_dataout 0 0 16 0 @rx_dataout 0 0 16 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_08p.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_08p.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_08p.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_08p.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_08p.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_08p_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_08p_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: LIB_FILE: cycloneiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v
new file mode 100644
index 0000000000000000000000000000000000000000..3b339e1e31598076b2473f0154c92680d1c07843
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v
@@ -0,0 +1,1396 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt_c3gxb
+
+// ============================================================
+// File Name: altpcie_serdes_3cgx_x1d_gen1_16p.v
+// Megafunction Name(s):
+// alt_c3gxb
+//
+// Simulation Library Files(s):
+// altera_mf;cycloneiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.1 Internal Build 87 08/09/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" equalization_setting=1 equalizer_dcgain_setting=1 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="2" pll_inclk_period=10000 pll_multiply_by="25" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=18 protocol="pcie" receiver_termination="oct_100_ohms" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=16 rx_common_mode="0.82v" rx_datapath_protocol="pipe" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altpcie_serdes_3cgx_x1d_gen1_16p" transmitter_termination="oct_100_ohms" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_bonding="indv" tx_channel_width=16 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="low" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=5 cal_blk_clk fixedclk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_areset pll_inclk pll_locked pll_powerdown powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_rlv rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle intended_device_family="Cyclone IV GX"
+//VERSION_BEGIN 10.1 cbx_alt_c3gxb 2010:08:09:21:16:11:SJ cbx_altclkbuf 2010:08:09:21:16:11:SJ cbx_altiobuf_bidir 2010:08:09:21:16:11:SJ cbx_altiobuf_in 2010:08:09:21:16:11:SJ cbx_altiobuf_out 2010:08:09:21:16:11:SJ cbx_altpll 2010:08:09:21:16:11:SJ cbx_cycloneii 2010:08:09:21:16:11:SJ cbx_lpm_add_sub 2010:08:09:21:16:11:SJ cbx_lpm_compare 2010:08:09:21:16:11:SJ cbx_lpm_decode 2010:08:09:21:16:11:SJ cbx_lpm_mux 2010:08:09:21:16:11:SJ cbx_mgl 2010:08:09:21:18:07:SJ cbx_stingray 2010:08:09:21:16:10:SJ cbx_stratix 2010:08:09:21:16:11:SJ cbx_stratixii 2010:08:09:21:16:11:SJ cbx_stratixiii 2010:08:09:21:16:11:SJ cbx_stratixv 2010:08:09:21:16:11:SJ cbx_util_mgl 2010:08:09:21:16:11:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
+module altpcie_serdes_3cgx_x1d_gen1_16p_alt_c3gxb
+ (
+ cal_blk_clk,
+ fixedclk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_areset,
+ pll_inclk,
+ pll_locked,
+ pll_powerdown,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_disperr,
+ rx_errdetect,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_rlv,
+ rx_syncstatus,
+ tx_clkout,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) /* synthesis synthesis_clearbox=2 */;
+ input cal_blk_clk;
+ input fixedclk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ input [0:0] pll_areset;
+ input [0:0] pll_inclk;
+ output [0:0] pll_locked;
+ input [0:0] pll_powerdown;
+ input [1:0] powerdn;
+ input reconfig_clk;
+ output [4:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ output [1:0] rx_ctrldetect;
+ input [0:0] rx_datain;
+ output [15:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [1:0] rx_disperr;
+ output [1:0] rx_errdetect;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [0:0] rx_rlv;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ output [0:0] tx_dataout;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 fixedclk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [0:0] pipe8b10binvpolarity;
+ tri0 [0:0] pll_areset;
+ tri0 [0:0] pll_powerdown;
+ tri0 [1:0] powerdn;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [1:0] tx_ctrlenable;
+ tri0 [15:0] tx_datain;
+ tri0 [0:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [0:0] tx_forcedispcompliance;
+ tri0 [0:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire [5:0] wire_pll0_clk;
+ wire wire_pll0_fref;
+ wire wire_pll0_icdrclk;
+ wire wire_pll0_locked;
+ wire wire_cal_blk0_nonusertocmu;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxanalogresetout;
+ wire [3:0] wire_cent_unit0_rxcrupowerdown;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [3:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire [1199:0] wire_cent_unit0_rxpmadprioout;
+ wire [3:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [3:0] wire_cent_unit0_txdividerpowerdown;
+ wire [3:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire [1199:0] wire_cent_unit0_txpmadprioout;
+ wire wire_receive_pcs0_cdrctrlearlyeios;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire [1:0] wire_receive_pcs0_ctrldetect;
+ wire [19:0] wire_receive_pcs0_dataout;
+ wire [1:0] wire_receive_pcs0_disperr;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [1:0] wire_receive_pcs0_errdetect;
+ wire [1:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire wire_receive_pcs0_rlv;
+ wire [1:0] wire_receive_pcs0_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_freqlocked;
+ wire wire_receive_pma0_locktorefout;
+ wire [9:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire [9:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire wire_transmit_pcs0_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ reg [0:0] fixedclk_div;
+ reg [1:0] reconfig_togxb_busy_reg;
+ wire cal_blk_powerdown;
+ wire [0:0] cent_unit_quadresetout;
+ wire [3:0] cent_unit_rxcrupowerdn;
+ wire [3:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1199:0] cent_unit_rxpmadprioin;
+ wire [1199:0] cent_unit_rxpmadprioout;
+ wire [599:0] cent_unit_tx_dprioin;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [3:0] cent_unit_txdividerpowerdown;
+ wire [599:0] cent_unit_txdprioout;
+ wire [3:0] cent_unit_txobpowerdn;
+ wire [1199:0] cent_unit_txpmadprioin;
+ wire [1199:0] cent_unit_txpmadprioout;
+ wire [0:0] fixedclk_div_in;
+ wire [0:0] fixedclk_enable;
+ wire [3:0] fixedclk_fast;
+ wire [0:0] fixedclk_sel;
+ wire [3:0] fixedclk_to_cmu;
+ wire [2:0] grayelecidleinfersel_from_tx;
+ wire [0:0] int_pipeenrevparallellpbkfromtx;
+ wire [0:0] nonusertocmu_out;
+ wire [0:0] pipedatavalid_out;
+ wire [0:0] pipeelecidle_out;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [3:0] rx_analogreset_in;
+ wire [3:0] rx_analogreset_out;
+ wire [0:0] rx_coreclk_in;
+ wire [0:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [2:0] rx_elecidleinfersel;
+ wire [0:0] rx_enapatternalign;
+ wire [0:0] rx_locktodata;
+ wire [0:0] rx_locktorefclk_wire;
+ wire [15:0] rx_out_wire;
+ wire [1:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [0:0] rx_phfifordenable;
+ wire [0:0] rx_phfiforeset;
+ wire [0:0] rx_phfifowrdisable;
+ wire [0:0] rx_pll_pfdrefclkout_wire;
+ wire [4:0] rx_pma_analogtestbus;
+ wire [0:0] rx_pma_clockout;
+ wire [9:0] rx_pma_recoverdataout_wire;
+ wire [1199:0] rx_pmadprioin_wire;
+ wire [1199:0] rx_pmadprioout;
+ wire [0:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [0:0] rx_prbscidenable;
+ wire [19:0] rx_revparallelfdbkdata;
+ wire [0:0] rx_rmfiforeset;
+ wire [0:0] rx_signaldetect_wire;
+ wire [3:0] tx_analogreset_out;
+ wire [0:0] tx_clkout_int_wire;
+ wire [0:0] tx_core_clkout_wire;
+ wire [0:0] tx_coreclk_in;
+ wire [15:0] tx_datain_wire;
+ wire [9:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [599:0] tx_dprioin_wire;
+ wire [1:0] tx_forcedisp_wire;
+ wire [0:0] tx_invpolarity;
+ wire [0:0] tx_localrefclk;
+ wire [0:0] tx_pcs_forceelecidleout;
+ wire [0:0] tx_phfiforeset;
+ wire [1:0] tx_pipepowerdownout;
+ wire [3:0] tx_pipepowerstateout;
+ wire [0:0] tx_pma_fastrefclk0in;
+ wire [0:0] tx_pma_refclk0in;
+ wire [0:0] tx_pma_refclk0inpulse;
+ wire [1199:0] tx_pmadprioin_wire;
+ wire [1199:0] tx_pmadprioout;
+ wire [0:0] tx_revparallellpbken;
+ wire [0:0] tx_rxdetectvalidout;
+ wire [0:0] tx_rxfoundout;
+ wire [599:0] tx_txdprioout;
+ wire [0:0] txdataout;
+ wire [0:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ altpll pll0
+ (
+ .activeclock(),
+ .areset(pll_powerdown[0]),
+ .clk(wire_pll0_clk),
+ .clkbad(),
+ .clkloss(),
+ .enable0(),
+ .enable1(),
+ .extclk(),
+ .fbout(),
+ .fref(wire_pll0_fref),
+ .icdrclk(wire_pll0_icdrclk),
+ .inclk({{1{1'b0}}, pll_inclk[0]}),
+ .locked(wire_pll0_locked),
+ .phasedone(),
+ .scandataout(),
+ .scandone(),
+ .sclkout0(),
+ .sclkout1(),
+ .vcooverrange(),
+ .vcounderrange()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clkena({6{1'b1}}),
+ .clkswitch(1'b0),
+ .configupdate(1'b0),
+ .extclkena({4{1'b1}}),
+ .fbin(1'b1),
+ .pfdena(1'b1),
+ .phasecounterselect({4{1'b1}}),
+ .phasestep(1'b1),
+ .phaseupdown(1'b1),
+ .pllena(1'b1),
+ .scanaclr(1'b0),
+ .scanclk(1'b0),
+ .scanclkena(1'b1),
+ .scandata(1'b0),
+ .scanread(1'b0),
+ .scanwrite(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ pll0.bandwidth_type = "AUTO",
+ pll0.clk0_divide_by = 2,
+ pll0.clk0_multiply_by = 25,
+ pll0.clk1_divide_by = 10,
+ pll0.clk1_multiply_by = 25,
+ pll0.clk2_divide_by = 10,
+ pll0.clk2_duty_cycle = 20,
+ pll0.clk2_multiply_by = 25,
+ pll0.dpa_divide_by = 2,
+ pll0.dpa_multiply_by = 25,
+ pll0.inclk0_input_frequency = 10000,
+ pll0.operation_mode = "no_compensation",
+ pll0.intended_device_family = "Cyclone IV GX",
+ pll0.lpm_type = "altpll";
+ cycloneiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ cycloneiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .coreclkout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkout(),
+ .rxanalogreset({rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpmadprioin({cent_unit_rxpmadprioin[1199:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txctrl({4{1'b0}}),
+ .txctrlout(),
+ .txdatain({32{1'b0}}),
+ .txdataout(),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout(),
+ .txpmadprioin({cent_unit_txpmadprioin[1199:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .pmacramtest(1'b0),
+ .refclkdig(1'b0),
+ .rxcoreclk(1'b0),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .scanclk(1'b0),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({2000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.dprio_config_mode = 6'h01,
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_channel_bonding = "none",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "local reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_channel_bonding = "none",
+ cent_unit0.tx0_rd_clk_mux_select = "central",
+ cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_coreclk_out_post_divider = "false",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
+ cycloneiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[9:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disperr(wire_receive_pcs0_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(wire_receive_pcs0_errdetect),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifooverflow(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .revbitorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(wire_receive_pcs0_rlv),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .refclk(1'b0),
+ .revbyteorderwa(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_cid_mode_enable = "true",
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "none",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "local reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_pipe_enable = "true",
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 32,
+ receive_pcs0.rxstatus_error_report_mode = 1,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
+ cycloneiv_hssi_rx_pma receive_pma0
+ (
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .crupowerdn(cent_unit_rxcrupowerdn[0]),
+ .datain(rx_datain[0]),
+ .datastrobeout(),
+ .deserclock(rx_deserclock_in[0]),
+ .diagnosticlpbkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlocked(wire_receive_pma0_freqlocked),
+ .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dpashift(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.effective_data_rate = "2500 Mbps",
+ receive_pma0.enable_local_divider = "false",
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "false",
+ receive_pma0.enable_pd2_deadzone_detection = "true",
+ receive_pma0.enable_second_order_loop = "false",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eq_setting = 1,
+ receive_pma0.force_signal_detect = "false",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.loop_1_digital_filter = 8,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.power_down_pd2_clocks = "false",
+ receive_pma0.ppm_gen1_2_xcnt_en = 1,
+ receive_pma0.ppm_post_eidle = 0,
+ receive_pma0.ppmselect = 8,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.signal_detect_hysteresis = 4,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma0.signal_detect_loss_threshold = 3,
+ receive_pma0.termination = "OCT 85 Ohms",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
+ cycloneiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrlenable({tx_ctrlenable[1:0]}),
+ .datain({{4{1'b0}}, tx_datain_wire[15:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({2{tx_forceelecidle[0]}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({tx_forcedisp_wire[1:0]}),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifooverflow(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(),
+ .pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(1'b0),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdenablesync(),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrlenable(),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({22{1'b0}}),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .refclk(1'b0),
+ .xgmctrl(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "none",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 4,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "local",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
+ cycloneiv_hssi_tx_pma transmit_pma0
+ (
+ .cgbpowerdn(cent_unit_txdividerpowerdown[0]),
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({tx_dataout_pcs_to_pma[9:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in(tx_pma_fastrefclk0in[0]),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in(tx_pma_refclk0in[0]),
+ .refclk0inpulse(tx_pma_refclk0inpulse[0]),
+ .reverselpbkin(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .diagnosticlpbkin(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.effective_data_rate = "2500 Mbps",
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.preemp_tap_1 = 18,
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "low",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_rx_detect = "true",
+ transmit_pma0.vod_selection = 5,
+ transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
+ // synopsys translate_off
+ initial
+ fixedclk_div = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk)
+ fixedclk_div <= (~ fixedclk_div_in);
+ // synopsys translate_off
+ initial
+ reconfig_togxb_busy_reg = 0;
+ // synopsys translate_on
+ always @ ( negedge fixedclk)
+ reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
+ assign
+ cal_blk_powerdown = 1'b0,
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]},
+ cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
+ cent_unit_rxpmadprioin = {{900{1'b0}}, rx_pmadprioout[299:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1199:0]},
+ cent_unit_tx_dprioin = {{450{1'b0}}, tx_txdprioout[149:0]},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]},
+ cent_unit_txpmadprioin = {{900{1'b0}}, tx_pmadprioout[299:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1199:0]},
+ fixedclk_div_in = fixedclk_div,
+ fixedclk_enable = reconfig_togxb_busy_reg[0],
+ fixedclk_fast = {4{1'b1}},
+ fixedclk_sel = reconfig_togxb_busy_reg[1],
+ fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk))},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs0_grayelecidleinferselout},
+ int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs0_pipeenrevparallellpbkout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[0]},
+ pipedatavalid_out = {wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[0]},
+ pipeelecidle_out = {wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs0_pipestatus},
+ pll_locked = {wire_pll0_locked},
+ reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ rx_analogreset_in = {{3{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]},
+ rx_coreclk_in = {tx_core_clkout_wire[0]},
+ rx_ctrldetect = {wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[15:0]},
+ rx_deserclock_in = {wire_pll0_icdrclk},
+ rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_disperr = {wire_receive_pcs0_disperr[1:0]},
+ rx_elecidleinfersel = {3{1'b0}},
+ rx_enapatternalign = 1'b0,
+ rx_errdetect = {wire_receive_pcs0_errdetect[1:0]},
+ rx_freqlocked = {(wire_receive_pma0_freqlocked & (~ rx_analogreset[0]))},
+ rx_locktodata = 1'b0,
+ rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
+ rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = 1'b1,
+ rx_phfiforeset = 1'b0,
+ rx_phfifowrdisable = 1'b0,
+ rx_pll_pfdrefclkout_wire = {wire_pll0_fref},
+ rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]},
+ rx_pma_clockout = {wire_receive_pma0_clockout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]},
+ rx_pmadprioin_wire = {{900{1'b0}}, cent_unit_rxpmadprioout[299:0]},
+ rx_pmadprioout = {{900{1'b0}}, wire_receive_pma0_dprioout},
+ rx_powerdown = 1'b0,
+ rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]},
+ rx_prbscidenable = 1'b0,
+ rx_revparallelfdbkdata = {wire_receive_pcs0_revparallelfdbkdata},
+ rx_rlv = {wire_receive_pcs0_rlv},
+ rx_rmfiforeset = 1'b0,
+ rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs0_syncstatus[1:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]},
+ tx_clkout = {tx_core_clkout_wire[0]},
+ tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
+ tx_core_clkout_wire = {tx_clkout_int_wire[0]},
+ tx_coreclk_in = {tx_clkout_int_wire[0]},
+ tx_datain_wire = {tx_datain[15:0]},
+ tx_dataout = {txdataout[0]},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]},
+ tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_dprioin_wire = {{450{1'b0}}, cent_unit_txdprioout[149:0]},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = 1'b0,
+ tx_localrefclk = {wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = 1'b0,
+ tx_pipepowerdownout = {wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs0_pipepowerstateout},
+ tx_pma_fastrefclk0in = {wire_pll0_clk[0]},
+ tx_pma_refclk0in = {wire_pll0_clk[1]},
+ tx_pma_refclk0inpulse = {wire_pll0_clk[2]},
+ tx_pmadprioin_wire = {{900{1'b0}}, cent_unit_txpmadprioout[299:0]},
+ tx_pmadprioout = {{900{1'b0}}, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = 1'b0,
+ tx_rxdetectvalidout = {wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
+ txdataout = {wire_transmit_pma0_dataout},
+ txdetectrxout = {wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+ initial/*synthesis enable_verilog_initial_construct*/
+ begin
+ $display("Warning: MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) alt_c3gxb|receiver_termination The value assigned is oct_100_ohms and the valid value list is OCT_85_OHMS|OCT_150_OHMS");
+ $display("Warning: MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) alt_c3gxb|transmitter_termination The value assigned is oct_100_ohms and the valid value list is OCT_85_OHMS|OCT_150_OHMS");
+ end
+endmodule //altpcie_serdes_3cgx_x1d_gen1_16p_alt_c3gxb
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_3cgx_x1d_gen1_16p (
+ cal_blk_clk,
+ fixedclk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_areset,
+ pll_inclk,
+ pll_powerdown,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_disperr,
+ rx_errdetect,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_rlv,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout)/* synthesis synthesis_clearbox = 2 */;
+
+ input cal_blk_clk;
+ input fixedclk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ input [0:0] pll_areset;
+ input [0:0] pll_inclk;
+ input [0:0] pll_powerdown;
+ input [1:0] powerdn;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ output [0:0] pll_locked;
+ output [4:0] reconfig_fromgxb;
+ output [1:0] rx_ctrldetect;
+ output [15:0] rx_dataout;
+ output [1:0] rx_disperr;
+ output [1:0] rx_errdetect;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [0:0] rx_rlv;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [1:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [4:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [2:0] sub_wire5;
+ wire [1:0] sub_wire6;
+ wire [1:0] sub_wire7;
+ wire [15:0] sub_wire8;
+ wire [1:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [0:0] sub_wire12;
+ wire [0:0] sub_wire13;
+ wire [1:0] sub_wire14;
+ wire [0:0] sub_wire15;
+ wire [1:0] rx_patterndetect = sub_wire0[1:0];
+ wire [0:0] pipephydonestatus = sub_wire1[0:0];
+ wire [0:0] pll_locked = sub_wire2[0:0];
+ wire [4:0] reconfig_fromgxb = sub_wire3[4:0];
+ wire [0:0] rx_freqlocked = sub_wire4[0:0];
+ wire [2:0] pipestatus = sub_wire5[2:0];
+ wire [1:0] rx_disperr = sub_wire6[1:0];
+ wire [1:0] rx_syncstatus = sub_wire7[1:0];
+ wire [15:0] rx_dataout = sub_wire8[15:0];
+ wire [1:0] rx_errdetect = sub_wire9[1:0];
+ wire [0:0] pipeelecidle = sub_wire10[0:0];
+ wire [0:0] rx_rlv = sub_wire11[0:0];
+ wire [0:0] tx_clkout = sub_wire12[0:0];
+ wire [0:0] tx_dataout = sub_wire13[0:0];
+ wire [1:0] rx_ctrldetect = sub_wire14[1:0];
+ wire [0:0] pipedatavalid = sub_wire15[0:0];
+
+ altpcie_serdes_3cgx_x1d_gen1_16p_alt_c3gxb altpcie_serdes_3cgx_x1d_gen1_16p_alt_c3gxb_component (
+ .reconfig_togxb (reconfig_togxb),
+ .cal_blk_clk (cal_blk_clk),
+ .tx_forceelecidle (tx_forceelecidle),
+ .fixedclk (fixedclk),
+ .rx_datain (rx_datain),
+ .rx_digitalreset (rx_digitalreset),
+ .pll_areset (pll_areset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .pll_powerdown (pll_powerdown),
+ .tx_datain (tx_datain),
+ .tx_digitalreset (tx_digitalreset),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .reconfig_clk (reconfig_clk),
+ .rx_analogreset (rx_analogreset),
+ .powerdn (powerdn),
+ .tx_ctrlenable (tx_ctrlenable),
+ .pll_inclk (pll_inclk),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .pipephydonestatus (sub_wire1),
+ .pll_locked (sub_wire2),
+ .reconfig_fromgxb (sub_wire3),
+ .rx_freqlocked (sub_wire4),
+ .pipestatus (sub_wire5),
+ .rx_disperr (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .rx_dataout (sub_wire8),
+ .rx_errdetect (sub_wire9),
+ .pipeelecidle (sub_wire10),
+ .rx_rlv (sub_wire11),
+ .tx_clkout (sub_wire12),
+ .tx_dataout (sub_wire13),
+ .rx_ctrldetect (sub_wire14),
+ .pipedatavalid (sub_wire15))/* synthesis synthesis_clearbox=2
+ clearbox_macroname = alt_c3gxb
+ clearbox_defparam = "effective_data_rate=2500 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=100.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_hint=CBX_MODULE_PREFIX=altpcie_serdes_3cgx_x1d_gen1_16p;lpm_type=alt_c3gxb;number_of_channels=1;operation_mode=duplex;pll_bandwidth_type=Auto;pll_control_width=1;pll_inclk_period=10000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=18;protocol=pcie;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=indv;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=2500;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=false;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;
+ rx_use_clkout=false;rx_use_coreclk=false;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=true;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_bonding=indv;tx_channel_width=16;tx_clkout_width=1;tx_common_mode=0.65V;tx_data_rate=2500;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=Auto;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=low;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=true;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=5;elec_idle_infer_enable=false;enable_0ppm=false;equalization_setting=1;gxb_powerdown_width=1;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=2;pll_multiply_by=25;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_deskew_pattern=0;rx_dwidth_factor=2;rx_enable_second_order_loop=false;rx_loop_1_digital_filter=8;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=altpcie_serdes_3cgx_x1d_gen1_16p;tx_bitslip_enable=FALSE;tx_dwidth_factor=2;tx_use_external_termination=false;" */;
+ defparam
+ altpcie_serdes_3cgx_x1d_gen1_16p_alt_c3gxb_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "156.25"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "18"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65V"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "5"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: pll_divide_by STRING "2"
+// Retrieval info: CONSTANT: pll_multiply_by STRING "25"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
+// Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_enable_second_order_loop STRING "false"
+// Retrieval info: CONSTANT: rx_loop_1_digital_filter NUMERIC "8"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: top_module_name STRING "altpcie_serdes_3cgx_x1d_gen1_16p"
+// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 2 0 OUTPUT NODEFVAL "rx_ctrldetect[1..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 16 0 OUTPUT NODEFVAL "rx_dataout[15..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_disperr 0 0 2 0 OUTPUT NODEFVAL "rx_disperr[1..0]"
+// Retrieval info: USED_PORT: rx_errdetect 0 0 2 0 OUTPUT NODEFVAL "rx_errdetect[1..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
+// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 2 0 INPUT NODEFVAL "tx_ctrlenable[1..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 16 0 INPUT NODEFVAL "tx_datain[15..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
+// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
+// Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 2 0 tx_ctrlenable 0 0 2 0
+// Retrieval info: CONNECT: @tx_datain 0 0 16 0 tx_datain 0 0 16 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
+// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 2 0 @rx_ctrldetect 0 0 2 0
+// Retrieval info: CONNECT: rx_dataout 0 0 16 0 @rx_dataout 0 0 16 0
+// Retrieval info: CONNECT: rx_disperr 0 0 2 0 @rx_disperr 0 0 2 0
+// Retrieval info: CONNECT: rx_errdetect 0 0 2 0 @rx_errdetect 0 0 2 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
+// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_16p.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_16p.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_16p.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_16p.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_16p.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_16p_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x1d_gen1_16p_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: LIB_FILE: cycloneiv_hssi
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..9d369f9f2d2425dd5f3790bf5c60c94b75fae962
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v
@@ -0,0 +1,1906 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt_c3gxb
+
+// ============================================================
+// File Name: altpcie_serdes_3cgx_x2d_gen1_08p.v
+// Megafunction Name(s):
+// alt_c3gxb
+//
+// Simulation Library Files(s):
+// altera_mf;cycloneiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" equalization_setting=1 equalizer_dcgain_setting=1 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=2 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="2" pll_inclk_period=10000 pll_multiply_by="25" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=18 protocol="pcie" receiver_termination="oct_100_ohms" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x2" rx_channel_width=16 rx_common_mode="0.82v" rx_datapath_protocol="pipe" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altpcie_serdes_3cgx_x2d_gen1_08p" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_bonding="x2" tx_channel_width=16 tx_clkout_width=2 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="low" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=5 cal_blk_clk coreclkout fixedclk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_areset pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle intended_device_family="Cyclone IV GX"
+//VERSION_BEGIN 10.0SP1 cbx_alt_c3gxb 2010:08:18:21:06:53:SJ cbx_altclkbuf 2010:08:18:21:06:53:SJ cbx_altiobuf_bidir 2010:08:18:21:06:53:SJ cbx_altiobuf_in 2010:08:18:21:06:53:SJ cbx_altiobuf_out 2010:08:18:21:06:53:SJ cbx_altpll 2010:08:18:21:06:53:SJ cbx_cycloneii 2010:08:18:21:06:53:SJ cbx_lpm_add_sub 2010:08:18:21:06:53:SJ cbx_lpm_compare 2010:08:18:21:06:53:SJ cbx_lpm_decode 2010:08:18:21:06:53:SJ cbx_lpm_mux 2010:08:18:21:06:53:SJ cbx_mgl 2010:08:18:21:24:06:SJ cbx_stingray 2010:08:18:21:06:53:SJ cbx_stratix 2010:08:18:21:06:53:SJ cbx_stratixii 2010:08:18:21:06:54:SJ cbx_stratixiii 2010:08:18:21:06:54:SJ cbx_stratixv 2010:08:18:21:06:54:SJ cbx_util_mgl 2010:08:18:21:06:53:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 2 cycloneiv_hssi_rx_pma 2 cycloneiv_hssi_tx_pcs 2 cycloneiv_hssi_tx_pma 2 reg 3
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
+module altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78
+ (
+ cal_blk_clk,
+ coreclkout,
+ fixedclk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_areset,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_disperr,
+ rx_errdetect,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) /* synthesis synthesis_clearbox=2 */;
+ input cal_blk_clk;
+ output [0:0] coreclkout;
+ input fixedclk;
+ input [0:0] gxb_powerdown;
+ input [1:0] pipe8b10binvpolarity;
+ output [1:0] pipedatavalid;
+ output [1:0] pipeelecidle;
+ output [1:0] pipephydonestatus;
+ output [5:0] pipestatus;
+ input [0:0] pll_areset;
+ input [0:0] pll_inclk;
+ output [0:0] pll_locked;
+ input [3:0] powerdn;
+ input reconfig_clk;
+ output [4:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ output [3:0] rx_ctrldetect;
+ input [1:0] rx_datain;
+ output [31:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [3:0] rx_disperr;
+ output [3:0] rx_errdetect;
+ output [1:0] rx_freqlocked;
+ output [3:0] rx_patterndetect;
+ output [3:0] rx_syncstatus;
+ input [3:0] tx_ctrlenable;
+ input [31:0] tx_datain;
+ output [1:0] tx_dataout;
+ input [1:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [1:0] tx_forcedispcompliance;
+ input [1:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 fixedclk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [1:0] pipe8b10binvpolarity;
+ tri0 [0:0] pll_areset;
+ tri0 [3:0] powerdn;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [3:0] tx_ctrlenable;
+ tri0 [31:0] tx_datain;
+ tri0 [1:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [1:0] tx_forcedispcompliance;
+ tri0 [1:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire [5:0] wire_pll0_clk;
+ wire wire_pll0_fref;
+ wire wire_pll0_icdrclk;
+ wire wire_pll0_locked;
+ wire wire_cal_blk0_nonusertocmu;
+ wire wire_cent_unit0_coreclkout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire wire_cent_unit0_quadresetout;
+ wire wire_cent_unit0_refclkout;
+ wire [3:0] wire_cent_unit0_rxanalogresetout;
+ wire [3:0] wire_cent_unit0_rxcrupowerdown;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [3:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [1199:0] wire_cent_unit0_rxpmadprioout;
+ wire [3:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [3:0] wire_cent_unit0_txdividerpowerdown;
+ wire [3:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1199:0] wire_cent_unit0_txpmadprioout;
+ wire wire_receive_pcs0_cdrctrlearlyeios;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [1:0] wire_receive_pcs0_ctrldetect;
+ wire [19:0] wire_receive_pcs0_dataout;
+ wire [1:0] wire_receive_pcs0_disperr;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [1:0] wire_receive_pcs0_errdetect;
+ wire [1:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [1:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_cdrctrlearlyeios;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [1:0] wire_receive_pcs1_ctrldetect;
+ wire [19:0] wire_receive_pcs1_dataout;
+ wire [1:0] wire_receive_pcs1_disperr;
+ wire [399:0] wire_receive_pcs1_dprioout;
+ wire [1:0] wire_receive_pcs1_errdetect;
+ wire [1:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire [1:0] wire_receive_pcs1_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_freqlocked;
+ wire wire_receive_pma0_locktorefout;
+ wire [9:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire [7:0] wire_receive_pma1_analogtestbus;
+ wire wire_receive_pma1_clockout;
+ wire [299:0] wire_receive_pma1_dprioout;
+ wire wire_receive_pma1_freqlocked;
+ wire wire_receive_pma1_locktorefout;
+ wire [9:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [9:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire wire_transmit_pcs0_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [9:0] wire_transmit_pcs1_dataout;
+ wire [149:0] wire_transmit_pcs1_dprioout;
+ wire wire_transmit_pcs1_forceelecidleout;
+ wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire wire_transmit_pcs1_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire [299:0] wire_transmit_pma1_dprioout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ reg [0:0] fixedclk_div;
+ reg [1:0] reconfig_togxb_busy_reg;
+ wire cal_blk_powerdown;
+ wire [1:0] cent_unit_quadresetout;
+ wire [1:0] cent_unit_rxcrupowerdn;
+ wire [1:0] cent_unit_rxibpowerdn;
+ wire [799:0] cent_unit_rxpcsdprioin;
+ wire [799:0] cent_unit_rxpcsdprioout;
+ wire [599:0] cent_unit_rxpmadprioin;
+ wire [599:0] cent_unit_rxpmadprioout;
+ wire [299:0] cent_unit_tx_dprioin;
+ wire [1:0] cent_unit_txdetectrxpowerdn;
+ wire [1:0] cent_unit_txdividerpowerdown;
+ wire [299:0] cent_unit_txdprioout;
+ wire [1:0] cent_unit_txobpowerdn;
+ wire [599:0] cent_unit_txpmadprioin;
+ wire [599:0] cent_unit_txpmadprioout;
+ wire [0:0] coreclkout_wire;
+ wire [0:0] fixedclk_div_in;
+ wire [0:0] fixedclk_enable;
+ wire [3:0] fixedclk_fast;
+ wire [0:0] fixedclk_sel;
+ wire [1:0] fixedclk_to_cmu;
+ wire [5:0] grayelecidleinfersel_from_tx;
+ wire [1:0] int_pipeenrevparallellpbkfromtx;
+ wire [1:0] int_rx_coreclkout;
+ wire [1:0] int_rx_phfifordenableout;
+ wire [1:0] int_rx_phfiforesetout;
+ wire [1:0] int_rx_phfifowrdisableout;
+ wire [1:0] int_rx_phfifoxnbytesel;
+ wire [1:0] int_rx_phfifoxnrdenable;
+ wire [1:0] int_rx_phfifoxnwrclk;
+ wire [1:0] int_rx_phfifoxnwrenable;
+ wire [0:0] int_rxcoreclk;
+ wire [0:0] int_rxphfifordenable;
+ wire [0:0] int_rxphfiforeset;
+ wire [0:0] int_rxphfifox4byteselout;
+ wire [0:0] int_rxphfifox4rdenableout;
+ wire [0:0] int_rxphfifox4wrclkout;
+ wire [0:0] int_rxphfifox4wrenableout;
+ wire [1:0] int_tx_coreclkout;
+ wire [1:0] int_tx_phfiforddisableout;
+ wire [1:0] int_tx_phfiforesetout;
+ wire [1:0] int_tx_phfifowrenableout;
+ wire [1:0] int_tx_phfifoxnbytesel;
+ wire [1:0] int_tx_phfifoxnrdclk;
+ wire [1:0] int_tx_phfifoxnrdenable;
+ wire [1:0] int_tx_phfifoxnwrenable;
+ wire [0:0] int_txcoreclk;
+ wire [0:0] int_txphfiforddisable;
+ wire [0:0] int_txphfiforeset;
+ wire [0:0] int_txphfifowrenable;
+ wire [0:0] int_txphfifox4byteselout;
+ wire [0:0] int_txphfifox4rdclkout;
+ wire [0:0] int_txphfifox4rdenableout;
+ wire [0:0] int_txphfifox4wrenableout;
+ wire [0:0] nonusertocmu_out;
+ wire [1:0] pipedatavalid_out;
+ wire [1:0] pipeelecidle_out;
+ wire [0:0] pll_powerdown;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [0:0] refclk_pma;
+ wire [1:0] rx_analogreset_in;
+ wire [1:0] rx_analogreset_out;
+ wire [1:0] rx_coreclk_in;
+ wire [1:0] rx_deserclock_in;
+ wire [1:0] rx_digitalreset_in;
+ wire [1:0] rx_digitalreset_out;
+ wire [5:0] rx_elecidleinfersel;
+ wire [1:0] rx_enapatternalign;
+ wire [1:0] rx_locktodata;
+ wire [1:0] rx_locktorefclk_wire;
+ wire [31:0] rx_out_wire;
+ wire [3:0] rx_pcs_rxfound_wire;
+ wire [799:0] rx_pcsdprioin_wire;
+ wire [799:0] rx_pcsdprioout;
+ wire [1:0] rx_phfifordenable;
+ wire [1:0] rx_phfiforeset;
+ wire [1:0] rx_phfifowrdisable;
+ wire [1:0] rx_pll_pfdrefclkout_wire;
+ wire [4:0] rx_pma_analogtestbus;
+ wire [1:0] rx_pma_clockout;
+ wire [19:0] rx_pma_recoverdataout_wire;
+ wire [599:0] rx_pmadprioin_wire;
+ wire [599:0] rx_pmadprioout;
+ wire [1:0] rx_powerdown;
+ wire [1:0] rx_powerdown_in;
+ wire [1:0] rx_prbscidenable;
+ wire [39:0] rx_revparallelfdbkdata;
+ wire [1:0] rx_rmfiforeset;
+ wire [1:0] rx_signaldetect_wire;
+ wire [0:0] rxphfifowrdisable;
+ wire [1:0] tx_analogreset_out;
+ wire [1:0] tx_clkout_int_wire;
+ wire [1:0] tx_coreclk_in;
+ wire [31:0] tx_datain_wire;
+ wire [19:0] tx_dataout_pcs_to_pma;
+ wire [1:0] tx_digitalreset_in;
+ wire [1:0] tx_digitalreset_out;
+ wire [299:0] tx_dprioin_wire;
+ wire [3:0] tx_forcedisp_wire;
+ wire [1:0] tx_invpolarity;
+ wire [1:0] tx_localrefclk;
+ wire [1:0] tx_pcs_forceelecidleout;
+ wire [1:0] tx_phfiforeset;
+ wire [3:0] tx_pipepowerdownout;
+ wire [7:0] tx_pipepowerstateout;
+ wire [1:0] tx_pma_fastrefclk0in;
+ wire [1:0] tx_pma_refclk0in;
+ wire [1:0] tx_pma_refclk0inpulse;
+ wire [599:0] tx_pmadprioin_wire;
+ wire [599:0] tx_pmadprioout;
+ wire [1:0] tx_revparallellpbken;
+ wire [1:0] tx_rxdetectvalidout;
+ wire [1:0] tx_rxfoundout;
+ wire [299:0] tx_txdprioout;
+ wire [1:0] txdataout;
+ wire [1:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ altpll pll0
+ (
+ .activeclock(),
+ .areset(pll_powerdown[0]),
+ .clk(wire_pll0_clk),
+ .clkbad(),
+ .clkloss(),
+ .enable0(),
+ .enable1(),
+ .extclk(),
+ .fbout(),
+ .fref(wire_pll0_fref),
+ .icdrclk(wire_pll0_icdrclk),
+ .inclk({{1{1'b0}}, pll_inclk[0]}),
+ .locked(wire_pll0_locked),
+ .phasedone(),
+ .scandataout(),
+ .scandone(),
+ .sclkout0(),
+ .sclkout1(),
+ .vcooverrange(),
+ .vcounderrange()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clkena({6{1'b1}}),
+ .clkswitch(1'b0),
+ .configupdate(1'b0),
+ .extclkena({4{1'b1}}),
+ .fbin(1'b1),
+ .pfdena(1'b1),
+ .phasecounterselect({4{1'b1}}),
+ .phasestep(1'b1),
+ .phaseupdown(1'b1),
+ .pllena(1'b1),
+ .scanaclr(1'b0),
+ .scanclk(1'b0),
+ .scanclkena(1'b1),
+ .scandata(1'b0),
+ .scanread(1'b0),
+ .scanwrite(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ pll0.bandwidth_type = "AUTO",
+ pll0.clk0_divide_by = 2,
+ pll0.clk0_multiply_by = 25,
+ pll0.clk1_divide_by = 10,
+ pll0.clk1_multiply_by = 25,
+ pll0.clk2_divide_by = 10,
+ pll0.clk2_duty_cycle = 20,
+ pll0.clk2_multiply_by = 25,
+ pll0.dpa_divide_by = 2,
+ pll0.dpa_multiply_by = 25,
+ pll0.inclk0_input_frequency = 10000,
+ pll0.operation_mode = "no_compensation",
+ pll0.intended_device_family = "Cyclone IV GX",
+ pll0.lpm_type = "altpll";
+ cycloneiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ cycloneiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .coreclkout(wire_cent_unit0_coreclkout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk({{2{1'b0}}, fixedclk_to_cmu[1:0]}),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkout(wire_cent_unit0_refclkout),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[1:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({{2{1'b0}}, rx_digitalreset_in[1:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({{800{1'b0}}, cent_unit_rxpcsdprioin[799:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({{600{1'b0}}, cent_unit_rxpmadprioin[599:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[1:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(tx_localrefclk[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(),
+ .txdatain({32{1'b0}}),
+ .txdataout(),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({{2{1'b0}}, tx_digitalreset_in[1:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({{300{1'b0}}, cent_unit_tx_dprioin[299:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpmadprioin({{600{1'b0}}, cent_unit_txpmadprioin[599:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .pmacramtest(1'b0),
+ .refclkdig(1'b0),
+ .scanclk(1'b0),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({2000{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.dprio_config_mode = 6'h01,
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_channel_bonding = "x2",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_channel_bonding = "x2",
+ cent_unit0.tx0_rd_clk_mux_select = "central",
+ cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_coreclk_out_post_divider = "true",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
+ cycloneiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[9:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disperr(wire_receive_pcs0_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(wire_receive_pcs0_errdetect),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifooverflow(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifox4bytesel(int_rx_phfifoxnbytesel[0]),
+ .phfifox4rdenable(int_rx_phfifoxnrdenable[0]),
+ .phfifox4wrclk(int_rx_phfifoxnwrclk[0]),
+ .phfifox4wrenable(int_rx_phfifoxnwrenable[0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .revbyteorderwa(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_cid_mode_enable = "true",
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x2",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 2),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_pipe_enable = "true",
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 32,
+ receive_pcs0.rxstatus_error_report_mode = 1,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
+ cycloneiv_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:10]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .disperr(wire_receive_pcs1_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(wire_receive_pcs1_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(wire_receive_pcs1_errdetect),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[1]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifooverflow(),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifox4bytesel(int_rx_phfifoxnbytesel[1]),
+ .phfifox4rdenable(int_rx_phfifoxnrdenable[1]),
+ .phfifox4wrclk(int_rx_phfifoxnwrclk[1]),
+ .phfifox4wrenable(int_rx_phfifoxnwrenable[1]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetect(),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .revbyteorderwa(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_cid_mode_enable = "true",
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_mask_cycle = 800,
+ receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x2",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 2),
+ receive_pcs1.channel_width = 16,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h01,
+ receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.protocol_hint = "pcie",
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_pipe_enable = "true",
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rx_phfifo_wait_cnt = 32,
+ receive_pcs1.rxstatus_error_report_mode = 1,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "true",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.lpm_type = "cycloneiv_hssi_rx_pcs";
+ cycloneiv_hssi_rx_pma receive_pma0
+ (
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .crupowerdn(cent_unit_rxcrupowerdn[0]),
+ .datain(rx_datain[0]),
+ .datastrobeout(),
+ .deserclock(rx_deserclock_in[0]),
+ .diagnosticlpbkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlocked(wire_receive_pma0_freqlocked),
+ .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dpashift(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 2),
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.effective_data_rate = "2500 Mbps",
+ receive_pma0.enable_local_divider = "false",
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "false",
+ receive_pma0.enable_pd2_deadzone_detection = "true",
+ receive_pma0.enable_second_order_loop = "false",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eq_setting = 1,
+ receive_pma0.force_signal_detect = "false",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.loop_1_digital_filter = 8,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.power_down_pd2_clocks = "false",
+ receive_pma0.ppm_gen1_2_xcnt_en = 1,
+ receive_pma0.ppm_post_eidle = 0,
+ receive_pma0.ppmselect = 8,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.signal_detect_hysteresis = 4,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma0.signal_detect_loss_threshold = 3,
+ receive_pma0.termination = "OCT 85 Ohms",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
+ cycloneiv_hssi_rx_pma receive_pma1
+ (
+ .analogtestbus(wire_receive_pma1_analogtestbus),
+ .clockout(wire_receive_pma1_clockout),
+ .crupowerdn(cent_unit_rxcrupowerdn[1]),
+ .datain(rx_datain[1]),
+ .datastrobeout(),
+ .deserclock(rx_deserclock_in[1]),
+ .diagnosticlpbkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(wire_receive_pma1_dprioout),
+ .freqlocked(wire_receive_pma1_freqlocked),
+ .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[1])),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dpashift(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 2),
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h01,
+ receive_pma1.effective_data_rate = "2500 Mbps",
+ receive_pma1.enable_local_divider = "false",
+ receive_pma1.enable_ltd = "false",
+ receive_pma1.enable_ltr = "false",
+ receive_pma1.enable_pd2_deadzone_detection = "true",
+ receive_pma1.enable_second_order_loop = "false",
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eq_setting = 1,
+ receive_pma1.force_signal_detect = "false",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.loop_1_digital_filter = 8,
+ receive_pma1.offset_cancellation = 1,
+ receive_pma1.power_down_pd2_clocks = "false",
+ receive_pma1.ppm_gen1_2_xcnt_en = 1,
+ receive_pma1.ppm_post_eidle = 0,
+ receive_pma1.ppmselect = 8,
+ receive_pma1.protocol_hint = "pcie",
+ receive_pma1.signal_detect_hysteresis = 4,
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma1.signal_detect_loss_threshold = 3,
+ receive_pma1.termination = "OCT 85 Ohms",
+ receive_pma1.use_external_termination = "false",
+ receive_pma1.lpm_type = "cycloneiv_hssi_rx_pma";
+ cycloneiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({tx_ctrlenable[1:0]}),
+ .datain({{4{1'b0}}, tx_datain_wire[15:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({2{tx_forceelecidle[0]}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({tx_forcedisp_wire[1:0]}),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifooverflow(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifox4bytesel(int_tx_phfifoxnbytesel[0]),
+ .phfifox4rdclk(int_tx_phfifoxnrdclk[0]),
+ .phfifox4rdenable(int_tx_phfifoxnrdenable[0]),
+ .phfifox4wrenable(int_tx_phfifoxnwrenable[0]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(1'b0),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrlenable(),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({22{1'b0}}),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .xgmctrl(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "x2",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 2),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 4,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "central",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
+ cycloneiv_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({tx_ctrlenable[3:2]}),
+ .datain({{4{1'b0}}, tx_datain_wire[31:16]}),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({2{tx_forceelecidle[1]}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(wire_transmit_pcs1_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({tx_forcedisp_wire[3:2]}),
+ .forceelecidle(tx_forceelecidle[1]),
+ .forceelecidleout(wire_transmit_pcs1_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifooverflow(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifox4bytesel(int_tx_phfifoxnbytesel[1]),
+ .phfifox4rdclk(int_tx_phfifoxnrdclk[1]),
+ .phfifox4rdenable(int_tx_phfifoxnrdenable[1]),
+ .phfifox4wrenable(int_tx_phfifoxnwrenable[1]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(1'b0),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrlenable(),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({22{1'b0}}),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .xgmctrl(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.bitslip_enable = "false",
+ transmit_pcs1.channel_bonding = "x2",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 2),
+ transmit_pcs1.channel_width = 16,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h01,
+ transmit_pcs1.elec_idle_delay = 4,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie",
+ transmit_pcs1.refclk_select = "central",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "true",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "cycloneiv_hssi_tx_pcs";
+ cycloneiv_hssi_tx_pma transmit_pma0
+ (
+ .cgbpowerdn(cent_unit_txdividerpowerdown[0]),
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({tx_dataout_pcs_to_pma[9:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in(tx_pma_fastrefclk0in[0]),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in(tx_pma_refclk0in[0]),
+ .refclk0inpulse(tx_pma_refclk0inpulse[0]),
+ .reverselpbkin(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .diagnosticlpbkin(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 2),
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.effective_data_rate = "2500 Mbps",
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.preemp_tap_1 = 18,
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "low",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_rx_detect = "true",
+ transmit_pma0.vod_selection = 5,
+ transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
+ cycloneiv_hssi_tx_pma transmit_pma1
+ (
+ .cgbpowerdn(cent_unit_txdividerpowerdown[1]),
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({tx_dataout_pcs_to_pma[19:10]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(wire_transmit_pma1_dprioout),
+ .fastrefclk0in(tx_pma_fastrefclk0in[1]),
+ .forceelecidle(tx_pcs_forceelecidleout[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in(tx_pma_refclk0in[1]),
+ .refclk0inpulse(tx_pma_refclk0inpulse[1]),
+ .reverselpbkin(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .diagnosticlpbkin(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 2),
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h01,
+ transmit_pma1.effective_data_rate = "2500 Mbps",
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.preemp_tap_1 = 18,
+ transmit_pma1.protocol_hint = "pcie",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "low",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_external_termination = "false",
+ transmit_pma1.use_rx_detect = "true",
+ transmit_pma1.vod_selection = 5,
+ transmit_pma1.lpm_type = "cycloneiv_hssi_tx_pma";
+ // synopsys translate_off
+ initial
+ fixedclk_div = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk)
+ fixedclk_div <= (~ fixedclk_div_in);
+ // synopsys translate_off
+ initial
+ reconfig_togxb_busy_reg = 0;
+ // synopsys translate_on
+ always @ ( negedge fixedclk)
+ reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
+ assign
+ cal_blk_powerdown = 1'b0,
+ cent_unit_quadresetout = {1'b0, wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[1:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[1:0]},
+ cent_unit_rxpcsdprioin = {rx_pcsdprioout[799:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[799:0]},
+ cent_unit_rxpmadprioin = {rx_pmadprioout[599:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[599:0]},
+ cent_unit_tx_dprioin = {tx_txdprioout[299:0]},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[1:0]},
+ cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[1:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[299:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[1:0]},
+ cent_unit_txpmadprioin = {tx_pmadprioout[599:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[599:0]},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_cent_unit0_coreclkout},
+ fixedclk_div_in = fixedclk_div,
+ fixedclk_enable = reconfig_togxb_busy_reg[0],
+ fixedclk_fast = {4{1'b1}},
+ fixedclk_sel = reconfig_togxb_busy_reg[1],
+ fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk))},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
+ int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
+ int_rx_coreclkout = {wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_phfifordenableout = {wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {2{int_rxphfifox4byteselout[0]}},
+ int_rx_phfifoxnrdenable = {2{int_rxphfifox4rdenableout[0]}},
+ int_rx_phfifoxnwrclk = {2{int_rxphfifox4wrclkout[0]}},
+ int_rx_phfifoxnwrenable = {2{int_rxphfifox4wrenableout[0]}},
+ int_rxcoreclk = {int_rx_coreclkout[0]},
+ int_rxphfifordenable = {int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_phfiforddisableout = {wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {2{int_txphfifox4byteselout[0]}},
+ int_tx_phfifoxnrdclk = {2{int_txphfifox4rdclkout[0]}},
+ int_tx_phfifoxnrdenable = {2{int_txphfifox4rdenableout[0]}},
+ int_tx_phfifoxnwrenable = {2{int_txphfifox4wrenableout[0]}},
+ int_txcoreclk = {int_tx_coreclkout[0]},
+ int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[1:0]},
+ pipedatavalid_out = {wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[1:0]},
+ pipeelecidle_out = {wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll_locked = {wire_pll0_locked},
+ pll_powerdown = 1'b0,
+ reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ refclk_pma = {wire_cent_unit0_refclkout},
+ rx_analogreset_in = {2{((~ reconfig_togxb_busy) & rx_analogreset[0])}},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[1:0]},
+ rx_coreclk_in = {2{coreclkout_wire[0]}},
+ rx_ctrldetect = {wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[31:0]},
+ rx_deserclock_in = {2{wire_pll0_icdrclk}},
+ rx_digitalreset_in = {2{rx_digitalreset[0]}},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[1:0]},
+ rx_disperr = {wire_receive_pcs1_disperr[1:0], wire_receive_pcs0_disperr[1:0]},
+ rx_elecidleinfersel = {6{1'b0}},
+ rx_enapatternalign = {2{1'b0}},
+ rx_errdetect = {wire_receive_pcs1_errdetect[1:0], wire_receive_pcs0_errdetect[1:0]},
+ rx_freqlocked = {(wire_receive_pma1_freqlocked & (~ rx_analogreset[0])), (wire_receive_pma0_freqlocked & (~ rx_analogreset[0]))},
+ rx_locktodata = {2{1'b0}},
+ rx_locktorefclk_wire = {wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[799:0]},
+ rx_pcsdprioout = {wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = {2{1'b1}},
+ rx_phfiforeset = {2{1'b0}},
+ rx_phfifowrdisable = {2{1'b0}},
+ rx_pll_pfdrefclkout_wire = {2{wire_pll0_fref}},
+ rx_pma_analogtestbus = {{3{1'b0}}, wire_receive_pma1_analogtestbus[6], wire_receive_pma0_analogtestbus[6]},
+ rx_pma_clockout = {wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma1_recoverdataout[9:0], wire_receive_pma0_recoverdataout[9:0]},
+ rx_pmadprioin_wire = {cent_unit_rxpmadprioout[599:0]},
+ rx_pmadprioout = {wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
+ rx_powerdown = {2{1'b0}},
+ rx_powerdown_in = {rx_powerdown[1:0]},
+ rx_prbscidenable = {2{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {2{1'b0}},
+ rx_signaldetect_wire = {wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
+ rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[1:0]},
+ tx_coreclk_in = {2{coreclkout_wire[0]}},
+ tx_datain_wire = {tx_datain[31:0]},
+ tx_dataout = {txdataout[1:0]},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs1_dataout[9:0], wire_transmit_pcs0_dataout[9:0]},
+ tx_digitalreset_in = {2{tx_digitalreset[0]}},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[1:0]},
+ tx_dprioin_wire = {cent_unit_txdprioout[299:0]},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = {2{1'b0}},
+ tx_localrefclk = {wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = {2{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pma_fastrefclk0in = {2{wire_pll0_clk[0]}},
+ tx_pma_refclk0in = {2{wire_pll0_clk[1]}},
+ tx_pma_refclk0inpulse = {2{wire_pll0_clk[2]}},
+ tx_pmadprioin_wire = {cent_unit_txpmadprioout[599:0]},
+ tx_pmadprioout = {wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = {2{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
+ txdataout = {wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ txdetectrxout = {wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+ initial/*synthesis enable_verilog_initial_construct*/
+ begin
+ $display("Warning: MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) alt_c3gxb|receiver_termination The value assigned is oct_100_ohms and the valid value list is OCT_85_OHMS|OCT_150_OHMS");
+ end
+endmodule //altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_3cgx_x2d_gen1_08p (
+ cal_blk_clk,
+ fixedclk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_areset,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_disperr,
+ rx_errdetect,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_dataout)/* synthesis synthesis_clearbox = 2 */;
+
+ input cal_blk_clk;
+ input fixedclk;
+ input [0:0] gxb_powerdown;
+ input [1:0] pipe8b10binvpolarity;
+ input [0:0] pll_areset;
+ input [0:0] pll_inclk;
+ input [3:0] powerdn;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [1:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [3:0] tx_ctrlenable;
+ input [31:0] tx_datain;
+ input [1:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [1:0] tx_forcedispcompliance;
+ input [1:0] tx_forceelecidle;
+ output [0:0] coreclkout;
+ output [1:0] pipedatavalid;
+ output [1:0] pipeelecidle;
+ output [1:0] pipephydonestatus;
+ output [5:0] pipestatus;
+ output [0:0] pll_locked;
+ output [4:0] reconfig_fromgxb;
+ output [3:0] rx_ctrldetect;
+ output [31:0] rx_dataout;
+ output [3:0] rx_disperr;
+ output [3:0] rx_errdetect;
+ output [1:0] rx_freqlocked;
+ output [3:0] rx_patterndetect;
+ output [3:0] rx_syncstatus;
+ output [1:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [3:0] sub_wire0;
+ wire [1:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [4:0] sub_wire3;
+ wire [1:0] sub_wire4;
+ wire [5:0] sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [3:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [31:0] sub_wire9;
+ wire [3:0] sub_wire10;
+ wire [1:0] sub_wire11;
+ wire [1:0] sub_wire12;
+ wire [3:0] sub_wire13;
+ wire [1:0] sub_wire14;
+ wire [3:0] rx_patterndetect = sub_wire0[3:0];
+ wire [1:0] pipephydonestatus = sub_wire1[1:0];
+ wire [0:0] pll_locked = sub_wire2[0:0];
+ wire [4:0] reconfig_fromgxb = sub_wire3[4:0];
+ wire [1:0] rx_freqlocked = sub_wire4[1:0];
+ wire [5:0] pipestatus = sub_wire5[5:0];
+ wire [3:0] rx_disperr = sub_wire6[3:0];
+ wire [3:0] rx_syncstatus = sub_wire7[3:0];
+ wire [0:0] coreclkout = sub_wire8[0:0];
+ wire [31:0] rx_dataout = sub_wire9[31:0];
+ wire [3:0] rx_errdetect = sub_wire10[3:0];
+ wire [1:0] pipeelecidle = sub_wire11[1:0];
+ wire [1:0] tx_dataout = sub_wire12[1:0];
+ wire [3:0] rx_ctrldetect = sub_wire13[3:0];
+ wire [1:0] pipedatavalid = sub_wire14[1:0];
+
+ altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78 altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78_component (
+ .reconfig_togxb (reconfig_togxb),
+ .cal_blk_clk (cal_blk_clk),
+ .tx_forceelecidle (tx_forceelecidle),
+ .fixedclk (fixedclk),
+ .rx_datain (rx_datain),
+ .rx_digitalreset (rx_digitalreset),
+ .pll_areset (pll_areset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .tx_datain (tx_datain),
+ .tx_digitalreset (tx_digitalreset),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .reconfig_clk (reconfig_clk),
+ .rx_analogreset (rx_analogreset),
+ .powerdn (powerdn),
+ .tx_ctrlenable (tx_ctrlenable),
+ .pll_inclk (pll_inclk),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .pipephydonestatus (sub_wire1),
+ .pll_locked (sub_wire2),
+ .reconfig_fromgxb (sub_wire3),
+ .rx_freqlocked (sub_wire4),
+ .pipestatus (sub_wire5),
+ .rx_disperr (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .coreclkout (sub_wire8),
+ .rx_dataout (sub_wire9),
+ .rx_errdetect (sub_wire10),
+ .pipeelecidle (sub_wire11),
+ .tx_dataout (sub_wire12),
+ .rx_ctrldetect (sub_wire13),
+ .pipedatavalid (sub_wire14))/* synthesis synthesis_clearbox=2
+ clearbox_macroname = alt_c3gxb
+ clearbox_defparam = "effective_data_rate=2500 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=100.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=2;operation_mode=duplex;pll_bandwidth_type=Auto;pll_control_width=1;pll_inclk_period=10000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=18;protocol=pcie;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=x2;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=2500;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=false;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;rx_use_clkout=false;rx_use_coreclk=false;
+ rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=true;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_bonding=x2;tx_channel_width=16;tx_clkout_width=2;tx_common_mode=0.65v;tx_data_rate=2500;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=Auto;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=low;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=true;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=5;coreclkout_control_width=1;elec_idle_infer_enable=false;enable_0ppm=false;equalization_setting=1;gxb_powerdown_width=1;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=2;pll_multiply_by=25;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_deskew_pattern=0;rx_dwidth_factor=2;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=altpcie_serdes_3cgx_x2d_gen1_08p;tx_bitslip_enable=FALSE;tx_dwidth_factor=2;tx_use_external_termination=false;" */;
+ defparam
+ altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x2"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "2"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "18"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x2"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x2"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "2"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "5"
+// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: pll_divide_by STRING "2"
+// Retrieval info: CONSTANT: pll_multiply_by STRING "25"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
+// Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: top_module_name STRING "altpcie_serdes_3cgx_x2d_gen1_08p"
+// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 2 0 INPUT NODEFVAL "pipe8b10binvpolarity[1..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 2 0 OUTPUT NODEFVAL "pipedatavalid[1..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 2 0 OUTPUT NODEFVAL "pipeelecidle[1..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 2 0 OUTPUT NODEFVAL "pipephydonestatus[1..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 6 0 OUTPUT NODEFVAL "pipestatus[5..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 4 0 INPUT NODEFVAL "powerdn[3..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 4 0 OUTPUT NODEFVAL "rx_ctrldetect[3..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 2 0 INPUT NODEFVAL "rx_datain[1..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 32 0 OUTPUT NODEFVAL "rx_dataout[31..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_disperr 0 0 4 0 OUTPUT NODEFVAL "rx_disperr[3..0]"
+// Retrieval info: USED_PORT: rx_errdetect 0 0 4 0 OUTPUT NODEFVAL "rx_errdetect[3..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 2 0 OUTPUT NODEFVAL "rx_freqlocked[1..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 4 0 OUTPUT NODEFVAL "rx_patterndetect[3..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 4 0 OUTPUT NODEFVAL "rx_syncstatus[3..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 4 0 INPUT NODEFVAL "tx_ctrlenable[3..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 32 0 INPUT NODEFVAL "tx_datain[31..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 2 0 OUTPUT NODEFVAL "tx_dataout[1..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 2 0 INPUT NODEFVAL "tx_detectrxloop[1..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 2 0 INPUT NODEFVAL "tx_forcedispcompliance[1..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 2 0 INPUT NODEFVAL "tx_forceelecidle[1..0]"
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 2 0 pipe8b10binvpolarity 0 0 2 0
+// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 4 0 powerdn 0 0 4 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 2 0 rx_datain 0 0 2 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 4 0 tx_ctrlenable 0 0 4 0
+// Retrieval info: CONNECT: @tx_datain 0 0 32 0 tx_datain 0 0 32 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 2 0 tx_detectrxloop 0 0 2 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 2 0 tx_forcedispcompliance 0 0 2 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 2 0 tx_forceelecidle 0 0 2 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 2 0 @pipedatavalid 0 0 2 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 2 0 @pipeelecidle 0 0 2 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 2 0 @pipephydonestatus 0 0 2 0
+// Retrieval info: CONNECT: pipestatus 0 0 6 0 @pipestatus 0 0 6 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 4 0 @rx_ctrldetect 0 0 4 0
+// Retrieval info: CONNECT: rx_dataout 0 0 32 0 @rx_dataout 0 0 32 0
+// Retrieval info: CONNECT: rx_disperr 0 0 4 0 @rx_disperr 0 0 4 0
+// Retrieval info: CONNECT: rx_errdetect 0 0 4 0 @rx_errdetect 0 0 4 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 2 0 @rx_freqlocked 0 0 2 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 4 0 @rx_syncstatus 0 0 4 0
+// Retrieval info: CONNECT: tx_dataout 0 0 2 0 @tx_dataout 0 0 2 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: LIB_FILE: cycloneiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..728cedbe433a91b5c06a8e0dcf71119d8e9f434e
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v
@@ -0,0 +1,2740 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt_c3gxb
+
+// ============================================================
+// File Name: altpcie_serdes_3cgx_x4d_gen1_08p.v
+// Megafunction Name(s):
+// alt_c3gxb
+//
+// Simulation Library Files(s):
+// altera_mf;cycloneiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" equalization_setting=1 equalizer_dcgain_setting=1 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="2" pll_inclk_period=10000 pll_multiply_by="25" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="pcie" receiver_termination="oct_100_ohms" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=16 rx_common_mode="0.82v" rx_datapath_protocol="pipe" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altpcie_serdes_3cgx_x4d_gen1_08p" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_bonding="x4" tx_channel_width=16 tx_clkout_width=4 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="low" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_areset pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle intended_device_family="Cyclone IV GX"
+//VERSION_BEGIN 10.0SP1 cbx_alt_c3gxb 2010:08:18:21:06:53:SJ cbx_altclkbuf 2010:08:18:21:06:53:SJ cbx_altiobuf_bidir 2010:08:18:21:06:53:SJ cbx_altiobuf_in 2010:08:18:21:06:53:SJ cbx_altiobuf_out 2010:08:18:21:06:53:SJ cbx_altpll 2010:08:18:21:06:53:SJ cbx_cycloneii 2010:08:18:21:06:53:SJ cbx_lpm_add_sub 2010:08:18:21:06:53:SJ cbx_lpm_compare 2010:08:18:21:06:53:SJ cbx_lpm_decode 2010:08:18:21:06:53:SJ cbx_lpm_mux 2010:08:18:21:06:53:SJ cbx_mgl 2010:08:18:21:24:06:SJ cbx_stingray 2010:08:18:21:06:53:SJ cbx_stratix 2010:08:18:21:06:53:SJ cbx_stratixii 2010:08:18:21:06:54:SJ cbx_stratixiii 2010:08:18:21:06:54:SJ cbx_stratixv 2010:08:18:21:06:54:SJ cbx_util_mgl 2010:08:18:21:06:53:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 4 cycloneiv_hssi_rx_pma 4 cycloneiv_hssi_tx_pcs 4 cycloneiv_hssi_tx_pma 4
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_3cgx_x4d_gen1_08p_alt_c3gxb_id48
+ (
+ cal_blk_clk,
+ coreclkout,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_areset,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) ;
+ input cal_blk_clk;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ input [0:0] pll_areset;
+ input [0:0] pll_inclk;
+ output [0:0] pll_locked;
+ input [7:0] powerdn;
+ input reconfig_clk;
+ output [4:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ output [7:0] rx_ctrldetect;
+ input [3:0] rx_datain;
+ output [63:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [3:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [7:0] rx_syncstatus;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ output [3:0] tx_dataout;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [3:0] pipe8b10binvpolarity;
+ tri0 [0:0] pll_areset;
+ tri0 [7:0] powerdn;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [7:0] tx_ctrlenable;
+ tri0 [63:0] tx_datain;
+ tri0 [3:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [3:0] tx_forcedispcompliance;
+ tri0 [3:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire [5:0] wire_pll0_clk;
+ wire wire_pll0_fref;
+ wire wire_pll0_icdrclk;
+ wire wire_pll0_locked;
+ wire wire_cal_blk0_nonusertocmu;
+ wire wire_cent_unit0_coreclkout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire wire_cent_unit0_quadresetout;
+ wire wire_cent_unit0_refclkout;
+ wire [3:0] wire_cent_unit0_rxanalogresetout;
+ wire [3:0] wire_cent_unit0_rxcrupowerdown;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [3:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [1199:0] wire_cent_unit0_rxpmadprioout;
+ wire [3:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [3:0] wire_cent_unit0_txdividerpowerdown;
+ wire [3:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1199:0] wire_cent_unit0_txpmadprioout;
+ wire wire_receive_pcs0_cdrctrlearlyeios;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [1:0] wire_receive_pcs0_ctrldetect;
+ wire [19:0] wire_receive_pcs0_dataout;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [1:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [1:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_cdrctrlearlyeios;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [1:0] wire_receive_pcs1_ctrldetect;
+ wire [19:0] wire_receive_pcs1_dataout;
+ wire [399:0] wire_receive_pcs1_dprioout;
+ wire [1:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire [1:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs2_cdrctrlearlyeios;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [1:0] wire_receive_pcs2_ctrldetect;
+ wire [19:0] wire_receive_pcs2_dataout;
+ wire [399:0] wire_receive_pcs2_dprioout;
+ wire [1:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_pipedatavalid;
+ wire wire_receive_pcs2_pipeelecidle;
+ wire wire_receive_pcs2_pipephydonestatus;
+ wire [2:0] wire_receive_pcs2_pipestatus;
+ wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
+ wire [1:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs3_cdrctrlearlyeios;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [1:0] wire_receive_pcs3_ctrldetect;
+ wire [19:0] wire_receive_pcs3_dataout;
+ wire [399:0] wire_receive_pcs3_dprioout;
+ wire [1:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_pipedatavalid;
+ wire wire_receive_pcs3_pipeelecidle;
+ wire wire_receive_pcs3_pipephydonestatus;
+ wire [2:0] wire_receive_pcs3_pipestatus;
+ wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
+ wire [1:0] wire_receive_pcs3_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_freqlocked;
+ wire wire_receive_pma0_locktorefout;
+ wire [9:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire [7:0] wire_receive_pma1_analogtestbus;
+ wire wire_receive_pma1_clockout;
+ wire [299:0] wire_receive_pma1_dprioout;
+ wire wire_receive_pma1_freqlocked;
+ wire wire_receive_pma1_locktorefout;
+ wire [9:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire [7:0] wire_receive_pma2_analogtestbus;
+ wire wire_receive_pma2_clockout;
+ wire [299:0] wire_receive_pma2_dprioout;
+ wire wire_receive_pma2_freqlocked;
+ wire wire_receive_pma2_locktorefout;
+ wire [9:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire [7:0] wire_receive_pma3_analogtestbus;
+ wire wire_receive_pma3_clockout;
+ wire [299:0] wire_receive_pma3_dprioout;
+ wire wire_receive_pma3_freqlocked;
+ wire wire_receive_pma3_locktorefout;
+ wire [9:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [9:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire wire_transmit_pcs0_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [9:0] wire_transmit_pcs1_dataout;
+ wire [149:0] wire_transmit_pcs1_dprioout;
+ wire wire_transmit_pcs1_forceelecidleout;
+ wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire wire_transmit_pcs1_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [9:0] wire_transmit_pcs2_dataout;
+ wire [149:0] wire_transmit_pcs2_dprioout;
+ wire wire_transmit_pcs2_forceelecidleout;
+ wire [2:0] wire_transmit_pcs2_grayelecidleinferselout;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire wire_transmit_pcs2_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs2_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs2_pipepowerstateout;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [9:0] wire_transmit_pcs3_dataout;
+ wire [149:0] wire_transmit_pcs3_dprioout;
+ wire wire_transmit_pcs3_forceelecidleout;
+ wire [2:0] wire_transmit_pcs3_grayelecidleinferselout;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire wire_transmit_pcs3_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs3_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs3_pipepowerstateout;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire [299:0] wire_transmit_pma1_dprioout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire [299:0] wire_transmit_pma2_dprioout;
+ wire wire_transmit_pma2_rxdetectvalidout;
+ wire wire_transmit_pma2_rxfoundout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire [299:0] wire_transmit_pma3_dprioout;
+ wire wire_transmit_pma3_rxdetectvalidout;
+ wire wire_transmit_pma3_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [3:0] cent_unit_quadresetout;
+ wire [3:0] cent_unit_rxcrupowerdn;
+ wire [3:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1199:0] cent_unit_rxpmadprioin;
+ wire [1199:0] cent_unit_rxpmadprioout;
+ wire [599:0] cent_unit_tx_dprioin;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [3:0] cent_unit_txdividerpowerdown;
+ wire [599:0] cent_unit_txdprioout;
+ wire [3:0] cent_unit_txobpowerdn;
+ wire [1199:0] cent_unit_txpmadprioin;
+ wire [1199:0] cent_unit_txpmadprioout;
+ wire [0:0] coreclkout_wire;
+ wire [3:0] fixedclk_to_cmu;
+ wire [11:0] grayelecidleinfersel_from_tx;
+ wire [3:0] int_pipeenrevparallellpbkfromtx;
+ wire [3:0] int_rx_coreclkout;
+ wire [3:0] int_rx_phfifordenableout;
+ wire [3:0] int_rx_phfiforesetout;
+ wire [3:0] int_rx_phfifowrdisableout;
+ wire [3:0] int_rx_phfifoxnbytesel;
+ wire [3:0] int_rx_phfifoxnrdenable;
+ wire [3:0] int_rx_phfifoxnwrclk;
+ wire [3:0] int_rx_phfifoxnwrenable;
+ wire [0:0] int_rxcoreclk;
+ wire [0:0] int_rxphfifordenable;
+ wire [0:0] int_rxphfiforeset;
+ wire [0:0] int_rxphfifox4byteselout;
+ wire [0:0] int_rxphfifox4rdenableout;
+ wire [0:0] int_rxphfifox4wrclkout;
+ wire [0:0] int_rxphfifox4wrenableout;
+ wire [3:0] int_tx_coreclkout;
+ wire [3:0] int_tx_phfiforddisableout;
+ wire [3:0] int_tx_phfiforesetout;
+ wire [3:0] int_tx_phfifowrenableout;
+ wire [3:0] int_tx_phfifoxnbytesel;
+ wire [3:0] int_tx_phfifoxnrdclk;
+ wire [3:0] int_tx_phfifoxnrdenable;
+ wire [3:0] int_tx_phfifoxnwrenable;
+ wire [0:0] int_txcoreclk;
+ wire [0:0] int_txphfiforddisable;
+ wire [0:0] int_txphfiforeset;
+ wire [0:0] int_txphfifowrenable;
+ wire [0:0] int_txphfifox4byteselout;
+ wire [0:0] int_txphfifox4rdclkout;
+ wire [0:0] int_txphfifox4rdenableout;
+ wire [0:0] int_txphfifox4wrenableout;
+ wire [0:0] nonusertocmu_out;
+ wire [3:0] pipedatavalid_out;
+ wire [3:0] pipeelecidle_out;
+ wire [0:0] pll_powerdown;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [0:0] refclk_pma;
+ wire [3:0] rx_analogreset_in;
+ wire [3:0] rx_analogreset_out;
+ wire [3:0] rx_coreclk_in;
+ wire [3:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [11:0] rx_elecidleinfersel;
+ wire [3:0] rx_enapatternalign;
+ wire [3:0] rx_locktodata;
+ wire [3:0] rx_locktorefclk_wire;
+ wire [63:0] rx_out_wire;
+ wire [7:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [3:0] rx_phfifordenable;
+ wire [3:0] rx_phfiforeset;
+ wire [3:0] rx_phfifowrdisable;
+ wire [3:0] rx_pll_pfdrefclkout_wire;
+ wire [4:0] rx_pma_analogtestbus;
+ wire [3:0] rx_pma_clockout;
+ wire [39:0] rx_pma_recoverdataout_wire;
+ wire [1199:0] rx_pmadprioin_wire;
+ wire [1199:0] rx_pmadprioout;
+ wire [3:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [3:0] rx_prbscidenable;
+ wire [79:0] rx_revparallelfdbkdata;
+ wire [3:0] rx_rmfiforeset;
+ wire [3:0] rx_signaldetect_wire;
+ wire [0:0] rxphfifowrdisable;
+ wire [3:0] tx_analogreset_out;
+ wire [3:0] tx_clkout_int_wire;
+ wire [3:0] tx_coreclk_in;
+ wire [63:0] tx_datain_wire;
+ wire [39:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [599:0] tx_dprioin_wire;
+ wire [7:0] tx_forcedisp_wire;
+ wire [3:0] tx_invpolarity;
+ wire [3:0] tx_localrefclk;
+ wire [3:0] tx_pcs_forceelecidleout;
+ wire [3:0] tx_phfiforeset;
+ wire [7:0] tx_pipepowerdownout;
+ wire [15:0] tx_pipepowerstateout;
+ wire [3:0] tx_pma_fastrefclk0in;
+ wire [3:0] tx_pma_refclk0in;
+ wire [3:0] tx_pma_refclk0inpulse;
+ wire [1199:0] tx_pmadprioin_wire;
+ wire [1199:0] tx_pmadprioout;
+ wire [3:0] tx_revparallellpbken;
+ wire [3:0] tx_rxdetectvalidout;
+ wire [3:0] tx_rxfoundout;
+ wire [599:0] tx_txdprioout;
+ wire [3:0] txdataout;
+ wire [3:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ altpll pll0
+ (
+ .activeclock(),
+ .areset(pll_powerdown[0]),
+ .clk(wire_pll0_clk),
+ .clkbad(),
+ .clkloss(),
+ .enable0(),
+ .enable1(),
+ .extclk(),
+ .fbout(),
+ .fref(wire_pll0_fref),
+ .icdrclk(wire_pll0_icdrclk),
+ .inclk({{1{1'b0}}, pll_inclk[0]}),
+ .locked(wire_pll0_locked),
+ .phasedone(),
+ .scandataout(),
+ .scandone(),
+ .sclkout0(),
+ .sclkout1(),
+ .vcooverrange(),
+ .vcounderrange()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clkena({6{1'b1}}),
+ .clkswitch(1'b0),
+ .configupdate(1'b0),
+ .extclkena({4{1'b1}}),
+ .fbin(1'b1),
+ .pfdena(1'b1),
+ .phasecounterselect({4{1'b1}}),
+ .phasestep(1'b1),
+ .phaseupdown(1'b1),
+ .pllena(1'b1),
+ .scanaclr(1'b0),
+ .scanclk(1'b0),
+ .scanclkena(1'b1),
+ .scandata(1'b0),
+ .scanread(1'b0),
+ .scanwrite(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ pll0.bandwidth_type = "AUTO",
+ pll0.clk0_divide_by = 2,
+ pll0.clk0_multiply_by = 25,
+ pll0.clk1_divide_by = 10,
+ pll0.clk1_multiply_by = 25,
+ pll0.clk2_divide_by = 10,
+ pll0.clk2_duty_cycle = 20,
+ pll0.clk2_multiply_by = 25,
+ pll0.dpa_divide_by = 2,
+ pll0.dpa_multiply_by = 25,
+ pll0.inclk0_input_frequency = 10000,
+ pll0.operation_mode = "no_compensation",
+ pll0.intended_device_family = "Cyclone IV GX",
+ pll0.lpm_type = "altpll";
+ cycloneiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ cycloneiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .coreclkout(wire_cent_unit0_coreclkout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk({fixedclk_to_cmu[3:0]}),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkout(wire_cent_unit0_refclkout),
+ .rxanalogreset({rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({cent_unit_rxpmadprioin[1199:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(tx_localrefclk[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(),
+ .txdatain({32{1'b0}}),
+ .txdataout(),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpmadprioin({cent_unit_txpmadprioin[1199:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .pmacramtest(1'b0),
+ .refclkdig(1'b0),
+ .scanclk(1'b0),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({2000{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.dprio_config_mode = 6'h01,
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_channel_bonding = "x4",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_channel_bonding = "x4",
+ cent_unit0.tx0_rd_clk_mux_select = "central",
+ cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_coreclk_out_post_divider = "true",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
+ cycloneiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[9:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifooverflow(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifox4bytesel(int_rx_phfifoxnbytesel[0]),
+ .phfifox4rdenable(int_rx_phfifoxnrdenable[0]),
+ .phfifox4wrclk(int_rx_phfifoxnwrclk[0]),
+ .phfifox4wrenable(int_rx_phfifoxnwrenable[0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .revbyteorderwa(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_cid_mode_enable = "true",
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x4",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_pipe_enable = "true",
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 32,
+ receive_pcs0.rxstatus_error_report_mode = 1,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
+ cycloneiv_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:10]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(wire_receive_pcs1_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[1]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifooverflow(),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifox4bytesel(int_rx_phfifoxnbytesel[1]),
+ .phfifox4rdenable(int_rx_phfifoxnrdenable[1]),
+ .phfifox4wrclk(int_rx_phfifoxnwrclk[1]),
+ .phfifox4wrenable(int_rx_phfifoxnwrenable[1]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetect(),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .revbyteorderwa(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_cid_mode_enable = "true",
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_mask_cycle = 800,
+ receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x4",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 16,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h01,
+ receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.protocol_hint = "pcie",
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_pipe_enable = "true",
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rx_phfifo_wait_cnt = 32,
+ receive_pcs1.rxstatus_error_report_mode = 1,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "true",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.lpm_type = "cycloneiv_hssi_rx_pcs";
+ cycloneiv_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs2_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[29:20]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(wire_receive_pcs2_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[8:6]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[2]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifooverflow(),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifox4bytesel(int_rx_phfifoxnbytesel[2]),
+ .phfifox4rdenable(int_rx_phfifoxnrdenable[2]),
+ .phfifox4wrclk(int_rx_phfifoxnwrclk[2]),
+ .phfifox4wrenable(int_rx_phfifoxnwrenable[2]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs2_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs2_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[2]),
+ .pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[5:4]),
+ .pipepowerstate(tx_pipepowerstateout[11:8]),
+ .pipestatetransdoneout(),
+ .pipestatus(wire_receive_pcs2_pipestatus),
+ .powerdn(powerdn[5:4]),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
+ .rlv(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[2]),
+ .rxfound(rx_pcs_rxfound_wire[5:4]),
+ .signaldetect(),
+ .signaldetected(rx_signaldetect_wire[2]),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .revbyteorderwa(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.allow_align_polarity_inversion = "false",
+ receive_pcs2.allow_pipe_polarity_inversion = "true",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 14,
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_cid_mode_enable = "true",
+ receive_pcs2.cdrctrl_enable = "true",
+ receive_pcs2.cdrctrl_mask_cycle = 800,
+ receive_pcs2.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs2.cdrctrl_rxvalid_mask = "true",
+ receive_pcs2.channel_bonding = "x4",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 16,
+ receive_pcs2.clk1_mux_select = "recovered clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "false",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "pipe",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.deskew_pattern = "0",
+ receive_pcs2.disable_auto_idle_insertion = "false",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h01,
+ receive_pcs2.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 16,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 17,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.protocol_hint = "pcie",
+ receive_pcs2.rate_match_back_to_back = "false",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs2.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs2.rate_match_pattern_size = 20,
+ receive_pcs2.rate_match_pipe_enable = "true",
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "true",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rx_phfifo_wait_cnt = 32,
+ receive_pcs2.rxstatus_error_report_mode = 1,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deskew_fifo = "false",
+ receive_pcs2.use_double_data_mode = "true",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.lpm_type = "cycloneiv_hssi_rx_pcs";
+ cycloneiv_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs3_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:30]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(wire_receive_pcs3_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[11:9]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[3]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifooverflow(),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifox4bytesel(int_rx_phfifoxnbytesel[3]),
+ .phfifox4rdenable(int_rx_phfifoxnrdenable[3]),
+ .phfifox4wrclk(int_rx_phfifoxnwrclk[3]),
+ .phfifox4wrenable(int_rx_phfifoxnwrenable[3]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs3_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs3_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[3]),
+ .pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[7:6]),
+ .pipepowerstate(tx_pipepowerstateout[15:12]),
+ .pipestatetransdoneout(),
+ .pipestatus(wire_receive_pcs3_pipestatus),
+ .powerdn(powerdn[7:6]),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
+ .rlv(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[3]),
+ .rxfound(rx_pcs_rxfound_wire[7:6]),
+ .signaldetect(),
+ .signaldetected(rx_signaldetect_wire[3]),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .revbyteorderwa(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.allow_align_polarity_inversion = "false",
+ receive_pcs3.allow_pipe_polarity_inversion = "true",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 14,
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_cid_mode_enable = "true",
+ receive_pcs3.cdrctrl_enable = "true",
+ receive_pcs3.cdrctrl_mask_cycle = 800,
+ receive_pcs3.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs3.cdrctrl_rxvalid_mask = "true",
+ receive_pcs3.channel_bonding = "x4",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 16,
+ receive_pcs3.clk1_mux_select = "recovered clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "false",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "pipe",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.deskew_pattern = "0",
+ receive_pcs3.disable_auto_idle_insertion = "false",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h01,
+ receive_pcs3.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 16,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 17,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.protocol_hint = "pcie",
+ receive_pcs3.rate_match_back_to_back = "false",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs3.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs3.rate_match_pattern_size = 20,
+ receive_pcs3.rate_match_pipe_enable = "true",
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "true",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rx_phfifo_wait_cnt = 32,
+ receive_pcs3.rxstatus_error_report_mode = 1,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deskew_fifo = "false",
+ receive_pcs3.use_double_data_mode = "true",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.lpm_type = "cycloneiv_hssi_rx_pcs";
+ cycloneiv_hssi_rx_pma receive_pma0
+ (
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .crupowerdn(cent_unit_rxcrupowerdn[0]),
+ .datain(rx_datain[0]),
+ .datastrobeout(),
+ .deserclock(rx_deserclock_in[0]),
+ .diagnosticlpbkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlocked(wire_receive_pma0_freqlocked),
+ .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dpashift(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.effective_data_rate = "2500 Mbps",
+ receive_pma0.enable_local_divider = "false",
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "false",
+ receive_pma0.enable_pd2_deadzone_detection = "true",
+ receive_pma0.enable_second_order_loop = "false",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eq_setting = 1,
+ receive_pma0.force_signal_detect = "false",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.loop_1_digital_filter = 8,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.power_down_pd2_clocks = "false",
+ receive_pma0.ppm_gen1_2_xcnt_en = 1,
+ receive_pma0.ppm_post_eidle = 0,
+ receive_pma0.ppmselect = 8,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.signal_detect_hysteresis = 4,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma0.signal_detect_loss_threshold = 3,
+ receive_pma0.termination = "OCT 85 Ohms",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
+ cycloneiv_hssi_rx_pma receive_pma1
+ (
+ .analogtestbus(wire_receive_pma1_analogtestbus),
+ .clockout(wire_receive_pma1_clockout),
+ .crupowerdn(cent_unit_rxcrupowerdn[1]),
+ .datain(rx_datain[1]),
+ .datastrobeout(),
+ .deserclock(rx_deserclock_in[1]),
+ .diagnosticlpbkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(wire_receive_pma1_dprioout),
+ .freqlocked(wire_receive_pma1_freqlocked),
+ .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[1])),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dpashift(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h01,
+ receive_pma1.effective_data_rate = "2500 Mbps",
+ receive_pma1.enable_local_divider = "false",
+ receive_pma1.enable_ltd = "false",
+ receive_pma1.enable_ltr = "false",
+ receive_pma1.enable_pd2_deadzone_detection = "true",
+ receive_pma1.enable_second_order_loop = "false",
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eq_setting = 1,
+ receive_pma1.force_signal_detect = "false",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.loop_1_digital_filter = 8,
+ receive_pma1.offset_cancellation = 1,
+ receive_pma1.power_down_pd2_clocks = "false",
+ receive_pma1.ppm_gen1_2_xcnt_en = 1,
+ receive_pma1.ppm_post_eidle = 0,
+ receive_pma1.ppmselect = 8,
+ receive_pma1.protocol_hint = "pcie",
+ receive_pma1.signal_detect_hysteresis = 4,
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma1.signal_detect_loss_threshold = 3,
+ receive_pma1.termination = "OCT 85 Ohms",
+ receive_pma1.use_external_termination = "false",
+ receive_pma1.lpm_type = "cycloneiv_hssi_rx_pma";
+ cycloneiv_hssi_rx_pma receive_pma2
+ (
+ .analogtestbus(wire_receive_pma2_analogtestbus),
+ .clockout(wire_receive_pma2_clockout),
+ .crupowerdn(cent_unit_rxcrupowerdn[2]),
+ .datain(rx_datain[2]),
+ .datastrobeout(),
+ .deserclock(rx_deserclock_in[2]),
+ .diagnosticlpbkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(wire_receive_pma2_dprioout),
+ .freqlocked(wire_receive_pma2_freqlocked),
+ .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[2])),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma2_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dpashift(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.allow_serial_loopback = "false",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.common_mode = "0.82V",
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h01,
+ receive_pma2.effective_data_rate = "2500 Mbps",
+ receive_pma2.enable_local_divider = "false",
+ receive_pma2.enable_ltd = "false",
+ receive_pma2.enable_ltr = "false",
+ receive_pma2.enable_pd2_deadzone_detection = "true",
+ receive_pma2.enable_second_order_loop = "false",
+ receive_pma2.eq_dc_gain = 3,
+ receive_pma2.eq_setting = 1,
+ receive_pma2.force_signal_detect = "false",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.loop_1_digital_filter = 8,
+ receive_pma2.offset_cancellation = 1,
+ receive_pma2.power_down_pd2_clocks = "false",
+ receive_pma2.ppm_gen1_2_xcnt_en = 1,
+ receive_pma2.ppm_post_eidle = 0,
+ receive_pma2.ppmselect = 8,
+ receive_pma2.protocol_hint = "pcie",
+ receive_pma2.signal_detect_hysteresis = 4,
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma2.signal_detect_loss_threshold = 3,
+ receive_pma2.termination = "OCT 85 Ohms",
+ receive_pma2.use_external_termination = "false",
+ receive_pma2.lpm_type = "cycloneiv_hssi_rx_pma";
+ cycloneiv_hssi_rx_pma receive_pma3
+ (
+ .analogtestbus(wire_receive_pma3_analogtestbus),
+ .clockout(wire_receive_pma3_clockout),
+ .crupowerdn(cent_unit_rxcrupowerdn[3]),
+ .datain(rx_datain[3]),
+ .datastrobeout(),
+ .deserclock(rx_deserclock_in[3]),
+ .diagnosticlpbkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_receive_pma3_dprioout),
+ .freqlocked(wire_receive_pma3_freqlocked),
+ .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[3])),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma3_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .dpashift(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.allow_serial_loopback = "false",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.common_mode = "0.82V",
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h01,
+ receive_pma3.effective_data_rate = "2500 Mbps",
+ receive_pma3.enable_local_divider = "false",
+ receive_pma3.enable_ltd = "false",
+ receive_pma3.enable_ltr = "false",
+ receive_pma3.enable_pd2_deadzone_detection = "true",
+ receive_pma3.enable_second_order_loop = "false",
+ receive_pma3.eq_dc_gain = 3,
+ receive_pma3.eq_setting = 1,
+ receive_pma3.force_signal_detect = "false",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.loop_1_digital_filter = 8,
+ receive_pma3.offset_cancellation = 1,
+ receive_pma3.power_down_pd2_clocks = "false",
+ receive_pma3.ppm_gen1_2_xcnt_en = 1,
+ receive_pma3.ppm_post_eidle = 0,
+ receive_pma3.ppmselect = 8,
+ receive_pma3.protocol_hint = "pcie",
+ receive_pma3.signal_detect_hysteresis = 4,
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma3.signal_detect_loss_threshold = 3,
+ receive_pma3.termination = "OCT 85 Ohms",
+ receive_pma3.use_external_termination = "false",
+ receive_pma3.lpm_type = "cycloneiv_hssi_rx_pma";
+ cycloneiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({tx_ctrlenable[1:0]}),
+ .datain({{4{1'b0}}, tx_datain_wire[15:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({2{tx_forceelecidle[0]}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({tx_forcedisp_wire[1:0]}),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifooverflow(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifox4bytesel(int_tx_phfifoxnbytesel[0]),
+ .phfifox4rdclk(int_tx_phfifoxnrdclk[0]),
+ .phfifox4rdenable(int_tx_phfifoxnrdenable[0]),
+ .phfifox4wrenable(int_tx_phfifoxnwrenable[0]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(1'b0),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrlenable(),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({22{1'b0}}),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .xgmctrl(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "x4",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 4,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "central",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
+ cycloneiv_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({tx_ctrlenable[3:2]}),
+ .datain({{4{1'b0}}, tx_datain_wire[31:16]}),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({2{tx_forceelecidle[1]}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(wire_transmit_pcs1_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({tx_forcedisp_wire[3:2]}),
+ .forceelecidle(tx_forceelecidle[1]),
+ .forceelecidleout(wire_transmit_pcs1_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifooverflow(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifox4bytesel(int_tx_phfifoxnbytesel[1]),
+ .phfifox4rdclk(int_tx_phfifoxnrdclk[1]),
+ .phfifox4rdenable(int_tx_phfifoxnrdenable[1]),
+ .phfifox4wrenable(int_tx_phfifoxnwrenable[1]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(1'b0),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrlenable(),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({22{1'b0}}),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .xgmctrl(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.bitslip_enable = "false",
+ transmit_pcs1.channel_bonding = "x4",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 16,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h01,
+ transmit_pcs1.elec_idle_delay = 4,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie",
+ transmit_pcs1.refclk_select = "central",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "true",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "cycloneiv_hssi_tx_pcs";
+ cycloneiv_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({tx_ctrlenable[5:4]}),
+ .datain({{4{1'b0}}, tx_datain_wire[47:32]}),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(tx_detectrxloop[2]),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dispval({2{tx_forceelecidle[2]}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(wire_transmit_pcs2_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[8:6]),
+ .enrevparallellpbk(tx_revparallellpbken[2]),
+ .forcedisp({tx_forcedisp_wire[5:4]}),
+ .forceelecidle(tx_forceelecidle[2]),
+ .forceelecidleout(wire_transmit_pcs2_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifooverflow(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifox4bytesel(int_tx_phfifoxnbytesel[2]),
+ .phfifox4rdclk(int_tx_phfifoxnrdclk[2]),
+ .phfifox4rdenable(int_tx_phfifoxnrdenable[2]),
+ .phfifox4wrenable(int_tx_phfifoxnwrenable[2]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs2_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
+ .pipestatetransdone(1'b0),
+ .powerdn(powerdn[5:4]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[59:40]),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrlenable(),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({22{1'b0}}),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .xgmctrl(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "false",
+ transmit_pcs2.bitslip_enable = "false",
+ transmit_pcs2.channel_bonding = "x4",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 16,
+ transmit_pcs2.core_clock_0ppm = "false",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "pipe",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "new",
+ transmit_pcs2.dprio_config_mode = 6'h01,
+ transmit_pcs2.elec_idle_delay = 4,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "true",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "pcie",
+ transmit_pcs2.refclk_select = "central",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "true",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "cycloneiv_hssi_tx_pcs";
+ cycloneiv_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({tx_ctrlenable[7:6]}),
+ .datain({{4{1'b0}}, tx_datain_wire[63:48]}),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(tx_detectrxloop[3]),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dispval({2{tx_forceelecidle[3]}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(wire_transmit_pcs3_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[11:9]),
+ .enrevparallellpbk(tx_revparallellpbken[3]),
+ .forcedisp({tx_forcedisp_wire[7:6]}),
+ .forceelecidle(tx_forceelecidle[3]),
+ .forceelecidleout(wire_transmit_pcs3_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifooverflow(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifox4bytesel(int_tx_phfifoxnbytesel[3]),
+ .phfifox4rdclk(int_tx_phfifoxnrdclk[3]),
+ .phfifox4rdenable(int_tx_phfifoxnrdenable[3]),
+ .phfifox4wrenable(int_tx_phfifoxnwrenable[3]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs3_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
+ .pipestatetransdone(1'b0),
+ .powerdn(powerdn[7:6]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[79:60]),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrlenable(),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({22{1'b0}}),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .xgmctrl(1'b0),
+ .xgmdatain({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "false",
+ transmit_pcs3.bitslip_enable = "false",
+ transmit_pcs3.channel_bonding = "x4",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 16,
+ transmit_pcs3.core_clock_0ppm = "false",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "pipe",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "new",
+ transmit_pcs3.dprio_config_mode = 6'h01,
+ transmit_pcs3.elec_idle_delay = 4,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "true",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "pcie",
+ transmit_pcs3.refclk_select = "central",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "true",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "cycloneiv_hssi_tx_pcs";
+ cycloneiv_hssi_tx_pma transmit_pma0
+ (
+ .cgbpowerdn(cent_unit_txdividerpowerdown[0]),
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({tx_dataout_pcs_to_pma[9:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in(tx_pma_fastrefclk0in[0]),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in(tx_pma_refclk0in[0]),
+ .refclk0inpulse(tx_pma_refclk0inpulse[0]),
+ .reverselpbkin(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .diagnosticlpbkin(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.effective_data_rate = "2500 Mbps",
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.preemp_tap_1 = 1,
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "low",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_rx_detect = "true",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
+ cycloneiv_hssi_tx_pma transmit_pma1
+ (
+ .cgbpowerdn(cent_unit_txdividerpowerdown[1]),
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({tx_dataout_pcs_to_pma[19:10]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(wire_transmit_pma1_dprioout),
+ .fastrefclk0in(tx_pma_fastrefclk0in[1]),
+ .forceelecidle(tx_pcs_forceelecidleout[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in(tx_pma_refclk0in[1]),
+ .refclk0inpulse(tx_pma_refclk0inpulse[1]),
+ .reverselpbkin(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .diagnosticlpbkin(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h01,
+ transmit_pma1.effective_data_rate = "2500 Mbps",
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.preemp_tap_1 = 1,
+ transmit_pma1.protocol_hint = "pcie",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "low",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_external_termination = "false",
+ transmit_pma1.use_rx_detect = "true",
+ transmit_pma1.vod_selection = 4,
+ transmit_pma1.lpm_type = "cycloneiv_hssi_tx_pma";
+ cycloneiv_hssi_tx_pma transmit_pma2
+ (
+ .cgbpowerdn(cent_unit_txdividerpowerdown[2]),
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({tx_dataout_pcs_to_pma[29:20]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(wire_transmit_pma2_dprioout),
+ .fastrefclk0in(tx_pma_fastrefclk0in[2]),
+ .forceelecidle(tx_pcs_forceelecidleout[2]),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in(tx_pma_refclk0in[2]),
+ .refclk0inpulse(tx_pma_refclk0inpulse[2]),
+ .reverselpbkin(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma2_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[2])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .diagnosticlpbkin(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h01,
+ transmit_pma2.effective_data_rate = "2500 Mbps",
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.preemp_tap_1 = 1,
+ transmit_pma2.protocol_hint = "pcie",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "low",
+ transmit_pma2.termination = "OCT 100 Ohms",
+ transmit_pma2.use_external_termination = "false",
+ transmit_pma2.use_rx_detect = "true",
+ transmit_pma2.vod_selection = 4,
+ transmit_pma2.lpm_type = "cycloneiv_hssi_tx_pma";
+ cycloneiv_hssi_tx_pma transmit_pma3
+ (
+ .cgbpowerdn(cent_unit_txdividerpowerdown[3]),
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({tx_dataout_pcs_to_pma[39:30]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_transmit_pma3_dprioout),
+ .fastrefclk0in(tx_pma_fastrefclk0in[3]),
+ .forceelecidle(tx_pcs_forceelecidleout[3]),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in(tx_pma_refclk0in[3]),
+ .refclk0inpulse(tx_pma_refclk0inpulse[3]),
+ .reverselpbkin(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma3_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[3])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .diagnosticlpbkin(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h01,
+ transmit_pma3.effective_data_rate = "2500 Mbps",
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.preemp_tap_1 = 1,
+ transmit_pma3.protocol_hint = "pcie",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "low",
+ transmit_pma3.termination = "OCT 100 Ohms",
+ transmit_pma3.use_external_termination = "false",
+ transmit_pma3.use_rx_detect = "true",
+ transmit_pma3.vod_selection = 4,
+ transmit_pma3.lpm_type = "cycloneiv_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b0,
+ cent_unit_quadresetout = {{3{1'b0}}, wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]},
+ cent_unit_rxpcsdprioin = {rx_pcsdprioout[1599:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
+ cent_unit_rxpmadprioin = {rx_pmadprioout[1199:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1199:0]},
+ cent_unit_tx_dprioin = {tx_txdprioout[599:0]},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]},
+ cent_unit_txpmadprioin = {tx_pmadprioout[1199:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1199:0]},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_cent_unit0_coreclkout},
+ fixedclk_to_cmu = {4{reconfig_clk}},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs3_grayelecidleinferselout, wire_transmit_pcs2_grayelecidleinferselout, wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
+ int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs3_pipeenrevparallellpbkout, wire_transmit_pcs2_pipeenrevparallellpbkout, wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
+ int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {4{int_rxphfifox4byteselout[0]}},
+ int_rx_phfifoxnrdenable = {4{int_rxphfifox4rdenableout[0]}},
+ int_rx_phfifoxnwrclk = {4{int_rxphfifox4wrclkout[0]}},
+ int_rx_phfifoxnwrenable = {4{int_rxphfifox4wrenableout[0]}},
+ int_rxcoreclk = {int_rx_coreclkout[0]},
+ int_rxphfifordenable = {int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {4{int_txphfifox4byteselout[0]}},
+ int_tx_phfifoxnrdclk = {4{int_txphfifox4rdclkout[0]}},
+ int_tx_phfifoxnrdenable = {4{int_txphfifox4rdenableout[0]}},
+ int_tx_phfifoxnwrenable = {4{int_txphfifox4wrenableout[0]}},
+ int_txcoreclk = {int_tx_coreclkout[0]},
+ int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[3:0]},
+ pipedatavalid_out = {wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[3:0]},
+ pipeelecidle_out = {wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll_locked = {wire_pll0_locked},
+ pll_powerdown = 1'b0,
+ reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ refclk_pma = {wire_cent_unit0_refclkout},
+ rx_analogreset_in = {4{((~ reconfig_togxb_busy) & rx_analogreset[0])}},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]},
+ rx_coreclk_in = {4{coreclkout_wire[0]}},
+ rx_ctrldetect = {wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[63:0]},
+ rx_deserclock_in = {4{wire_pll0_icdrclk}},
+ rx_digitalreset_in = {4{rx_digitalreset[0]}},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_elecidleinfersel = {12{1'b0}},
+ rx_enapatternalign = {4{1'b0}},
+ rx_freqlocked = {(wire_receive_pma3_freqlocked & (~ rx_analogreset[0])), (wire_receive_pma2_freqlocked & (~ rx_analogreset[0])), (wire_receive_pma1_freqlocked & (~ rx_analogreset[0])), (wire_receive_pma0_freqlocked & (~ rx_analogreset[0]))},
+ rx_locktodata = {4{1'b0}},
+ rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[1599:0]},
+ rx_pcsdprioout = {wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = {4{1'b1}},
+ rx_phfiforeset = {4{1'b0}},
+ rx_phfifowrdisable = {4{1'b0}},
+ rx_pll_pfdrefclkout_wire = {4{wire_pll0_fref}},
+ rx_pma_analogtestbus = {1'b0, wire_receive_pma3_analogtestbus[6], wire_receive_pma2_analogtestbus[6], wire_receive_pma1_analogtestbus[6], wire_receive_pma0_analogtestbus[6]},
+ rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[9:0], wire_receive_pma2_recoverdataout[9:0], wire_receive_pma1_recoverdataout[9:0], wire_receive_pma0_recoverdataout[9:0]},
+ rx_pmadprioin_wire = {cent_unit_rxpmadprioout[1199:0]},
+ rx_pmadprioout = {wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
+ rx_powerdown = {4{1'b0}},
+ rx_powerdown_in = {rx_powerdown[3:0]},
+ rx_prbscidenable = {4{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {4{1'b0}},
+ rx_signaldetect_wire = {wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
+ rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]},
+ tx_coreclk_in = {4{coreclkout_wire[0]}},
+ tx_datain_wire = {tx_datain[63:0]},
+ tx_dataout = {txdataout[3:0]},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout[9:0], wire_transmit_pcs2_dataout[9:0], wire_transmit_pcs1_dataout[9:0], wire_transmit_pcs0_dataout[9:0]},
+ tx_digitalreset_in = {4{tx_digitalreset[0]}},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_dprioin_wire = {cent_unit_txdprioout[599:0]},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[3], 1'b0, tx_forcedispcompliance[2], 1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = {4{1'b0}},
+ tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = {4{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pma_fastrefclk0in = {4{wire_pll0_clk[0]}},
+ tx_pma_refclk0in = {4{wire_pll0_clk[1]}},
+ tx_pma_refclk0inpulse = {4{wire_pll0_clk[2]}},
+ tx_pmadprioin_wire = {cent_unit_txpmadprioout[1199:0]},
+ tx_pmadprioout = {wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = {4{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
+ txdataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+ initial/*synthesis enable_verilog_initial_construct*/
+ begin
+ $display("Warning: MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) alt_c3gxb|receiver_termination The value assigned is oct_100_ohms and the valid value list is OCT_85_OHMS|OCT_150_OHMS");
+ end
+endmodule //altpcie_serdes_3cgx_x4d_gen1_08p_alt_c3gxb_id48
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_3cgx_x4d_gen1_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_areset,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_syncstatus,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ input [0:0] pll_areset;
+ input [0:0] pll_inclk;
+ input [7:0] powerdn;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+ output [0:0] coreclkout;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ output [0:0] pll_locked;
+ output [4:0] reconfig_fromgxb;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [3:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [7:0] rx_syncstatus;
+ output [3:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [3:0] sub_wire0;
+ wire [7:0] sub_wire1;
+ wire [3:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [4:0] sub_wire4;
+ wire [3:0] sub_wire5;
+ wire [11:0] sub_wire6;
+ wire [7:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [63:0] sub_wire9;
+ wire [3:0] sub_wire10;
+ wire [3:0] sub_wire11;
+ wire [7:0] sub_wire12;
+ wire [3:0] pipedatavalid = sub_wire0[3:0];
+ wire [7:0] rx_patterndetect = sub_wire1[7:0];
+ wire [3:0] pipephydonestatus = sub_wire2[3:0];
+ wire [0:0] pll_locked = sub_wire3[0:0];
+ wire [4:0] reconfig_fromgxb = sub_wire4[4:0];
+ wire [3:0] rx_freqlocked = sub_wire5[3:0];
+ wire [11:0] pipestatus = sub_wire6[11:0];
+ wire [7:0] rx_syncstatus = sub_wire7[7:0];
+ wire [0:0] coreclkout = sub_wire8[0:0];
+ wire [63:0] rx_dataout = sub_wire9[63:0];
+ wire [3:0] pipeelecidle = sub_wire10[3:0];
+ wire [3:0] tx_dataout = sub_wire11[3:0];
+ wire [7:0] rx_ctrldetect = sub_wire12[7:0];
+
+ altpcie_serdes_3cgx_x4d_gen1_08p_alt_c3gxb_id48 altpcie_serdes_3cgx_x4d_gen1_08p_alt_c3gxb_id48_component (
+ .pll_inclk (pll_inclk),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_detectrxloop (tx_detectrxloop),
+ .cal_blk_clk (cal_blk_clk),
+ .tx_forceelecidle (tx_forceelecidle),
+ .rx_datain (rx_datain),
+ .rx_digitalreset (rx_digitalreset),
+ .pll_areset (pll_areset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .tx_datain (tx_datain),
+ .tx_digitalreset (tx_digitalreset),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .reconfig_clk (reconfig_clk),
+ .rx_analogreset (rx_analogreset),
+ .powerdn (powerdn),
+ .tx_ctrlenable (tx_ctrlenable),
+ .pipedatavalid (sub_wire0),
+ .rx_patterndetect (sub_wire1),
+ .pipephydonestatus (sub_wire2),
+ .pll_locked (sub_wire3),
+ .reconfig_fromgxb (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .pipestatus (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .coreclkout (sub_wire8),
+ .rx_dataout (sub_wire9),
+ .pipeelecidle (sub_wire10),
+ .tx_dataout (sub_wire11),
+ .rx_ctrldetect (sub_wire12));
+ defparam
+ altpcie_serdes_3cgx_x4d_gen1_08p_alt_c3gxb_id48_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "GEN 1-X4"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: pll_divide_by STRING "2"
+// Retrieval info: CONSTANT: pll_multiply_by STRING "25"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
+// Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: top_module_name STRING "altpcie_serdes_3cgx_x4d_gen1_08p"
+// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
+// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
+// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x4d_gen1_08p.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x4d_gen1_08p.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x4d_gen1_08p.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x4d_gen1_08p.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x4d_gen1_08p.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x4d_gen1_08p_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x4d_gen1_08p_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: LIB_FILE: cycloneiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..6b3c238d5519c8d75ea8939137988438de2c68f3
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v
@@ -0,0 +1,1563 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_4sgx_x1d_gen1_08p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Internal Build 106 07/20/2008 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" elec_idle_infer_enable="false" enable_0ppm="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gxb_analog_power="2.5v" gxb_powerdown_width=1 intended_device_speed_grade=2 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_dprio_mode=0 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=800 rx_cru_divide_by=2 rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_multiply_by=25 rx_cru_n_divider=2 rx_cru_pfd_clk_select=0 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="indv" tx_channel_width=8 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=800 tx_pll_divide_by=2 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_multiply_by=25 tx_pll_n_divider=2 tx_pll_pfd_clk_select=0 tx_pll_vco_post_scale_divider=2 tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 8.1 cbx_alt4gxb 2008:07:18:07:31:37:SJ cbx_mgl 2008:07:11:15:23:48:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 2 stratixiv_hssi_rx_pcs 1 stratixiv_hssi_rx_pma 1 stratixiv_hssi_tx_pcs 1 stratixiv_hssi_tx_pma 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_4sgx_x1d_gen1_08p_alt4gxb_of69
+ (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) /* synthesis synthesis_clearbox=1 */;
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [1:0] powerdn;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ output [0:0] rx_ctrldetect;
+ input [0:0] rx_datain;
+ output [7:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [0:0] rx_freqlocked;
+ output [0:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [0:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ input [0:0] tx_ctrlenable;
+ input [7:0] tx_datain;
+ output [0:0] tx_dataout;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_ch_clk_div0_analogrefclkout;
+ wire wire_ch_clk_div0_analogrefclkpulse;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxadcepowerdown;
+ wire [3:0] wire_cent_unit0_rxadceresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire [1:0] analogfastrefclkout;
+ wire [1:0] analogrefclkout;
+ wire [0:0] analogrefclkpulse;
+ wire cal_blk_powerdown;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [3:0] cent_unit_rxadcepowerdn;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire fixedclk;
+ wire [5:0] fixedclk_in;
+ wire [0:0] nonusertocmu_out;
+ wire [0:0] pipedatavalid_out;
+ wire [0:0] pipeelecidle_out;
+ wire [9:0] pll0_clkin;
+ wire [3:0] pll0_out;
+ wire [1:0] pll_ch_dataout_wire;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire reconfig_clk;
+ wire [3:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [0:0] rx_bitslip;
+ wire [0:0] rx_coreclk_in;
+ wire [8:0] rx_cruclk_in;
+ wire [3:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [2:0] rx_elecidleinfersel;
+ wire [0:0] rx_enapatternalign;
+ wire [0:0] rx_freqlocked_wire;
+ wire [0:0] rx_locktodata;
+ wire [0:0] rx_locktodata_wire;
+ wire [0:0] rx_locktorefclk_wire;
+ wire [7:0] rx_out_wire;
+ wire [1:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [0:0] rx_phfifordenable;
+ wire [0:0] rx_phfiforeset;
+ wire [0:0] rx_phfifowrdisable;
+ wire [0:0] rx_pipestatetransdoneout;
+ wire [0:0] rx_pldcruclk_in;
+ wire [3:0] rx_pll_clkout;
+ wire [0:0] rx_pll_pfdrefclkout_wire;
+ wire [0:0] rx_plllocked_wire;
+ wire [0:0] rx_pma_clockout;
+ wire [0:0] rx_pma_dataout;
+ wire [0:0] rx_pma_locktorefout;
+ wire [19:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [0:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [0:0] rx_prbscidenable;
+ wire [19:0] rx_revparallelfdbkdata;
+ wire [0:0] rx_rmfiforeset;
+ wire [3:0] rx_rxadceresetout;
+ wire [5:0] rx_rxcruresetout;
+ wire [0:0] rx_signaldetect_wire;
+ wire [5:0] tx_analogreset_out;
+ wire [0:0] tx_clkout_int_wire;
+ wire [0:0] tx_core_clkout_wire;
+ wire [0:0] tx_coreclk_in;
+ wire [7:0] tx_datain_wire;
+ wire [43:0] tx_datainfull;
+ wire [19:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [0:0] tx_forcedisp_wire;
+ wire [0:0] tx_invpolarity;
+ wire [0:0] tx_localrefclk;
+ wire [0:0] tx_phfiforeset;
+ wire [0:0] tx_pipedeemph;
+ wire [2:0] tx_pipemargin;
+ wire [1:0] tx_pipepowerdownout;
+ wire [3:0] tx_pipepowerstateout;
+ wire [0:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [0:0] tx_revparallellpbken;
+ wire [0:0] tx_rxdetectvalidout;
+ wire [0:0] tx_rxfoundout;
+ wire [0:0] txdetectrxout;
+
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider ch_clk_div0
+ (
+ .analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_ch_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(pll0_out[3:0]),
+ .coreclkout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(),
+ .rateswitchout(),
+ .refclkout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .dprioin({100{1'b0}}),
+ .powerdn(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
+ ch_clk_div0.data_rate = 800,
+ ch_clk_div0.divide_by = 5,
+ ch_clk_div0.divider_type = "CHANNEL_REGULAR",
+ ch_clk_div0.dprio_config_mode = 6'h00,
+ ch_clk_div0.enable_dynamic_divider = "false",
+ ch_clk_div0.enable_refclk_out = "false",
+ ch_clk_div0.inclk_select = 0,
+ ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
+ ch_clk_div0.pre_divide_by = 1,
+ ch_clk_div0.refclk_divide_by = 2,
+ ch_clk_div0.refclk_multiply_by = 25,
+ ch_clk_div0.select_local_rate_switch_done = "false",
+ ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_coreclkout_phase_shift = 0,
+ ch_clk_div0.sim_refclkout_phase_shift = 0,
+ ch_clk_div0.use_coreclk_out_post_divider = "false",
+ ch_clk_div0.use_refclk_post_divider = "false",
+ ch_clk_div0.use_vco_bypass = "false",
+ ch_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(),
+ .cmudividerdprioin({600{1'b0}}),
+ .cmudividerdprioout(),
+ .cmuplldprioin({1800{1'b0}}),
+ .cmuplldprioout(),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(1'b1),
+ .dpriodisableout(),
+ .dprioin(1'b0),
+ .dprioload(1'b0),
+ .dpriooe(),
+ .dprioout(),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk(fixedclk_in[5:0]),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(wire_cent_unit0_rxadcepowerdown),
+ .rxadceresetout(wire_cent_unit0_rxadceresetout),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxdprioout(),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({1600{1'b0}}),
+ .rxpcsdprioout(),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpmadprioin({1800{1'b0}}),
+ .rxpmadprioout(),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txdprioout(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({600{1'b0}}),
+ .txpcsdprioout(),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout(),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({1800{1'b0}}),
+ .txpmadprioout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .rateswitch(1'b0),
+ .rateswitchdonein(1'b0),
+ .rxclk(1'b0),
+ .rxcoreclk(1'b0),
+ .rxdprioin({1200{1'b0}}),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({6000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txdprioin({600{1'b0}}),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 250000,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "none",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "local reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "false",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "none",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "false",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "2.5V",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.charge_pump_current_bits = 0,
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.inclk1_input_period = 5000,
+ rx_cdr_pll0.inclk2_input_period = 5000,
+ rx_cdr_pll0.inclk3_input_period = 5000,
+ rx_cdr_pll0.inclk4_input_period = 5000,
+ rx_cdr_pll0.inclk5_input_period = 5000,
+ rx_cdr_pll0.inclk6_input_period = 5000,
+ rx_cdr_pll0.inclk7_input_period = 5000,
+ rx_cdr_pll0.inclk8_input_period = 5000,
+ rx_cdr_pll0.inclk9_input_period = 5000,
+ rx_cdr_pll0.loop_filter_c_bits = 0,
+ rx_cdr_pll0.loop_filter_r_bits = 0,
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 2,
+ rx_cdr_pll0.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll0.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.protocol_hint = "pcie",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_data_rate = 800,
+ rx_cdr_pll0.vco_divide_by = 2,
+ rx_cdr_pll0.vco_multiply_by = 25,
+ rx_cdr_pll0.vco_post_scale = 2,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.channel_num = 4,
+ tx_pll0.charge_pump_current_bits = 0,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.inclk1_input_period = 5000,
+ tx_pll0.inclk2_input_period = 5000,
+ tx_pll0.inclk3_input_period = 5000,
+ tx_pll0.inclk4_input_period = 5000,
+ tx_pll0.inclk5_input_period = 5000,
+ tx_pll0.inclk6_input_period = 5000,
+ tx_pll0.inclk7_input_period = 5000,
+ tx_pll0.inclk8_input_period = 5000,
+ tx_pll0.inclk9_input_period = 5000,
+ tx_pll0.loop_filter_c_bits = 0,
+ tx_pll0.loop_filter_r_bits = 0,
+ tx_pll0.m = 25,
+ tx_pll0.n = 2,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.protocol_hint = "pcie",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_data_rate = 0,
+ tx_pll0.vco_divide_by = 0,
+ tx_pll0.vco_multiply_by = 0,
+ tx_pll0.vco_post_scale = 2,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[0]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(),
+ .phfifooverflow(),
+ .phfifoptrsresetout(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(),
+ .phfifowrenableout(),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxnwrclk({3{1'b0}}),
+ .phfifoxnwrenable({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "none",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 8,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "local reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h00,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "none",
+ receive_pcs0.ph_fifo_xn_select = 1,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 250000,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "false",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[0]),
+ .adcereset(rx_rxadceresetout[0]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(1'b1),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h00,
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 0,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 4,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
+ .datain({{32{1'b0}}, tx_datain_wire[7:0]}),
+ .datainfull(tx_datainfull[43:0]),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(1'b1),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifooverflow(),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifobyteserdisable(1'b0),
+ .phfifoptrsreset(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdclk({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .phfifoxnwrenable({3{1'b0}}),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.channel_bonding = "none",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 8,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h00,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs0.ph_fifo_xn_select = 1,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "local",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "false",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(1'b1),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(),
+ .fastrefclk0in(analogfastrefclkout[1:0]),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({analogrefclkout[1:0]}),
+ .refclk0inpulse(analogrefclkpulse[0]),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "AUTO",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 0,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h00,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
+ analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
+ analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
+ cal_blk_powerdown = 1'b1,
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxadcepowerdn = {wire_cent_unit0_rxadcepowerdown},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ fixedclk = 1'b0,
+ fixedclk_in = {5'b00000, fixedclk},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[0]},
+ pipedatavalid_out = {wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[0]},
+ pipeelecidle_out = {wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs0_pipestatus},
+ pll0_clkin = {9'b000000000, pll_inclk_wire[0]},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_clk = 1'b0,
+ rx_analogreset_in = {3'b000, rx_analogreset[0]},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_bitslip = 1'b0,
+ rx_coreclk_in = {tx_core_clkout_wire[0]},
+ rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
+ rx_dataout = {rx_out_wire[7:0]},
+ rx_deserclock_in = {rx_pll_clkout[3:0]},
+ rx_digitalreset_in = {3'b000, rx_digitalreset[0]},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
+ rx_elecidleinfersel = {3{1'b0}},
+ rx_enapatternalign = 1'b0,
+ rx_freqlocked = {rx_freqlocked_wire[0]},
+ rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = 1'b0,
+ rx_locktodata_wire = {rx_locktodata[0]},
+ rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
+ rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {1200'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ rx_phfifordenable = 1'b1,
+ rx_phfiforeset = 1'b0,
+ rx_phfifowrdisable = 1'b0,
+ rx_pipestatetransdoneout = {wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[0]},
+ rx_pll_clkout = {wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {rx_plllocked_wire[0]},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
+ rx_pma_clockout = {wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ rx_powerdown = 1'b0,
+ rx_powerdown_in = {3'b000, rx_powerdown[0]},
+ rx_prbscidenable = 1'b0,
+ rx_revparallelfdbkdata = {wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = 1'b0,
+ rx_rxadceresetout = {wire_cent_unit0_rxadceresetout},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout = {tx_core_clkout_wire[0]},
+ tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
+ tx_core_clkout_wire = {tx_clkout_int_wire[0]},
+ tx_coreclk_in = {tx_core_clkout_wire[0]},
+ tx_datain_wire = {tx_datain[7:0]},
+ tx_datainfull = {44{1'b0}},
+ tx_dataout = {wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {3'b000, tx_digitalreset[0]},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
+ tx_dprioin_wire = {1050'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 150'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ tx_forcedisp_wire = {tx_forcedispcompliance[0]},
+ tx_invpolarity = 1'b0,
+ tx_localrefclk = {wire_transmit_pma0_clockout},
+ tx_phfiforeset = 1'b0,
+ tx_pipedeemph = 1'b0,
+ tx_pipemargin = {3{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = 1'b0,
+ tx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ tx_revparallellpbken = 1'b0,
+ tx_rxdetectvalidout = {wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma0_rxfoundout},
+ txdetectrxout = {wire_transmit_pcs0_txdetectrx};
+endmodule //altpcie_serdes_4sgx_x1d_gen1_08p_alt4gxb_of69
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_4sgx_x1d_gen1_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout)/* synthesis synthesis_clearbox = 1 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [1:0] powerdn;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [0:0] tx_ctrlenable;
+ input [7:0] tx_datain;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ output [0:0] pll_locked;
+ output [0:0] rx_ctrldetect;
+ output [7:0] rx_dataout;
+ output [0:0] rx_freqlocked;
+ output [0:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [0:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [0:0] sub_wire7;
+ wire [2:0] sub_wire8;
+ wire [0:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [7:0] sub_wire12;
+ wire [0:0] rx_patterndetect = sub_wire0[0:0];
+ wire [0:0] rx_ctrldetect = sub_wire1[0:0];
+ wire [0:0] pipedatavalid = sub_wire2[0:0];
+ wire [0:0] pipephydonestatus = sub_wire3[0:0];
+ wire [0:0] rx_pll_locked = sub_wire4[0:0];
+ wire [0:0] rx_freqlocked = sub_wire5[0:0];
+ wire [0:0] tx_dataout = sub_wire6[0:0];
+ wire [0:0] pipeelecidle = sub_wire7[0:0];
+ wire [2:0] pipestatus = sub_wire8[2:0];
+ wire [0:0] rx_syncstatus = sub_wire9[0:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [0:0] pll_locked = sub_wire11[0:0];
+ wire [7:0] rx_dataout = sub_wire12[7:0];
+
+ altpcie_serdes_4sgx_x1d_gen1_08p_alt4gxb_of69 altpcie_serdes_4sgx_x1d_gen1_08p_alt4gxb_of69_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .rx_datain (rx_datain),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .rx_ctrldetect (sub_wire1),
+ .pipedatavalid (sub_wire2),
+ .pipephydonestatus (sub_wire3),
+ .rx_pll_locked (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .tx_dataout (sub_wire6),
+ .pipeelecidle (sub_wire7),
+ .pipestatus (sub_wire8),
+ .rx_syncstatus (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .pll_locked (sub_wire11),
+ .rx_dataout (sub_wire12));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.82"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.65"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.5"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE NUMERIC "2"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "auto"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_analog_power STRING "2.5v"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: rx_cru_divide_by NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_multiply_by NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: tx_pll_divide_by NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_multiply_by NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 1 0 OUTPUT NODEFVAL "rx_pll_locked[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 1 0 @rx_pll_locked 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_08p.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_08p.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_08p.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_08p.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_08p.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_08p_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_08p_bb.v TRUE FALSE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v
new file mode 100644
index 0000000000000000000000000000000000000000..2ad802b1d04f7fda3a5f23dfbadd30bb139c9c72
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v
@@ -0,0 +1,1656 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_4sgx_x1d_gen1_16p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Internal Build 106 07/20/2008 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" elec_idle_infer_enable="false" enable_0ppm="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gxb_analog_power="3.0v" gxb_powerdown_width=1 intended_device_speed_grade=2 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" preemphasis_ctrl_1stposttap_setting=3 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_dprio_mode=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=800 rx_cru_divide_by=2 rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_multiply_by=25 rx_cru_n_divider=2 rx_cru_pfd_clk_select=0 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.4v" tx_channel_bonding="indv" tx_channel_width=16 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=800 tx_pll_divide_by=2 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_multiply_by=25 tx_pll_n_divider=2 tx_pll_pfd_clk_select=0 tx_pll_vco_post_scale_divider=2 tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 8.1 cbx_alt4gxb 2008:07:18:07:31:37:SJ cbx_mgl 2008:07:11:15:23:48:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 2 stratixiv_hssi_rx_pcs 1 stratixiv_hssi_rx_pma 1 stratixiv_hssi_tx_pcs 1 stratixiv_hssi_tx_pma 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_4sgx_x1d_gen1_16p_alt4gxb_hcd9
+ (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) /* synthesis synthesis_clearbox=1 */;
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [1:0] powerdn;
+ input reconfig_clk;
+ output [0:0] reconfig_fromgxb;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ output [1:0] rx_ctrldetect;
+ input [0:0] rx_datain;
+ output [15:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ output [0:0] tx_dataout;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_ch_clk_div0_analogrefclkout;
+ wire wire_ch_clk_div0_analogrefclkpulse;
+ wire [99:0] wire_ch_clk_div0_dprioout;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxadcepowerdown;
+ wire [3:0] wire_cent_unit0_rxadceresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire [299:0] wire_tx_pll0_dprioout;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire [1:0] analogfastrefclkout;
+ wire [1:0] analogrefclkout;
+ wire [0:0] analogrefclkpulse;
+ wire cal_blk_powerdown;
+ wire [599:0] cent_unit_cmudividerdprioout;
+ wire [1799:0] cent_unit_cmuplldprioout;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [3:0] cent_unit_rxadcepowerdn;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1799:0] cent_unit_rxpmadprioin;
+ wire [1799:0] cent_unit_rxpmadprioout;
+ wire [1199:0] cent_unit_tx_dprioin;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [599:0] cent_unit_txdprioout;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [1799:0] cent_unit_txpmadprioin;
+ wire [1799:0] cent_unit_txpmadprioout;
+ wire [599:0] clk_div_cmudividerdprioin;
+ wire fixedclk;
+ wire [5:0] fixedclk_in;
+ wire [0:0] nonusertocmu_out;
+ wire [0:0] pipedatavalid_out;
+ wire [0:0] pipeelecidle_out;
+ wire [9:0] pll0_clkin;
+ wire [299:0] pll0_dprioin;
+ wire [299:0] pll0_dprioout;
+ wire [3:0] pll0_out;
+ wire [1:0] pll_ch_dataout_wire;
+ wire [299:0] pll_ch_dprioout;
+ wire [1799:0] pll_cmuplldprioout;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [1:0] refclkdividerdprioin;
+ wire [3:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [0:0] rx_bitslip;
+ wire [0:0] rx_coreclk_in;
+ wire [8:0] rx_cruclk_in;
+ wire [3:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [2:0] rx_elecidleinfersel;
+ wire [0:0] rx_enapatternalign;
+ wire [0:0] rx_freqlocked_wire;
+ wire [0:0] rx_locktodata;
+ wire [0:0] rx_locktodata_wire;
+ wire [0:0] rx_locktorefclk_wire;
+ wire [15:0] rx_out_wire;
+ wire [1:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [0:0] rx_phfifordenable;
+ wire [0:0] rx_phfiforeset;
+ wire [0:0] rx_phfifowrdisable;
+ wire [0:0] rx_pipestatetransdoneout;
+ wire [0:0] rx_pldcruclk_in;
+ wire [3:0] rx_pll_clkout;
+ wire [0:0] rx_pll_pfdrefclkout_wire;
+ wire [0:0] rx_plllocked_wire;
+ wire [0:0] rx_pma_clockout;
+ wire [0:0] rx_pma_dataout;
+ wire [0:0] rx_pma_locktorefout;
+ wire [19:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [1799:0] rx_pmadprioout;
+ wire [0:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [0:0] rx_prbscidenable;
+ wire [19:0] rx_revparallelfdbkdata;
+ wire [0:0] rx_rmfiforeset;
+ wire [3:0] rx_rxadceresetout;
+ wire [5:0] rx_rxcruresetout;
+ wire [0:0] rx_signaldetect_wire;
+ wire [299:0] rxpll_dprioin;
+ wire [5:0] tx_analogreset_out;
+ wire [0:0] tx_clkout_int_wire;
+ wire [0:0] tx_core_clkout_wire;
+ wire [0:0] tx_coreclk_in;
+ wire [15:0] tx_datain_wire;
+ wire [87:0] tx_datainfull;
+ wire [19:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [1:0] tx_forcedisp_wire;
+ wire [0:0] tx_invpolarity;
+ wire [0:0] tx_localrefclk;
+ wire [0:0] tx_phfiforeset;
+ wire [0:0] tx_pipedeemph;
+ wire [2:0] tx_pipemargin;
+ wire [1:0] tx_pipepowerdownout;
+ wire [3:0] tx_pipepowerstateout;
+ wire [0:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [1799:0] tx_pmadprioout;
+ wire [0:0] tx_revparallellpbken;
+ wire [0:0] tx_rxdetectvalidout;
+ wire [0:0] tx_rxfoundout;
+ wire [599:0] tx_txdprioout;
+ wire [0:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider ch_clk_div0
+ (
+ .analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_ch_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(pll0_out[3:0]),
+ .coreclkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[99:0]),
+ .dprioout(wire_ch_clk_div0_dprioout),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(),
+ .rateswitchout(),
+ .refclkout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .powerdn(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
+ ch_clk_div0.data_rate = 800,
+ ch_clk_div0.divide_by = 5,
+ ch_clk_div0.divider_type = "CHANNEL_REGULAR",
+ ch_clk_div0.dprio_config_mode = 6'h01,
+ ch_clk_div0.enable_dynamic_divider = "false",
+ ch_clk_div0.enable_refclk_out = "false",
+ ch_clk_div0.inclk_select = 0,
+ ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
+ ch_clk_div0.pre_divide_by = 1,
+ ch_clk_div0.refclk_divide_by = 2,
+ ch_clk_div0.refclk_multiply_by = 25,
+ ch_clk_div0.select_local_rate_switch_done = "false",
+ ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_coreclkout_phase_shift = 0,
+ ch_clk_div0.sim_refclkout_phase_shift = 0,
+ ch_clk_div0.use_coreclk_out_post_divider = "true",
+ ch_clk_div0.use_refclk_post_divider = "false",
+ ch_clk_div0.use_vco_bypass = "false",
+ ch_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(),
+ .cmudividerdprioin(clk_div_cmudividerdprioin[599:0]),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk(fixedclk_in[5:0]),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin(refclkdividerdprioin[1:0]),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(wire_cent_unit0_rxadcepowerdown),
+ .rxadceresetout(wire_cent_unit0_rxadceresetout),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxdprioout(),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin(cent_unit_rxpcsdprioin[1599:0]),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpmadprioin(cent_unit_rxpmadprioin[1799:0]),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txdprioout(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin(cent_unit_tx_dprioin[599:0]),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout(),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin(cent_unit_txpmadprioin[1799:0]),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .rateswitch(1'b0),
+ .rateswitchdonein(1'b0),
+ .rxclk(1'b0),
+ .rxcoreclk(1'b0),
+ .rxdprioin({1200{1'b0}}),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({6000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txdprioin({600{1'b0}}),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 250000,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "none",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "local reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "none",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "3.0V",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.charge_pump_current_bits = 0,
+ rx_cdr_pll0.dprio_config_mode = 6'h01,
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.inclk1_input_period = 5000,
+ rx_cdr_pll0.inclk2_input_period = 5000,
+ rx_cdr_pll0.inclk3_input_period = 5000,
+ rx_cdr_pll0.inclk4_input_period = 5000,
+ rx_cdr_pll0.inclk5_input_period = 5000,
+ rx_cdr_pll0.inclk6_input_period = 5000,
+ rx_cdr_pll0.inclk7_input_period = 5000,
+ rx_cdr_pll0.inclk8_input_period = 5000,
+ rx_cdr_pll0.inclk9_input_period = 5000,
+ rx_cdr_pll0.loop_filter_c_bits = 0,
+ rx_cdr_pll0.loop_filter_r_bits = 0,
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 2,
+ rx_cdr_pll0.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll0.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.protocol_hint = "pcie",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_data_rate = 800,
+ rx_cdr_pll0.vco_divide_by = 2,
+ rx_cdr_pll0.vco_multiply_by = 25,
+ rx_cdr_pll0.vco_post_scale = 2,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(pll0_dprioin[299:0]),
+ .dprioout(wire_tx_pll0_dprioout),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .earlyeios(1'b0),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.channel_num = 4,
+ tx_pll0.charge_pump_current_bits = 0,
+ tx_pll0.dprio_config_mode = 6'h01,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.inclk1_input_period = 5000,
+ tx_pll0.inclk2_input_period = 5000,
+ tx_pll0.inclk3_input_period = 5000,
+ tx_pll0.inclk4_input_period = 5000,
+ tx_pll0.inclk5_input_period = 5000,
+ tx_pll0.inclk6_input_period = 5000,
+ tx_pll0.inclk7_input_period = 5000,
+ tx_pll0.inclk8_input_period = 5000,
+ tx_pll0.inclk9_input_period = 5000,
+ tx_pll0.loop_filter_c_bits = 0,
+ tx_pll0.loop_filter_r_bits = 0,
+ tx_pll0.m = 25,
+ tx_pll0.n = 2,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.protocol_hint = "pcie",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_data_rate = 0,
+ tx_pll0.vco_divide_by = 0,
+ tx_pll0.vco_multiply_by = 0,
+ tx_pll0.vco_post_scale = 2,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[0]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(),
+ .phfifooverflow(),
+ .phfifoptrsresetout(),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(),
+ .phfifowrenableout(),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxnwrclk({3{1'b0}}),
+ .phfifoxnwrenable({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "none",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "local reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "none",
+ receive_pcs0.ph_fifo_xn_select = 1,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 250000,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[0]),
+ .adcereset(rx_rxadceresetout[0]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 0,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 4,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
+ .datain({{24{1'b0}}, tx_datain_wire[15:0]}),
+ .datainfull(tx_datainfull[43:0]),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifooverflow(),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifobyteserdisable(1'b0),
+ .phfifoptrsreset(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdclk({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .phfifoxnwrenable({3{1'b0}}),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.channel_bonding = "none",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs0.ph_fifo_xn_select = 1,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "local",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in(analogfastrefclkout[1:0]),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({analogrefclkout[1:0]}),
+ .refclk0inpulse(analogrefclkpulse[0]),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "1.4V",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 0,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 3,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
+ analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
+ analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
+ cal_blk_powerdown = 1'b1,
+ cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxadcepowerdn = {wire_cent_unit0_rxadcepowerdown},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {1200'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, rx_pcsdprioout[399:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout},
+ cent_unit_rxpmadprioin = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, rx_pmadprioout[299:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout},
+ cent_unit_tx_dprioin = {1050'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, tx_txdprioout[149:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, tx_pmadprioout[299:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout},
+ clk_div_cmudividerdprioin = {500'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, wire_ch_clk_div0_dprioout},
+ fixedclk = 1'b0,
+ fixedclk_in = {5'b00000, fixedclk},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[0]},
+ pipedatavalid_out = {wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[0]},
+ pipeelecidle_out = {wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs0_pipestatus},
+ pll0_clkin = {9'b000000000, pll_inclk_wire[0]},
+ pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
+ pll0_dprioout = {wire_tx_pll0_dprioout},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, pll0_dprioout[299:0], 900'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, pll_ch_dprioout[299:0]},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {wire_cent_unit0_dprioout},
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ rx_analogreset_in = {3'b000, rx_analogreset[0]},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_bitslip = 1'b0,
+ rx_coreclk_in = {tx_core_clkout_wire[0]},
+ rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[15:0]},
+ rx_deserclock_in = {rx_pll_clkout[3:0]},
+ rx_digitalreset_in = {3'b000, rx_digitalreset[0]},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
+ rx_elecidleinfersel = {3{1'b0}},
+ rx_enapatternalign = 1'b0,
+ rx_freqlocked = {rx_freqlocked_wire[0]},
+ rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = 1'b0,
+ rx_locktodata_wire = {rx_locktodata[0]},
+ rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {1200'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, cent_unit_rxpcsdprioout[399:0]},
+ rx_pcsdprioout = {1200'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = 1'b1,
+ rx_phfiforeset = 1'b0,
+ rx_phfifowrdisable = 1'b0,
+ rx_pipestatetransdoneout = {wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[0]},
+ rx_pll_clkout = {wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {rx_plllocked_wire[0]},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
+ rx_pma_clockout = {wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, cent_unit_rxpmadprioout[299:0]},
+ rx_pmadprioout = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, wire_receive_pma0_dprioout},
+ rx_powerdown = 1'b0,
+ rx_powerdown_in = {3'b000, rx_powerdown[0]},
+ rx_prbscidenable = 1'b0,
+ rx_revparallelfdbkdata = {wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = 1'b0,
+ rx_rxadceresetout = {wire_cent_unit0_rxadceresetout},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs0_syncstatus[1:0]},
+ rxpll_dprioin = {cent_unit_cmuplldprioout[299:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout = {tx_core_clkout_wire[0]},
+ tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
+ tx_core_clkout_wire = {tx_clkout_int_wire[0]},
+ tx_coreclk_in = {tx_core_clkout_wire[0]},
+ tx_datain_wire = {tx_datain[15:0]},
+ tx_datainfull = {88{1'b0}},
+ tx_dataout = {wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {3'b000, tx_digitalreset[0]},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
+ tx_dprioin_wire = {1050'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, cent_unit_txdprioout[149:0]},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = 1'b0,
+ tx_localrefclk = {wire_transmit_pma0_clockout},
+ tx_phfiforeset = 1'b0,
+ tx_pipedeemph = 1'b0,
+ tx_pipemargin = {3{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = 1'b0,
+ tx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, cent_unit_txpmadprioout[299:0]},
+ tx_pmadprioout = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = 1'b0,
+ tx_rxdetectvalidout = {wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {450'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, wire_transmit_pcs0_dprioout},
+ txdetectrxout = {wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+endmodule //altpcie_serdes_4sgx_x1d_gen1_16p_alt4gxb_hcd9
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_4sgx_x1d_gen1_16p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout)/* synthesis synthesis_clearbox = 1 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [1:0] powerdn;
+ input reconfig_clk;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ output [0:0] pll_locked;
+ output [0:0] reconfig_fromgxb;
+ output [1:0] rx_ctrldetect;
+ output [15:0] rx_dataout;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [1:0] sub_wire0;
+ wire [1:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [0:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [0:0] sub_wire7;
+ wire [2:0] sub_wire8;
+ wire [1:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [0:0] sub_wire12;
+ wire [15:0] sub_wire13;
+ wire [1:0] rx_patterndetect = sub_wire0[1:0];
+ wire [1:0] rx_ctrldetect = sub_wire1[1:0];
+ wire [0:0] pipedatavalid = sub_wire2[0:0];
+ wire [0:0] pipephydonestatus = sub_wire3[0:0];
+ wire [0:0] rx_pll_locked = sub_wire4[0:0];
+ wire [0:0] rx_freqlocked = sub_wire5[0:0];
+ wire [0:0] tx_dataout = sub_wire6[0:0];
+ wire [0:0] pipeelecidle = sub_wire7[0:0];
+ wire [2:0] pipestatus = sub_wire8[2:0];
+ wire [1:0] rx_syncstatus = sub_wire9[1:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [0:0] reconfig_fromgxb = sub_wire11[0:0];
+ wire [0:0] pll_locked = sub_wire12[0:0];
+ wire [15:0] rx_dataout = sub_wire13[15:0];
+
+ altpcie_serdes_4sgx_x1d_gen1_16p_alt4gxb_hcd9 altpcie_serdes_4sgx_x1d_gen1_16p_alt4gxb_hcd9_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .reconfig_clk (reconfig_clk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .rx_ctrldetect (sub_wire1),
+ .pipedatavalid (sub_wire2),
+ .pipephydonestatus (sub_wire3),
+ .rx_pll_locked (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .tx_dataout (sub_wire6),
+ .pipeelecidle (sub_wire7),
+ .pipestatus (sub_wire8),
+ .rx_syncstatus (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .pll_locked (sub_wire12),
+ .rx_dataout (sub_wire13));
+ defparam
+ altpcie_serdes_4sgx_x1d_gen1_16p_alt4gxb_hcd9_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.82"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.65"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.4"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE NUMERIC "2"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "3"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.4v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_analog_power STRING "3.0v"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: rx_cru_divide_by NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_multiply_by NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: tx_pll_divide_by NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_multiply_by NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 2 0 OUTPUT NODEFVAL "rx_ctrldetect[1..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 16 0 OUTPUT NODEFVAL "rx_dataout[15..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 1 0 OUTPUT NODEFVAL "rx_pll_locked[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 2 0 INPUT NODEFVAL "tx_ctrlenable[1..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 16 0 INPUT NODEFVAL "tx_datain[15..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 2 0 @rx_ctrldetect 0 0 2 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 16 0 @rx_dataout 0 0 16 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 1 0 @rx_pll_locked 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 2 0 tx_ctrlenable 0 0 2 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: CONNECT: @tx_datain 0 0 16 0 tx_datain 0 0 16 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_16p.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_16p.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_16p.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_16p.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_16p.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_16p_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen1_16p_bb.v TRUE FALSE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..093e6a304513ce1da195787009cf9cd953fced92
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v
@@ -0,0 +1,1885 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_4sgx_x1d_gen2_08p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.0 Internal Build 118 02/15/2011 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" effective_data_rate="5000 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="3.0v" gxb_powerdown_width=1 input_clock_frequency="100.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="pcie2" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=1 rx_data_rate=5000 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="indv" tx_channel_width=16 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=5000 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=1 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=3 cal_blk_clk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn rateswitch reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
+//VERSION_BEGIN 11.0 cbx_alt4gxb 2011:02:15:21:24:41:SJ cbx_mgl 2011:02:15:21:26:30:SJ cbx_tgx 2011:02:15:21:24:41:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = reg 20 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 2 stratixiv_hssi_rx_pcs 1 stratixiv_hssi_rx_pma 1 stratixiv_hssi_tx_pcs 1 stratixiv_hssi_tx_pma 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
+module altpcie_serdes_4sgx_x1d_gen2_08p_alt4gxb_euba
+ (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ rateswitch,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ tx_pipedeemph,
+ tx_pipemargin) /* synthesis synthesis_clearbox=2 */;
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [1:0] powerdn;
+ input [0:0] rateswitch;
+ input reconfig_clk;
+ output [16:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ output [1:0] rx_ctrldetect;
+ input [0:0] rx_datain;
+ output [15:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ output [0:0] tx_dataout;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+ input [0:0] tx_pipedeemph;
+ input [2:0] tx_pipemargin;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [0:0] pipe8b10binvpolarity;
+ tri0 pll_inclk;
+ tri0 [1:0] powerdn;
+ tri0 [0:0] rateswitch;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [0:0] rx_cruclk;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [1:0] tx_ctrlenable;
+ tri0 [15:0] tx_datain;
+ tri0 [0:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [0:0] tx_forcedispcompliance;
+ tri0 [0:0] tx_forceelecidle;
+ tri0 [0:0] tx_pipedeemph;
+ tri0 [2:0] tx_pipemargin;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire [9:0] wire_pcie_sw_sel_delay_blk0c_d;
+ reg [9:0] pcie_sw_sel_delay_blk0c;
+ wire [9:0] wire_pcie_sw_sel_delay_blk0c_prn;
+ wire [9:0] wire_pllreset_delay_blk0c_d;
+ reg [9:0] pllreset_delay_blk0c;
+ wire [9:0] wire_pllreset_delay_blk0c_prn;
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_ch_clk_div0_analogrefclkout;
+ wire wire_ch_clk_div0_analogrefclkpulse;
+ wire [99:0] wire_ch_clk_div0_dprioout;
+ wire wire_ch_clk_div0_rateswitchdone;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire [9:0] wire_cent_unit0_digitaltestout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire [299:0] wire_tx_pll0_dprioout;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_autospdrateswitchout;
+ wire wire_receive_pcs0_cdrctrlearlyeios;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire wire_receive_pcs0_signaldetect;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire wire_transmit_pcs0_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire [1:0] analogfastrefclkout;
+ wire [1:0] analogrefclkout;
+ wire [0:0] analogrefclkpulse;
+ wire cal_blk_powerdown;
+ wire [599:0] cent_unit_cmudividerdprioout;
+ wire [1799:0] cent_unit_cmuplldprioout;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1799:0] cent_unit_rxpmadprioin;
+ wire [1799:0] cent_unit_rxpmadprioout;
+ wire [1199:0] cent_unit_tx_dprioin;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [5:0] cent_unit_txdetectrxpowerdn;
+ wire [599:0] cent_unit_txdprioout;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [1799:0] cent_unit_txpmadprioin;
+ wire [1799:0] cent_unit_txpmadprioout;
+ wire [599:0] clk_div_cmudividerdprioin;
+ wire fixedclk;
+ wire [5:0] fixedclk_to_cmu;
+ wire [2:0] grayelecidleinfersel_from_tx;
+ wire [0:0] int_clk_div_ch_rateswitchdone;
+ wire [0:0] int_pcie_sw;
+ wire [0:0] int_pcie_sw_select;
+ wire [0:0] int_pipeenrevparallellpbkfromtx;
+ wire [0:0] int_pll_reset_delayed;
+ wire [0:0] int_rx_phfifobyteserdisable;
+ wire [0:0] int_rx_phfifoptrsresetout;
+ wire [0:0] int_rxpcs_cdrctrlearlyeios;
+ wire [0:0] nonusertocmu_out;
+ wire [0:0] pcie_sw_wire;
+ wire [0:0] pipedatavalid_out;
+ wire [0:0] pipeelecidle_out;
+ wire [9:0] pll0_clkin;
+ wire [299:0] pll0_dprioin;
+ wire [299:0] pll0_dprioout;
+ wire [3:0] pll0_out;
+ wire [1:0] pll_ch_dataout_wire;
+ wire [299:0] pll_ch_dprioout;
+ wire [1799:0] pll_cmuplldprioout;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [5:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [0:0] rx_coreclk_in;
+ wire [9:0] rx_cruclk_in;
+ wire [3:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [2:0] rx_elecidleinfersel;
+ wire [0:0] rx_enapatternalign;
+ wire [0:0] rx_freqlocked_wire;
+ wire [0:0] rx_locktodata;
+ wire [0:0] rx_locktodata_wire;
+ wire [0:0] rx_locktorefclk_wire;
+ wire [15:0] rx_out_wire;
+ wire [1:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [0:0] rx_phfifordenable;
+ wire [0:0] rx_phfiforeset;
+ wire [0:0] rx_phfifowrdisable;
+ wire [0:0] rx_pipestatetransdoneout;
+ wire [0:0] rx_pldcruclk_in;
+ wire [3:0] rx_pll_clkout;
+ wire [0:0] rx_pll_pfdrefclkout_wire;
+ wire [0:0] rx_plllocked_wire;
+ wire [16:0] rx_pma_analogtestbus;
+ wire [0:0] rx_pma_clockout;
+ wire [0:0] rx_pma_dataout;
+ wire [0:0] rx_pma_locktorefout;
+ wire [19:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [1799:0] rx_pmadprioout;
+ wire [0:0] rx_powerdown;
+ wire [5:0] rx_powerdown_in;
+ wire [0:0] rx_prbscidenable;
+ wire [19:0] rx_revparallelfdbkdata;
+ wire [0:0] rx_rmfiforeset;
+ wire [5:0] rx_rxcruresetout;
+ wire [0:0] rx_signaldetect_wire;
+ wire [1799:0] rxpll_dprioin;
+ wire [5:0] tx_analogreset_out;
+ wire [0:0] tx_clkout_int_wire;
+ wire [0:0] tx_core_clkout_wire;
+ wire [0:0] tx_coreclk_in;
+ wire [15:0] tx_datain_wire;
+ wire [19:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [1:0] tx_forcedisp_wire;
+ wire [0:0] tx_invpolarity;
+ wire [0:0] tx_localrefclk;
+ wire [0:0] tx_pcs_forceelecidleout;
+ wire [0:0] tx_phfiforeset;
+ wire [1:0] tx_pipepowerdownout;
+ wire [3:0] tx_pipepowerstateout;
+ wire [0:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [1799:0] tx_pmadprioout;
+ wire [0:0] tx_revparallellpbken;
+ wire [0:0] tx_rxdetectvalidout;
+ wire [0:0] tx_rxfoundout;
+ wire [599:0] tx_txdprioout;
+ wire [0:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+ wire [0:0] wire_cent_unit_testin0;
+
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[0:0])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[0:0] == 1'b0) pcie_sw_sel_delay_blk0c[0:0] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[0:0] <= wire_pcie_sw_sel_delay_blk0c_d[0:0];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[1:1])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[1:1] == 1'b0) pcie_sw_sel_delay_blk0c[1:1] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[1:1] <= wire_pcie_sw_sel_delay_blk0c_d[1:1];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[2:2])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[2:2] == 1'b0) pcie_sw_sel_delay_blk0c[2:2] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[2:2] <= wire_pcie_sw_sel_delay_blk0c_d[2:2];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[3:3])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[3:3] == 1'b0) pcie_sw_sel_delay_blk0c[3:3] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[3:3] <= wire_pcie_sw_sel_delay_blk0c_d[3:3];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[4:4])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[4:4] == 1'b0) pcie_sw_sel_delay_blk0c[4:4] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[4:4] <= wire_pcie_sw_sel_delay_blk0c_d[4:4];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[5:5])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[5:5] == 1'b0) pcie_sw_sel_delay_blk0c[5:5] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[5:5] <= wire_pcie_sw_sel_delay_blk0c_d[5:5];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[6:6])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[6:6] == 1'b0) pcie_sw_sel_delay_blk0c[6:6] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[6:6] <= wire_pcie_sw_sel_delay_blk0c_d[6:6];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[7:7])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[7:7] == 1'b0) pcie_sw_sel_delay_blk0c[7:7] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[7:7] <= wire_pcie_sw_sel_delay_blk0c_d[7:7];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[8:8])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[8:8] == 1'b0) pcie_sw_sel_delay_blk0c[8:8] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[8:8] <= wire_pcie_sw_sel_delay_blk0c_d[8:8];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[9:9])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[9:9] == 1'b0) pcie_sw_sel_delay_blk0c[9:9] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[9:9] <= wire_pcie_sw_sel_delay_blk0c_d[9:9];
+ assign
+ wire_pcie_sw_sel_delay_blk0c_d = {pcie_sw_sel_delay_blk0c[8:0], pllreset_delay_blk0c[9]};
+ assign
+ wire_pcie_sw_sel_delay_blk0c_prn = {10{(~ pll_powerdown[0])}};
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[0:0])
+ if (wire_pllreset_delay_blk0c_prn[0:0] == 1'b0) pllreset_delay_blk0c[0:0] <= 1'b1;
+ else pllreset_delay_blk0c[0:0] <= wire_pllreset_delay_blk0c_d[0:0];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[1:1])
+ if (wire_pllreset_delay_blk0c_prn[1:1] == 1'b0) pllreset_delay_blk0c[1:1] <= 1'b1;
+ else pllreset_delay_blk0c[1:1] <= wire_pllreset_delay_blk0c_d[1:1];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[2:2])
+ if (wire_pllreset_delay_blk0c_prn[2:2] == 1'b0) pllreset_delay_blk0c[2:2] <= 1'b1;
+ else pllreset_delay_blk0c[2:2] <= wire_pllreset_delay_blk0c_d[2:2];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[3:3])
+ if (wire_pllreset_delay_blk0c_prn[3:3] == 1'b0) pllreset_delay_blk0c[3:3] <= 1'b1;
+ else pllreset_delay_blk0c[3:3] <= wire_pllreset_delay_blk0c_d[3:3];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[4:4])
+ if (wire_pllreset_delay_blk0c_prn[4:4] == 1'b0) pllreset_delay_blk0c[4:4] <= 1'b1;
+ else pllreset_delay_blk0c[4:4] <= wire_pllreset_delay_blk0c_d[4:4];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[5:5])
+ if (wire_pllreset_delay_blk0c_prn[5:5] == 1'b0) pllreset_delay_blk0c[5:5] <= 1'b1;
+ else pllreset_delay_blk0c[5:5] <= wire_pllreset_delay_blk0c_d[5:5];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[6:6])
+ if (wire_pllreset_delay_blk0c_prn[6:6] == 1'b0) pllreset_delay_blk0c[6:6] <= 1'b1;
+ else pllreset_delay_blk0c[6:6] <= wire_pllreset_delay_blk0c_d[6:6];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[7:7])
+ if (wire_pllreset_delay_blk0c_prn[7:7] == 1'b0) pllreset_delay_blk0c[7:7] <= 1'b1;
+ else pllreset_delay_blk0c[7:7] <= wire_pllreset_delay_blk0c_d[7:7];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[8:8])
+ if (wire_pllreset_delay_blk0c_prn[8:8] == 1'b0) pllreset_delay_blk0c[8:8] <= 1'b1;
+ else pllreset_delay_blk0c[8:8] <= wire_pllreset_delay_blk0c_d[8:8];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[9:9])
+ if (wire_pllreset_delay_blk0c_prn[9:9] == 1'b0) pllreset_delay_blk0c[9:9] <= 1'b1;
+ else pllreset_delay_blk0c[9:9] <= wire_pllreset_delay_blk0c_d[9:9];
+ assign
+ wire_pllreset_delay_blk0c_d = {pllreset_delay_blk0c[8:0], (pll_powerdown[0] | (~ pll_locked_out[0]))};
+ assign
+ wire_pllreset_delay_blk0c_prn = {10{(~ pll_powerdown[0])}};
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider ch_clk_div0
+ (
+ .analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_ch_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(pll0_out[3:0]),
+ .coreclkout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[99:0]),
+ .dprioout(wire_ch_clk_div0_dprioout),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(int_pcie_sw[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_ch_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .powerdn(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
+ ch_clk_div0.divide_by = 5,
+ ch_clk_div0.divider_type = "CHANNEL_REGULAR",
+ ch_clk_div0.effective_data_rate = "5000 Mbps",
+ ch_clk_div0.enable_dynamic_divider = "true",
+ ch_clk_div0.enable_refclk_out = "false",
+ ch_clk_div0.inclk_select = 0,
+ ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
+ ch_clk_div0.pre_divide_by = 1,
+ ch_clk_div0.select_local_rate_switch_done = "true",
+ ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ ch_clk_div0.sim_coreclkout_phase_shift = 0,
+ ch_clk_div0.sim_refclkout_phase_shift = 0,
+ ch_clk_div0.use_coreclk_out_post_divider = "true",
+ ch_clk_div0.use_refclk_post_divider = "false",
+ ch_clk_div0.use_vco_bypass = "false",
+ ch_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet({{3{1'b0}}, wire_cent_unit_testin0[0]}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(),
+ .cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(wire_cent_unit0_digitaltestout),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .fixedclk({{5{1'b0}}, fixedclk_to_cmu[0]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout(),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchdonein(1'b0),
+ .rxclk(1'b0),
+ .rxcoreclk(1'b0),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.central_test_bus_select = 0,
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 249950,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "none",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "local reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "none",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "3.0V",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[0]),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({rx_cruclk_in[9:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .rateswitch(int_pcie_sw[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.bandwidth_type = "Medium",
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll0.enable_dynamic_divider = "true",
+ rx_cdr_pll0.fast_lock_control = "false",
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 1,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_post_scale = 1,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(pll0_dprioin[299:0]),
+ .dprioout(wire_tx_pll0_dprioout),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.bandwidth_type = "High",
+ tx_pll0.channel_num = 4,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.input_clock_frequency = "100.0 MHz",
+ tx_pll0.logical_tx_pll_number = 0,
+ tx_pll0.m = 25,
+ tx_pll0.n = 1,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pfd_fb_select = "internal",
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_post_scale = 1,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs0_autospdrateswitchout),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(tx_localrefclk[0]),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(),
+ .phfifowrenableout(),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchisdone(int_clk_div_ch_rateswitchdone[0]),
+ .rateswitchout(),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(wire_receive_pcs0_signaldetect),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxnwrclk({3{1'b0}}),
+ .phfifoxnwrenable({3{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_cid_mode_enable = "true",
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "none",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "local reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "none",
+ receive_pcs0.ph_fifo_xn_select = 1,
+ receive_pcs0.pipe_auto_speed_nego_enable = "true",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 249950,
+ receive_pcs0.protocol_hint = "pcie2",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_pipe_enable = "true",
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 32,
+ receive_pcs0.rxstatus_error_report_mode = 1,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.test_bus_sel = 10,
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.adaptive_equalization_mode = "none",
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "true",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.eyemon_bandwidth = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "pcie2",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis = 4,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma0.signal_detect_loss_threshold = 3,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
+ .datain({{24{1'b0}}, tx_datain_wire[15:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[0]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(),
+ .pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnbytesel({3{1'b0}}),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxnrdclk({3{1'b0}}),
+ .phfifoxnrdenable({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .phfifoxnwrenable({3{1'b0}}),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0),
+ .refclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "none",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs0.ph_fifo_xn_select = 1,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.pipe_voltage_swing_control = "false",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie2",
+ transmit_pcs0.refclk_select = "local",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in(analogfastrefclkout[1:0]),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({analogrefclkout[1:0]}),
+ .refclk0inpulse(analogrefclkpulse[0]),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "auto",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 0,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.logical_protocol_hint_0 = "pcie2",
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.physical_clkin0_mapping = "x1",
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_1_a = 28,
+ transmit_pma0.preemp_tap_1_b = 22,
+ transmit_pma0.preemp_tap_1_c = 7,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie2",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 3,
+ transmit_pma0.vod_selection_a = 6,
+ transmit_pma0.vod_selection_c = 1,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
+ analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
+ analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
+ cal_blk_powerdown = 1'b0,
+ cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
+ cent_unit_rxpmadprioin = {{1500{1'b0}}, rx_pmadprioout[299:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]},
+ cent_unit_tx_dprioin = {{1050{1'b0}}, tx_txdprioout[149:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {{1500{1'b0}}, tx_pmadprioout[299:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]},
+ clk_div_cmudividerdprioin = {{500{1'b0}}, wire_ch_clk_div0_dprioout},
+ fixedclk = 1'b0,
+ fixedclk_to_cmu = {6{reconfig_clk}},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs0_grayelecidleinferselout},
+ int_clk_div_ch_rateswitchdone = {wire_ch_clk_div0_rateswitchdone},
+ int_pcie_sw = {((int_pcie_sw_select[0] & int_pll_reset_delayed[0]) | ((~ int_pcie_sw_select[0]) & pcie_sw_wire[0]))},
+ int_pcie_sw_select = {pcie_sw_sel_delay_blk0c[9]},
+ int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs0_pipeenrevparallellpbkout},
+ int_pll_reset_delayed = {pllreset_delay_blk0c[9]},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs0_phfifoptrsresetout},
+ int_rxpcs_cdrctrlearlyeios = {wire_receive_pcs0_cdrctrlearlyeios},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pcie_sw_wire = {wire_cent_unit0_digitaltestout[2]},
+ pipedatavalid = {pipedatavalid_out[0]},
+ pipedatavalid_out = {wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[0]},
+ pipeelecidle_out = {wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs0_pipestatus},
+ pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
+ pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
+ pll0_dprioout = {wire_tx_pll0_dprioout},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], {900{1'b0}}, pll_ch_dprioout[299:0]},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ rx_analogreset_in = {{5{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_coreclk_in = {tx_core_clkout_wire[0]},
+ rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[15:0]},
+ rx_deserclock_in = {rx_pll_clkout[3:0]},
+ rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_elecidleinfersel = {3{1'b0}},
+ rx_enapatternalign = 1'b0,
+ rx_freqlocked = {(rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = 1'b0,
+ rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[0])},
+ rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
+ rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = 1'b1,
+ rx_phfiforeset = 1'b0,
+ rx_phfifowrdisable = 1'b0,
+ rx_pipestatetransdoneout = {wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[0]},
+ rx_pll_clkout = {wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {(rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
+ rx_pma_analogtestbus = {{12{1'b0}}, wire_receive_pma0_analogtestbus[5:2], 1'b0},
+ rx_pma_clockout = {wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_rxpmadprioout[299:0]},
+ rx_pmadprioout = {{1500{1'b0}}, wire_receive_pma0_dprioout},
+ rx_powerdown = 1'b0,
+ rx_powerdown_in = {{5{1'b0}}, rx_powerdown[0]},
+ rx_prbscidenable = 1'b0,
+ rx_revparallelfdbkdata = {wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = 1'b0,
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs0_syncstatus[1:0]},
+ rxpll_dprioin = {{1500{1'b0}}, cent_unit_cmuplldprioout[299:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout = {tx_core_clkout_wire[0]},
+ tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
+ tx_core_clkout_wire = {tx_clkout_int_wire[0]},
+ tx_coreclk_in = {tx_core_clkout_wire[0]},
+ tx_datain_wire = {tx_datain[15:0]},
+ tx_dataout = {wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_dprioin_wire = {{1050{1'b0}}, cent_unit_txdprioout[149:0]},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = 1'b0,
+ tx_localrefclk = {wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = 1'b0,
+ tx_pipepowerdownout = {wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = 1'b0,
+ tx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_txpmadprioout[299:0]},
+ tx_pmadprioout = {{1500{1'b0}}, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = 1'b0,
+ tx_rxdetectvalidout = {wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
+ txdetectrxout = {wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout},
+ wire_cent_unit_testin0 = {wire_receive_pcs0_autospdrateswitchout};
+endmodule //altpcie_serdes_4sgx_x1d_gen2_08p_alt4gxb_euba
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_4sgx_x1d_gen2_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ rateswitch,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ tx_pipedeemph,
+ tx_pipemargin,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_clkout,
+ tx_dataout)/* synthesis synthesis_clearbox = 2 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [0:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [1:0] powerdn;
+ input [0:0] rateswitch;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [0:0] rx_cruclk;
+ input [0:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [1:0] tx_ctrlenable;
+ input [15:0] tx_datain;
+ input [0:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [0:0] tx_forcedispcompliance;
+ input [0:0] tx_forceelecidle;
+ input [0:0] tx_pipedeemph;
+ input [2:0] tx_pipemargin;
+ output [0:0] pipedatavalid;
+ output [0:0] pipeelecidle;
+ output [0:0] pipephydonestatus;
+ output [2:0] pipestatus;
+ output [0:0] pll_locked;
+ output [16:0] reconfig_fromgxb;
+ output [1:0] rx_ctrldetect;
+ output [15:0] rx_dataout;
+ output [0:0] rx_freqlocked;
+ output [1:0] rx_patterndetect;
+ output [0:0] rx_pll_locked;
+ output [1:0] rx_syncstatus;
+ output [0:0] tx_clkout;
+ output [0:0] tx_dataout;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [0:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+
+
+ wire [1:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [16:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [2:0] sub_wire5;
+ wire [0:0] sub_wire6;
+ wire [1:0] sub_wire7;
+ wire [15:0] sub_wire8;
+ wire [0:0] sub_wire9;
+ wire [0:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [1:0] sub_wire12;
+ wire [0:0] sub_wire13;
+ wire [1:0] rx_patterndetect = sub_wire0[1:0];
+ wire [0:0] pipephydonestatus = sub_wire1[0:0];
+ wire [0:0] pll_locked = sub_wire2[0:0];
+ wire [16:0] reconfig_fromgxb = sub_wire3[16:0];
+ wire [0:0] rx_freqlocked = sub_wire4[0:0];
+ wire [2:0] pipestatus = sub_wire5[2:0];
+ wire [0:0] rx_pll_locked = sub_wire6[0:0];
+ wire [1:0] rx_syncstatus = sub_wire7[1:0];
+ wire [15:0] rx_dataout = sub_wire8[15:0];
+ wire [0:0] pipeelecidle = sub_wire9[0:0];
+ wire [0:0] tx_clkout = sub_wire10[0:0];
+ wire [0:0] tx_dataout = sub_wire11[0:0];
+ wire [1:0] rx_ctrldetect = sub_wire12[1:0];
+ wire [0:0] pipedatavalid = sub_wire13[0:0];
+
+ altpcie_serdes_4sgx_x1d_gen2_08p_alt4gxb_euba altpcie_serdes_4sgx_x1d_gen2_08p_alt4gxb_euba_component (
+ .reconfig_togxb (reconfig_togxb),
+ .cal_blk_clk (cal_blk_clk),
+ .tx_forceelecidle (tx_forceelecidle),
+ .rx_datain (rx_datain),
+ .rx_digitalreset (rx_digitalreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .tx_datain (tx_datain),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_pipedeemph (tx_pipedeemph),
+ .gxb_powerdown (gxb_powerdown),
+ .rx_cruclk (rx_cruclk),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .rateswitch (rateswitch),
+ .reconfig_clk (reconfig_clk),
+ .rx_analogreset (rx_analogreset),
+ .powerdn (powerdn),
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_pipemargin (tx_pipemargin),
+ .pll_inclk (pll_inclk),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .pipephydonestatus (sub_wire1),
+ .pll_locked (sub_wire2),
+ .reconfig_fromgxb (sub_wire3),
+ .rx_freqlocked (sub_wire4),
+ .pipestatus (sub_wire5),
+ .rx_pll_locked (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .rx_dataout (sub_wire8),
+ .pipeelecidle (sub_wire9),
+ .tx_clkout (sub_wire10),
+ .tx_dataout (sub_wire11),
+ .rx_ctrldetect (sub_wire12),
+ .pipedatavalid (sub_wire13))/* synthesis synthesis_clearbox=2
+ clearbox_macroname = alt4gxb
+ clearbox_defparam = "effective_data_rate=5000 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gxb_analog_power=3.0v;gx_channel_type=AUTO;input_clock_frequency=100.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=none;lpm_type=alt4gxb;number_of_channels=1;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;protocol=pcie2;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=indv;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_bandwidth_type=Medium;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=5000;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=2;rx_use_align_state_machine=true;
+ rx_use_clkout=false;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=true;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=auto;tx_channel_bonding=indv;tx_channel_width=16;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=5000;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=off;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=true;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=3;elec_idle_infer_enable=false;enable_0ppm=false;gxb_powerdown_width=1;number_of_quads=1;rateswitch_control_width=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_cru_m_divider=25;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=1;rx_dwidth_factor=2;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=2;tx_pll_clock_post_divider=1;tx_pll_m_divider=25;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=1;tx_use_external_termination=false;" */;
+ defparam
+ altpcie_serdes_4sgx_x1d_gen2_08p_alt4gxb_euba_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "5000.0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "5000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "5000"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 2-x1"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "5000 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "3.0v"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie2"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "5000"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "auto"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "5000"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: rateswitch_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
+// Retrieval info: USED_PORT: rateswitch 0 0 1 0 INPUT NODEFVAL "rateswitch[0..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 2 0 OUTPUT NODEFVAL "rx_ctrldetect[1..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 16 0 OUTPUT NODEFVAL "rx_dataout[15..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 1 0 OUTPUT NODEFVAL "rx_pll_locked[0..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
+// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 2 0 INPUT NODEFVAL "tx_ctrlenable[1..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 16 0 INPUT NODEFVAL "tx_datain[15..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
+// Retrieval info: USED_PORT: tx_pipedeemph 0 0 1 0 INPUT NODEFVAL "tx_pipedeemph[0..0]"
+// Retrieval info: USED_PORT: tx_pipemargin 0 0 3 0 INPUT NODEFVAL "tx_pipemargin[2..0]"
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
+// Retrieval info: CONNECT: @rateswitch 0 0 1 0 rateswitch 0 0 1 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
+// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 2 0 tx_ctrlenable 0 0 2 0
+// Retrieval info: CONNECT: @tx_datain 0 0 16 0 tx_datain 0 0 16 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
+// Retrieval info: CONNECT: @tx_pipedeemph 0 0 1 0 tx_pipedeemph 0 0 1 0
+// Retrieval info: CONNECT: @tx_pipemargin 0 0 3 0 tx_pipemargin 0 0 3 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
+// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 2 0 @rx_ctrldetect 0 0 2 0
+// Retrieval info: CONNECT: rx_dataout 0 0 16 0 @rx_dataout 0 0 16 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 1 0 @rx_pll_locked 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
+// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
+// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen2_08p.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen2_08p.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen2_08p.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen2_08p.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen2_08p.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen2_08p_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x1d_gen2_08p_bb.v TRUE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..405964627d6a5814f46c7aa5cb41c9b8c2a85998
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v
@@ -0,0 +1,3694 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_4sgx_x4d_gen1_08p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Internal Build 106 07/20/2008 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" elec_idle_infer_enable="false" enable_0ppm="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gxb_analog_power="2.5v" gxb_powerdown_width=1 intended_device_speed_grade=2 loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_dprio_mode=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=800 rx_cru_divide_by=2 rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_multiply_by=25 rx_cru_n_divider=2 rx_cru_pfd_clk_select=0 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x4" tx_channel_width=8 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=800 tx_pll_divide_by=2 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_multiply_by=25 tx_pll_n_divider=2 tx_pll_pfd_clk_select=0 tx_pll_vco_post_scale_divider=2 tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 8.1 cbx_alt4gxb 2008:07:18:07:31:37:SJ cbx_mgl 2008:07:11:15:23:48:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 5 stratixiv_hssi_rx_pcs 4 stratixiv_hssi_rx_pma 4 stratixiv_hssi_tx_pcs 4 stratixiv_hssi_tx_pma 4
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_4sgx_x4d_gen1_08p_alt4gxb_01d9
+ (
+ cal_blk_clk,
+ coreclkout,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) /* synthesis synthesis_clearbox=1 */;
+ input cal_blk_clk;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [7:0] powerdn;
+ input reconfig_clk;
+ output [0:0] reconfig_fromgxb;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ output [3:0] rx_ctrldetect;
+ input [3:0] rx_datain;
+ output [31:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [3:0] rx_freqlocked;
+ output [3:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [3:0] rx_syncstatus;
+ input [3:0] tx_ctrlenable;
+ input [31:0] tx_datain;
+ output [3:0] tx_dataout;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_central_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div0_analogrefclkout;
+ wire wire_central_clk_div0_analogrefclkpulse;
+ wire wire_central_clk_div0_coreclkout;
+ wire [99:0] wire_central_clk_div0_dprioout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_refclkout;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxadcepowerdown;
+ wire [3:0] wire_cent_unit0_rxadceresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire [299:0] wire_rx_cdr_pll1_dprioout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire [299:0] wire_rx_cdr_pll2_dprioout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire [299:0] wire_rx_cdr_pll3_dprioout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire [299:0] wire_tx_pll0_dprioout;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire wire_receive_pcs0_rateswitchout;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire [399:0] wire_receive_pcs1_dprioout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire wire_receive_pcs1_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire wire_receive_pcs1_rateswitchout;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire [399:0] wire_receive_pcs2_dprioout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_pipedatavalid;
+ wire wire_receive_pcs2_pipeelecidle;
+ wire wire_receive_pcs2_pipephydonestatus;
+ wire wire_receive_pcs2_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs2_pipestatus;
+ wire wire_receive_pcs2_rateswitchout;
+ wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire [399:0] wire_receive_pcs3_dprioout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_pipedatavalid;
+ wire wire_receive_pcs3_pipeelecidle;
+ wire wire_receive_pcs3_pipephydonestatus;
+ wire wire_receive_pcs3_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs3_pipestatus;
+ wire wire_receive_pcs3_rateswitchout;
+ wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire [299:0] wire_receive_pma1_dprioout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire [299:0] wire_receive_pma2_dprioout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire [299:0] wire_receive_pma3_dprioout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_clkout;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire [149:0] wire_transmit_pcs1_dprioout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs2_clkout;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire [149:0] wire_transmit_pcs2_dprioout;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs2_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs2_pipepowerstateout;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs3_clkout;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire [149:0] wire_transmit_pcs3_dprioout;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs3_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs3_pipepowerstateout;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire [299:0] wire_transmit_pma1_dprioout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire [299:0] wire_transmit_pma2_dprioout;
+ wire wire_transmit_pma2_rxdetectvalidout;
+ wire wire_transmit_pma2_rxfoundout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire [299:0] wire_transmit_pma3_dprioout;
+ wire wire_transmit_pma3_rxdetectvalidout;
+ wire wire_transmit_pma3_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [0:0] cent_unit_clkdivpowerdn;
+ wire [599:0] cent_unit_cmudividerdprioout;
+ wire [1799:0] cent_unit_cmuplldprioout;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [3:0] cent_unit_rxadcepowerdn;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1799:0] cent_unit_rxpmadprioin;
+ wire [1799:0] cent_unit_rxpmadprioout;
+ wire [1199:0] cent_unit_tx_dprioin;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [599:0] cent_unit_txdprioout;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [1799:0] cent_unit_txpmadprioin;
+ wire [1799:0] cent_unit_txpmadprioout;
+ wire [3:0] clk_div_clk0in;
+ wire [599:0] clk_div_cmudividerdprioin;
+ wire [0:0] clk_div_pclkin;
+ wire [1:0] cmu_analogfastrefclkout;
+ wire [1:0] cmu_analogrefclkout;
+ wire [0:0] cmu_analogrefclkpulse;
+ wire [0:0] coreclkout_wire;
+ wire fixedclk;
+ wire [5:0] fixedclk_in;
+ wire [0:0] int_hiprateswtichdone;
+ wire [3:0] int_rx_coreclkout;
+ wire [3:0] int_rx_phfifobyteserdisable;
+ wire [3:0] int_rx_phfifoptrsresetout;
+ wire [3:0] int_rx_phfifordenableout;
+ wire [3:0] int_rx_phfiforesetout;
+ wire [3:0] int_rx_phfifowrdisableout;
+ wire [11:0] int_rx_phfifoxnbytesel;
+ wire [11:0] int_rx_phfifoxnrdenable;
+ wire [11:0] int_rx_phfifoxnwrclk;
+ wire [11:0] int_rx_phfifoxnwrenable;
+ wire [0:0] int_rxcoreclk;
+ wire [0:0] int_rxphfifordenable;
+ wire [0:0] int_rxphfiforeset;
+ wire [0:0] int_rxphfifox4byteselout;
+ wire [0:0] int_rxphfifox4rdenableout;
+ wire [0:0] int_rxphfifox4wrclkout;
+ wire [0:0] int_rxphfifox4wrenableout;
+ wire [3:0] int_tx_coreclkout;
+ wire [3:0] int_tx_phfiforddisableout;
+ wire [3:0] int_tx_phfiforesetout;
+ wire [3:0] int_tx_phfifowrenableout;
+ wire [11:0] int_tx_phfifoxnbytesel;
+ wire [11:0] int_tx_phfifoxnrdclk;
+ wire [11:0] int_tx_phfifoxnrdenable;
+ wire [11:0] int_tx_phfifoxnwrenable;
+ wire [0:0] int_txcoreclk;
+ wire [0:0] int_txphfiforddisable;
+ wire [0:0] int_txphfiforeset;
+ wire [0:0] int_txphfifowrenable;
+ wire [0:0] int_txphfifox4byteselout;
+ wire [0:0] int_txphfifox4rdclkout;
+ wire [0:0] int_txphfifox4rdenableout;
+ wire [0:0] int_txphfifox4wrenableout;
+ wire [0:0] nonusertocmu_out;
+ wire [3:0] pipedatavalid_out;
+ wire [3:0] pipeelecidle_out;
+ wire [9:0] pll0_clkin;
+ wire [299:0] pll0_dprioin;
+ wire [299:0] pll0_dprioout;
+ wire [3:0] pll0_out;
+ wire [3:0] pll1_out;
+ wire [7:0] pll_ch_dataout_wire;
+ wire [1199:0] pll_ch_dprioout;
+ wire [1799:0] pll_cmuplldprioout;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [0:0] refclk_pma;
+ wire [1:0] refclkdividerdprioin;
+ wire [3:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [3:0] rx_bitslip;
+ wire [3:0] rx_coreclk_in;
+ wire [35:0] rx_cruclk_in;
+ wire [15:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [11:0] rx_elecidleinfersel;
+ wire [3:0] rx_enapatternalign;
+ wire [3:0] rx_freqlocked_wire;
+ wire [3:0] rx_locktodata;
+ wire [3:0] rx_locktodata_wire;
+ wire [3:0] rx_locktorefclk_wire;
+ wire [31:0] rx_out_wire;
+ wire [7:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [3:0] rx_phfifordenable;
+ wire [3:0] rx_phfiforeset;
+ wire [3:0] rx_phfifowrdisable;
+ wire [3:0] rx_pipestatetransdoneout;
+ wire [3:0] rx_pldcruclk_in;
+ wire [15:0] rx_pll_clkout;
+ wire [3:0] rx_pll_pfdrefclkout_wire;
+ wire [3:0] rx_plllocked_wire;
+ wire [3:0] rx_pma_clockout;
+ wire [3:0] rx_pma_dataout;
+ wire [3:0] rx_pma_locktorefout;
+ wire [79:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [1799:0] rx_pmadprioout;
+ wire [3:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [3:0] rx_prbscidenable;
+ wire [79:0] rx_revparallelfdbkdata;
+ wire [3:0] rx_rmfiforeset;
+ wire [3:0] rx_rxadceresetout;
+ wire [5:0] rx_rxcruresetout;
+ wire [3:0] rx_signaldetect_wire;
+ wire [0:0] rxphfifowrdisable;
+ wire [299:0] rxpll_dprioin;
+ wire [5:0] tx_analogreset_out;
+ wire [3:0] tx_clkout_int_wire;
+ wire [3:0] tx_coreclk_in;
+ wire [31:0] tx_datain_wire;
+ wire [175:0] tx_datainfull;
+ wire [79:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [3:0] tx_forcedisp_wire;
+ wire [3:0] tx_invpolarity;
+ wire [3:0] tx_localrefclk;
+ wire [3:0] tx_phfiforeset;
+ wire [3:0] tx_pipedeemph;
+ wire [11:0] tx_pipemargin;
+ wire [7:0] tx_pipepowerdownout;
+ wire [15:0] tx_pipepowerstateout;
+ wire [3:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [1799:0] tx_pmadprioout;
+ wire [3:0] tx_revparallellpbken;
+ wire [3:0] tx_rxdetectvalidout;
+ wire [3:0] tx_rxfoundout;
+ wire [599:0] tx_txdprioout;
+ wire [3:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[3:0]),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[99:0]),
+ .dprioout(wire_central_clk_div0_dprioout),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkin({2{clk_div_pclkin[0]}}),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .vcobypassin(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.data_rate = 800,
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.enable_dynamic_divider = "false",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclk_divide_by = 2,
+ central_clk_div0.refclk_multiply_by = 25,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_rate_switch_base_clock = "true",
+ central_clk_div0.select_local_refclk = "true",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "false",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin(clk_div_cmudividerdprioin[599:0]),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk(fixedclk_in[5:0]),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin(refclkdividerdprioin[1:0]),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(wire_cent_unit0_rxadcepowerdown),
+ .rxadceresetout(wire_cent_unit0_rxadceresetout),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxdprioout(),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin(cent_unit_rxpcsdprioin[1599:0]),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin(cent_unit_rxpmadprioin[1799:0]),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txdprioout(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin(cent_unit_tx_dprioin[599:0]),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin(cent_unit_txpmadprioin[1799:0]),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .rateswitch(1'b0),
+ .rxdprioin({1200{1'b0}}),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({6000{1'b0}}),
+ .txdprioin({600{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.dprio_config_mode = 6'h01,
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 250000,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "x4",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "false",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "x4",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "false",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "2.5V",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.charge_pump_current_bits = 0,
+ rx_cdr_pll0.dprio_config_mode = 6'h01,
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.inclk1_input_period = 5000,
+ rx_cdr_pll0.inclk2_input_period = 5000,
+ rx_cdr_pll0.inclk3_input_period = 5000,
+ rx_cdr_pll0.inclk4_input_period = 5000,
+ rx_cdr_pll0.inclk5_input_period = 5000,
+ rx_cdr_pll0.inclk6_input_period = 5000,
+ rx_cdr_pll0.inclk7_input_period = 5000,
+ rx_cdr_pll0.inclk8_input_period = 5000,
+ rx_cdr_pll0.inclk9_input_period = 5000,
+ rx_cdr_pll0.loop_filter_c_bits = 0,
+ rx_cdr_pll0.loop_filter_r_bits = 0,
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 2,
+ rx_cdr_pll0.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll0.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.protocol_hint = "pcie",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_data_rate = 800,
+ rx_cdr_pll0.vco_divide_by = 2,
+ rx_cdr_pll0.vco_multiply_by = 25,
+ rx_cdr_pll0.vco_post_scale = 2,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll1_dprioout),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[17:9]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.charge_pump_current_bits = 0,
+ rx_cdr_pll1.dprio_config_mode = 6'h01,
+ rx_cdr_pll1.inclk0_input_period = 10000,
+ rx_cdr_pll1.inclk1_input_period = 5000,
+ rx_cdr_pll1.inclk2_input_period = 5000,
+ rx_cdr_pll1.inclk3_input_period = 5000,
+ rx_cdr_pll1.inclk4_input_period = 5000,
+ rx_cdr_pll1.inclk5_input_period = 5000,
+ rx_cdr_pll1.inclk6_input_period = 5000,
+ rx_cdr_pll1.inclk7_input_period = 5000,
+ rx_cdr_pll1.inclk8_input_period = 5000,
+ rx_cdr_pll1.inclk9_input_period = 5000,
+ rx_cdr_pll1.loop_filter_c_bits = 0,
+ rx_cdr_pll1.loop_filter_r_bits = 0,
+ rx_cdr_pll1.m = 25,
+ rx_cdr_pll1.n = 2,
+ rx_cdr_pll1.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll1.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll1.pfd_clk_select = 0,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.protocol_hint = "pcie",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_data_rate = 800,
+ rx_cdr_pll1.vco_divide_by = 2,
+ rx_cdr_pll1.vco_multiply_by = 25,
+ rx_cdr_pll1.vco_post_scale = 2,
+ rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll2_dprioout),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[26:18]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.charge_pump_current_bits = 0,
+ rx_cdr_pll2.dprio_config_mode = 6'h01,
+ rx_cdr_pll2.inclk0_input_period = 10000,
+ rx_cdr_pll2.inclk1_input_period = 5000,
+ rx_cdr_pll2.inclk2_input_period = 5000,
+ rx_cdr_pll2.inclk3_input_period = 5000,
+ rx_cdr_pll2.inclk4_input_period = 5000,
+ rx_cdr_pll2.inclk5_input_period = 5000,
+ rx_cdr_pll2.inclk6_input_period = 5000,
+ rx_cdr_pll2.inclk7_input_period = 5000,
+ rx_cdr_pll2.inclk8_input_period = 5000,
+ rx_cdr_pll2.inclk9_input_period = 5000,
+ rx_cdr_pll2.loop_filter_c_bits = 0,
+ rx_cdr_pll2.loop_filter_r_bits = 0,
+ rx_cdr_pll2.m = 25,
+ rx_cdr_pll2.n = 2,
+ rx_cdr_pll2.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll2.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll2.pfd_clk_select = 0,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.protocol_hint = "pcie",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_data_rate = 800,
+ rx_cdr_pll2.vco_divide_by = 2,
+ rx_cdr_pll2.vco_multiply_by = 25,
+ rx_cdr_pll2.vco_post_scale = 2,
+ rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll3_dprioout),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[35:27]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.charge_pump_current_bits = 0,
+ rx_cdr_pll3.dprio_config_mode = 6'h01,
+ rx_cdr_pll3.inclk0_input_period = 10000,
+ rx_cdr_pll3.inclk1_input_period = 5000,
+ rx_cdr_pll3.inclk2_input_period = 5000,
+ rx_cdr_pll3.inclk3_input_period = 5000,
+ rx_cdr_pll3.inclk4_input_period = 5000,
+ rx_cdr_pll3.inclk5_input_period = 5000,
+ rx_cdr_pll3.inclk6_input_period = 5000,
+ rx_cdr_pll3.inclk7_input_period = 5000,
+ rx_cdr_pll3.inclk8_input_period = 5000,
+ rx_cdr_pll3.inclk9_input_period = 5000,
+ rx_cdr_pll3.loop_filter_c_bits = 0,
+ rx_cdr_pll3.loop_filter_r_bits = 0,
+ rx_cdr_pll3.m = 25,
+ rx_cdr_pll3.n = 2,
+ rx_cdr_pll3.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll3.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll3.pfd_clk_select = 0,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.protocol_hint = "pcie",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_data_rate = 800,
+ rx_cdr_pll3.vco_divide_by = 2,
+ rx_cdr_pll3.vco_multiply_by = 25,
+ rx_cdr_pll3.vco_post_scale = 2,
+ rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(pll0_dprioin[299:0]),
+ .dprioout(wire_tx_pll0_dprioout),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .earlyeios(1'b0),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.channel_num = 4,
+ tx_pll0.charge_pump_current_bits = 0,
+ tx_pll0.dprio_config_mode = 6'h01,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.inclk1_input_period = 5000,
+ tx_pll0.inclk2_input_period = 5000,
+ tx_pll0.inclk3_input_period = 5000,
+ tx_pll0.inclk4_input_period = 5000,
+ tx_pll0.inclk5_input_period = 5000,
+ tx_pll0.inclk6_input_period = 5000,
+ tx_pll0.inclk7_input_period = 5000,
+ tx_pll0.inclk8_input_period = 5000,
+ tx_pll0.inclk9_input_period = 5000,
+ tx_pll0.loop_filter_c_bits = 0,
+ tx_pll0.loop_filter_r_bits = 0,
+ tx_pll0.m = 25,
+ tx_pll0.n = 2,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.protocol_hint = "pcie",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_data_rate = 0,
+ tx_pll0.vco_divide_by = 0,
+ tx_pll0.vco_multiply_by = 0,
+ tx_pll0.vco_post_scale = 2,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[0]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x4",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 8,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 250000,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "false",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[1]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(wire_receive_pcs1_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.auto_spd_self_switch_enable = "false",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_mask_cycle = 800,
+ receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x4",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 8,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h01,
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "false",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 250000,
+ receive_pcs1.protocol_hint = "pcie",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rxstatus_error_report_mode = 0,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "false",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[2]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(wire_receive_pcs2_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[8:6]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs2_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs2_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[5:4]),
+ .pipepowerstate(tx_pipepowerstateout[11:8]),
+ .pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs2_pipestatus),
+ .powerdn(powerdn[5:4]),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[2]),
+ .rxfound(rx_pcs_rxfound_wire[5:4]),
+ .signaldetected(rx_signaldetect_wire[2]),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "false",
+ receive_pcs2.allow_pipe_polarity_inversion = "true",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 14,
+ receive_pcs2.auto_spd_self_switch_enable = "false",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_enable = "true",
+ receive_pcs2.cdrctrl_mask_cycle = 800,
+ receive_pcs2.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs2.cdrctrl_rxvalid_mask = "true",
+ receive_pcs2.channel_bonding = "x4",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 8,
+ receive_pcs2.clk1_mux_select = "recovered clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "false",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "pipe",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs2.deskew_pattern = "0",
+ receive_pcs2.disable_auto_idle_insertion = "false",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h01,
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 16,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 17,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "false",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 250000,
+ receive_pcs2.protocol_hint = "pcie",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "false",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs2.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs2.rate_match_pattern_size = 20,
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "true",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rxstatus_error_report_mode = 0,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "false",
+ receive_pcs2.use_double_data_mode = "false",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[3]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(wire_receive_pcs3_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[11:9]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs3_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs3_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[7:6]),
+ .pipepowerstate(tx_pipepowerstateout[15:12]),
+ .pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs3_pipestatus),
+ .powerdn(powerdn[7:6]),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[3]),
+ .rxfound(rx_pcs_rxfound_wire[7:6]),
+ .signaldetected(rx_signaldetect_wire[3]),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "false",
+ receive_pcs3.allow_pipe_polarity_inversion = "true",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 14,
+ receive_pcs3.auto_spd_self_switch_enable = "false",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_enable = "true",
+ receive_pcs3.cdrctrl_mask_cycle = 800,
+ receive_pcs3.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs3.cdrctrl_rxvalid_mask = "true",
+ receive_pcs3.channel_bonding = "x4",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 8,
+ receive_pcs3.clk1_mux_select = "recovered clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "false",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "pipe",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs3.deskew_pattern = "0",
+ receive_pcs3.disable_auto_idle_insertion = "false",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h01,
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 16,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 17,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "false",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 250000,
+ receive_pcs3.protocol_hint = "pcie",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "false",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs3.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs3.rate_match_pattern_size = 20,
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "true",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rxstatus_error_report_mode = 0,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "false",
+ receive_pcs3.use_double_data_mode = "false",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[0]),
+ .adcereset(rx_rxadceresetout[0]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 0,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 4,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[1]),
+ .adcereset(rx_rxadceresetout[1]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(wire_receive_pma1_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h01,
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eqa_ctrl = 0,
+ receive_pma1.eqb_ctrl = 0,
+ receive_pma1.eqc_ctrl = 0,
+ receive_pma1.eqd_ctrl = 0,
+ receive_pma1.eqv_ctrl = 0,
+ receive_pma1.force_signal_detect = "true",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 0,
+ receive_pma1.protocol_hint = "pcie",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma1.signal_detect_loss_threshold = 4,
+ receive_pma1.termination = "OCT 100 Ohms",
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[2]),
+ .adcereset(rx_rxadceresetout[2]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(wire_receive_pma2_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma2_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.allow_serial_loopback = "false",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = "0.82V",
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h01,
+ receive_pma2.eq_dc_gain = 3,
+ receive_pma2.eqa_ctrl = 0,
+ receive_pma2.eqb_ctrl = 0,
+ receive_pma2.eqc_ctrl = 0,
+ receive_pma2.eqd_ctrl = 0,
+ receive_pma2.eqv_ctrl = 0,
+ receive_pma2.force_signal_detect = "true",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 0,
+ receive_pma2.protocol_hint = "pcie",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma2.signal_detect_loss_threshold = 4,
+ receive_pma2.termination = "OCT 100 Ohms",
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[3]),
+ .adcereset(rx_rxadceresetout[3]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_receive_pma3_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma3_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.allow_serial_loopback = "false",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = "0.82V",
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h01,
+ receive_pma3.eq_dc_gain = 3,
+ receive_pma3.eqa_ctrl = 0,
+ receive_pma3.eqb_ctrl = 0,
+ receive_pma3.eqc_ctrl = 0,
+ receive_pma3.eqd_ctrl = 0,
+ receive_pma3.eqv_ctrl = 0,
+ receive_pma3.force_signal_detect = "true",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 0,
+ receive_pma3.protocol_hint = "pcie",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma3.signal_detect_loss_threshold = 4,
+ receive_pma3.termination = "OCT 100 Ohms",
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
+ .datain({{32{1'b0}}, tx_datain_wire[7:0]}),
+ .datainfull(tx_datainfull[43:0]),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.channel_bonding = "x4",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 8,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "false",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(wire_transmit_pcs1_clkout),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[1]}),
+ .datain({{32{1'b0}}, tx_datain_wire[15:8]}),
+ .datainfull(tx_datainfull[87:44]),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[1]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(wire_transmit_pcs1_dprioout),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[1]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[1]),
+ .pipetxdeemph(tx_pipedeemph[1]),
+ .pipetxmargin(tx_pipemargin[5:3]),
+ .pipetxswing(tx_pipeswing[1]),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.auto_spd_self_switch_enable = "false",
+ transmit_pcs1.channel_bonding = "x4",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 8,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h01,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "false",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(wire_transmit_pcs2_clkout),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[2]}),
+ .datain({{32{1'b0}}, tx_datain_wire[23:16]}),
+ .datainfull(tx_datainfull[131:88]),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(tx_detectrxloop[2]),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[2]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(wire_transmit_pcs2_dprioout),
+ .enrevparallellpbk(tx_revparallellpbken[2]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[2]),
+ .pipetxdeemph(tx_pipedeemph[2]),
+ .pipetxmargin(tx_pipemargin[8:6]),
+ .pipetxswing(tx_pipeswing[2]),
+ .powerdn(powerdn[5:4]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[59:40]),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "false",
+ transmit_pcs2.auto_spd_self_switch_enable = "false",
+ transmit_pcs2.channel_bonding = "x4",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 8,
+ transmit_pcs2.core_clock_0ppm = "false",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "pipe",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "new",
+ transmit_pcs2.dprio_config_mode = 6'h01,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "true",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "pcie",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "false",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(wire_transmit_pcs3_clkout),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[3]}),
+ .datain({{32{1'b0}}, tx_datain_wire[31:24]}),
+ .datainfull(tx_datainfull[175:132]),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(tx_detectrxloop[3]),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[3]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(wire_transmit_pcs3_dprioout),
+ .enrevparallellpbk(tx_revparallellpbken[3]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[3]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[3]),
+ .pipetxdeemph(tx_pipedeemph[3]),
+ .pipetxmargin(tx_pipemargin[11:9]),
+ .pipetxswing(tx_pipeswing[3]),
+ .powerdn(powerdn[7:6]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[79:60]),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "false",
+ transmit_pcs3.auto_spd_self_switch_enable = "false",
+ transmit_pcs3.channel_bonding = "x4",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 8,
+ transmit_pcs3.core_clock_0ppm = "false",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "pipe",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "new",
+ transmit_pcs3.dprio_config_mode = 6'h01,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "true",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "pcie",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "false",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "auto",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(wire_transmit_pma1_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "auto",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h01,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.preemp_pretap = 0,
+ transmit_pma1.preemp_pretap_inv = "false",
+ transmit_pma1.preemp_tap_1 = 0,
+ transmit_pma1.preemp_tap_2 = 0,
+ transmit_pma1.preemp_tap_2_inv = "false",
+ transmit_pma1.protocol_hint = "pcie",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "off",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = 4,
+ transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(wire_transmit_pma2_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma2_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[2])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "auto",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h01,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.preemp_pretap = 0,
+ transmit_pma2.preemp_pretap_inv = "false",
+ transmit_pma2.preemp_tap_1 = 0,
+ transmit_pma2.preemp_tap_2 = 0,
+ transmit_pma2.preemp_tap_2_inv = "false",
+ transmit_pma2.protocol_hint = "pcie",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "off",
+ transmit_pma2.termination = "OCT 100 Ohms",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = 4,
+ transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_transmit_pma3_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma3_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[3])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "auto",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h01,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.preemp_pretap = 0,
+ transmit_pma3.preemp_pretap_inv = "false",
+ transmit_pma3.preemp_tap_1 = 0,
+ transmit_pma3.preemp_tap_2 = 0,
+ transmit_pma3.preemp_tap_2_inv = "false",
+ transmit_pma3.protocol_hint = "pcie",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "off",
+ transmit_pma3.termination = "OCT 100 Ohms",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = 4,
+ transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b1,
+ cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxadcepowerdn = {wire_cent_unit0_rxadcepowerdown},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {rx_pcsdprioout[1599:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout},
+ cent_unit_rxpmadprioin = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, rx_pmadprioout[1199:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout},
+ cent_unit_tx_dprioin = {600'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, tx_txdprioout[599:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, tx_pmadprioout[1199:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout},
+ clk_div_clk0in = {pll0_out[3:0]},
+ clk_div_cmudividerdprioin = {100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, wire_central_clk_div0_dprioout, 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ clk_div_pclkin = {1'b0},
+ cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
+ cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
+ cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div0_coreclkout},
+ fixedclk = 1'b0,
+ fixedclk_in = {{2{1'b0}}, {4{fixedclk}}},
+ int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
+ int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
+ int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
+ int_rxcoreclk = {int_rx_coreclkout[0]},
+ int_rxphfifordenable = {int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
+ int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
+ int_txcoreclk = {int_tx_coreclkout[0]},
+ int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[3:0]},
+ pipedatavalid_out = {wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[3:0]},
+ pipeelecidle_out = {wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll0_clkin = {9'b000000000, pll_inclk_wire[0]},
+ pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
+ pll0_dprioout = {wire_tx_pll0_dprioout},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, pll0_dprioout[299:0], 900'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, pll_ch_dprioout[299:0]},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {wire_cent_unit0_dprioout},
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ refclk_pma = {wire_central_clk_div0_refclkout},
+ rx_analogreset_in = {4{rx_analogreset[0]}},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_bitslip = {4{1'b0}},
+ rx_coreclk_in = {4{coreclkout_wire[0]}},
+ rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[3], 8'b00000000, rx_pldcruclk_in[2], 8'b00000000, rx_pldcruclk_in[1], 8'b00000000, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs3_ctrldetect[0], wire_receive_pcs2_ctrldetect[0], wire_receive_pcs1_ctrldetect[0], wire_receive_pcs0_ctrldetect[0]},
+ rx_dataout = {rx_out_wire[31:0]},
+ rx_deserclock_in = {rx_pll_clkout[15:0]},
+ rx_digitalreset_in = {4{rx_digitalreset[0]}},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
+ rx_elecidleinfersel = {12{1'b0}},
+ rx_enapatternalign = {4{1'b0}},
+ rx_freqlocked = {rx_freqlocked_wire[3:0]},
+ rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = {4{1'b0}},
+ rx_locktodata_wire = {rx_locktodata[3:0]},
+ rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs3_dataout[7:0], wire_receive_pcs2_dataout[7:0], wire_receive_pcs1_dataout[7:0], wire_receive_pcs0_dataout[7:0]},
+ rx_patterndetect = {wire_receive_pcs3_patterndetect[0], wire_receive_pcs2_patterndetect[0], wire_receive_pcs1_patterndetect[0], wire_receive_pcs0_patterndetect[0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[1599:0]},
+ rx_pcsdprioout = {wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = {4{1'b1}},
+ rx_phfiforeset = {4{1'b0}},
+ rx_phfifowrdisable = {4{1'b0}},
+ rx_pipestatetransdoneout = {wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[3:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {rx_plllocked_wire[3:0]},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, cent_unit_rxpmadprioout[1199:0]},
+ rx_pmadprioout = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
+ rx_powerdown = {4{1'b0}},
+ rx_powerdown_in = {rx_powerdown[3:0]},
+ rx_prbscidenable = {4{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {4{1'b0}},
+ rx_rxadceresetout = {wire_cent_unit0_rxadceresetout},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs3_syncstatus[0], wire_receive_pcs2_syncstatus[0], wire_receive_pcs1_syncstatus[0], wire_receive_pcs0_syncstatus[0]},
+ rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
+ rxpll_dprioin = {cent_unit_cmuplldprioout[299:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout_int_wire = {wire_transmit_pcs3_clkout, wire_transmit_pcs2_clkout, wire_transmit_pcs1_clkout, wire_transmit_pcs0_clkout},
+ tx_coreclk_in = {4{coreclkout_wire[0]}},
+ tx_datain_wire = {tx_datain[31:0]},
+ tx_datainfull = {176{1'b0}},
+ tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {4{tx_digitalreset[0]}},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
+ tx_dprioin_wire = {600'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, cent_unit_txdprioout[599:0]},
+ tx_forcedisp_wire = {tx_forcedispcompliance[3:0]},
+ tx_invpolarity = {4{1'b0}},
+ tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_phfiforeset = {4{1'b0}},
+ tx_pipedeemph = {4{1'b0}},
+ tx_pipemargin = {12{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = {4{1'b0}},
+ tx_pmadprioin_wire = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, cent_unit_txpmadprioout[1199:0]},
+ tx_pmadprioout = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = {4{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
+ txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+endmodule //altpcie_serdes_4sgx_x4d_gen1_08p_alt4gxb_01d9
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_4sgx_x4d_gen1_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout)/* synthesis synthesis_clearbox = 1 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [7:0] powerdn;
+ input reconfig_clk;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ input [3:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [3:0] tx_ctrlenable;
+ input [31:0] tx_datain;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+ output [0:0] coreclkout;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ output [0:0] pll_locked;
+ output [0:0] reconfig_fromgxb;
+ output [3:0] rx_ctrldetect;
+ output [31:0] rx_dataout;
+ output [3:0] rx_freqlocked;
+ output [3:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [3:0] rx_syncstatus;
+ output [3:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [3:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [3:0] sub_wire2;
+ wire [3:0] sub_wire3;
+ wire [3:0] sub_wire4;
+ wire [3:0] sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [3:0] sub_wire7;
+ wire [3:0] sub_wire8;
+ wire [11:0] sub_wire9;
+ wire [3:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [0:0] sub_wire12;
+ wire [31:0] sub_wire13;
+ wire [3:0] rx_patterndetect = sub_wire0[3:0];
+ wire [0:0] coreclkout = sub_wire1[0:0];
+ wire [3:0] rx_ctrldetect = sub_wire2[3:0];
+ wire [3:0] pipedatavalid = sub_wire3[3:0];
+ wire [3:0] pipephydonestatus = sub_wire4[3:0];
+ wire [3:0] rx_pll_locked = sub_wire5[3:0];
+ wire [3:0] rx_freqlocked = sub_wire6[3:0];
+ wire [3:0] tx_dataout = sub_wire7[3:0];
+ wire [3:0] pipeelecidle = sub_wire8[3:0];
+ wire [11:0] pipestatus = sub_wire9[11:0];
+ wire [3:0] rx_syncstatus = sub_wire10[3:0];
+ wire [0:0] reconfig_fromgxb = sub_wire11[0:0];
+ wire [0:0] pll_locked = sub_wire12[0:0];
+ wire [31:0] rx_dataout = sub_wire13[31:0];
+
+ altpcie_serdes_4sgx_x4d_gen1_08p_alt4gxb_01d9 altpcie_serdes_4sgx_x4d_gen1_08p_alt4gxb_01d9_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .reconfig_clk (reconfig_clk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .coreclkout (sub_wire1),
+ .rx_ctrldetect (sub_wire2),
+ .pipedatavalid (sub_wire3),
+ .pipephydonestatus (sub_wire4),
+ .rx_pll_locked (sub_wire5),
+ .rx_freqlocked (sub_wire6),
+ .tx_dataout (sub_wire7),
+ .pipeelecidle (sub_wire8),
+ .pipestatus (sub_wire9),
+ .rx_syncstatus (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .pll_locked (sub_wire12),
+ .rx_dataout (sub_wire13));
+ defparam
+ altpcie_serdes_4sgx_x4d_gen1_08p_alt4gxb_01d9_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.82"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x4"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.65"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.5"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE NUMERIC "2"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "auto"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_analog_power STRING "2.5v"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: rx_cru_divide_by NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_multiply_by NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: tx_pll_divide_by NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_multiply_by NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 4 0 OUTPUT NODEFVAL "rx_ctrldetect[3..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 32 0 OUTPUT NODEFVAL "rx_dataout[31..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 4 0 OUTPUT NODEFVAL "rx_patterndetect[3..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 4 0 OUTPUT NODEFVAL "rx_syncstatus[3..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 4 0 INPUT NODEFVAL "tx_ctrlenable[3..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 32 0 INPUT NODEFVAL "tx_datain[31..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 4 0 @rx_ctrldetect 0 0 4 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 32 0 @rx_dataout 0 0 32 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 4 0 @rx_syncstatus 0 0 4 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 4 0 tx_ctrlenable 0 0 4 0
+// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
+// Retrieval info: CONNECT: @tx_datain 0 0 32 0 tx_datain 0 0 32 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_08p.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_08p.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_08p.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_08p.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_08p.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_08p_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_08p_bb.v TRUE FALSE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v
new file mode 100644
index 0000000000000000000000000000000000000000..eb679d3da3f09c1d48810d3f609386d0d1ede651
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v
@@ -0,0 +1,3694 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_4sgx_x4d_gen1_16p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Internal Build 106 07/20/2008 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" elec_idle_infer_enable="false" enable_0ppm="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gxb_analog_power="3.0v" gxb_powerdown_width=1 intended_device_speed_grade=2 loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" preemphasis_ctrl_1stposttap_setting=3 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_dprio_mode=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=800 rx_cru_divide_by=2 rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_multiply_by=25 rx_cru_n_divider=2 rx_cru_pfd_clk_select=0 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.4v" tx_channel_bonding="x4" tx_channel_width=16 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=800 tx_pll_divide_by=2 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_multiply_by=25 tx_pll_n_divider=2 tx_pll_pfd_clk_select=0 tx_pll_vco_post_scale_divider=2 tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 8.1 cbx_alt4gxb 2008:07:18:07:31:37:SJ cbx_mgl 2008:07:11:15:23:48:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 5 stratixiv_hssi_rx_pcs 4 stratixiv_hssi_rx_pma 4 stratixiv_hssi_tx_pcs 4 stratixiv_hssi_tx_pma 4
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9
+ (
+ cal_blk_clk,
+ coreclkout,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) /* synthesis synthesis_clearbox=1 */;
+ input cal_blk_clk;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [7:0] powerdn;
+ input reconfig_clk;
+ output [0:0] reconfig_fromgxb;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ output [7:0] rx_ctrldetect;
+ input [3:0] rx_datain;
+ output [63:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [3:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ output [3:0] tx_dataout;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_central_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div0_analogrefclkout;
+ wire wire_central_clk_div0_analogrefclkpulse;
+ wire wire_central_clk_div0_coreclkout;
+ wire [99:0] wire_central_clk_div0_dprioout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_refclkout;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [3:0] wire_cent_unit0_rxadcepowerdown;
+ wire [3:0] wire_cent_unit0_rxadceresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire [299:0] wire_rx_cdr_pll1_dprioout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire [299:0] wire_rx_cdr_pll2_dprioout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire [299:0] wire_rx_cdr_pll3_dprioout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire [299:0] wire_tx_pll0_dprioout;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire wire_receive_pcs0_rateswitchout;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire [399:0] wire_receive_pcs1_dprioout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire wire_receive_pcs1_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire wire_receive_pcs1_rateswitchout;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire [399:0] wire_receive_pcs2_dprioout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_pipedatavalid;
+ wire wire_receive_pcs2_pipeelecidle;
+ wire wire_receive_pcs2_pipephydonestatus;
+ wire wire_receive_pcs2_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs2_pipestatus;
+ wire wire_receive_pcs2_rateswitchout;
+ wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire [399:0] wire_receive_pcs3_dprioout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_pipedatavalid;
+ wire wire_receive_pcs3_pipeelecidle;
+ wire wire_receive_pcs3_pipephydonestatus;
+ wire wire_receive_pcs3_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs3_pipestatus;
+ wire wire_receive_pcs3_rateswitchout;
+ wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire [299:0] wire_receive_pma1_dprioout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire [299:0] wire_receive_pma2_dprioout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire [299:0] wire_receive_pma3_dprioout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire wire_transmit_pcs0_clkout;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_clkout;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire [149:0] wire_transmit_pcs1_dprioout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs2_clkout;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire [149:0] wire_transmit_pcs2_dprioout;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs2_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs2_pipepowerstateout;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs3_clkout;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire [149:0] wire_transmit_pcs3_dprioout;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire [1:0] wire_transmit_pcs3_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs3_pipepowerstateout;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire [299:0] wire_transmit_pma1_dprioout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire [299:0] wire_transmit_pma2_dprioout;
+ wire wire_transmit_pma2_rxdetectvalidout;
+ wire wire_transmit_pma2_rxfoundout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire [299:0] wire_transmit_pma3_dprioout;
+ wire wire_transmit_pma3_rxdetectvalidout;
+ wire wire_transmit_pma3_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [0:0] cent_unit_clkdivpowerdn;
+ wire [599:0] cent_unit_cmudividerdprioout;
+ wire [1799:0] cent_unit_cmuplldprioout;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [3:0] cent_unit_rxadcepowerdn;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1799:0] cent_unit_rxpmadprioin;
+ wire [1799:0] cent_unit_rxpmadprioout;
+ wire [1199:0] cent_unit_tx_dprioin;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [3:0] cent_unit_txdetectrxpowerdn;
+ wire [599:0] cent_unit_txdprioout;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [1799:0] cent_unit_txpmadprioin;
+ wire [1799:0] cent_unit_txpmadprioout;
+ wire [3:0] clk_div_clk0in;
+ wire [599:0] clk_div_cmudividerdprioin;
+ wire [0:0] clk_div_pclkin;
+ wire [1:0] cmu_analogfastrefclkout;
+ wire [1:0] cmu_analogrefclkout;
+ wire [0:0] cmu_analogrefclkpulse;
+ wire [0:0] coreclkout_wire;
+ wire fixedclk;
+ wire [5:0] fixedclk_in;
+ wire [0:0] int_hiprateswtichdone;
+ wire [3:0] int_rx_coreclkout;
+ wire [3:0] int_rx_phfifobyteserdisable;
+ wire [3:0] int_rx_phfifoptrsresetout;
+ wire [3:0] int_rx_phfifordenableout;
+ wire [3:0] int_rx_phfiforesetout;
+ wire [3:0] int_rx_phfifowrdisableout;
+ wire [11:0] int_rx_phfifoxnbytesel;
+ wire [11:0] int_rx_phfifoxnrdenable;
+ wire [11:0] int_rx_phfifoxnwrclk;
+ wire [11:0] int_rx_phfifoxnwrenable;
+ wire [0:0] int_rxcoreclk;
+ wire [0:0] int_rxphfifordenable;
+ wire [0:0] int_rxphfiforeset;
+ wire [0:0] int_rxphfifox4byteselout;
+ wire [0:0] int_rxphfifox4rdenableout;
+ wire [0:0] int_rxphfifox4wrclkout;
+ wire [0:0] int_rxphfifox4wrenableout;
+ wire [3:0] int_tx_coreclkout;
+ wire [3:0] int_tx_phfiforddisableout;
+ wire [3:0] int_tx_phfiforesetout;
+ wire [3:0] int_tx_phfifowrenableout;
+ wire [11:0] int_tx_phfifoxnbytesel;
+ wire [11:0] int_tx_phfifoxnrdclk;
+ wire [11:0] int_tx_phfifoxnrdenable;
+ wire [11:0] int_tx_phfifoxnwrenable;
+ wire [0:0] int_txcoreclk;
+ wire [0:0] int_txphfiforddisable;
+ wire [0:0] int_txphfiforeset;
+ wire [0:0] int_txphfifowrenable;
+ wire [0:0] int_txphfifox4byteselout;
+ wire [0:0] int_txphfifox4rdclkout;
+ wire [0:0] int_txphfifox4rdenableout;
+ wire [0:0] int_txphfifox4wrenableout;
+ wire [0:0] nonusertocmu_out;
+ wire [3:0] pipedatavalid_out;
+ wire [3:0] pipeelecidle_out;
+ wire [9:0] pll0_clkin;
+ wire [299:0] pll0_dprioin;
+ wire [299:0] pll0_dprioout;
+ wire [3:0] pll0_out;
+ wire [3:0] pll1_out;
+ wire [7:0] pll_ch_dataout_wire;
+ wire [1199:0] pll_ch_dprioout;
+ wire [1799:0] pll_cmuplldprioout;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [0:0] refclk_pma;
+ wire [1:0] refclkdividerdprioin;
+ wire [3:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [3:0] rx_bitslip;
+ wire [3:0] rx_coreclk_in;
+ wire [35:0] rx_cruclk_in;
+ wire [15:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [11:0] rx_elecidleinfersel;
+ wire [3:0] rx_enapatternalign;
+ wire [3:0] rx_freqlocked_wire;
+ wire [3:0] rx_locktodata;
+ wire [3:0] rx_locktodata_wire;
+ wire [3:0] rx_locktorefclk_wire;
+ wire [63:0] rx_out_wire;
+ wire [7:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [3:0] rx_phfifordenable;
+ wire [3:0] rx_phfiforeset;
+ wire [3:0] rx_phfifowrdisable;
+ wire [3:0] rx_pipestatetransdoneout;
+ wire [3:0] rx_pldcruclk_in;
+ wire [15:0] rx_pll_clkout;
+ wire [3:0] rx_pll_pfdrefclkout_wire;
+ wire [3:0] rx_plllocked_wire;
+ wire [3:0] rx_pma_clockout;
+ wire [3:0] rx_pma_dataout;
+ wire [3:0] rx_pma_locktorefout;
+ wire [79:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [1799:0] rx_pmadprioout;
+ wire [3:0] rx_powerdown;
+ wire [3:0] rx_powerdown_in;
+ wire [3:0] rx_prbscidenable;
+ wire [79:0] rx_revparallelfdbkdata;
+ wire [3:0] rx_rmfiforeset;
+ wire [3:0] rx_rxadceresetout;
+ wire [5:0] rx_rxcruresetout;
+ wire [3:0] rx_signaldetect_wire;
+ wire [0:0] rxphfifowrdisable;
+ wire [299:0] rxpll_dprioin;
+ wire [5:0] tx_analogreset_out;
+ wire [3:0] tx_clkout_int_wire;
+ wire [3:0] tx_coreclk_in;
+ wire [63:0] tx_datain_wire;
+ wire [351:0] tx_datainfull;
+ wire [79:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [7:0] tx_forcedisp_wire;
+ wire [3:0] tx_invpolarity;
+ wire [3:0] tx_localrefclk;
+ wire [3:0] tx_phfiforeset;
+ wire [3:0] tx_pipedeemph;
+ wire [11:0] tx_pipemargin;
+ wire [7:0] tx_pipepowerdownout;
+ wire [15:0] tx_pipepowerstateout;
+ wire [3:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [1799:0] tx_pmadprioout;
+ wire [3:0] tx_revparallellpbken;
+ wire [3:0] tx_rxdetectvalidout;
+ wire [3:0] tx_rxfoundout;
+ wire [599:0] tx_txdprioout;
+ wire [3:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[3:0]),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[99:0]),
+ .dprioout(wire_central_clk_div0_dprioout),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkin({2{clk_div_pclkin[0]}}),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .vcobypassin(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.data_rate = 800,
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.enable_dynamic_divider = "false",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclk_divide_by = 2,
+ central_clk_div0.refclk_multiply_by = 25,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_rate_switch_base_clock = "true",
+ central_clk_div0.select_local_refclk = "true",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "true",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin(clk_div_cmudividerdprioin[599:0]),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .fixedclk(fixedclk_in[5:0]),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin(refclkdividerdprioin[1:0]),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(wire_cent_unit0_rxadcepowerdown),
+ .rxadceresetout(wire_cent_unit0_rxadceresetout),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset(rx_digitalreset_in[3:0]),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxdprioout(),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin(cent_unit_rxpcsdprioin[1599:0]),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin(cent_unit_rxpmadprioin[1799:0]),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset(tx_digitalreset_in[3:0]),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txdprioout(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin(cent_unit_tx_dprioin[599:0]),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin(cent_unit_txpmadprioin[1799:0]),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .rateswitch(1'b0),
+ .rxdprioin({1200{1'b0}}),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({6000{1'b0}}),
+ .txdprioin({600{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.dprio_config_mode = 6'h01,
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 250000,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "x4",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "x4",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "3.0V",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.charge_pump_current_bits = 0,
+ rx_cdr_pll0.dprio_config_mode = 6'h01,
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.inclk1_input_period = 5000,
+ rx_cdr_pll0.inclk2_input_period = 5000,
+ rx_cdr_pll0.inclk3_input_period = 5000,
+ rx_cdr_pll0.inclk4_input_period = 5000,
+ rx_cdr_pll0.inclk5_input_period = 5000,
+ rx_cdr_pll0.inclk6_input_period = 5000,
+ rx_cdr_pll0.inclk7_input_period = 5000,
+ rx_cdr_pll0.inclk8_input_period = 5000,
+ rx_cdr_pll0.inclk9_input_period = 5000,
+ rx_cdr_pll0.loop_filter_c_bits = 0,
+ rx_cdr_pll0.loop_filter_r_bits = 0,
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 2,
+ rx_cdr_pll0.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll0.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.protocol_hint = "pcie",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_data_rate = 800,
+ rx_cdr_pll0.vco_divide_by = 2,
+ rx_cdr_pll0.vco_multiply_by = 25,
+ rx_cdr_pll0.vco_post_scale = 2,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll1_dprioout),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[17:9]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.charge_pump_current_bits = 0,
+ rx_cdr_pll1.dprio_config_mode = 6'h01,
+ rx_cdr_pll1.inclk0_input_period = 10000,
+ rx_cdr_pll1.inclk1_input_period = 5000,
+ rx_cdr_pll1.inclk2_input_period = 5000,
+ rx_cdr_pll1.inclk3_input_period = 5000,
+ rx_cdr_pll1.inclk4_input_period = 5000,
+ rx_cdr_pll1.inclk5_input_period = 5000,
+ rx_cdr_pll1.inclk6_input_period = 5000,
+ rx_cdr_pll1.inclk7_input_period = 5000,
+ rx_cdr_pll1.inclk8_input_period = 5000,
+ rx_cdr_pll1.inclk9_input_period = 5000,
+ rx_cdr_pll1.loop_filter_c_bits = 0,
+ rx_cdr_pll1.loop_filter_r_bits = 0,
+ rx_cdr_pll1.m = 25,
+ rx_cdr_pll1.n = 2,
+ rx_cdr_pll1.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll1.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll1.pfd_clk_select = 0,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.protocol_hint = "pcie",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_data_rate = 800,
+ rx_cdr_pll1.vco_divide_by = 2,
+ rx_cdr_pll1.vco_multiply_by = 25,
+ rx_cdr_pll1.vco_post_scale = 2,
+ rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll2_dprioout),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[26:18]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.charge_pump_current_bits = 0,
+ rx_cdr_pll2.dprio_config_mode = 6'h01,
+ rx_cdr_pll2.inclk0_input_period = 10000,
+ rx_cdr_pll2.inclk1_input_period = 5000,
+ rx_cdr_pll2.inclk2_input_period = 5000,
+ rx_cdr_pll2.inclk3_input_period = 5000,
+ rx_cdr_pll2.inclk4_input_period = 5000,
+ rx_cdr_pll2.inclk5_input_period = 5000,
+ rx_cdr_pll2.inclk6_input_period = 5000,
+ rx_cdr_pll2.inclk7_input_period = 5000,
+ rx_cdr_pll2.inclk8_input_period = 5000,
+ rx_cdr_pll2.inclk9_input_period = 5000,
+ rx_cdr_pll2.loop_filter_c_bits = 0,
+ rx_cdr_pll2.loop_filter_r_bits = 0,
+ rx_cdr_pll2.m = 25,
+ rx_cdr_pll2.n = 2,
+ rx_cdr_pll2.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll2.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll2.pfd_clk_select = 0,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.protocol_hint = "pcie",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_data_rate = 800,
+ rx_cdr_pll2.vco_divide_by = 2,
+ rx_cdr_pll2.vco_multiply_by = 25,
+ rx_cdr_pll2.vco_post_scale = 2,
+ rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll3_dprioout),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({{1{1'b0}}, rx_cruclk_in[35:27]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.charge_pump_current_bits = 0,
+ rx_cdr_pll3.dprio_config_mode = 6'h01,
+ rx_cdr_pll3.inclk0_input_period = 10000,
+ rx_cdr_pll3.inclk1_input_period = 5000,
+ rx_cdr_pll3.inclk2_input_period = 5000,
+ rx_cdr_pll3.inclk3_input_period = 5000,
+ rx_cdr_pll3.inclk4_input_period = 5000,
+ rx_cdr_pll3.inclk5_input_period = 5000,
+ rx_cdr_pll3.inclk6_input_period = 5000,
+ rx_cdr_pll3.inclk7_input_period = 5000,
+ rx_cdr_pll3.inclk8_input_period = 5000,
+ rx_cdr_pll3.inclk9_input_period = 5000,
+ rx_cdr_pll3.loop_filter_c_bits = 0,
+ rx_cdr_pll3.loop_filter_r_bits = 0,
+ rx_cdr_pll3.m = 25,
+ rx_cdr_pll3.n = 2,
+ rx_cdr_pll3.pd_charge_pump_current_bits = 0,
+ rx_cdr_pll3.pd_loop_filter_r_bits = 0,
+ rx_cdr_pll3.pfd_clk_select = 0,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.protocol_hint = "pcie",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_data_rate = 800,
+ rx_cdr_pll3.vco_divide_by = 2,
+ rx_cdr_pll3.vco_multiply_by = 25,
+ rx_cdr_pll3.vco_post_scale = 2,
+ rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(pll0_dprioin[299:0]),
+ .dprioout(wire_tx_pll0_dprioout),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .earlyeios(1'b0),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.channel_num = 4,
+ tx_pll0.charge_pump_current_bits = 0,
+ tx_pll0.dprio_config_mode = 6'h01,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.inclk1_input_period = 5000,
+ tx_pll0.inclk2_input_period = 5000,
+ tx_pll0.inclk3_input_period = 5000,
+ tx_pll0.inclk4_input_period = 5000,
+ tx_pll0.inclk5_input_period = 5000,
+ tx_pll0.inclk6_input_period = 5000,
+ tx_pll0.inclk7_input_period = 5000,
+ tx_pll0.inclk8_input_period = 5000,
+ tx_pll0.inclk9_input_period = 5000,
+ tx_pll0.loop_filter_c_bits = 0,
+ tx_pll0.loop_filter_r_bits = 0,
+ tx_pll0.m = 25,
+ tx_pll0.n = 2,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.protocol_hint = "pcie",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_data_rate = 0,
+ tx_pll0.vco_divide_by = 0,
+ tx_pll0.vco_multiply_by = 0,
+ tx_pll0.vco_post_scale = 2,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[0]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x4",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 250000,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[1]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(wire_receive_pcs1_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.auto_spd_self_switch_enable = "false",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_mask_cycle = 800,
+ receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x4",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 16,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h01,
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "false",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 250000,
+ receive_pcs1.protocol_hint = "pcie",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rxstatus_error_report_mode = 0,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "true",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[2]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(wire_receive_pcs2_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[8:6]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs2_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs2_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[5:4]),
+ .pipepowerstate(tx_pipepowerstateout[11:8]),
+ .pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs2_pipestatus),
+ .powerdn(powerdn[5:4]),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[2]),
+ .rxfound(rx_pcs_rxfound_wire[5:4]),
+ .signaldetected(rx_signaldetect_wire[2]),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "false",
+ receive_pcs2.allow_pipe_polarity_inversion = "true",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 14,
+ receive_pcs2.auto_spd_self_switch_enable = "false",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_enable = "true",
+ receive_pcs2.cdrctrl_mask_cycle = 800,
+ receive_pcs2.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs2.cdrctrl_rxvalid_mask = "true",
+ receive_pcs2.channel_bonding = "x4",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 16,
+ receive_pcs2.clk1_mux_select = "recovered clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "false",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "pipe",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs2.deskew_pattern = "0",
+ receive_pcs2.disable_auto_idle_insertion = "false",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h01,
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 16,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 17,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "false",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 250000,
+ receive_pcs2.protocol_hint = "pcie",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "false",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs2.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs2.rate_match_pattern_size = 20,
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "true",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rxstatus_error_report_mode = 0,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "false",
+ receive_pcs2.use_double_data_mode = "true",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslip(rx_bitslip[3]),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(wire_receive_pcs3_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[11:9]),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs3_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs3_pipeelecidle),
+ .pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[7:6]),
+ .pipepowerstate(tx_pipepowerstateout[15:12]),
+ .pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs3_pipestatus),
+ .powerdn(powerdn[7:6]),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[3]),
+ .rxfound(rx_pcs_rxfound_wire[7:6]),
+ .signaldetected(rx_signaldetect_wire[3]),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .cdrctrllocktorefcl(1'b0),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "false",
+ receive_pcs3.allow_pipe_polarity_inversion = "true",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 14,
+ receive_pcs3.auto_spd_self_switch_enable = "false",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_enable = "true",
+ receive_pcs3.cdrctrl_mask_cycle = 800,
+ receive_pcs3.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs3.cdrctrl_rxvalid_mask = "true",
+ receive_pcs3.channel_bonding = "x4",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 16,
+ receive_pcs3.clk1_mux_select = "recovered clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "false",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "pipe",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs3.deskew_pattern = "0",
+ receive_pcs3.disable_auto_idle_insertion = "false",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h01,
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 16,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 17,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "false",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 250000,
+ receive_pcs3.protocol_hint = "pcie",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "false",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs3.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs3.rate_match_pattern_size = 20,
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "true",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rxstatus_error_report_mode = 0,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "false",
+ receive_pcs3.use_double_data_mode = "true",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[0]),
+ .adcereset(rx_rxadceresetout[0]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 0,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma0.signal_detect_loss_threshold = 4,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[1]),
+ .adcereset(rx_rxadceresetout[1]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(wire_receive_pma1_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h01,
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eqa_ctrl = 0,
+ receive_pma1.eqb_ctrl = 0,
+ receive_pma1.eqc_ctrl = 0,
+ receive_pma1.eqd_ctrl = 0,
+ receive_pma1.eqv_ctrl = 0,
+ receive_pma1.force_signal_detect = "true",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 0,
+ receive_pma1.protocol_hint = "pcie",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma1.signal_detect_loss_threshold = 4,
+ receive_pma1.termination = "OCT 100 Ohms",
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[2]),
+ .adcereset(rx_rxadceresetout[2]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(wire_receive_pma2_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma2_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.allow_serial_loopback = "false",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = "0.82V",
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h01,
+ receive_pma2.eq_dc_gain = 3,
+ receive_pma2.eqa_ctrl = 0,
+ receive_pma2.eqb_ctrl = 0,
+ receive_pma2.eqc_ctrl = 0,
+ receive_pma2.eqd_ctrl = 0,
+ receive_pma2.eqv_ctrl = 0,
+ receive_pma2.force_signal_detect = "true",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 0,
+ receive_pma2.protocol_hint = "pcie",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma2.signal_detect_loss_threshold = 4,
+ receive_pma2.termination = "OCT 100 Ohms",
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .adcepowerdn(cent_unit_rxadcepowerdn[3]),
+ .adcereset(rx_rxadceresetout[3]),
+ .analogtestbus(),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_receive_pma3_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma3_signaldetect)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcestandby(1'b0),
+ .ppmdetectdividedclk(1'b0),
+ .testbussel({4{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.allow_serial_loopback = "false",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = "0.82V",
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h01,
+ receive_pma3.eq_dc_gain = 3,
+ receive_pma3.eqa_ctrl = 0,
+ receive_pma3.eqb_ctrl = 0,
+ receive_pma3.eqc_ctrl = 0,
+ receive_pma3.eqd_ctrl = 0,
+ receive_pma3.eqv_ctrl = 0,
+ receive_pma3.force_signal_detect = "true",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 0,
+ receive_pma3.protocol_hint = "pcie",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 2,
+ receive_pma3.signal_detect_loss_threshold = 4,
+ receive_pma3.termination = "OCT 100 Ohms",
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(wire_transmit_pcs0_clkout),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
+ .datain({{24{1'b0}}, tx_datain_wire[15:0]}),
+ .datainfull(tx_datainfull[43:0]),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.channel_bonding = "x4",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(wire_transmit_pcs1_clkout),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
+ .datain({{24{1'b0}}, tx_datain_wire[31:16]}),
+ .datainfull(tx_datainfull[87:44]),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[1]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(wire_transmit_pcs1_dprioout),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[1]),
+ .pipetxdeemph(tx_pipedeemph[1]),
+ .pipetxmargin(tx_pipemargin[5:3]),
+ .pipetxswing(tx_pipeswing[1]),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.auto_spd_self_switch_enable = "false",
+ transmit_pcs1.channel_bonding = "x4",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 16,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h01,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "true",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(wire_transmit_pcs2_clkout),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[5:4]}),
+ .datain({{24{1'b0}}, tx_datain_wire[47:32]}),
+ .datainfull(tx_datainfull[131:88]),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(tx_detectrxloop[2]),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[2]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(wire_transmit_pcs2_dprioout),
+ .enrevparallellpbk(tx_revparallellpbken[2]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[5:4]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[2]),
+ .pipetxdeemph(tx_pipedeemph[2]),
+ .pipetxmargin(tx_pipemargin[8:6]),
+ .pipetxswing(tx_pipeswing[2]),
+ .powerdn(powerdn[5:4]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[59:40]),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "false",
+ transmit_pcs2.auto_spd_self_switch_enable = "false",
+ transmit_pcs2.channel_bonding = "x4",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 16,
+ transmit_pcs2.core_clock_0ppm = "false",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "pipe",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "new",
+ transmit_pcs2.dprio_config_mode = 6'h01,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "true",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "pcie",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "true",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(wire_transmit_pcs3_clkout),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[7:6]}),
+ .datain({{24{1'b0}}, tx_datain_wire[63:48]}),
+ .datainfull(tx_datainfull[175:132]),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(tx_detectrxloop[3]),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[3]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(wire_transmit_pcs3_dprioout),
+ .enrevparallellpbk(tx_revparallellpbken[3]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[7:6]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[3]),
+ .pipetxdeemph(tx_pipedeemph[3]),
+ .pipetxmargin(tx_pipemargin[11:9]),
+ .pipetxswing(tx_pipeswing[3]),
+ .powerdn(powerdn[7:6]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[79:60]),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout()
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .analogreset(1'b0),
+ .bitslipboundaryselect({5{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "false",
+ transmit_pcs3.auto_spd_self_switch_enable = "false",
+ transmit_pcs3.channel_bonding = "x4",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 16,
+ transmit_pcs3.core_clock_0ppm = "false",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "pipe",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "new",
+ transmit_pcs3.dprio_config_mode = 6'h01,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "true",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "pcie",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "true",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "1.4V",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 3,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(wire_transmit_pma1_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "1.4V",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h01,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.preemp_pretap = 0,
+ transmit_pma1.preemp_pretap_inv = "false",
+ transmit_pma1.preemp_tap_1 = 3,
+ transmit_pma1.preemp_tap_2 = 0,
+ transmit_pma1.preemp_tap_2_inv = "false",
+ transmit_pma1.protocol_hint = "pcie",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "off",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = 4,
+ transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(wire_transmit_pma2_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma2_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[2])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "1.4V",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h01,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.preemp_pretap = 0,
+ transmit_pma2.preemp_pretap_inv = "false",
+ transmit_pma2.preemp_tap_1 = 3,
+ transmit_pma2.preemp_tap_2 = 0,
+ transmit_pma2.preemp_tap_2_inv = "false",
+ transmit_pma2.protocol_hint = "pcie",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "off",
+ transmit_pma2.termination = "OCT 100 Ohms",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = 4,
+ transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_transmit_pma3_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .fastrefclk4in(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .refclk4in(1'b0),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma3_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[3])
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .pclk(1'b0),
+ .rxdetectclk(1'b0)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "1.4V",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h01,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.preemp_pretap = 0,
+ transmit_pma3.preemp_pretap_inv = "false",
+ transmit_pma3.preemp_tap_1 = 3,
+ transmit_pma3.preemp_tap_2 = 0,
+ transmit_pma3.preemp_tap_2_inv = "false",
+ transmit_pma3.protocol_hint = "pcie",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "off",
+ transmit_pma3.termination = "OCT 100 Ohms",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = 4,
+ transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b1,
+ cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxadcepowerdn = {wire_cent_unit0_rxadcepowerdown},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {rx_pcsdprioout[1599:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout},
+ cent_unit_rxpmadprioin = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, rx_pmadprioout[1199:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout},
+ cent_unit_tx_dprioin = {600'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, tx_txdprioout[599:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, tx_pmadprioout[1199:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout},
+ clk_div_clk0in = {pll0_out[3:0]},
+ clk_div_cmudividerdprioin = {100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, wire_central_clk_div0_dprioout, 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
+ clk_div_pclkin = {1'b0},
+ cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
+ cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
+ cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div0_coreclkout},
+ fixedclk = 1'b0,
+ fixedclk_in = {{2{1'b0}}, {4{fixedclk}}},
+ int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
+ int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
+ int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
+ int_rxcoreclk = {int_rx_coreclkout[0]},
+ int_rxphfifordenable = {int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
+ int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
+ int_txcoreclk = {int_tx_coreclkout[0]},
+ int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[3:0]},
+ pipedatavalid_out = {wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[3:0]},
+ pipeelecidle_out = {wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll0_clkin = {9'b000000000, pll_inclk_wire[0]},
+ pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
+ pll0_dprioout = {wire_tx_pll0_dprioout},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, pll0_dprioout[299:0], 900'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, pll_ch_dprioout[299:0]},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {wire_cent_unit0_dprioout},
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ refclk_pma = {wire_central_clk_div0_refclkout},
+ rx_analogreset_in = {4{rx_analogreset[0]}},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_bitslip = {4{1'b0}},
+ rx_coreclk_in = {4{coreclkout_wire[0]}},
+ rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[3], 8'b00000000, rx_pldcruclk_in[2], 8'b00000000, rx_pldcruclk_in[1], 8'b00000000, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[63:0]},
+ rx_deserclock_in = {rx_pll_clkout[15:0]},
+ rx_digitalreset_in = {4{rx_digitalreset[0]}},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
+ rx_elecidleinfersel = {12{1'b0}},
+ rx_enapatternalign = {4{1'b0}},
+ rx_freqlocked = {rx_freqlocked_wire[3:0]},
+ rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = {4{1'b0}},
+ rx_locktodata_wire = {rx_locktodata[3:0]},
+ rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[1599:0]},
+ rx_pcsdprioout = {wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = {4{1'b1}},
+ rx_phfiforeset = {4{1'b0}},
+ rx_phfifowrdisable = {4{1'b0}},
+ rx_pipestatetransdoneout = {wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[3:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {rx_plllocked_wire[3:0]},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, cent_unit_rxpmadprioout[1199:0]},
+ rx_pmadprioout = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
+ rx_powerdown = {4{1'b0}},
+ rx_powerdown_in = {rx_powerdown[3:0]},
+ rx_prbscidenable = {4{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {4{1'b0}},
+ rx_rxadceresetout = {wire_cent_unit0_rxadceresetout},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
+ rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
+ rxpll_dprioin = {cent_unit_cmuplldprioout[299:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_clkout_int_wire = {wire_transmit_pcs3_clkout, wire_transmit_pcs2_clkout, wire_transmit_pcs1_clkout, wire_transmit_pcs0_clkout},
+ tx_coreclk_in = {4{coreclkout_wire[0]}},
+ tx_datain_wire = {tx_datain[63:0]},
+ tx_datainfull = {352{1'b0}},
+ tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {4{tx_digitalreset[0]}},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
+ tx_dprioin_wire = {600'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, cent_unit_txdprioout[599:0]},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[3], 1'b0, tx_forcedispcompliance[2], 1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = {4{1'b0}},
+ tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_phfiforeset = {4{1'b0}},
+ tx_pipedeemph = {4{1'b0}},
+ tx_pipemargin = {12{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = {4{1'b0}},
+ tx_pmadprioin_wire = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, cent_unit_txpmadprioout[1199:0]},
+ tx_pmadprioout = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = {4{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
+ txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+endmodule //altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_4sgx_x4d_gen1_16p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout)/* synthesis synthesis_clearbox = 1 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [7:0] powerdn;
+ input reconfig_clk;
+ input [2:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ input [3:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+ output [0:0] coreclkout;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ output [0:0] pll_locked;
+ output [0:0] reconfig_fromgxb;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [3:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ output [3:0] tx_dataout;
+
+ parameter starting_channel_number = 0;
+
+
+ wire [7:0] sub_wire0;
+ wire [0:0] sub_wire1;
+ wire [7:0] sub_wire2;
+ wire [3:0] sub_wire3;
+ wire [3:0] sub_wire4;
+ wire [3:0] sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [3:0] sub_wire7;
+ wire [3:0] sub_wire8;
+ wire [11:0] sub_wire9;
+ wire [7:0] sub_wire10;
+ wire [0:0] sub_wire11;
+ wire [0:0] sub_wire12;
+ wire [63:0] sub_wire13;
+ wire [7:0] rx_patterndetect = sub_wire0[7:0];
+ wire [0:0] coreclkout = sub_wire1[0:0];
+ wire [7:0] rx_ctrldetect = sub_wire2[7:0];
+ wire [3:0] pipedatavalid = sub_wire3[3:0];
+ wire [3:0] pipephydonestatus = sub_wire4[3:0];
+ wire [3:0] rx_pll_locked = sub_wire5[3:0];
+ wire [3:0] rx_freqlocked = sub_wire6[3:0];
+ wire [3:0] tx_dataout = sub_wire7[3:0];
+ wire [3:0] pipeelecidle = sub_wire8[3:0];
+ wire [11:0] pipestatus = sub_wire9[11:0];
+ wire [7:0] rx_syncstatus = sub_wire10[7:0];
+ wire [0:0] reconfig_fromgxb = sub_wire11[0:0];
+ wire [0:0] pll_locked = sub_wire12[0:0];
+ wire [63:0] rx_dataout = sub_wire13[63:0];
+
+ altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9 altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9_component (
+ .tx_forceelecidle (tx_forceelecidle),
+ .pll_inclk (pll_inclk),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .powerdn (powerdn),
+ .reconfig_clk (reconfig_clk),
+ .rx_datain (rx_datain),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .coreclkout (sub_wire1),
+ .rx_ctrldetect (sub_wire2),
+ .pipedatavalid (sub_wire3),
+ .pipephydonestatus (sub_wire4),
+ .rx_pll_locked (sub_wire5),
+ .rx_freqlocked (sub_wire6),
+ .tx_dataout (sub_wire7),
+ .pipeelecidle (sub_wire8),
+ .pipestatus (sub_wire9),
+ .rx_syncstatus (sub_wire10),
+ .reconfig_fromgxb (sub_wire11),
+ .pll_locked (sub_wire12),
+ .rx_dataout (sub_wire13));
+ defparam
+ altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500.00"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.82"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x4"
+// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.65"
+// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.4"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE NUMERIC "2"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "3"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.4v"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_analog_power STRING "3.0v"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: rx_cru_divide_by NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_multiply_by NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "800"
+// Retrieval info: CONSTANT: tx_pll_divide_by NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_multiply_by NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_pfd_clk_select NUMERIC "0"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p_bb.v TRUE FALSE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..7900d4b0a33f41ea5f787d40fd11b4c1648fb695
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v
@@ -0,0 +1,4027 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_4sgx_x4d_gen2_08p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.0 Internal Build 118 02/15/2011 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="5000 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="3.0v" gxb_powerdown_width=1 input_clock_frequency="100.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="pcie2" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="auto" rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=1 rx_data_rate=5000 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x4" tx_channel_width=16 tx_clkout_width=4 tx_common_mode="0.65v" tx_data_rate=5000 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=1 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=3 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn rateswitch reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
+//VERSION_BEGIN 11.0 cbx_alt4gxb 2011:02:15:21:24:41:SJ cbx_mgl 2011:02:15:21:26:30:SJ cbx_tgx 2011:02:15:21:24:41:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = reg 26 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 5 stratixiv_hssi_rx_pcs 4 stratixiv_hssi_rx_pma 4 stratixiv_hssi_tx_pcs 4 stratixiv_hssi_tx_pma 4
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
+module altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea
+ (
+ cal_blk_clk,
+ coreclkout,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ rateswitch,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ tx_pipedeemph,
+ tx_pipemargin) /* synthesis synthesis_clearbox=2 */;
+ input cal_blk_clk;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [7:0] powerdn;
+ input [0:0] rateswitch;
+ input reconfig_clk;
+ output [16:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ output [7:0] rx_ctrldetect;
+ input [3:0] rx_datain;
+ output [63:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [3:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ output [3:0] tx_dataout;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+ input [3:0] tx_pipedeemph;
+ input [11:0] tx_pipemargin;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [3:0] pipe8b10binvpolarity;
+ tri0 pll_inclk;
+ tri0 [7:0] powerdn;
+ tri0 [0:0] rateswitch;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [3:0] rx_cruclk;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [7:0] tx_ctrlenable;
+ tri0 [63:0] tx_datain;
+ tri0 [3:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [3:0] tx_forcedispcompliance;
+ tri0 [3:0] tx_forceelecidle;
+ tri0 [3:0] tx_pipedeemph;
+ tri0 [11:0] tx_pipemargin;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire [9:0] wire_pcie_sw_sel_delay_blk0c_d;
+ reg [9:0] pcie_sw_sel_delay_blk0c;
+ wire [9:0] wire_pcie_sw_sel_delay_blk0c_prn;
+ wire [9:0] wire_pllreset_delay_blk0c_d;
+ reg [9:0] pllreset_delay_blk0c;
+ wire [9:0] wire_pllreset_delay_blk0c_prn;
+ wire [2:0] wire_rx_digitalreset_reg0c_d;
+ reg [2:0] rx_digitalreset_reg0c;
+ wire [2:0] wire_rx_digitalreset_reg0c_clk;
+ wire [2:0] wire_tx_digitalreset_reg0c_d;
+ reg [2:0] tx_digitalreset_reg0c;
+ wire [2:0] wire_tx_digitalreset_reg0c_clk;
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_central_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div0_analogrefclkout;
+ wire wire_central_clk_div0_analogrefclkpulse;
+ wire wire_central_clk_div0_coreclkout;
+ wire [99:0] wire_central_clk_div0_dprioout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_refclkout;
+ wire wire_cent_unit0_autospdx4configsel;
+ wire wire_cent_unit0_autospdx4rateswitchout;
+ wire wire_cent_unit0_autospdx4spdchg;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire [9:0] wire_cent_unit0_digitaltestout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire wire_cent_unit0_phfifiox4ptrsreset;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire [299:0] wire_rx_cdr_pll1_dprioout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire [299:0] wire_rx_cdr_pll2_dprioout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire [299:0] wire_rx_cdr_pll3_dprioout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire [299:0] wire_tx_pll0_dprioout;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_autospdrateswitchout;
+ wire wire_receive_pcs0_cdrctrlearlyeios;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire wire_receive_pcs0_rateswitchout;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire wire_receive_pcs0_signaldetect;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_autospdrateswitchout;
+ wire wire_receive_pcs1_cdrctrlearlyeios;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire [399:0] wire_receive_pcs1_dprioout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire wire_receive_pcs1_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire wire_receive_pcs1_rateswitchout;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire wire_receive_pcs1_signaldetect;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs2_autospdrateswitchout;
+ wire wire_receive_pcs2_cdrctrlearlyeios;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire [399:0] wire_receive_pcs2_dprioout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_pipedatavalid;
+ wire wire_receive_pcs2_pipeelecidle;
+ wire wire_receive_pcs2_pipephydonestatus;
+ wire wire_receive_pcs2_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs2_pipestatus;
+ wire wire_receive_pcs2_rateswitchout;
+ wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
+ wire wire_receive_pcs2_signaldetect;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs3_autospdrateswitchout;
+ wire wire_receive_pcs3_cdrctrlearlyeios;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire [399:0] wire_receive_pcs3_dprioout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_pipedatavalid;
+ wire wire_receive_pcs3_pipeelecidle;
+ wire wire_receive_pcs3_pipephydonestatus;
+ wire wire_receive_pcs3_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs3_pipestatus;
+ wire wire_receive_pcs3_rateswitchout;
+ wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
+ wire wire_receive_pcs3_signaldetect;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire [7:0] wire_receive_pma1_analogtestbus;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire [299:0] wire_receive_pma1_dprioout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire [7:0] wire_receive_pma2_analogtestbus;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire [299:0] wire_receive_pma2_dprioout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire [7:0] wire_receive_pma3_analogtestbus;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire [299:0] wire_receive_pma3_dprioout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire wire_transmit_pcs0_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire [149:0] wire_transmit_pcs1_dprioout;
+ wire wire_transmit_pcs1_forceelecidleout;
+ wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire wire_transmit_pcs1_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire [149:0] wire_transmit_pcs2_dprioout;
+ wire wire_transmit_pcs2_forceelecidleout;
+ wire [2:0] wire_transmit_pcs2_grayelecidleinferselout;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire wire_transmit_pcs2_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs2_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs2_pipepowerstateout;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire [149:0] wire_transmit_pcs3_dprioout;
+ wire wire_transmit_pcs3_forceelecidleout;
+ wire [2:0] wire_transmit_pcs3_grayelecidleinferselout;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire wire_transmit_pcs3_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs3_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs3_pipepowerstateout;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire [299:0] wire_transmit_pma1_dprioout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire [299:0] wire_transmit_pma2_dprioout;
+ wire wire_transmit_pma2_rxdetectvalidout;
+ wire wire_transmit_pma2_rxfoundout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire [299:0] wire_transmit_pma3_dprioout;
+ wire wire_transmit_pma3_rxdetectvalidout;
+ wire wire_transmit_pma3_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [0:0] cent_unit_clkdivpowerdn;
+ wire [599:0] cent_unit_cmudividerdprioout;
+ wire [1799:0] cent_unit_cmuplldprioout;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1799:0] cent_unit_rxpmadprioin;
+ wire [1799:0] cent_unit_rxpmadprioout;
+ wire [1199:0] cent_unit_tx_dprioin;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [5:0] cent_unit_txdetectrxpowerdn;
+ wire [599:0] cent_unit_txdprioout;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [1799:0] cent_unit_txpmadprioin;
+ wire [1799:0] cent_unit_txpmadprioout;
+ wire [3:0] clk_div_clk0in;
+ wire [599:0] clk_div_cmudividerdprioin;
+ wire [1:0] cmu_analogfastrefclkout;
+ wire [1:0] cmu_analogrefclkout;
+ wire [0:0] cmu_analogrefclkpulse;
+ wire [0:0] coreclkout_wire;
+ wire fixedclk;
+ wire [5:0] fixedclk_to_cmu;
+ wire [11:0] grayelecidleinfersel_from_tx;
+ wire [0:0] int_autospdx4configsel;
+ wire [0:0] int_autospdx4spdchg;
+ wire [0:0] int_hiprateswtichdone;
+ wire [0:0] int_pcie_sw;
+ wire [0:0] int_pcie_sw_select;
+ wire [0:0] int_phfifiox4ptrsreset;
+ wire [3:0] int_pipeenrevparallellpbkfromtx;
+ wire [0:0] int_pll_reset_delayed;
+ wire [0:0] int_rateswitch;
+ wire [11:0] int_rx_autospdxnconfigsel;
+ wire [11:0] int_rx_autospdxnspdchg;
+ wire [3:0] int_rx_coreclkout;
+ wire [0:0] int_rx_digitalreset_reg;
+ wire [11:0] int_rx_phfifioxnptrsreset;
+ wire [3:0] int_rx_phfifobyteserdisable;
+ wire [3:0] int_rx_phfifoptrsresetout;
+ wire [3:0] int_rx_phfifordenableout;
+ wire [3:0] int_rx_phfiforesetout;
+ wire [3:0] int_rx_phfifowrdisableout;
+ wire [11:0] int_rx_phfifoxnbytesel;
+ wire [11:0] int_rx_phfifoxnrdenable;
+ wire [11:0] int_rx_phfifoxnwrclk;
+ wire [11:0] int_rx_phfifoxnwrenable;
+ wire [3:0] int_rx_rateswitchout;
+ wire [0:0] int_rxcoreclk;
+ wire [3:0] int_rxpcs_cdrctrlearlyeios;
+ wire [0:0] int_rxphfifordenable;
+ wire [0:0] int_rxphfiforeset;
+ wire [0:0] int_rxphfifox4byteselout;
+ wire [0:0] int_rxphfifox4rdenableout;
+ wire [0:0] int_rxphfifox4wrclkout;
+ wire [0:0] int_rxphfifox4wrenableout;
+ wire [3:0] int_tx_coreclkout;
+ wire [0:0] int_tx_digitalreset_reg;
+ wire [11:0] int_tx_phfifioxnptrsreset;
+ wire [3:0] int_tx_phfiforddisableout;
+ wire [3:0] int_tx_phfiforesetout;
+ wire [3:0] int_tx_phfifowrenableout;
+ wire [11:0] int_tx_phfifoxnbytesel;
+ wire [11:0] int_tx_phfifoxnrdclk;
+ wire [11:0] int_tx_phfifoxnrdenable;
+ wire [11:0] int_tx_phfifoxnwrenable;
+ wire [0:0] int_txcoreclk;
+ wire [0:0] int_txphfiforddisable;
+ wire [0:0] int_txphfiforeset;
+ wire [0:0] int_txphfifowrenable;
+ wire [0:0] int_txphfifox4byteselout;
+ wire [0:0] int_txphfifox4rdclkout;
+ wire [0:0] int_txphfifox4rdenableout;
+ wire [0:0] int_txphfifox4wrenableout;
+ wire [0:0] nonusertocmu_out;
+ wire [0:0] pcie_sw_wire;
+ wire [3:0] pipedatavalid_out;
+ wire [3:0] pipeelecidle_out;
+ wire [9:0] pll0_clkin;
+ wire [299:0] pll0_dprioin;
+ wire [299:0] pll0_dprioout;
+ wire [3:0] pll0_out;
+ wire [7:0] pll_ch_dataout_wire;
+ wire [1199:0] pll_ch_dprioout;
+ wire [1799:0] pll_cmuplldprioout;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [0:0] refclk_pma;
+ wire [5:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [3:0] rx_coreclk_in;
+ wire [39:0] rx_cruclk_in;
+ wire [15:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [11:0] rx_elecidleinfersel;
+ wire [3:0] rx_enapatternalign;
+ wire [3:0] rx_freqlocked_wire;
+ wire [3:0] rx_locktodata;
+ wire [3:0] rx_locktodata_wire;
+ wire [3:0] rx_locktorefclk_wire;
+ wire [63:0] rx_out_wire;
+ wire [7:0] rx_pcs_rxfound_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [3:0] rx_phfifordenable;
+ wire [3:0] rx_phfiforeset;
+ wire [3:0] rx_phfifowrdisable;
+ wire [3:0] rx_pipestatetransdoneout;
+ wire [3:0] rx_pldcruclk_in;
+ wire [15:0] rx_pll_clkout;
+ wire [3:0] rx_pll_pfdrefclkout_wire;
+ wire [3:0] rx_plllocked_wire;
+ wire [67:0] rx_pma_analogtestbus;
+ wire [3:0] rx_pma_clockout;
+ wire [3:0] rx_pma_dataout;
+ wire [3:0] rx_pma_locktorefout;
+ wire [79:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [1799:0] rx_pmadprioout;
+ wire [3:0] rx_powerdown;
+ wire [5:0] rx_powerdown_in;
+ wire [3:0] rx_prbscidenable;
+ wire [79:0] rx_revparallelfdbkdata;
+ wire [3:0] rx_rmfiforeset;
+ wire [5:0] rx_rxcruresetout;
+ wire [3:0] rx_signaldetect_wire;
+ wire [0:0] rxphfifowrdisable;
+ wire [1799:0] rxpll_dprioin;
+ wire [5:0] tx_analogreset_out;
+ wire [3:0] tx_clkout_int_wire;
+ wire [3:0] tx_coreclk_in;
+ wire [63:0] tx_datain_wire;
+ wire [79:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [7:0] tx_forcedisp_wire;
+ wire [3:0] tx_invpolarity;
+ wire [3:0] tx_localrefclk;
+ wire [3:0] tx_pcs_forceelecidleout;
+ wire [3:0] tx_phfiforeset;
+ wire [7:0] tx_pipepowerdownout;
+ wire [15:0] tx_pipepowerstateout;
+ wire [3:0] tx_pipeswing;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [1799:0] tx_pmadprioout;
+ wire [3:0] tx_revparallellpbken;
+ wire [3:0] tx_rxdetectvalidout;
+ wire [3:0] tx_rxfoundout;
+ wire [599:0] tx_txdprioout;
+ wire [3:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[0:0])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[0:0] == 1'b0) pcie_sw_sel_delay_blk0c[0:0] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[0:0] <= wire_pcie_sw_sel_delay_blk0c_d[0:0];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[1:1])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[1:1] == 1'b0) pcie_sw_sel_delay_blk0c[1:1] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[1:1] <= wire_pcie_sw_sel_delay_blk0c_d[1:1];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[2:2])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[2:2] == 1'b0) pcie_sw_sel_delay_blk0c[2:2] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[2:2] <= wire_pcie_sw_sel_delay_blk0c_d[2:2];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[3:3])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[3:3] == 1'b0) pcie_sw_sel_delay_blk0c[3:3] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[3:3] <= wire_pcie_sw_sel_delay_blk0c_d[3:3];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[4:4])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[4:4] == 1'b0) pcie_sw_sel_delay_blk0c[4:4] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[4:4] <= wire_pcie_sw_sel_delay_blk0c_d[4:4];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[5:5])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[5:5] == 1'b0) pcie_sw_sel_delay_blk0c[5:5] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[5:5] <= wire_pcie_sw_sel_delay_blk0c_d[5:5];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[6:6])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[6:6] == 1'b0) pcie_sw_sel_delay_blk0c[6:6] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[6:6] <= wire_pcie_sw_sel_delay_blk0c_d[6:6];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[7:7])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[7:7] == 1'b0) pcie_sw_sel_delay_blk0c[7:7] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[7:7] <= wire_pcie_sw_sel_delay_blk0c_d[7:7];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[8:8])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[8:8] == 1'b0) pcie_sw_sel_delay_blk0c[8:8] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[8:8] <= wire_pcie_sw_sel_delay_blk0c_d[8:8];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[9:9])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[9:9] == 1'b0) pcie_sw_sel_delay_blk0c[9:9] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[9:9] <= wire_pcie_sw_sel_delay_blk0c_d[9:9];
+ assign
+ wire_pcie_sw_sel_delay_blk0c_d = {pcie_sw_sel_delay_blk0c[8:0], pllreset_delay_blk0c[9]};
+ assign
+ wire_pcie_sw_sel_delay_blk0c_prn = {10{(~ pll_powerdown[0])}};
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[0:0])
+ if (wire_pllreset_delay_blk0c_prn[0:0] == 1'b0) pllreset_delay_blk0c[0:0] <= 1'b1;
+ else pllreset_delay_blk0c[0:0] <= wire_pllreset_delay_blk0c_d[0:0];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[1:1])
+ if (wire_pllreset_delay_blk0c_prn[1:1] == 1'b0) pllreset_delay_blk0c[1:1] <= 1'b1;
+ else pllreset_delay_blk0c[1:1] <= wire_pllreset_delay_blk0c_d[1:1];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[2:2])
+ if (wire_pllreset_delay_blk0c_prn[2:2] == 1'b0) pllreset_delay_blk0c[2:2] <= 1'b1;
+ else pllreset_delay_blk0c[2:2] <= wire_pllreset_delay_blk0c_d[2:2];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[3:3])
+ if (wire_pllreset_delay_blk0c_prn[3:3] == 1'b0) pllreset_delay_blk0c[3:3] <= 1'b1;
+ else pllreset_delay_blk0c[3:3] <= wire_pllreset_delay_blk0c_d[3:3];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[4:4])
+ if (wire_pllreset_delay_blk0c_prn[4:4] == 1'b0) pllreset_delay_blk0c[4:4] <= 1'b1;
+ else pllreset_delay_blk0c[4:4] <= wire_pllreset_delay_blk0c_d[4:4];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[5:5])
+ if (wire_pllreset_delay_blk0c_prn[5:5] == 1'b0) pllreset_delay_blk0c[5:5] <= 1'b1;
+ else pllreset_delay_blk0c[5:5] <= wire_pllreset_delay_blk0c_d[5:5];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[6:6])
+ if (wire_pllreset_delay_blk0c_prn[6:6] == 1'b0) pllreset_delay_blk0c[6:6] <= 1'b1;
+ else pllreset_delay_blk0c[6:6] <= wire_pllreset_delay_blk0c_d[6:6];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[7:7])
+ if (wire_pllreset_delay_blk0c_prn[7:7] == 1'b0) pllreset_delay_blk0c[7:7] <= 1'b1;
+ else pllreset_delay_blk0c[7:7] <= wire_pllreset_delay_blk0c_d[7:7];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[8:8])
+ if (wire_pllreset_delay_blk0c_prn[8:8] == 1'b0) pllreset_delay_blk0c[8:8] <= 1'b1;
+ else pllreset_delay_blk0c[8:8] <= wire_pllreset_delay_blk0c_d[8:8];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[9:9])
+ if (wire_pllreset_delay_blk0c_prn[9:9] == 1'b0) pllreset_delay_blk0c[9:9] <= 1'b1;
+ else pllreset_delay_blk0c[9:9] <= wire_pllreset_delay_blk0c_d[9:9];
+ assign
+ wire_pllreset_delay_blk0c_d = {pllreset_delay_blk0c[8:0], (pll_powerdown[0] | (~ pll_locked_out[0]))};
+ assign
+ wire_pllreset_delay_blk0c_prn = {10{(~ pll_powerdown[0])}};
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
+ rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
+ rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
+ rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
+ assign
+ wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
+ tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
+ tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
+ tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
+ assign
+ wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[3:0]),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[499:400]),
+ .dprioout(wire_central_clk_div0_dprioout),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(int_pcie_sw[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.effective_data_rate = "5000 Mbps",
+ central_clk_div0.enable_dynamic_divider = "true",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_rate_switch_base_clock = "true",
+ central_clk_div0.select_local_rate_switch_done = "true",
+ central_clk_div0.select_local_refclk = "true",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "true",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(wire_cent_unit0_autospdx4configsel),
+ .autospdx4rateswitchout(wire_cent_unit0_autospdx4rateswitchout),
+ .autospdx4spdchg(wire_cent_unit0_autospdx4spdchg),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(wire_cent_unit0_digitaltestout),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(wire_cent_unit0_phfifiox4ptrsreset),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitch(int_rateswitch[0]),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.central_test_bus_select = 0,
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "true",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 249950,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "x4",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "x4",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "3.0V",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[0]),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({rx_cruclk_in[9:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .rateswitch(int_pcie_sw[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.bandwidth_type = "Auto",
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll0.enable_dynamic_divider = "true",
+ rx_cdr_pll0.fast_lock_control = "false",
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 1,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_post_scale = 1,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[599:300]),
+ .dprioout(wire_rx_cdr_pll1_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[1]),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({rx_cruclk_in[19:10]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .rateswitch(int_pcie_sw[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.bandwidth_type = "Auto",
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.dprio_config_mode = 6'h00,
+ rx_cdr_pll1.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll1.enable_dynamic_divider = "true",
+ rx_cdr_pll1.fast_lock_control = "false",
+ rx_cdr_pll1.inclk0_input_period = 10000,
+ rx_cdr_pll1.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll1.m = 25,
+ rx_cdr_pll1.n = 1,
+ rx_cdr_pll1.pfd_clk_select = 0,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_post_scale = 1,
+ rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[899:600]),
+ .dprioout(wire_rx_cdr_pll2_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[2]),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({rx_cruclk_in[29:20]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .rateswitch(int_pcie_sw[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.bandwidth_type = "Auto",
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.dprio_config_mode = 6'h00,
+ rx_cdr_pll2.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll2.enable_dynamic_divider = "true",
+ rx_cdr_pll2.fast_lock_control = "false",
+ rx_cdr_pll2.inclk0_input_period = 10000,
+ rx_cdr_pll2.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll2.m = 25,
+ rx_cdr_pll2.n = 1,
+ rx_cdr_pll2.pfd_clk_select = 0,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_post_scale = 1,
+ rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[1199:900]),
+ .dprioout(wire_rx_cdr_pll3_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[3]),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({rx_cruclk_in[39:30]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .rateswitch(int_pcie_sw[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.bandwidth_type = "Auto",
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.dprio_config_mode = 6'h00,
+ rx_cdr_pll3.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll3.enable_dynamic_divider = "true",
+ rx_cdr_pll3.fast_lock_control = "false",
+ rx_cdr_pll3.inclk0_input_period = 10000,
+ rx_cdr_pll3.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll3.m = 25,
+ rx_cdr_pll3.n = 1,
+ rx_cdr_pll3.pfd_clk_select = 0,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_post_scale = 1,
+ rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(pll0_dprioin[299:0]),
+ .dprioout(wire_tx_pll0_dprioout),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.bandwidth_type = "High",
+ tx_pll0.channel_num = 4,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.input_clock_frequency = "100.0 MHz",
+ tx_pll0.logical_tx_pll_number = 0,
+ tx_pll0.m = 25,
+ tx_pll0.n = 1,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pfd_fb_select = "internal",
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_post_scale = 1,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs0_autospdrateswitchout),
+ .autospdspdchgout(),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[2:0]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[2:0]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(wire_receive_pcs0_signaldetect),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_cid_mode_enable = "true",
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x4",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "true",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 249950,
+ receive_pcs0.protocol_hint = "pcie2",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_pipe_enable = "true",
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 32,
+ receive_pcs0.rxstatus_error_report_mode = 1,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.test_bus_sel = 10,
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs1_autospdrateswitchout),
+ .autospdspdchgout(),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[5:3]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[5:3]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(wire_receive_pcs1_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetect(wire_receive_pcs1_signaldetect),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.auto_spd_self_switch_enable = "false",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_cid_mode_enable = "true",
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x4",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 16,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h01,
+ receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "true",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 249950,
+ receive_pcs1.protocol_hint = "pcie2",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_pipe_enable = "true",
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rx_phfifo_wait_cnt = 32,
+ receive_pcs1.rxstatus_error_report_mode = 1,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.test_bus_sel = 10,
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "true",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs2_autospdrateswitchout),
+ .autospdspdchgout(),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[8:6]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[8:6]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs2_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(wire_receive_pcs2_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[8:6]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs2_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs2_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[2]),
+ .pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[5:4]),
+ .pipepowerstate(tx_pipepowerstateout[11:8]),
+ .pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs2_pipestatus),
+ .powerdn(powerdn[5:4]),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[2]),
+ .rxfound(rx_pcs_rxfound_wire[5:4]),
+ .signaldetect(wire_receive_pcs2_signaldetect),
+ .signaldetected(rx_signaldetect_wire[2]),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "false",
+ receive_pcs2.allow_pipe_polarity_inversion = "true",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 14,
+ receive_pcs2.auto_spd_self_switch_enable = "false",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs2.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_cid_mode_enable = "true",
+ receive_pcs2.cdrctrl_enable = "true",
+ receive_pcs2.cdrctrl_rxvalid_mask = "true",
+ receive_pcs2.channel_bonding = "x4",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 16,
+ receive_pcs2.clk1_mux_select = "recovered clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "false",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "pipe",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs2.deskew_pattern = "0",
+ receive_pcs2.disable_auto_idle_insertion = "false",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h01,
+ receive_pcs2.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 16,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 17,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "true",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 249950,
+ receive_pcs2.protocol_hint = "pcie2",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "false",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs2.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs2.rate_match_pattern_size = 20,
+ receive_pcs2.rate_match_pipe_enable = "true",
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "true",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rx_phfifo_wait_cnt = 32,
+ receive_pcs2.rxstatus_error_report_mode = 1,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.test_bus_sel = 10,
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "false",
+ receive_pcs2.use_double_data_mode = "true",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs3_autospdrateswitchout),
+ .autospdspdchgout(),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[11:9]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[11:9]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs3_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(wire_receive_pcs3_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[11:9]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs3_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs3_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[3]),
+ .pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[7:6]),
+ .pipepowerstate(tx_pipepowerstateout[15:12]),
+ .pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs3_pipestatus),
+ .powerdn(powerdn[7:6]),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[3]),
+ .rxfound(rx_pcs_rxfound_wire[7:6]),
+ .signaldetect(wire_receive_pcs3_signaldetect),
+ .signaldetected(rx_signaldetect_wire[3]),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "false",
+ receive_pcs3.allow_pipe_polarity_inversion = "true",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 14,
+ receive_pcs3.auto_spd_self_switch_enable = "false",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs3.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_cid_mode_enable = "true",
+ receive_pcs3.cdrctrl_enable = "true",
+ receive_pcs3.cdrctrl_rxvalid_mask = "true",
+ receive_pcs3.channel_bonding = "x4",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 16,
+ receive_pcs3.clk1_mux_select = "recovered clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "false",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "pipe",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs3.deskew_pattern = "0",
+ receive_pcs3.disable_auto_idle_insertion = "false",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h01,
+ receive_pcs3.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 16,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 17,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "true",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 249950,
+ receive_pcs3.protocol_hint = "pcie2",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "false",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs3.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs3.rate_match_pattern_size = 20,
+ receive_pcs3.rate_match_pipe_enable = "true",
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "true",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rx_phfifo_wait_cnt = 32,
+ receive_pcs3.rxstatus_error_report_mode = 1,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.test_bus_sel = 10,
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "false",
+ receive_pcs3.use_double_data_mode = "true",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.adaptive_equalization_mode = "none",
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "true",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.eyemon_bandwidth = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "pcie2",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis = 4,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma0.signal_detect_loss_threshold = 3,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma1_analogtestbus),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(wire_receive_pma1_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.adaptive_equalization_mode = "none",
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h01,
+ receive_pma1.enable_ltd = "false",
+ receive_pma1.enable_ltr = "true",
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eqa_ctrl = 0,
+ receive_pma1.eqb_ctrl = 0,
+ receive_pma1.eqc_ctrl = 0,
+ receive_pma1.eqd_ctrl = 0,
+ receive_pma1.eqv_ctrl = 0,
+ receive_pma1.eyemon_bandwidth = 0,
+ receive_pma1.force_signal_detect = "true",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 1,
+ receive_pma1.ppmselect = 32,
+ receive_pma1.protocol_hint = "pcie2",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis = 4,
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma1.signal_detect_loss_threshold = 3,
+ receive_pma1.termination = "OCT 100 Ohms",
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_external_termination = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma2_analogtestbus),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(wire_receive_pma2_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma2_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.adaptive_equalization_mode = "none",
+ receive_pma2.allow_serial_loopback = "false",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = "0.82V",
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h01,
+ receive_pma2.enable_ltd = "false",
+ receive_pma2.enable_ltr = "true",
+ receive_pma2.eq_dc_gain = 3,
+ receive_pma2.eqa_ctrl = 0,
+ receive_pma2.eqb_ctrl = 0,
+ receive_pma2.eqc_ctrl = 0,
+ receive_pma2.eqd_ctrl = 0,
+ receive_pma2.eqv_ctrl = 0,
+ receive_pma2.eyemon_bandwidth = 0,
+ receive_pma2.force_signal_detect = "true",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 1,
+ receive_pma2.ppmselect = 32,
+ receive_pma2.protocol_hint = "pcie2",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis = 4,
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma2.signal_detect_loss_threshold = 3,
+ receive_pma2.termination = "OCT 100 Ohms",
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_external_termination = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma3_analogtestbus),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_receive_pma3_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma3_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.adaptive_equalization_mode = "none",
+ receive_pma3.allow_serial_loopback = "false",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = "0.82V",
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h01,
+ receive_pma3.enable_ltd = "false",
+ receive_pma3.enable_ltr = "true",
+ receive_pma3.eq_dc_gain = 3,
+ receive_pma3.eqa_ctrl = 0,
+ receive_pma3.eqb_ctrl = 0,
+ receive_pma3.eqc_ctrl = 0,
+ receive_pma3.eqd_ctrl = 0,
+ receive_pma3.eqv_ctrl = 0,
+ receive_pma3.eyemon_bandwidth = 0,
+ receive_pma3.force_signal_detect = "true",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 1,
+ receive_pma3.ppmselect = 32,
+ receive_pma3.protocol_hint = "pcie2",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis = 4,
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma3.signal_detect_loss_threshold = 3,
+ receive_pma3.termination = "OCT 100 Ohms",
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_external_termination = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
+ .datain({{24{1'b0}}, tx_datain_wire[15:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[0]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "x4",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.pipe_voltage_swing_control = "false",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie2",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
+ .datain({{24{1'b0}}, tx_datain_wire[31:16]}),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[1]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(wire_transmit_pcs1_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .forceelecidleout(wire_transmit_pcs1_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[1]),
+ .pipetxdeemph(tx_pipedeemph[1]),
+ .pipetxmargin(tx_pipemargin[5:3]),
+ .pipetxswing(tx_pipeswing[1]),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.auto_spd_self_switch_enable = "false",
+ transmit_pcs1.bitslip_enable = "false",
+ transmit_pcs1.channel_bonding = "x4",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 16,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h01,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.pipe_voltage_swing_control = "false",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie2",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "true",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[5:4]}),
+ .datain({{24{1'b0}}, tx_datain_wire[47:32]}),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(tx_detectrxloop[2]),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[2]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(wire_transmit_pcs2_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[8:6]),
+ .enrevparallellpbk(tx_revparallellpbken[2]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[5:4]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .forceelecidleout(wire_transmit_pcs2_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs2_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[2]),
+ .pipetxdeemph(tx_pipedeemph[2]),
+ .pipetxmargin(tx_pipemargin[8:6]),
+ .pipetxswing(tx_pipeswing[2]),
+ .powerdn(powerdn[5:4]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[59:40]),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "false",
+ transmit_pcs2.auto_spd_self_switch_enable = "false",
+ transmit_pcs2.bitslip_enable = "false",
+ transmit_pcs2.channel_bonding = "x4",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 16,
+ transmit_pcs2.core_clock_0ppm = "false",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "pipe",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "new",
+ transmit_pcs2.dprio_config_mode = 6'h01,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "true",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.pipe_voltage_swing_control = "false",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "pcie2",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "true",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[7:6]}),
+ .datain({{24{1'b0}}, tx_datain_wire[63:48]}),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(tx_detectrxloop[3]),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[3]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(wire_transmit_pcs3_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[11:9]),
+ .enrevparallellpbk(tx_revparallellpbken[3]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[7:6]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .forceelecidleout(wire_transmit_pcs3_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs3_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[3]),
+ .pipetxdeemph(tx_pipedeemph[3]),
+ .pipetxmargin(tx_pipemargin[11:9]),
+ .pipetxswing(tx_pipeswing[3]),
+ .powerdn(powerdn[7:6]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[79:60]),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "false",
+ transmit_pcs3.auto_spd_self_switch_enable = "false",
+ transmit_pcs3.bitslip_enable = "false",
+ transmit_pcs3.channel_bonding = "x4",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 16,
+ transmit_pcs3.core_clock_0ppm = "false",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "pipe",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "new",
+ transmit_pcs3.dprio_config_mode = 6'h01,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "true",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.pipe_voltage_swing_control = "false",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "pcie2",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "true",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "auto",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.logical_protocol_hint_0 = "pcie2",
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.physical_clkin1_mapping = "x4",
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_1_a = 28,
+ transmit_pma0.preemp_tap_1_b = 22,
+ transmit_pma0.preemp_tap_1_c = 7,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie2",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 3,
+ transmit_pma0.vod_selection_a = 6,
+ transmit_pma0.vod_selection_c = 1,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(wire_transmit_pma1_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "auto",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h01,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.logical_protocol_hint_0 = "pcie2",
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.physical_clkin1_mapping = "x4",
+ transmit_pma1.preemp_pretap = 0,
+ transmit_pma1.preemp_pretap_inv = "false",
+ transmit_pma1.preemp_tap_1 = 0,
+ transmit_pma1.preemp_tap_1_a = 28,
+ transmit_pma1.preemp_tap_1_b = 22,
+ transmit_pma1.preemp_tap_1_c = 7,
+ transmit_pma1.preemp_tap_2 = 0,
+ transmit_pma1.preemp_tap_2_inv = "false",
+ transmit_pma1.protocol_hint = "pcie2",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "off",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_external_termination = "false",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = 3,
+ transmit_pma1.vod_selection_a = 6,
+ transmit_pma1.vod_selection_c = 1,
+ transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(wire_transmit_pma2_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[2]),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma2_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[2])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "auto",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h01,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.logical_protocol_hint_0 = "pcie2",
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.physical_clkin1_mapping = "x4",
+ transmit_pma2.preemp_pretap = 0,
+ transmit_pma2.preemp_pretap_inv = "false",
+ transmit_pma2.preemp_tap_1 = 0,
+ transmit_pma2.preemp_tap_1_a = 28,
+ transmit_pma2.preemp_tap_1_b = 22,
+ transmit_pma2.preemp_tap_1_c = 7,
+ transmit_pma2.preemp_tap_2 = 0,
+ transmit_pma2.preemp_tap_2_inv = "false",
+ transmit_pma2.protocol_hint = "pcie2",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "off",
+ transmit_pma2.termination = "OCT 100 Ohms",
+ transmit_pma2.use_external_termination = "false",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = 3,
+ transmit_pma2.vod_selection_a = 6,
+ transmit_pma2.vod_selection_c = 1,
+ transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_transmit_pma3_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[3]),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma3_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[3])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "auto",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h01,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.logical_protocol_hint_0 = "pcie2",
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.physical_clkin1_mapping = "x4",
+ transmit_pma3.preemp_pretap = 0,
+ transmit_pma3.preemp_pretap_inv = "false",
+ transmit_pma3.preemp_tap_1 = 0,
+ transmit_pma3.preemp_tap_1_a = 28,
+ transmit_pma3.preemp_tap_1_b = 22,
+ transmit_pma3.preemp_tap_1_c = 7,
+ transmit_pma3.preemp_tap_2 = 0,
+ transmit_pma3.preemp_tap_2_inv = "false",
+ transmit_pma3.protocol_hint = "pcie2",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "off",
+ transmit_pma3.termination = "OCT 100 Ohms",
+ transmit_pma3.use_external_termination = "false",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = 3,
+ transmit_pma3.vod_selection_a = 6,
+ transmit_pma3.vod_selection_c = 1,
+ transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b0,
+ cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {rx_pcsdprioout[1599:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
+ cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]},
+ cent_unit_tx_dprioin = {{600{1'b0}}, tx_txdprioout[599:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]},
+ clk_div_clk0in = {pll0_out[3:0]},
+ clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
+ cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
+ cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
+ cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div0_coreclkout},
+ fixedclk = 1'b0,
+ fixedclk_to_cmu = {6{reconfig_clk}},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs3_grayelecidleinferselout, wire_transmit_pcs2_grayelecidleinferselout, wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
+ int_autospdx4configsel = {wire_cent_unit0_autospdx4configsel},
+ int_autospdx4spdchg = {wire_cent_unit0_autospdx4spdchg},
+ int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
+ int_pcie_sw = {((int_pcie_sw_select[0] & int_pll_reset_delayed[0]) | ((~ int_pcie_sw_select[0]) & pcie_sw_wire[0]))},
+ int_pcie_sw_select = {pcie_sw_sel_delay_blk0c[9]},
+ int_phfifiox4ptrsreset = {wire_cent_unit0_phfifiox4ptrsreset},
+ int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs3_pipeenrevparallellpbkout, wire_transmit_pcs2_pipeenrevparallellpbkout, wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
+ int_pll_reset_delayed = {pllreset_delay_blk0c[9]},
+ int_rateswitch = {int_rx_rateswitchout[0]},
+ int_rx_autospdxnconfigsel = {int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}},
+ int_rx_autospdxnspdchg = {int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}},
+ int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
+ int_rx_phfifioxnptrsreset = {int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
+ int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
+ int_rx_rateswitchout = {wire_receive_pcs3_rateswitchout, wire_receive_pcs2_rateswitchout, wire_receive_pcs1_rateswitchout, wire_receive_pcs0_rateswitchout},
+ int_rxcoreclk = {int_rx_coreclkout[0]},
+ int_rxpcs_cdrctrlearlyeios = {wire_receive_pcs3_cdrctrlearlyeios, wire_receive_pcs2_cdrctrlearlyeios, wire_receive_pcs1_cdrctrlearlyeios, wire_receive_pcs0_cdrctrlearlyeios},
+ int_rxphfifordenable = {int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
+ int_tx_phfifioxnptrsreset = {int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
+ int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
+ int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
+ int_txcoreclk = {int_tx_coreclkout[0]},
+ int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pcie_sw_wire = {wire_cent_unit0_digitaltestout[2]},
+ pipedatavalid = {pipedatavalid_out[3:0]},
+ pipedatavalid_out = {wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[3:0]},
+ pipeelecidle_out = {wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
+ pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
+ pll0_dprioout = {wire_tx_pll0_dprioout},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], pll_ch_dprioout[1199:0]},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ refclk_pma = {wire_central_clk_div0_refclkout},
+ rx_analogreset_in = {{2{1'b0}}, {4{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_coreclk_in = {4{coreclkout_wire[0]}},
+ rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[63:0]},
+ rx_deserclock_in = {rx_pll_clkout[15:0]},
+ rx_digitalreset_in = {4{int_rx_digitalreset_reg[0]}},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_elecidleinfersel = {12{1'b0}},
+ rx_enapatternalign = {4{1'b0}},
+ rx_freqlocked = {(rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = {4{1'b0}},
+ rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
+ rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[1599:0]},
+ rx_pcsdprioout = {wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = {4{1'b1}},
+ rx_phfiforeset = {4{1'b0}},
+ rx_phfifowrdisable = {4{1'b0}},
+ rx_pipestatetransdoneout = {wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[3:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {(rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_analogtestbus = {{51{1'b0}}, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
+ rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
+ rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
+ rx_powerdown = {4{1'b0}},
+ rx_powerdown_in = {{2{1'b0}}, rx_powerdown[3:0]},
+ rx_prbscidenable = {4{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {4{1'b0}},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
+ rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
+ rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_coreclk_in = {4{coreclkout_wire[0]}},
+ tx_datain_wire = {tx_datain[63:0]},
+ tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {4{int_tx_digitalreset_reg[0]}},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_dprioin_wire = {{600{1'b0}}, cent_unit_txdprioout[599:0]},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[3], 1'b0, tx_forcedispcompliance[2], 1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = {4{1'b0}},
+ tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = {4{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = {4{1'b0}},
+ tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
+ tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = {4{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
+ txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+endmodule //altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_4sgx_x4d_gen2_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ rateswitch,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ tx_pipedeemph,
+ tx_pipemargin,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout)/* synthesis synthesis_clearbox = 2 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [3:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [7:0] powerdn;
+ input [0:0] rateswitch;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [3:0] rx_cruclk;
+ input [3:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [3:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_forcedispcompliance;
+ input [3:0] tx_forceelecidle;
+ input [3:0] tx_pipedeemph;
+ input [11:0] tx_pipemargin;
+ output [0:0] coreclkout;
+ output [3:0] pipedatavalid;
+ output [3:0] pipeelecidle;
+ output [3:0] pipephydonestatus;
+ output [11:0] pipestatus;
+ output [0:0] pll_locked;
+ output [16:0] reconfig_fromgxb;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [3:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ output [3:0] tx_dataout;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [3:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+
+
+ wire [7:0] sub_wire0;
+ wire [3:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [16:0] sub_wire3;
+ wire [3:0] sub_wire4;
+ wire [11:0] sub_wire5;
+ wire [3:0] sub_wire6;
+ wire [7:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [63:0] sub_wire9;
+ wire [3:0] sub_wire10;
+ wire [3:0] sub_wire11;
+ wire [7:0] sub_wire12;
+ wire [3:0] sub_wire13;
+ wire [7:0] rx_patterndetect = sub_wire0[7:0];
+ wire [3:0] pipephydonestatus = sub_wire1[3:0];
+ wire [0:0] pll_locked = sub_wire2[0:0];
+ wire [16:0] reconfig_fromgxb = sub_wire3[16:0];
+ wire [3:0] rx_freqlocked = sub_wire4[3:0];
+ wire [11:0] pipestatus = sub_wire5[11:0];
+ wire [3:0] rx_pll_locked = sub_wire6[3:0];
+ wire [7:0] rx_syncstatus = sub_wire7[7:0];
+ wire [0:0] coreclkout = sub_wire8[0:0];
+ wire [63:0] rx_dataout = sub_wire9[63:0];
+ wire [3:0] pipeelecidle = sub_wire10[3:0];
+ wire [3:0] tx_dataout = sub_wire11[3:0];
+ wire [7:0] rx_ctrldetect = sub_wire12[7:0];
+ wire [3:0] pipedatavalid = sub_wire13[3:0];
+
+ altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea_component (
+ .reconfig_togxb (reconfig_togxb),
+ .cal_blk_clk (cal_blk_clk),
+ .tx_forceelecidle (tx_forceelecidle),
+ .rx_datain (rx_datain),
+ .rx_digitalreset (rx_digitalreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .tx_datain (tx_datain),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_pipedeemph (tx_pipedeemph),
+ .gxb_powerdown (gxb_powerdown),
+ .rx_cruclk (rx_cruclk),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .rateswitch (rateswitch),
+ .reconfig_clk (reconfig_clk),
+ .rx_analogreset (rx_analogreset),
+ .powerdn (powerdn),
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_pipemargin (tx_pipemargin),
+ .pll_inclk (pll_inclk),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .pipephydonestatus (sub_wire1),
+ .pll_locked (sub_wire2),
+ .reconfig_fromgxb (sub_wire3),
+ .rx_freqlocked (sub_wire4),
+ .pipestatus (sub_wire5),
+ .rx_pll_locked (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .coreclkout (sub_wire8),
+ .rx_dataout (sub_wire9),
+ .pipeelecidle (sub_wire10),
+ .tx_dataout (sub_wire11),
+ .rx_ctrldetect (sub_wire12),
+ .pipedatavalid (sub_wire13))/* synthesis synthesis_clearbox=2
+ clearbox_macroname = alt4gxb
+ clearbox_defparam = "effective_data_rate=5000 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gxb_analog_power=3.0v;gx_channel_type=AUTO;input_clock_frequency=100.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=none;lpm_type=alt4gxb;number_of_channels=4;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;protocol=pcie2;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=x4;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_bandwidth_type=Auto;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=5000;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;
+ rx_use_clkout=false;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=true;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_bonding=x4;tx_channel_width=16;tx_clkout_width=4;tx_common_mode=0.65v;tx_data_rate=5000;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=off;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=true;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=3;coreclkout_control_width=1;elec_idle_infer_enable=false;enable_0ppm=false;gxb_powerdown_width=1;number_of_quads=1;rateswitch_control_width=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_cru_m_divider=25;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=1;rx_dwidth_factor=2;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=2;tx_pll_clock_post_divider=1;tx_pll_m_divider=25;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=1;tx_use_external_termination=false;" */;
+ defparam
+ altpcie_serdes_4sgx_x4d_gen2_08p_alt4gxb_a0ea_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "5000.0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "5000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "5000"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 2-x4"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "5000 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "3.0v"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie2"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "5000"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "5000"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
+// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: rateswitch_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
+// Retrieval info: USED_PORT: rateswitch 0 0 1 0 INPUT NODEFVAL "rateswitch[0..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
+// Retrieval info: USED_PORT: tx_pipedeemph 0 0 4 0 INPUT NODEFVAL "tx_pipedeemph[3..0]"
+// Retrieval info: USED_PORT: tx_pipemargin 0 0 12 0 INPUT NODEFVAL "tx_pipemargin[11..0]"
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
+// Retrieval info: CONNECT: @rateswitch 0 0 1 0 rateswitch 0 0 1 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
+// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
+// Retrieval info: CONNECT: @tx_pipedeemph 0 0 4 0 tx_pipedeemph 0 0 4 0
+// Retrieval info: CONNECT: @tx_pipemargin 0 0 12 0 tx_pipemargin 0 0 12 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
+// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen2_08p_bb.v TRUE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..8e9632ed60f5f1aeb26877feb88fa9a84b4c5595
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v
@@ -0,0 +1,6736 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_4sgx_x8d_gen1_08p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.1 Internal Build 134 10/13/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="2.5v" gxb_powerdown_width=1 input_clock_frequency="100.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="none" number_of_channels=8 number_of_quads=2 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=34 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x8" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_n_divider=2 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x8" tx_channel_width=8 tx_clkout_width=8 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_n_divider=2 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=2 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
+//VERSION_BEGIN 10.1 cbx_alt4gxb 2010:10:13:21:30:47:SJ cbx_mgl 2010:10:13:21:32:12:SJ cbx_tgx 2010:10:13:21:30:47:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = reg 6 stratixiv_hssi_calibration_block 2 stratixiv_hssi_clock_divider 2 stratixiv_hssi_cmu 2 stratixiv_hssi_pll 9 stratixiv_hssi_rx_pcs 8 stratixiv_hssi_rx_pma 8 stratixiv_hssi_tx_pcs 8 stratixiv_hssi_tx_pma 8
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module altpcie_serdes_4sgx_x8d_gen1_08p_alt4gxb_ko7a
+ (
+ cal_blk_clk,
+ coreclkout,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle) ;
+ input cal_blk_clk;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input [7:0] pipe8b10binvpolarity;
+ output [7:0] pipedatavalid;
+ output [7:0] pipeelecidle;
+ output [7:0] pipephydonestatus;
+ output [23:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [15:0] powerdn;
+ input reconfig_clk;
+ output [33:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [7:0] rx_cruclk;
+ output [7:0] rx_ctrldetect;
+ input [7:0] rx_datain;
+ output [63:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [7:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [7:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ output [7:0] tx_dataout;
+ input [7:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [7:0] tx_forcedispcompliance;
+ input [7:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [7:0] pipe8b10binvpolarity;
+ tri0 pll_inclk;
+ tri0 [15:0] powerdn;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [7:0] rx_cruclk;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [7:0] tx_ctrlenable;
+ tri0 [63:0] tx_datain;
+ tri0 [7:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [7:0] tx_forcedispcompliance;
+ tri0 [7:0] tx_forceelecidle;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire [2:0] wire_rx_digitalreset_reg0c_d;
+ reg [2:0] rx_digitalreset_reg0c;
+ wire [2:0] wire_rx_digitalreset_reg0c_clk;
+ wire [2:0] wire_tx_digitalreset_reg0c_d;
+ reg [2:0] tx_digitalreset_reg0c;
+ wire [2:0] wire_tx_digitalreset_reg0c_clk;
+ wire wire_cal_blk0_nonusertocmu;
+ wire wire_cal_blk1_nonusertocmu;
+ wire [1:0] wire_central_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div0_analogrefclkout;
+ wire wire_central_clk_div0_analogrefclkpulse;
+ wire wire_central_clk_div0_coreclkout;
+ wire [99:0] wire_central_clk_div0_dprioout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_refclkout;
+ wire [1:0] wire_central_clk_div1_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div1_analogrefclkout;
+ wire wire_central_clk_div1_analogrefclkpulse;
+ wire wire_central_clk_div1_coreclkout;
+ wire [99:0] wire_central_clk_div1_dprioout;
+ wire wire_central_clk_div1_rateswitchdone;
+ wire wire_central_clk_div1_refclkout;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire [1:0] wire_cent_unit1_clkdivpowerdn;
+ wire [599:0] wire_cent_unit1_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit1_cmuplldprioout;
+ wire wire_cent_unit1_dpriodisableout;
+ wire wire_cent_unit1_dprioout;
+ wire [1:0] wire_cent_unit1_pllpowerdn;
+ wire [1:0] wire_cent_unit1_pllresetout;
+ wire wire_cent_unit1_quadresetout;
+ wire [5:0] wire_cent_unit1_rxanalogresetout;
+ wire [5:0] wire_cent_unit1_rxcrupowerdown;
+ wire [5:0] wire_cent_unit1_rxcruresetout;
+ wire [3:0] wire_cent_unit1_rxdigitalresetout;
+ wire [5:0] wire_cent_unit1_rxibpowerdown;
+ wire [1599:0] wire_cent_unit1_rxpcsdprioout;
+ wire wire_cent_unit1_rxphfifox4byteselout;
+ wire wire_cent_unit1_rxphfifox4rdenableout;
+ wire wire_cent_unit1_rxphfifox4wrclkout;
+ wire wire_cent_unit1_rxphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit1_rxpmadprioout;
+ wire [5:0] wire_cent_unit1_txanalogresetout;
+ wire [3:0] wire_cent_unit1_txctrlout;
+ wire [31:0] wire_cent_unit1_txdataout;
+ wire [5:0] wire_cent_unit1_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit1_txdigitalresetout;
+ wire [5:0] wire_cent_unit1_txobpowerdown;
+ wire [599:0] wire_cent_unit1_txpcsdprioout;
+ wire wire_cent_unit1_txphfifox4byteselout;
+ wire wire_cent_unit1_txphfifox4rdclkout;
+ wire wire_cent_unit1_txphfifox4rdenableout;
+ wire wire_cent_unit1_txphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit1_txpmadprioout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire [299:0] wire_rx_cdr_pll1_dprioout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire [299:0] wire_rx_cdr_pll2_dprioout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire [299:0] wire_rx_cdr_pll3_dprioout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll4_clk;
+ wire [1:0] wire_rx_cdr_pll4_dataout;
+ wire [299:0] wire_rx_cdr_pll4_dprioout;
+ wire wire_rx_cdr_pll4_freqlocked;
+ wire wire_rx_cdr_pll4_locked;
+ wire wire_rx_cdr_pll4_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll5_clk;
+ wire [1:0] wire_rx_cdr_pll5_dataout;
+ wire [299:0] wire_rx_cdr_pll5_dprioout;
+ wire wire_rx_cdr_pll5_freqlocked;
+ wire wire_rx_cdr_pll5_locked;
+ wire wire_rx_cdr_pll5_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll6_clk;
+ wire [1:0] wire_rx_cdr_pll6_dataout;
+ wire [299:0] wire_rx_cdr_pll6_dprioout;
+ wire wire_rx_cdr_pll6_freqlocked;
+ wire wire_rx_cdr_pll6_locked;
+ wire wire_rx_cdr_pll6_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll7_clk;
+ wire [1:0] wire_rx_cdr_pll7_dataout;
+ wire [299:0] wire_rx_cdr_pll7_dprioout;
+ wire wire_rx_cdr_pll7_freqlocked;
+ wire wire_rx_cdr_pll7_locked;
+ wire wire_rx_cdr_pll7_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire [299:0] wire_tx_pll0_dprioout;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_cdrctrlearlyeios;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire wire_receive_pcs0_iqpphfifobyteselout;
+ wire wire_receive_pcs0_iqpphfifordenableout;
+ wire wire_receive_pcs0_iqpphfifowrclkout;
+ wire wire_receive_pcs0_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire wire_receive_pcs0_rateswitchout;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire wire_receive_pcs0_signaldetect;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_cdrctrlearlyeios;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire [399:0] wire_receive_pcs1_dprioout;
+ wire wire_receive_pcs1_iqpphfifobyteselout;
+ wire wire_receive_pcs1_iqpphfifordenableout;
+ wire wire_receive_pcs1_iqpphfifowrclkout;
+ wire wire_receive_pcs1_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire wire_receive_pcs1_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire wire_receive_pcs1_rateswitchout;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire wire_receive_pcs1_signaldetect;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs2_cdrctrlearlyeios;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire [399:0] wire_receive_pcs2_dprioout;
+ wire wire_receive_pcs2_iqpphfifobyteselout;
+ wire wire_receive_pcs2_iqpphfifordenableout;
+ wire wire_receive_pcs2_iqpphfifowrclkout;
+ wire wire_receive_pcs2_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_pipedatavalid;
+ wire wire_receive_pcs2_pipeelecidle;
+ wire wire_receive_pcs2_pipephydonestatus;
+ wire wire_receive_pcs2_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs2_pipestatus;
+ wire wire_receive_pcs2_rateswitchout;
+ wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
+ wire wire_receive_pcs2_signaldetect;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs3_cdrctrlearlyeios;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire [399:0] wire_receive_pcs3_dprioout;
+ wire wire_receive_pcs3_iqpphfifobyteselout;
+ wire wire_receive_pcs3_iqpphfifordenableout;
+ wire wire_receive_pcs3_iqpphfifowrclkout;
+ wire wire_receive_pcs3_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_pipedatavalid;
+ wire wire_receive_pcs3_pipeelecidle;
+ wire wire_receive_pcs3_pipephydonestatus;
+ wire wire_receive_pcs3_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs3_pipestatus;
+ wire wire_receive_pcs3_rateswitchout;
+ wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
+ wire wire_receive_pcs3_signaldetect;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire wire_receive_pcs4_cdrctrlearlyeios;
+ wire wire_receive_pcs4_cdrctrllocktorefclkout;
+ wire wire_receive_pcs4_coreclkout;
+ wire [3:0] wire_receive_pcs4_ctrldetect;
+ wire [39:0] wire_receive_pcs4_dataout;
+ wire [399:0] wire_receive_pcs4_dprioout;
+ wire wire_receive_pcs4_iqpphfifobyteselout;
+ wire wire_receive_pcs4_iqpphfifordenableout;
+ wire wire_receive_pcs4_iqpphfifowrclkout;
+ wire wire_receive_pcs4_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs4_patterndetect;
+ wire wire_receive_pcs4_phfifobyteserdisableout;
+ wire wire_receive_pcs4_phfifoptrsresetout;
+ wire wire_receive_pcs4_phfifordenableout;
+ wire wire_receive_pcs4_phfiforesetout;
+ wire wire_receive_pcs4_phfifowrdisableout;
+ wire wire_receive_pcs4_pipedatavalid;
+ wire wire_receive_pcs4_pipeelecidle;
+ wire wire_receive_pcs4_pipephydonestatus;
+ wire wire_receive_pcs4_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs4_pipestatus;
+ wire wire_receive_pcs4_rateswitchout;
+ wire [19:0] wire_receive_pcs4_revparallelfdbkdata;
+ wire wire_receive_pcs4_signaldetect;
+ wire [3:0] wire_receive_pcs4_syncstatus;
+ wire wire_receive_pcs5_cdrctrlearlyeios;
+ wire wire_receive_pcs5_cdrctrllocktorefclkout;
+ wire wire_receive_pcs5_coreclkout;
+ wire [3:0] wire_receive_pcs5_ctrldetect;
+ wire [39:0] wire_receive_pcs5_dataout;
+ wire [399:0] wire_receive_pcs5_dprioout;
+ wire wire_receive_pcs5_iqpphfifobyteselout;
+ wire wire_receive_pcs5_iqpphfifordenableout;
+ wire wire_receive_pcs5_iqpphfifowrclkout;
+ wire wire_receive_pcs5_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs5_patterndetect;
+ wire wire_receive_pcs5_phfifobyteserdisableout;
+ wire wire_receive_pcs5_phfifoptrsresetout;
+ wire wire_receive_pcs5_phfifordenableout;
+ wire wire_receive_pcs5_phfiforesetout;
+ wire wire_receive_pcs5_phfifowrdisableout;
+ wire wire_receive_pcs5_pipedatavalid;
+ wire wire_receive_pcs5_pipeelecidle;
+ wire wire_receive_pcs5_pipephydonestatus;
+ wire wire_receive_pcs5_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs5_pipestatus;
+ wire wire_receive_pcs5_rateswitchout;
+ wire [19:0] wire_receive_pcs5_revparallelfdbkdata;
+ wire wire_receive_pcs5_signaldetect;
+ wire [3:0] wire_receive_pcs5_syncstatus;
+ wire wire_receive_pcs6_cdrctrlearlyeios;
+ wire wire_receive_pcs6_cdrctrllocktorefclkout;
+ wire wire_receive_pcs6_coreclkout;
+ wire [3:0] wire_receive_pcs6_ctrldetect;
+ wire [39:0] wire_receive_pcs6_dataout;
+ wire [399:0] wire_receive_pcs6_dprioout;
+ wire wire_receive_pcs6_iqpphfifobyteselout;
+ wire wire_receive_pcs6_iqpphfifordenableout;
+ wire wire_receive_pcs6_iqpphfifowrclkout;
+ wire wire_receive_pcs6_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs6_patterndetect;
+ wire wire_receive_pcs6_phfifobyteserdisableout;
+ wire wire_receive_pcs6_phfifoptrsresetout;
+ wire wire_receive_pcs6_phfifordenableout;
+ wire wire_receive_pcs6_phfiforesetout;
+ wire wire_receive_pcs6_phfifowrdisableout;
+ wire wire_receive_pcs6_pipedatavalid;
+ wire wire_receive_pcs6_pipeelecidle;
+ wire wire_receive_pcs6_pipephydonestatus;
+ wire wire_receive_pcs6_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs6_pipestatus;
+ wire wire_receive_pcs6_rateswitchout;
+ wire [19:0] wire_receive_pcs6_revparallelfdbkdata;
+ wire wire_receive_pcs6_signaldetect;
+ wire [3:0] wire_receive_pcs6_syncstatus;
+ wire wire_receive_pcs7_cdrctrlearlyeios;
+ wire wire_receive_pcs7_cdrctrllocktorefclkout;
+ wire wire_receive_pcs7_coreclkout;
+ wire [3:0] wire_receive_pcs7_ctrldetect;
+ wire [39:0] wire_receive_pcs7_dataout;
+ wire [399:0] wire_receive_pcs7_dprioout;
+ wire wire_receive_pcs7_iqpphfifobyteselout;
+ wire wire_receive_pcs7_iqpphfifordenableout;
+ wire wire_receive_pcs7_iqpphfifowrclkout;
+ wire wire_receive_pcs7_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs7_patterndetect;
+ wire wire_receive_pcs7_phfifobyteserdisableout;
+ wire wire_receive_pcs7_phfifoptrsresetout;
+ wire wire_receive_pcs7_phfifordenableout;
+ wire wire_receive_pcs7_phfiforesetout;
+ wire wire_receive_pcs7_phfifowrdisableout;
+ wire wire_receive_pcs7_pipedatavalid;
+ wire wire_receive_pcs7_pipeelecidle;
+ wire wire_receive_pcs7_pipephydonestatus;
+ wire wire_receive_pcs7_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs7_pipestatus;
+ wire wire_receive_pcs7_rateswitchout;
+ wire [19:0] wire_receive_pcs7_revparallelfdbkdata;
+ wire wire_receive_pcs7_signaldetect;
+ wire [3:0] wire_receive_pcs7_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire [7:0] wire_receive_pma1_analogtestbus;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire [299:0] wire_receive_pma1_dprioout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire [7:0] wire_receive_pma2_analogtestbus;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire [299:0] wire_receive_pma2_dprioout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire [7:0] wire_receive_pma3_analogtestbus;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire [299:0] wire_receive_pma3_dprioout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire [7:0] wire_receive_pma4_analogtestbus;
+ wire wire_receive_pma4_clockout;
+ wire wire_receive_pma4_dataout;
+ wire [299:0] wire_receive_pma4_dprioout;
+ wire wire_receive_pma4_locktorefout;
+ wire [63:0] wire_receive_pma4_recoverdataout;
+ wire wire_receive_pma4_signaldetect;
+ wire [7:0] wire_receive_pma5_analogtestbus;
+ wire wire_receive_pma5_clockout;
+ wire wire_receive_pma5_dataout;
+ wire [299:0] wire_receive_pma5_dprioout;
+ wire wire_receive_pma5_locktorefout;
+ wire [63:0] wire_receive_pma5_recoverdataout;
+ wire wire_receive_pma5_signaldetect;
+ wire [7:0] wire_receive_pma6_analogtestbus;
+ wire wire_receive_pma6_clockout;
+ wire wire_receive_pma6_dataout;
+ wire [299:0] wire_receive_pma6_dprioout;
+ wire wire_receive_pma6_locktorefout;
+ wire [63:0] wire_receive_pma6_recoverdataout;
+ wire wire_receive_pma6_signaldetect;
+ wire [7:0] wire_receive_pma7_analogtestbus;
+ wire wire_receive_pma7_clockout;
+ wire wire_receive_pma7_dataout;
+ wire [299:0] wire_receive_pma7_dprioout;
+ wire wire_receive_pma7_locktorefout;
+ wire [63:0] wire_receive_pma7_recoverdataout;
+ wire wire_receive_pma7_signaldetect;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire wire_transmit_pcs0_iqpphfifobyteselout;
+ wire wire_transmit_pcs0_iqpphfifordclkout;
+ wire wire_transmit_pcs0_iqpphfifordenableout;
+ wire wire_transmit_pcs0_iqpphfifowrenableout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire wire_transmit_pcs0_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire [149:0] wire_transmit_pcs1_dprioout;
+ wire wire_transmit_pcs1_forceelecidleout;
+ wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
+ wire wire_transmit_pcs1_iqpphfifobyteselout;
+ wire wire_transmit_pcs1_iqpphfifordclkout;
+ wire wire_transmit_pcs1_iqpphfifordenableout;
+ wire wire_transmit_pcs1_iqpphfifowrenableout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire wire_transmit_pcs1_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire [149:0] wire_transmit_pcs2_dprioout;
+ wire wire_transmit_pcs2_forceelecidleout;
+ wire [2:0] wire_transmit_pcs2_grayelecidleinferselout;
+ wire wire_transmit_pcs2_iqpphfifobyteselout;
+ wire wire_transmit_pcs2_iqpphfifordclkout;
+ wire wire_transmit_pcs2_iqpphfifordenableout;
+ wire wire_transmit_pcs2_iqpphfifowrenableout;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire wire_transmit_pcs2_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs2_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs2_pipepowerstateout;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire [149:0] wire_transmit_pcs3_dprioout;
+ wire wire_transmit_pcs3_forceelecidleout;
+ wire [2:0] wire_transmit_pcs3_grayelecidleinferselout;
+ wire wire_transmit_pcs3_iqpphfifobyteselout;
+ wire wire_transmit_pcs3_iqpphfifordclkout;
+ wire wire_transmit_pcs3_iqpphfifordenableout;
+ wire wire_transmit_pcs3_iqpphfifowrenableout;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire wire_transmit_pcs3_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs3_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs3_pipepowerstateout;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pcs4_coreclkout;
+ wire [19:0] wire_transmit_pcs4_dataout;
+ wire [149:0] wire_transmit_pcs4_dprioout;
+ wire wire_transmit_pcs4_forceelecidleout;
+ wire [2:0] wire_transmit_pcs4_grayelecidleinferselout;
+ wire wire_transmit_pcs4_iqpphfifobyteselout;
+ wire wire_transmit_pcs4_iqpphfifordclkout;
+ wire wire_transmit_pcs4_iqpphfifordenableout;
+ wire wire_transmit_pcs4_iqpphfifowrenableout;
+ wire wire_transmit_pcs4_phfiforddisableout;
+ wire wire_transmit_pcs4_phfiforesetout;
+ wire wire_transmit_pcs4_phfifowrenableout;
+ wire wire_transmit_pcs4_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs4_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs4_pipepowerstateout;
+ wire wire_transmit_pcs4_txdetectrx;
+ wire wire_transmit_pcs5_coreclkout;
+ wire [19:0] wire_transmit_pcs5_dataout;
+ wire [149:0] wire_transmit_pcs5_dprioout;
+ wire wire_transmit_pcs5_forceelecidleout;
+ wire [2:0] wire_transmit_pcs5_grayelecidleinferselout;
+ wire wire_transmit_pcs5_iqpphfifobyteselout;
+ wire wire_transmit_pcs5_iqpphfifordclkout;
+ wire wire_transmit_pcs5_iqpphfifordenableout;
+ wire wire_transmit_pcs5_iqpphfifowrenableout;
+ wire wire_transmit_pcs5_phfiforddisableout;
+ wire wire_transmit_pcs5_phfiforesetout;
+ wire wire_transmit_pcs5_phfifowrenableout;
+ wire wire_transmit_pcs5_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs5_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs5_pipepowerstateout;
+ wire wire_transmit_pcs5_txdetectrx;
+ wire wire_transmit_pcs6_coreclkout;
+ wire [19:0] wire_transmit_pcs6_dataout;
+ wire [149:0] wire_transmit_pcs6_dprioout;
+ wire wire_transmit_pcs6_forceelecidleout;
+ wire [2:0] wire_transmit_pcs6_grayelecidleinferselout;
+ wire wire_transmit_pcs6_iqpphfifobyteselout;
+ wire wire_transmit_pcs6_iqpphfifordclkout;
+ wire wire_transmit_pcs6_iqpphfifordenableout;
+ wire wire_transmit_pcs6_iqpphfifowrenableout;
+ wire wire_transmit_pcs6_phfiforddisableout;
+ wire wire_transmit_pcs6_phfiforesetout;
+ wire wire_transmit_pcs6_phfifowrenableout;
+ wire wire_transmit_pcs6_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs6_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs6_pipepowerstateout;
+ wire wire_transmit_pcs6_txdetectrx;
+ wire wire_transmit_pcs7_coreclkout;
+ wire [19:0] wire_transmit_pcs7_dataout;
+ wire [149:0] wire_transmit_pcs7_dprioout;
+ wire wire_transmit_pcs7_forceelecidleout;
+ wire [2:0] wire_transmit_pcs7_grayelecidleinferselout;
+ wire wire_transmit_pcs7_iqpphfifobyteselout;
+ wire wire_transmit_pcs7_iqpphfifordclkout;
+ wire wire_transmit_pcs7_iqpphfifordenableout;
+ wire wire_transmit_pcs7_iqpphfifowrenableout;
+ wire wire_transmit_pcs7_phfiforddisableout;
+ wire wire_transmit_pcs7_phfiforesetout;
+ wire wire_transmit_pcs7_phfifowrenableout;
+ wire wire_transmit_pcs7_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs7_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs7_pipepowerstateout;
+ wire wire_transmit_pcs7_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire [299:0] wire_transmit_pma1_dprioout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire [299:0] wire_transmit_pma2_dprioout;
+ wire wire_transmit_pma2_rxdetectvalidout;
+ wire wire_transmit_pma2_rxfoundout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire [299:0] wire_transmit_pma3_dprioout;
+ wire wire_transmit_pma3_rxdetectvalidout;
+ wire wire_transmit_pma3_rxfoundout;
+ wire wire_transmit_pma4_clockout;
+ wire wire_transmit_pma4_dataout;
+ wire [299:0] wire_transmit_pma4_dprioout;
+ wire wire_transmit_pma4_rxdetectvalidout;
+ wire wire_transmit_pma4_rxfoundout;
+ wire wire_transmit_pma5_clockout;
+ wire wire_transmit_pma5_dataout;
+ wire [299:0] wire_transmit_pma5_dprioout;
+ wire wire_transmit_pma5_rxdetectvalidout;
+ wire wire_transmit_pma5_rxfoundout;
+ wire wire_transmit_pma6_clockout;
+ wire wire_transmit_pma6_dataout;
+ wire [299:0] wire_transmit_pma6_dprioout;
+ wire wire_transmit_pma6_rxdetectvalidout;
+ wire wire_transmit_pma6_rxfoundout;
+ wire wire_transmit_pma7_clockout;
+ wire wire_transmit_pma7_dataout;
+ wire [299:0] wire_transmit_pma7_dprioout;
+ wire wire_transmit_pma7_rxdetectvalidout;
+ wire wire_transmit_pma7_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [1:0] cent_unit_clkdivpowerdn;
+ wire [1199:0] cent_unit_cmudividerdprioout;
+ wire [3599:0] cent_unit_cmuplldprioout;
+ wire [3:0] cent_unit_pllpowerdn;
+ wire [3:0] cent_unit_pllresetout;
+ wire [1:0] cent_unit_quadresetout;
+ wire [11:0] cent_unit_rxcrupowerdn;
+ wire [11:0] cent_unit_rxibpowerdn;
+ wire [3199:0] cent_unit_rxpcsdprioin;
+ wire [3199:0] cent_unit_rxpcsdprioout;
+ wire [3599:0] cent_unit_rxpmadprioin;
+ wire [3599:0] cent_unit_rxpmadprioout;
+ wire [2399:0] cent_unit_tx_dprioin;
+ wire [63:0] cent_unit_tx_xgmdataout;
+ wire [7:0] cent_unit_txctrlout;
+ wire [11:0] cent_unit_txdetectrxpowerdn;
+ wire [1199:0] cent_unit_txdprioout;
+ wire [11:0] cent_unit_txobpowerdn;
+ wire [3599:0] cent_unit_txpmadprioin;
+ wire [3599:0] cent_unit_txpmadprioout;
+ wire [7:0] clk_div_clk0in;
+ wire [1199:0] clk_div_cmudividerdprioin;
+ wire [1:0] clk_div_pclkin;
+ wire [3:0] cmu_analogfastrefclkout;
+ wire [3:0] cmu_analogrefclkout;
+ wire [1:0] cmu_analogrefclkpulse;
+ wire [0:0] coreclkout_bi_quad_wire;
+ wire [1:0] coreclkout_wire;
+ wire [11:0] fixedclk_to_cmu;
+ wire [23:0] grayelecidleinfersel_from_tx;
+ wire [1:0] int_autospdx4rateswitchout;
+ wire [7:0] int_hipautospdrateswitchout;
+ wire [1:0] int_hiprateswtichdone;
+ wire [7:0] int_pipeenrevparallellpbkfromtx;
+ wire [1:0] int_rateswitch;
+ wire [7:0] int_rx_coreclkout;
+ wire [0:0] int_rx_digitalreset_reg;
+ wire [7:0] int_rx_iqpphfifobyteselout;
+ wire [7:0] int_rx_iqpphfifordenableout;
+ wire [7:0] int_rx_iqpphfifowrclkout;
+ wire [7:0] int_rx_iqpphfifowrenableout;
+ wire [15:0] int_rx_iqpphfifoxnbytesel;
+ wire [15:0] int_rx_iqpphfifoxnrdenable;
+ wire [15:0] int_rx_iqpphfifoxnwrclk;
+ wire [15:0] int_rx_iqpphfifoxnwrenable;
+ wire [7:0] int_rx_phfifobyteserdisable;
+ wire [7:0] int_rx_phfifoptrsresetout;
+ wire [7:0] int_rx_phfifordenableout;
+ wire [7:0] int_rx_phfiforesetout;
+ wire [7:0] int_rx_phfifowrdisableout;
+ wire [23:0] int_rx_phfifoxnbytesel;
+ wire [23:0] int_rx_phfifoxnrdenable;
+ wire [23:0] int_rx_phfifoxnwrclk;
+ wire [23:0] int_rx_phfifoxnwrenable;
+ wire [1:0] int_rxcoreclk;
+ wire [7:0] int_rxpcs_cdrctrlearlyeios;
+ wire [1:0] int_rxphfifordenable;
+ wire [1:0] int_rxphfiforeset;
+ wire [1:0] int_rxphfifox4byteselout;
+ wire [1:0] int_rxphfifox4rdenableout;
+ wire [1:0] int_rxphfifox4wrclkout;
+ wire [1:0] int_rxphfifox4wrenableout;
+ wire [7:0] int_tx_coreclkout;
+ wire [0:0] int_tx_digitalreset_reg;
+ wire [7:0] int_tx_iqpphfifobyteselout;
+ wire [7:0] int_tx_iqpphfifordclkout;
+ wire [7:0] int_tx_iqpphfifordenableout;
+ wire [7:0] int_tx_iqpphfifowrenableout;
+ wire [15:0] int_tx_iqpphfifoxnbytesel;
+ wire [15:0] int_tx_iqpphfifoxnrdclk;
+ wire [15:0] int_tx_iqpphfifoxnrdenable;
+ wire [15:0] int_tx_iqpphfifoxnwrenable;
+ wire [7:0] int_tx_phfiforddisableout;
+ wire [7:0] int_tx_phfiforesetout;
+ wire [7:0] int_tx_phfifowrenableout;
+ wire [23:0] int_tx_phfifoxnbytesel;
+ wire [23:0] int_tx_phfifoxnrdclk;
+ wire [23:0] int_tx_phfifoxnrdenable;
+ wire [23:0] int_tx_phfifoxnwrenable;
+ wire [1:0] int_txcoreclk;
+ wire [1:0] int_txphfiforddisable;
+ wire [1:0] int_txphfiforeset;
+ wire [1:0] int_txphfifowrenable;
+ wire [1:0] int_txphfifox4byteselout;
+ wire [1:0] int_txphfifox4rdclkout;
+ wire [1:0] int_txphfifox4rdenableout;
+ wire [1:0] int_txphfifox4wrenableout;
+ wire [1:0] nonusertocmu_out;
+ wire [7:0] pipedatavalid_out;
+ wire [7:0] pipeelecidle_out;
+ wire [19:0] pll0_clkin;
+ wire [599:0] pll0_dprioin;
+ wire [599:0] pll0_dprioout;
+ wire [7:0] pll0_out;
+ wire [15:0] pll_ch_dataout_wire;
+ wire [2399:0] pll_ch_dprioout;
+ wire [3599:0] pll_cmuplldprioout;
+ wire [0:0] pll_inclk_wire;
+ wire [1:0] pll_locked_out;
+ wire [0:0] pll_powerdown;
+ wire [3:0] pllpowerdn_in;
+ wire [3:0] pllreset_in;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [1:0] refclk_pma;
+ wire [11:0] rx_analogreset_in;
+ wire [11:0] rx_analogreset_out;
+ wire [7:0] rx_coreclk_in;
+ wire [79:0] rx_cruclk_in;
+ wire [31:0] rx_deserclock_in;
+ wire [7:0] rx_digitalreset_in;
+ wire [7:0] rx_digitalreset_out;
+ wire [23:0] rx_elecidleinfersel;
+ wire [7:0] rx_enapatternalign;
+ wire [7:0] rx_freqlocked_wire;
+ wire [7:0] rx_locktodata;
+ wire [7:0] rx_locktodata_wire;
+ wire [7:0] rx_locktorefclk_wire;
+ wire [63:0] rx_out_wire;
+ wire [15:0] rx_pcs_rxfound_wire;
+ wire [3199:0] rx_pcsdprioin_wire;
+ wire [3199:0] rx_pcsdprioout;
+ wire [7:0] rx_phfifordenable;
+ wire [7:0] rx_phfiforeset;
+ wire [7:0] rx_phfifowrdisable;
+ wire [7:0] rx_pipestatetransdoneout;
+ wire [7:0] rx_pldcruclk_in;
+ wire [31:0] rx_pll_clkout;
+ wire [7:0] rx_pll_pfdrefclkout_wire;
+ wire [7:0] rx_plllocked_wire;
+ wire [135:0] rx_pma_analogtestbus;
+ wire [7:0] rx_pma_clockout;
+ wire [7:0] rx_pma_dataout;
+ wire [7:0] rx_pma_locktorefout;
+ wire [159:0] rx_pma_recoverdataout_wire;
+ wire [3599:0] rx_pmadprioin_wire;
+ wire [3599:0] rx_pmadprioout;
+ wire [7:0] rx_powerdown;
+ wire [11:0] rx_powerdown_in;
+ wire [7:0] rx_prbscidenable;
+ wire [159:0] rx_revparallelfdbkdata;
+ wire [7:0] rx_rmfiforeset;
+ wire [11:0] rx_rxcruresetout;
+ wire [7:0] rx_signaldetect_wire;
+ wire [1:0] rxphfifowrdisable;
+ wire [3599:0] rxpll_dprioin;
+ wire [11:0] tx_analogreset_out;
+ wire [7:0] tx_clkout_int_wire;
+ wire [7:0] tx_coreclk_in;
+ wire [63:0] tx_datain_wire;
+ wire [159:0] tx_dataout_pcs_to_pma;
+ wire [7:0] tx_digitalreset_in;
+ wire [7:0] tx_digitalreset_out;
+ wire [2399:0] tx_dprioin_wire;
+ wire [7:0] tx_forcedisp_wire;
+ wire [7:0] tx_invpolarity;
+ wire [7:0] tx_localrefclk;
+ wire [7:0] tx_pcs_forceelecidleout;
+ wire [7:0] tx_phfiforeset;
+ wire [7:0] tx_pipedeemph;
+ wire [23:0] tx_pipemargin;
+ wire [15:0] tx_pipepowerdownout;
+ wire [31:0] tx_pipepowerstateout;
+ wire [7:0] tx_pipeswing;
+ wire [3599:0] tx_pmadprioin_wire;
+ wire [3599:0] tx_pmadprioout;
+ wire [7:0] tx_revparallellpbken;
+ wire [7:0] tx_rxdetectvalidout;
+ wire [7:0] tx_rxfoundout;
+ wire [1199:0] tx_txdprioout;
+ wire [7:0] txdetectrxout;
+ wire [1:0] w_cent_unit_dpriodisableout1w;
+
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
+ rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
+ rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
+ rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
+ assign
+ wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
+ tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
+ tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
+ tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
+ assign
+ wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_calibration_block cal_blk1
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk1_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[3:0]),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[499:400]),
+ .dprioout(wire_central_clk_div0_dprioout),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(int_autospdx4rateswitchout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.effective_data_rate = "2500 Mbps",
+ central_clk_div0.enable_dynamic_divider = "false",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_refclk = "true",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "false",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_clock_divider central_clk_div1
+ (
+ .analogfastrefclkout(wire_central_clk_div1_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div1_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div1_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[7:4]),
+ .coreclkout(wire_central_clk_div1_coreclkout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(cent_unit_cmudividerdprioout[1099:1000]),
+ .dprioout(wire_central_clk_div1_dprioout),
+ .powerdn(cent_unit_clkdivpowerdn[1]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div1_rateswitchdone),
+ .rateswitchdonein({{1{1'b0}}, int_hiprateswtichdone[0]}),
+ .rateswitchout(),
+ .refclkin({{1{1'b0}}, clk_div_pclkin[1]}),
+ .refclkout(wire_central_clk_div1_refclkout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .refclkdig(1'b0),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div1.divide_by = 5,
+ central_clk_div1.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div1.effective_data_rate = "2500 Mbps",
+ central_clk_div1.enable_dynamic_divider = "false",
+ central_clk_div1.enable_refclk_out = "true",
+ central_clk_div1.inclk_select = 0,
+ central_clk_div1.logical_channel_address = 0,
+ central_clk_div1.pre_divide_by = 1,
+ central_clk_div1.refclkin_select = 0,
+ central_clk_div1.select_local_refclk = "false",
+ central_clk_div1.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div1.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div1.sim_coreclkout_phase_shift = 0,
+ central_clk_div1.sim_refclkout_phase_shift = 0,
+ central_clk_div1.use_coreclk_out_post_divider = "false",
+ central_clk_div1.use_refclk_post_divider = "false",
+ central_clk_div1.use_vco_bypass = "false",
+ central_clk_div1.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitch(int_rateswitch[0]),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "driver",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 249950,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "x8",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "false",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "x8",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "false",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "2.5V",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_cmu cent_unit1
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit1_clkdivpowerdn),
+ .cmudividerdprioin({clk_div_cmudividerdprioin[1199:600]}),
+ .cmudividerdprioout(wire_cent_unit1_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[3599:1800]),
+ .cmuplldprioout(wire_cent_unit1_cmuplldprioout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit1_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit1_dprioout),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .fixedclk({{2{1'b0}}, fixedclk_to_cmu[9:6]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[1]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit1_pllpowerdn),
+ .pllresetout(wire_cent_unit1_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit1_quadresetout),
+ .rateswitch(int_rateswitch[1]),
+ .rateswitchdonein(int_hiprateswtichdone[1]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[7:4]}),
+ .rxanalogresetout(wire_cent_unit1_rxanalogresetout),
+ .rxclk(refclk_pma[1]),
+ .rxcoreclk(int_rxcoreclk[1]),
+ .rxcrupowerdown(wire_cent_unit1_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit1_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({rx_digitalreset_in[7:4]}),
+ .rxdigitalresetout(wire_cent_unit1_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit1_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[3199:1600]}),
+ .rxpcsdprioout(wire_cent_unit1_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[1]),
+ .rxphfiforeset(int_rxphfiforeset[1]),
+ .rxphfifowrdisable(rxphfifowrdisable[1]),
+ .rxphfifox4byteselout(wire_cent_unit1_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit1_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit1_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit1_rxphfifox4wrenableout),
+ .rxpmadprioin({cent_unit_rxpmadprioin[3599:1800]}),
+ .rxpmadprioout(wire_cent_unit1_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[7:4]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit1_txanalogresetout),
+ .txclk(refclk_pma[1]),
+ .txcoreclk(int_txcoreclk[1]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit1_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit1_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit1_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[7:4]}),
+ .txdigitalresetout(wire_cent_unit1_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit1_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[1199:600]}),
+ .txpcsdprioout(wire_cent_unit1_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[1]),
+ .txphfiforeset(int_txphfiforeset[1]),
+ .txphfifowrenable(int_txphfifowrenable[1]),
+ .txphfifox4byteselout(wire_cent_unit1_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit1_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit1_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit1_txphfifox4wrenableout),
+ .txpmadprioin({cent_unit_txpmadprioin[3599:1800]}),
+ .txpmadprioout(wire_cent_unit1_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}}),
+ .txpllreset({2{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit1.auto_spd_phystatus_notify_count = 14,
+ cent_unit1.bonded_quad_mode = "receiver",
+ cent_unit1.devaddr = ((((starting_channel_number / 4) + 1) % 32) + 1),
+ cent_unit1.in_xaui_mode = "false",
+ cent_unit1.offset_all_errors_align = "false",
+ cent_unit1.pipe_auto_speed_nego_enable = "false",
+ cent_unit1.pipe_freq_scale_mode = "Frequency",
+ cent_unit1.pma_done_count = 249950,
+ cent_unit1.portaddr = (((starting_channel_number + 4) / 128) + 1),
+ cent_unit1.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit1.rx0_channel_bonding = "x8",
+ cent_unit1.rx0_clk1_mux_select = "recovered clock",
+ cent_unit1.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit1.rx0_ph_fifo_reg_mode = "false",
+ cent_unit1.rx0_rd_clk_mux_select = "core clock",
+ cent_unit1.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit1.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit1.rx0_use_double_data_mode = "false",
+ cent_unit1.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit1.tx0_channel_bonding = "x8",
+ cent_unit1.tx0_ph_fifo_reg_mode = "false",
+ cent_unit1.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit1.tx0_use_double_data_mode = "false",
+ cent_unit1.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit1.use_deskew_fifo = "false",
+ cent_unit1.vcceh_voltage = "2.5V",
+ cent_unit1.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[0]),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({rx_cruclk_in[9:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .rateswitch(int_hipautospdrateswitchout[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.bandwidth_type = "Medium",
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll0.enable_dynamic_divider = "false",
+ rx_cdr_pll0.fast_lock_control = "false",
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 2,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_post_scale = 2,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[599:300]),
+ .dprioout(wire_rx_cdr_pll1_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[1]),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({rx_cruclk_in[19:10]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .rateswitch(int_hipautospdrateswitchout[1]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.bandwidth_type = "Medium",
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.dprio_config_mode = 6'h00,
+ rx_cdr_pll1.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll1.enable_dynamic_divider = "false",
+ rx_cdr_pll1.fast_lock_control = "false",
+ rx_cdr_pll1.inclk0_input_period = 10000,
+ rx_cdr_pll1.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll1.m = 25,
+ rx_cdr_pll1.n = 2,
+ rx_cdr_pll1.pfd_clk_select = 0,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_post_scale = 2,
+ rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[899:600]),
+ .dprioout(wire_rx_cdr_pll2_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[2]),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({rx_cruclk_in[29:20]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .rateswitch(int_hipautospdrateswitchout[2]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.bandwidth_type = "Medium",
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.dprio_config_mode = 6'h00,
+ rx_cdr_pll2.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll2.enable_dynamic_divider = "false",
+ rx_cdr_pll2.fast_lock_control = "false",
+ rx_cdr_pll2.inclk0_input_period = 10000,
+ rx_cdr_pll2.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll2.m = 25,
+ rx_cdr_pll2.n = 2,
+ rx_cdr_pll2.pfd_clk_select = 0,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_post_scale = 2,
+ rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[1199:900]),
+ .dprioout(wire_rx_cdr_pll3_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[3]),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({rx_cruclk_in[39:30]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .rateswitch(int_hipautospdrateswitchout[3]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.bandwidth_type = "Medium",
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.dprio_config_mode = 6'h00,
+ rx_cdr_pll3.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll3.enable_dynamic_divider = "false",
+ rx_cdr_pll3.fast_lock_control = "false",
+ rx_cdr_pll3.inclk0_input_period = 10000,
+ rx_cdr_pll3.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll3.m = 25,
+ rx_cdr_pll3.n = 2,
+ rx_cdr_pll3.pfd_clk_select = 0,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_post_scale = 2,
+ rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll4
+ (
+ .areset(rx_rxcruresetout[6]),
+ .clk(wire_rx_cdr_pll4_clk),
+ .datain(rx_pma_dataout[4]),
+ .dataout(wire_rx_cdr_pll4_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rxpll_dprioin[2099:1800]),
+ .dprioout(wire_rx_cdr_pll4_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[4]),
+ .freqlocked(wire_rx_cdr_pll4_freqlocked),
+ .inclk({rx_cruclk_in[49:40]}),
+ .locked(wire_rx_cdr_pll4_locked),
+ .locktorefclk(rx_pma_locktorefout[4]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll4_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[6]),
+ .rateswitch(int_hipautospdrateswitchout[4]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll4.bandwidth_type = "Medium",
+ rx_cdr_pll4.channel_num = ((starting_channel_number + 4) % 4),
+ rx_cdr_pll4.dprio_config_mode = 6'h00,
+ rx_cdr_pll4.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll4.enable_dynamic_divider = "false",
+ rx_cdr_pll4.fast_lock_control = "false",
+ rx_cdr_pll4.inclk0_input_period = 10000,
+ rx_cdr_pll4.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll4.m = 25,
+ rx_cdr_pll4.n = 2,
+ rx_cdr_pll4.pfd_clk_select = 0,
+ rx_cdr_pll4.pll_type = "RX CDR",
+ rx_cdr_pll4.use_refclk_pin = "false",
+ rx_cdr_pll4.vco_post_scale = 2,
+ rx_cdr_pll4.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll5
+ (
+ .areset(rx_rxcruresetout[7]),
+ .clk(wire_rx_cdr_pll5_clk),
+ .datain(rx_pma_dataout[5]),
+ .dataout(wire_rx_cdr_pll5_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rxpll_dprioin[2399:2100]),
+ .dprioout(wire_rx_cdr_pll5_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[5]),
+ .freqlocked(wire_rx_cdr_pll5_freqlocked),
+ .inclk({rx_cruclk_in[59:50]}),
+ .locked(wire_rx_cdr_pll5_locked),
+ .locktorefclk(rx_pma_locktorefout[5]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll5_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[7]),
+ .rateswitch(int_hipautospdrateswitchout[5]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll5.bandwidth_type = "Medium",
+ rx_cdr_pll5.channel_num = ((starting_channel_number + 5) % 4),
+ rx_cdr_pll5.dprio_config_mode = 6'h00,
+ rx_cdr_pll5.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll5.enable_dynamic_divider = "false",
+ rx_cdr_pll5.fast_lock_control = "false",
+ rx_cdr_pll5.inclk0_input_period = 10000,
+ rx_cdr_pll5.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll5.m = 25,
+ rx_cdr_pll5.n = 2,
+ rx_cdr_pll5.pfd_clk_select = 0,
+ rx_cdr_pll5.pll_type = "RX CDR",
+ rx_cdr_pll5.use_refclk_pin = "false",
+ rx_cdr_pll5.vco_post_scale = 2,
+ rx_cdr_pll5.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll6
+ (
+ .areset(rx_rxcruresetout[8]),
+ .clk(wire_rx_cdr_pll6_clk),
+ .datain(rx_pma_dataout[6]),
+ .dataout(wire_rx_cdr_pll6_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rxpll_dprioin[2699:2400]),
+ .dprioout(wire_rx_cdr_pll6_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[6]),
+ .freqlocked(wire_rx_cdr_pll6_freqlocked),
+ .inclk({rx_cruclk_in[69:60]}),
+ .locked(wire_rx_cdr_pll6_locked),
+ .locktorefclk(rx_pma_locktorefout[6]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll6_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[8]),
+ .rateswitch(int_hipautospdrateswitchout[6]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll6.bandwidth_type = "Medium",
+ rx_cdr_pll6.channel_num = ((starting_channel_number + 6) % 4),
+ rx_cdr_pll6.dprio_config_mode = 6'h00,
+ rx_cdr_pll6.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll6.enable_dynamic_divider = "false",
+ rx_cdr_pll6.fast_lock_control = "false",
+ rx_cdr_pll6.inclk0_input_period = 10000,
+ rx_cdr_pll6.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll6.m = 25,
+ rx_cdr_pll6.n = 2,
+ rx_cdr_pll6.pfd_clk_select = 0,
+ rx_cdr_pll6.pll_type = "RX CDR",
+ rx_cdr_pll6.use_refclk_pin = "false",
+ rx_cdr_pll6.vco_post_scale = 2,
+ rx_cdr_pll6.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll7
+ (
+ .areset(rx_rxcruresetout[9]),
+ .clk(wire_rx_cdr_pll7_clk),
+ .datain(rx_pma_dataout[7]),
+ .dataout(wire_rx_cdr_pll7_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rxpll_dprioin[2999:2700]),
+ .dprioout(wire_rx_cdr_pll7_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[7]),
+ .freqlocked(wire_rx_cdr_pll7_freqlocked),
+ .inclk({rx_cruclk_in[79:70]}),
+ .locked(wire_rx_cdr_pll7_locked),
+ .locktorefclk(rx_pma_locktorefout[7]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll7_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[9]),
+ .rateswitch(int_hipautospdrateswitchout[7]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll7.bandwidth_type = "Medium",
+ rx_cdr_pll7.channel_num = ((starting_channel_number + 7) % 4),
+ rx_cdr_pll7.dprio_config_mode = 6'h00,
+ rx_cdr_pll7.effective_data_rate = "2500 Mbps",
+ rx_cdr_pll7.enable_dynamic_divider = "false",
+ rx_cdr_pll7.fast_lock_control = "false",
+ rx_cdr_pll7.inclk0_input_period = 10000,
+ rx_cdr_pll7.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll7.m = 25,
+ rx_cdr_pll7.n = 2,
+ rx_cdr_pll7.pfd_clk_select = 0,
+ rx_cdr_pll7.pll_type = "RX CDR",
+ rx_cdr_pll7.use_refclk_pin = "false",
+ rx_cdr_pll7.vco_post_scale = 2,
+ rx_cdr_pll7.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(pll0_dprioin[299:0]),
+ .dprioout(wire_tx_pll0_dprioout),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.bandwidth_type = "High",
+ tx_pll0.channel_num = 4,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 10000,
+ tx_pll0.input_clock_frequency = "100.0 MHz",
+ tx_pll0.logical_tx_pll_number = 0,
+ tx_pll0.m = 25,
+ tx_pll0.n = 2,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pfd_fb_select = "internal",
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_post_scale = 2,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs0_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs0_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs0_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs0_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[1:0]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[1:0]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[1:0]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[1:0]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(wire_receive_pcs0_signaldetect),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_cid_mode_enable = "true",
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x8",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 8,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 249950,
+ receive_pcs0.protocol_hint = "pcie",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_pipe_enable = "true",
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 32,
+ receive_pcs0.rxstatus_error_report_mode = 1,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "false",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(wire_receive_pcs1_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs1_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs1_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs1_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs1_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[3:2]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[3:2]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[3:2]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[3:2]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetect(wire_receive_pcs1_signaldetect),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.auto_spd_self_switch_enable = "false",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_cid_mode_enable = "true",
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x8",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 8,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h01,
+ receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "false",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 249950,
+ receive_pcs1.protocol_hint = "pcie",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_pipe_enable = "true",
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rx_phfifo_wait_cnt = 32,
+ receive_pcs1.rxstatus_error_report_mode = 1,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "false",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs2_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(wire_receive_pcs2_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[8:6]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs2_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs2_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs2_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs2_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[5:4]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[5:4]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[5:4]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[5:4]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs2_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs2_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[2]),
+ .pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[5:4]),
+ .pipepowerstate(tx_pipepowerstateout[11:8]),
+ .pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs2_pipestatus),
+ .powerdn(powerdn[5:4]),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[2]),
+ .rxfound(rx_pcs_rxfound_wire[5:4]),
+ .signaldetect(wire_receive_pcs2_signaldetect),
+ .signaldetected(rx_signaldetect_wire[2]),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "false",
+ receive_pcs2.allow_pipe_polarity_inversion = "true",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 14,
+ receive_pcs2.auto_spd_self_switch_enable = "false",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs2.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_cid_mode_enable = "true",
+ receive_pcs2.cdrctrl_enable = "true",
+ receive_pcs2.cdrctrl_rxvalid_mask = "true",
+ receive_pcs2.channel_bonding = "x8",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 8,
+ receive_pcs2.clk1_mux_select = "recovered clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "false",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "pipe",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs2.deskew_pattern = "0",
+ receive_pcs2.disable_auto_idle_insertion = "false",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h01,
+ receive_pcs2.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 16,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 17,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "false",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 249950,
+ receive_pcs2.protocol_hint = "pcie",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "false",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs2.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs2.rate_match_pattern_size = 20,
+ receive_pcs2.rate_match_pipe_enable = "true",
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "true",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rx_phfifo_wait_cnt = 32,
+ receive_pcs2.rxstatus_error_report_mode = 1,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "false",
+ receive_pcs2.use_double_data_mode = "false",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs3_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(wire_receive_pcs3_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[11:9]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs3_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs3_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs3_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs3_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[7:6]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[7:6]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[7:6]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[7:6]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs3_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs3_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[3]),
+ .pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[7:6]),
+ .pipepowerstate(tx_pipepowerstateout[15:12]),
+ .pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs3_pipestatus),
+ .powerdn(powerdn[7:6]),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[3]),
+ .rxfound(rx_pcs_rxfound_wire[7:6]),
+ .signaldetect(wire_receive_pcs3_signaldetect),
+ .signaldetected(rx_signaldetect_wire[3]),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "false",
+ receive_pcs3.allow_pipe_polarity_inversion = "true",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 14,
+ receive_pcs3.auto_spd_self_switch_enable = "false",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs3.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_cid_mode_enable = "true",
+ receive_pcs3.cdrctrl_enable = "true",
+ receive_pcs3.cdrctrl_rxvalid_mask = "true",
+ receive_pcs3.channel_bonding = "x8",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 8,
+ receive_pcs3.clk1_mux_select = "recovered clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "false",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "pipe",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs3.deskew_pattern = "0",
+ receive_pcs3.disable_auto_idle_insertion = "false",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h01,
+ receive_pcs3.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 16,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 17,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "false",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 249950,
+ receive_pcs3.protocol_hint = "pcie",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "false",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs3.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs3.rate_match_pattern_size = 20,
+ receive_pcs3.rate_match_pipe_enable = "true",
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "true",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rx_phfifo_wait_cnt = 32,
+ receive_pcs3.rxstatus_error_report_mode = 1,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "false",
+ receive_pcs3.use_double_data_mode = "false",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs4
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs4_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs4_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[4]),
+ .coreclkout(wire_receive_pcs4_coreclkout),
+ .ctrldetect(wire_receive_pcs4_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[99:80]),
+ .dataout(wire_receive_pcs4_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[4]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pcsdprioin_wire[1999:1600]),
+ .dprioout(wire_receive_pcs4_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[4]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[14:12]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs4_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs4_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs4_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs4_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[9:8]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[9:8]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[9:8]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[9:8]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs4_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs4_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs4_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[4]),
+ .phfifordenableout(wire_receive_pcs4_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[4]),
+ .phfiforesetout(wire_receive_pcs4_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[4]),
+ .phfifowrdisableout(wire_receive_pcs4_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[14:12]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[14:12]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[14:12]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[14:12]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[4]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs4_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs4_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[4]),
+ .pipephydonestatus(wire_receive_pcs4_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[9:8]),
+ .pipepowerstate(tx_pipepowerstateout[19:16]),
+ .pipestatetransdoneout(wire_receive_pcs4_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs4_pipestatus),
+ .powerdn(powerdn[9:8]),
+ .prbscidenable(rx_prbscidenable[4]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(wire_receive_pcs4_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[4]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs4_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[4]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[4]),
+ .rxfound(rx_pcs_rxfound_wire[9:8]),
+ .signaldetect(wire_receive_pcs4_signaldetect),
+ .signaldetected(rx_signaldetect_wire[4]),
+ .syncstatus(wire_receive_pcs4_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs4.align_pattern = "0101111100",
+ receive_pcs4.align_pattern_length = 10,
+ receive_pcs4.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs4.allow_align_polarity_inversion = "false",
+ receive_pcs4.allow_pipe_polarity_inversion = "true",
+ receive_pcs4.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs4.auto_spd_phystatus_notify_count = 14,
+ receive_pcs4.auto_spd_self_switch_enable = "false",
+ receive_pcs4.bit_slip_enable = "false",
+ receive_pcs4.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs4.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs4.byte_order_mode = "none",
+ receive_pcs4.byte_order_pad_pattern = "0",
+ receive_pcs4.byte_order_pattern = "0",
+ receive_pcs4.byte_order_pld_ctrl_enable = "false",
+ receive_pcs4.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs4.cdrctrl_cid_mode_enable = "true",
+ receive_pcs4.cdrctrl_enable = "true",
+ receive_pcs4.cdrctrl_rxvalid_mask = "true",
+ receive_pcs4.channel_bonding = "x8",
+ receive_pcs4.channel_number = ((starting_channel_number + 4) % 4),
+ receive_pcs4.channel_width = 8,
+ receive_pcs4.clk1_mux_select = "recovered clock",
+ receive_pcs4.clk2_mux_select = "digital reference clock",
+ receive_pcs4.core_clock_0ppm = "false",
+ receive_pcs4.datapath_low_latency_mode = "false",
+ receive_pcs4.datapath_protocol = "pipe",
+ receive_pcs4.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs4.dec_8b_10b_mode = "normal",
+ receive_pcs4.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs4.deskew_pattern = "0",
+ receive_pcs4.disable_auto_idle_insertion = "false",
+ receive_pcs4.disable_running_disp_in_word_align = "false",
+ receive_pcs4.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs4.dprio_config_mode = 6'h01,
+ receive_pcs4.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs4.elec_idle_infer_enable = "false",
+ receive_pcs4.elec_idle_num_com_detect = 3,
+ receive_pcs4.enable_bit_reversal = "false",
+ receive_pcs4.enable_deep_align = "false",
+ receive_pcs4.enable_deep_align_byte_swap = "false",
+ receive_pcs4.enable_self_test_mode = "false",
+ receive_pcs4.enable_true_complement_match_in_word_align = "false",
+ receive_pcs4.force_signal_detect_dig = "true",
+ receive_pcs4.hip_enable = "false",
+ receive_pcs4.infiniband_invalid_code = 0,
+ receive_pcs4.insert_pad_on_underflow = "false",
+ receive_pcs4.iqp_ph_fifo_xn_select = 1,
+ receive_pcs4.logical_channel_address = (starting_channel_number + 4),
+ receive_pcs4.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs4.num_align_cons_good_data = 16,
+ receive_pcs4.num_align_cons_pat = 4,
+ receive_pcs4.num_align_loss_sync_error = 17,
+ receive_pcs4.ph_fifo_low_latency_enable = "true",
+ receive_pcs4.ph_fifo_reg_mode = "false",
+ receive_pcs4.ph_fifo_xn_mapping0 = "none",
+ receive_pcs4.ph_fifo_xn_mapping1 = "up",
+ receive_pcs4.ph_fifo_xn_mapping2 = "none",
+ receive_pcs4.ph_fifo_xn_select = 1,
+ receive_pcs4.pipe_auto_speed_nego_enable = "false",
+ receive_pcs4.pipe_freq_scale_mode = "Frequency",
+ receive_pcs4.pma_done_count = 249950,
+ receive_pcs4.protocol_hint = "pcie",
+ receive_pcs4.rate_match_almost_empty_threshold = 11,
+ receive_pcs4.rate_match_almost_full_threshold = 13,
+ receive_pcs4.rate_match_back_to_back = "false",
+ receive_pcs4.rate_match_delete_threshold = 13,
+ receive_pcs4.rate_match_empty_threshold = 5,
+ receive_pcs4.rate_match_fifo_mode = "true",
+ receive_pcs4.rate_match_full_threshold = 20,
+ receive_pcs4.rate_match_insert_threshold = 11,
+ receive_pcs4.rate_match_ordered_set_based = "false",
+ receive_pcs4.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs4.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs4.rate_match_pattern_size = 20,
+ receive_pcs4.rate_match_pipe_enable = "true",
+ receive_pcs4.rate_match_reset_enable = "false",
+ receive_pcs4.rate_match_skip_set_based = "true",
+ receive_pcs4.rate_match_start_threshold = 7,
+ receive_pcs4.rd_clk_mux_select = "core clock",
+ receive_pcs4.recovered_clk_mux_select = "recovered clock",
+ receive_pcs4.run_length = 40,
+ receive_pcs4.run_length_enable = "true",
+ receive_pcs4.rx_detect_bypass = "false",
+ receive_pcs4.rx_phfifo_wait_cnt = 32,
+ receive_pcs4.rxstatus_error_report_mode = 1,
+ receive_pcs4.self_test_mode = "incremental",
+ receive_pcs4.use_alignment_state_machine = "true",
+ receive_pcs4.use_deserializer_double_data_mode = "false",
+ receive_pcs4.use_deskew_fifo = "false",
+ receive_pcs4.use_double_data_mode = "false",
+ receive_pcs4.use_parallel_loopback = "false",
+ receive_pcs4.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs4.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs5
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs5_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs5_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[5]),
+ .coreclkout(wire_receive_pcs5_coreclkout),
+ .ctrldetect(wire_receive_pcs5_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[119:100]),
+ .dataout(wire_receive_pcs5_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[5]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pcsdprioin_wire[2399:2000]),
+ .dprioout(wire_receive_pcs5_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[5]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[17:15]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs5_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs5_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs5_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs5_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[11:10]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[11:10]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[11:10]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[11:10]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs5_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs5_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs5_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[5]),
+ .phfifordenableout(wire_receive_pcs5_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[5]),
+ .phfiforesetout(wire_receive_pcs5_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[5]),
+ .phfifowrdisableout(wire_receive_pcs5_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[17:15]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[17:15]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[17:15]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[17:15]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[5]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs5_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs5_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[5]),
+ .pipephydonestatus(wire_receive_pcs5_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[11:10]),
+ .pipepowerstate(tx_pipepowerstateout[23:20]),
+ .pipestatetransdoneout(wire_receive_pcs5_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs5_pipestatus),
+ .powerdn(powerdn[11:10]),
+ .prbscidenable(rx_prbscidenable[5]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(wire_receive_pcs5_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[5]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs5_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[5]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[5]),
+ .rxfound(rx_pcs_rxfound_wire[11:10]),
+ .signaldetect(wire_receive_pcs5_signaldetect),
+ .signaldetected(rx_signaldetect_wire[5]),
+ .syncstatus(wire_receive_pcs5_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs5.align_pattern = "0101111100",
+ receive_pcs5.align_pattern_length = 10,
+ receive_pcs5.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs5.allow_align_polarity_inversion = "false",
+ receive_pcs5.allow_pipe_polarity_inversion = "true",
+ receive_pcs5.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs5.auto_spd_phystatus_notify_count = 14,
+ receive_pcs5.auto_spd_self_switch_enable = "false",
+ receive_pcs5.bit_slip_enable = "false",
+ receive_pcs5.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs5.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs5.byte_order_mode = "none",
+ receive_pcs5.byte_order_pad_pattern = "0",
+ receive_pcs5.byte_order_pattern = "0",
+ receive_pcs5.byte_order_pld_ctrl_enable = "false",
+ receive_pcs5.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs5.cdrctrl_cid_mode_enable = "true",
+ receive_pcs5.cdrctrl_enable = "true",
+ receive_pcs5.cdrctrl_rxvalid_mask = "true",
+ receive_pcs5.channel_bonding = "x8",
+ receive_pcs5.channel_number = ((starting_channel_number + 5) % 4),
+ receive_pcs5.channel_width = 8,
+ receive_pcs5.clk1_mux_select = "recovered clock",
+ receive_pcs5.clk2_mux_select = "digital reference clock",
+ receive_pcs5.core_clock_0ppm = "false",
+ receive_pcs5.datapath_low_latency_mode = "false",
+ receive_pcs5.datapath_protocol = "pipe",
+ receive_pcs5.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs5.dec_8b_10b_mode = "normal",
+ receive_pcs5.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs5.deskew_pattern = "0",
+ receive_pcs5.disable_auto_idle_insertion = "false",
+ receive_pcs5.disable_running_disp_in_word_align = "false",
+ receive_pcs5.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs5.dprio_config_mode = 6'h01,
+ receive_pcs5.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs5.elec_idle_infer_enable = "false",
+ receive_pcs5.elec_idle_num_com_detect = 3,
+ receive_pcs5.enable_bit_reversal = "false",
+ receive_pcs5.enable_deep_align = "false",
+ receive_pcs5.enable_deep_align_byte_swap = "false",
+ receive_pcs5.enable_self_test_mode = "false",
+ receive_pcs5.enable_true_complement_match_in_word_align = "false",
+ receive_pcs5.force_signal_detect_dig = "true",
+ receive_pcs5.hip_enable = "false",
+ receive_pcs5.infiniband_invalid_code = 0,
+ receive_pcs5.insert_pad_on_underflow = "false",
+ receive_pcs5.logical_channel_address = (starting_channel_number + 5),
+ receive_pcs5.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs5.num_align_cons_good_data = 16,
+ receive_pcs5.num_align_cons_pat = 4,
+ receive_pcs5.num_align_loss_sync_error = 17,
+ receive_pcs5.ph_fifo_low_latency_enable = "true",
+ receive_pcs5.ph_fifo_reg_mode = "false",
+ receive_pcs5.ph_fifo_xn_mapping0 = "none",
+ receive_pcs5.ph_fifo_xn_mapping1 = "up",
+ receive_pcs5.ph_fifo_xn_mapping2 = "none",
+ receive_pcs5.ph_fifo_xn_select = 1,
+ receive_pcs5.pipe_auto_speed_nego_enable = "false",
+ receive_pcs5.pipe_freq_scale_mode = "Frequency",
+ receive_pcs5.pma_done_count = 249950,
+ receive_pcs5.protocol_hint = "pcie",
+ receive_pcs5.rate_match_almost_empty_threshold = 11,
+ receive_pcs5.rate_match_almost_full_threshold = 13,
+ receive_pcs5.rate_match_back_to_back = "false",
+ receive_pcs5.rate_match_delete_threshold = 13,
+ receive_pcs5.rate_match_empty_threshold = 5,
+ receive_pcs5.rate_match_fifo_mode = "true",
+ receive_pcs5.rate_match_full_threshold = 20,
+ receive_pcs5.rate_match_insert_threshold = 11,
+ receive_pcs5.rate_match_ordered_set_based = "false",
+ receive_pcs5.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs5.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs5.rate_match_pattern_size = 20,
+ receive_pcs5.rate_match_pipe_enable = "true",
+ receive_pcs5.rate_match_reset_enable = "false",
+ receive_pcs5.rate_match_skip_set_based = "true",
+ receive_pcs5.rate_match_start_threshold = 7,
+ receive_pcs5.rd_clk_mux_select = "core clock",
+ receive_pcs5.recovered_clk_mux_select = "recovered clock",
+ receive_pcs5.run_length = 40,
+ receive_pcs5.run_length_enable = "true",
+ receive_pcs5.rx_detect_bypass = "false",
+ receive_pcs5.rx_phfifo_wait_cnt = 32,
+ receive_pcs5.rxstatus_error_report_mode = 1,
+ receive_pcs5.self_test_mode = "incremental",
+ receive_pcs5.use_alignment_state_machine = "true",
+ receive_pcs5.use_deserializer_double_data_mode = "false",
+ receive_pcs5.use_deskew_fifo = "false",
+ receive_pcs5.use_double_data_mode = "false",
+ receive_pcs5.use_parallel_loopback = "false",
+ receive_pcs5.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs5.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs6
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs6_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs6_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[6]),
+ .coreclkout(wire_receive_pcs6_coreclkout),
+ .ctrldetect(wire_receive_pcs6_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[139:120]),
+ .dataout(wire_receive_pcs6_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[6]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pcsdprioin_wire[2799:2400]),
+ .dprioout(wire_receive_pcs6_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[6]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[20:18]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs6_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs6_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs6_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs6_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[13:12]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[13:12]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[13:12]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[13:12]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs6_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs6_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs6_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[6]),
+ .phfifordenableout(wire_receive_pcs6_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[6]),
+ .phfiforesetout(wire_receive_pcs6_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[6]),
+ .phfifowrdisableout(wire_receive_pcs6_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[20:18]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[20:18]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[20:18]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[20:18]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[6]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs6_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs6_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[6]),
+ .pipephydonestatus(wire_receive_pcs6_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[13:12]),
+ .pipepowerstate(tx_pipepowerstateout[27:24]),
+ .pipestatetransdoneout(wire_receive_pcs6_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs6_pipestatus),
+ .powerdn(powerdn[13:12]),
+ .prbscidenable(rx_prbscidenable[6]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(wire_receive_pcs6_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[6]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs6_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[6]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[6]),
+ .rxfound(rx_pcs_rxfound_wire[13:12]),
+ .signaldetect(wire_receive_pcs6_signaldetect),
+ .signaldetected(rx_signaldetect_wire[6]),
+ .syncstatus(wire_receive_pcs6_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs6.align_pattern = "0101111100",
+ receive_pcs6.align_pattern_length = 10,
+ receive_pcs6.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs6.allow_align_polarity_inversion = "false",
+ receive_pcs6.allow_pipe_polarity_inversion = "true",
+ receive_pcs6.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs6.auto_spd_phystatus_notify_count = 14,
+ receive_pcs6.auto_spd_self_switch_enable = "false",
+ receive_pcs6.bit_slip_enable = "false",
+ receive_pcs6.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs6.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs6.byte_order_mode = "none",
+ receive_pcs6.byte_order_pad_pattern = "0",
+ receive_pcs6.byte_order_pattern = "0",
+ receive_pcs6.byte_order_pld_ctrl_enable = "false",
+ receive_pcs6.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs6.cdrctrl_cid_mode_enable = "true",
+ receive_pcs6.cdrctrl_enable = "true",
+ receive_pcs6.cdrctrl_rxvalid_mask = "true",
+ receive_pcs6.channel_bonding = "x8",
+ receive_pcs6.channel_number = ((starting_channel_number + 6) % 4),
+ receive_pcs6.channel_width = 8,
+ receive_pcs6.clk1_mux_select = "recovered clock",
+ receive_pcs6.clk2_mux_select = "digital reference clock",
+ receive_pcs6.core_clock_0ppm = "false",
+ receive_pcs6.datapath_low_latency_mode = "false",
+ receive_pcs6.datapath_protocol = "pipe",
+ receive_pcs6.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs6.dec_8b_10b_mode = "normal",
+ receive_pcs6.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs6.deskew_pattern = "0",
+ receive_pcs6.disable_auto_idle_insertion = "false",
+ receive_pcs6.disable_running_disp_in_word_align = "false",
+ receive_pcs6.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs6.dprio_config_mode = 6'h01,
+ receive_pcs6.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs6.elec_idle_infer_enable = "false",
+ receive_pcs6.elec_idle_num_com_detect = 3,
+ receive_pcs6.enable_bit_reversal = "false",
+ receive_pcs6.enable_deep_align = "false",
+ receive_pcs6.enable_deep_align_byte_swap = "false",
+ receive_pcs6.enable_self_test_mode = "false",
+ receive_pcs6.enable_true_complement_match_in_word_align = "false",
+ receive_pcs6.force_signal_detect_dig = "true",
+ receive_pcs6.hip_enable = "false",
+ receive_pcs6.infiniband_invalid_code = 0,
+ receive_pcs6.insert_pad_on_underflow = "false",
+ receive_pcs6.logical_channel_address = (starting_channel_number + 6),
+ receive_pcs6.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs6.num_align_cons_good_data = 16,
+ receive_pcs6.num_align_cons_pat = 4,
+ receive_pcs6.num_align_loss_sync_error = 17,
+ receive_pcs6.ph_fifo_low_latency_enable = "true",
+ receive_pcs6.ph_fifo_reg_mode = "false",
+ receive_pcs6.ph_fifo_xn_mapping0 = "none",
+ receive_pcs6.ph_fifo_xn_mapping1 = "up",
+ receive_pcs6.ph_fifo_xn_mapping2 = "none",
+ receive_pcs6.ph_fifo_xn_select = 1,
+ receive_pcs6.pipe_auto_speed_nego_enable = "false",
+ receive_pcs6.pipe_freq_scale_mode = "Frequency",
+ receive_pcs6.pma_done_count = 249950,
+ receive_pcs6.protocol_hint = "pcie",
+ receive_pcs6.rate_match_almost_empty_threshold = 11,
+ receive_pcs6.rate_match_almost_full_threshold = 13,
+ receive_pcs6.rate_match_back_to_back = "false",
+ receive_pcs6.rate_match_delete_threshold = 13,
+ receive_pcs6.rate_match_empty_threshold = 5,
+ receive_pcs6.rate_match_fifo_mode = "true",
+ receive_pcs6.rate_match_full_threshold = 20,
+ receive_pcs6.rate_match_insert_threshold = 11,
+ receive_pcs6.rate_match_ordered_set_based = "false",
+ receive_pcs6.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs6.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs6.rate_match_pattern_size = 20,
+ receive_pcs6.rate_match_pipe_enable = "true",
+ receive_pcs6.rate_match_reset_enable = "false",
+ receive_pcs6.rate_match_skip_set_based = "true",
+ receive_pcs6.rate_match_start_threshold = 7,
+ receive_pcs6.rd_clk_mux_select = "core clock",
+ receive_pcs6.recovered_clk_mux_select = "recovered clock",
+ receive_pcs6.run_length = 40,
+ receive_pcs6.run_length_enable = "true",
+ receive_pcs6.rx_detect_bypass = "false",
+ receive_pcs6.rx_phfifo_wait_cnt = 32,
+ receive_pcs6.rxstatus_error_report_mode = 1,
+ receive_pcs6.self_test_mode = "incremental",
+ receive_pcs6.use_alignment_state_machine = "true",
+ receive_pcs6.use_deserializer_double_data_mode = "false",
+ receive_pcs6.use_deskew_fifo = "false",
+ receive_pcs6.use_double_data_mode = "false",
+ receive_pcs6.use_parallel_loopback = "false",
+ receive_pcs6.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs6.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs7
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs7_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs7_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[7]),
+ .coreclkout(wire_receive_pcs7_coreclkout),
+ .ctrldetect(wire_receive_pcs7_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[159:140]),
+ .dataout(wire_receive_pcs7_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[7]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pcsdprioin_wire[3199:2800]),
+ .dprioout(wire_receive_pcs7_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[7]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[23:21]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpphfifobyteselout(wire_receive_pcs7_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(wire_receive_pcs7_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs7_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs7_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[15:14]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[15:14]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[15:14]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[15:14]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs7_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs7_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs7_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[7]),
+ .phfifordenableout(wire_receive_pcs7_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[7]),
+ .phfiforesetout(wire_receive_pcs7_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[7]),
+ .phfifowrdisableout(wire_receive_pcs7_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[23:21]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[23:21]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[23:21]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[23:21]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[7]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs7_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs7_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[7]),
+ .pipephydonestatus(wire_receive_pcs7_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[15:14]),
+ .pipepowerstate(tx_pipepowerstateout[31:28]),
+ .pipestatetransdoneout(wire_receive_pcs7_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs7_pipestatus),
+ .powerdn(powerdn[15:14]),
+ .prbscidenable(rx_prbscidenable[7]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(wire_receive_pcs7_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[7]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs7_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[7]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[7]),
+ .rxfound(rx_pcs_rxfound_wire[15:14]),
+ .signaldetect(wire_receive_pcs7_signaldetect),
+ .signaldetected(rx_signaldetect_wire[7]),
+ .syncstatus(wire_receive_pcs7_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs7.align_pattern = "0101111100",
+ receive_pcs7.align_pattern_length = 10,
+ receive_pcs7.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs7.allow_align_polarity_inversion = "false",
+ receive_pcs7.allow_pipe_polarity_inversion = "true",
+ receive_pcs7.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs7.auto_spd_phystatus_notify_count = 14,
+ receive_pcs7.auto_spd_self_switch_enable = "false",
+ receive_pcs7.bit_slip_enable = "false",
+ receive_pcs7.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs7.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs7.byte_order_mode = "none",
+ receive_pcs7.byte_order_pad_pattern = "0",
+ receive_pcs7.byte_order_pattern = "0",
+ receive_pcs7.byte_order_pld_ctrl_enable = "false",
+ receive_pcs7.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs7.cdrctrl_cid_mode_enable = "true",
+ receive_pcs7.cdrctrl_enable = "true",
+ receive_pcs7.cdrctrl_rxvalid_mask = "true",
+ receive_pcs7.channel_bonding = "x8",
+ receive_pcs7.channel_number = ((starting_channel_number + 7) % 4),
+ receive_pcs7.channel_width = 8,
+ receive_pcs7.clk1_mux_select = "recovered clock",
+ receive_pcs7.clk2_mux_select = "digital reference clock",
+ receive_pcs7.core_clock_0ppm = "false",
+ receive_pcs7.datapath_low_latency_mode = "false",
+ receive_pcs7.datapath_protocol = "pipe",
+ receive_pcs7.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs7.dec_8b_10b_mode = "normal",
+ receive_pcs7.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs7.deskew_pattern = "0",
+ receive_pcs7.disable_auto_idle_insertion = "false",
+ receive_pcs7.disable_running_disp_in_word_align = "false",
+ receive_pcs7.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs7.dprio_config_mode = 6'h01,
+ receive_pcs7.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs7.elec_idle_infer_enable = "false",
+ receive_pcs7.elec_idle_num_com_detect = 3,
+ receive_pcs7.enable_bit_reversal = "false",
+ receive_pcs7.enable_deep_align = "false",
+ receive_pcs7.enable_deep_align_byte_swap = "false",
+ receive_pcs7.enable_self_test_mode = "false",
+ receive_pcs7.enable_true_complement_match_in_word_align = "false",
+ receive_pcs7.force_signal_detect_dig = "true",
+ receive_pcs7.hip_enable = "false",
+ receive_pcs7.infiniband_invalid_code = 0,
+ receive_pcs7.insert_pad_on_underflow = "false",
+ receive_pcs7.logical_channel_address = (starting_channel_number + 7),
+ receive_pcs7.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs7.num_align_cons_good_data = 16,
+ receive_pcs7.num_align_cons_pat = 4,
+ receive_pcs7.num_align_loss_sync_error = 17,
+ receive_pcs7.ph_fifo_low_latency_enable = "true",
+ receive_pcs7.ph_fifo_reg_mode = "false",
+ receive_pcs7.ph_fifo_xn_mapping0 = "none",
+ receive_pcs7.ph_fifo_xn_mapping1 = "up",
+ receive_pcs7.ph_fifo_xn_mapping2 = "none",
+ receive_pcs7.ph_fifo_xn_select = 1,
+ receive_pcs7.pipe_auto_speed_nego_enable = "false",
+ receive_pcs7.pipe_freq_scale_mode = "Frequency",
+ receive_pcs7.pma_done_count = 249950,
+ receive_pcs7.protocol_hint = "pcie",
+ receive_pcs7.rate_match_almost_empty_threshold = 11,
+ receive_pcs7.rate_match_almost_full_threshold = 13,
+ receive_pcs7.rate_match_back_to_back = "false",
+ receive_pcs7.rate_match_delete_threshold = 13,
+ receive_pcs7.rate_match_empty_threshold = 5,
+ receive_pcs7.rate_match_fifo_mode = "true",
+ receive_pcs7.rate_match_full_threshold = 20,
+ receive_pcs7.rate_match_insert_threshold = 11,
+ receive_pcs7.rate_match_ordered_set_based = "false",
+ receive_pcs7.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs7.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs7.rate_match_pattern_size = 20,
+ receive_pcs7.rate_match_pipe_enable = "true",
+ receive_pcs7.rate_match_reset_enable = "false",
+ receive_pcs7.rate_match_skip_set_based = "true",
+ receive_pcs7.rate_match_start_threshold = 7,
+ receive_pcs7.rd_clk_mux_select = "core clock",
+ receive_pcs7.recovered_clk_mux_select = "recovered clock",
+ receive_pcs7.run_length = 40,
+ receive_pcs7.run_length_enable = "true",
+ receive_pcs7.rx_detect_bypass = "false",
+ receive_pcs7.rx_phfifo_wait_cnt = 32,
+ receive_pcs7.rxstatus_error_report_mode = 1,
+ receive_pcs7.self_test_mode = "incremental",
+ receive_pcs7.use_alignment_state_machine = "true",
+ receive_pcs7.use_deserializer_double_data_mode = "false",
+ receive_pcs7.use_deskew_fifo = "false",
+ receive_pcs7.use_double_data_mode = "false",
+ receive_pcs7.use_parallel_loopback = "false",
+ receive_pcs7.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs7.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.adaptive_equalization_mode = "none",
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "true",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.eyemon_bandwidth = 0,
+ receive_pma0.force_signal_detect = "false",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "pcie",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis = 4,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma0.signal_detect_loss_threshold = 3,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma1_analogtestbus),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(wire_receive_pma1_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.adaptive_equalization_mode = "none",
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h01,
+ receive_pma1.enable_ltd = "false",
+ receive_pma1.enable_ltr = "true",
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eqa_ctrl = 0,
+ receive_pma1.eqb_ctrl = 0,
+ receive_pma1.eqc_ctrl = 0,
+ receive_pma1.eqd_ctrl = 0,
+ receive_pma1.eqv_ctrl = 0,
+ receive_pma1.eyemon_bandwidth = 0,
+ receive_pma1.force_signal_detect = "false",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 1,
+ receive_pma1.ppmselect = 32,
+ receive_pma1.protocol_hint = "pcie",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis = 4,
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma1.signal_detect_loss_threshold = 3,
+ receive_pma1.termination = "OCT 100 Ohms",
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_external_termination = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma2_analogtestbus),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(wire_receive_pma2_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma2_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.adaptive_equalization_mode = "none",
+ receive_pma2.allow_serial_loopback = "false",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = "0.82V",
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h01,
+ receive_pma2.enable_ltd = "false",
+ receive_pma2.enable_ltr = "true",
+ receive_pma2.eq_dc_gain = 3,
+ receive_pma2.eqa_ctrl = 0,
+ receive_pma2.eqb_ctrl = 0,
+ receive_pma2.eqc_ctrl = 0,
+ receive_pma2.eqd_ctrl = 0,
+ receive_pma2.eqv_ctrl = 0,
+ receive_pma2.eyemon_bandwidth = 0,
+ receive_pma2.force_signal_detect = "false",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 1,
+ receive_pma2.ppmselect = 32,
+ receive_pma2.protocol_hint = "pcie",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis = 4,
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma2.signal_detect_loss_threshold = 3,
+ receive_pma2.termination = "OCT 100 Ohms",
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_external_termination = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma3_analogtestbus),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_receive_pma3_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma3_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.adaptive_equalization_mode = "none",
+ receive_pma3.allow_serial_loopback = "false",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = "0.82V",
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h01,
+ receive_pma3.enable_ltd = "false",
+ receive_pma3.enable_ltr = "true",
+ receive_pma3.eq_dc_gain = 3,
+ receive_pma3.eqa_ctrl = 0,
+ receive_pma3.eqb_ctrl = 0,
+ receive_pma3.eqc_ctrl = 0,
+ receive_pma3.eqd_ctrl = 0,
+ receive_pma3.eqv_ctrl = 0,
+ receive_pma3.eyemon_bandwidth = 0,
+ receive_pma3.force_signal_detect = "false",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 1,
+ receive_pma3.ppmselect = 32,
+ receive_pma3.protocol_hint = "pcie",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis = 4,
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma3.signal_detect_loss_threshold = 3,
+ receive_pma3.termination = "OCT 100 Ohms",
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_external_termination = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma4
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma4_analogtestbus),
+ .clockout(wire_receive_pma4_clockout),
+ .datain(rx_datain[4]),
+ .dataout(wire_receive_pma4_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[19:16]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pmadprioin_wire[2099:1800]),
+ .dprioout(wire_receive_pma4_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[4]),
+ .locktoref(rx_locktorefclk_wire[4]),
+ .locktorefout(wire_receive_pma4_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[4]),
+ .powerdn(cent_unit_rxibpowerdn[6]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[4]),
+ .recoverdatain(pll_ch_dataout_wire[9:8]),
+ .recoverdataout(wire_receive_pma4_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[6]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma4_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma4.adaptive_equalization_mode = "none",
+ receive_pma4.allow_serial_loopback = "false",
+ receive_pma4.channel_number = ((starting_channel_number + 4) % 4),
+ receive_pma4.channel_type = "auto",
+ receive_pma4.common_mode = "0.82V",
+ receive_pma4.deserialization_factor = 10,
+ receive_pma4.dprio_config_mode = 6'h01,
+ receive_pma4.enable_ltd = "false",
+ receive_pma4.enable_ltr = "true",
+ receive_pma4.eq_dc_gain = 3,
+ receive_pma4.eqa_ctrl = 0,
+ receive_pma4.eqb_ctrl = 0,
+ receive_pma4.eqc_ctrl = 0,
+ receive_pma4.eqd_ctrl = 0,
+ receive_pma4.eqv_ctrl = 0,
+ receive_pma4.eyemon_bandwidth = 0,
+ receive_pma4.force_signal_detect = "false",
+ receive_pma4.logical_channel_address = (starting_channel_number + 4),
+ receive_pma4.low_speed_test_select = 0,
+ receive_pma4.offset_cancellation = 1,
+ receive_pma4.ppmselect = 32,
+ receive_pma4.protocol_hint = "pcie",
+ receive_pma4.send_direct_reverse_serial_loopback = "None",
+ receive_pma4.signal_detect_hysteresis = 4,
+ receive_pma4.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma4.signal_detect_loss_threshold = 3,
+ receive_pma4.termination = "OCT 100 Ohms",
+ receive_pma4.use_deser_double_data_width = "false",
+ receive_pma4.use_external_termination = "false",
+ receive_pma4.use_pma_direct = "false",
+ receive_pma4.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma5
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma5_analogtestbus),
+ .clockout(wire_receive_pma5_clockout),
+ .datain(rx_datain[5]),
+ .dataout(wire_receive_pma5_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[23:20]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pmadprioin_wire[2399:2100]),
+ .dprioout(wire_receive_pma5_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[5]),
+ .locktoref(rx_locktorefclk_wire[5]),
+ .locktorefout(wire_receive_pma5_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[5]),
+ .powerdn(cent_unit_rxibpowerdn[7]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[5]),
+ .recoverdatain(pll_ch_dataout_wire[11:10]),
+ .recoverdataout(wire_receive_pma5_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[7]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma5_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma5.adaptive_equalization_mode = "none",
+ receive_pma5.allow_serial_loopback = "false",
+ receive_pma5.channel_number = ((starting_channel_number + 5) % 4),
+ receive_pma5.channel_type = "auto",
+ receive_pma5.common_mode = "0.82V",
+ receive_pma5.deserialization_factor = 10,
+ receive_pma5.dprio_config_mode = 6'h01,
+ receive_pma5.enable_ltd = "false",
+ receive_pma5.enable_ltr = "true",
+ receive_pma5.eq_dc_gain = 3,
+ receive_pma5.eqa_ctrl = 0,
+ receive_pma5.eqb_ctrl = 0,
+ receive_pma5.eqc_ctrl = 0,
+ receive_pma5.eqd_ctrl = 0,
+ receive_pma5.eqv_ctrl = 0,
+ receive_pma5.eyemon_bandwidth = 0,
+ receive_pma5.force_signal_detect = "false",
+ receive_pma5.logical_channel_address = (starting_channel_number + 5),
+ receive_pma5.low_speed_test_select = 0,
+ receive_pma5.offset_cancellation = 1,
+ receive_pma5.ppmselect = 32,
+ receive_pma5.protocol_hint = "pcie",
+ receive_pma5.send_direct_reverse_serial_loopback = "None",
+ receive_pma5.signal_detect_hysteresis = 4,
+ receive_pma5.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma5.signal_detect_loss_threshold = 3,
+ receive_pma5.termination = "OCT 100 Ohms",
+ receive_pma5.use_deser_double_data_width = "false",
+ receive_pma5.use_external_termination = "false",
+ receive_pma5.use_pma_direct = "false",
+ receive_pma5.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma6
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma6_analogtestbus),
+ .clockout(wire_receive_pma6_clockout),
+ .datain(rx_datain[6]),
+ .dataout(wire_receive_pma6_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[27:24]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pmadprioin_wire[2699:2400]),
+ .dprioout(wire_receive_pma6_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[6]),
+ .locktoref(rx_locktorefclk_wire[6]),
+ .locktorefout(wire_receive_pma6_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[6]),
+ .powerdn(cent_unit_rxibpowerdn[8]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[6]),
+ .recoverdatain(pll_ch_dataout_wire[13:12]),
+ .recoverdataout(wire_receive_pma6_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[8]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma6_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma6.adaptive_equalization_mode = "none",
+ receive_pma6.allow_serial_loopback = "false",
+ receive_pma6.channel_number = ((starting_channel_number + 6) % 4),
+ receive_pma6.channel_type = "auto",
+ receive_pma6.common_mode = "0.82V",
+ receive_pma6.deserialization_factor = 10,
+ receive_pma6.dprio_config_mode = 6'h01,
+ receive_pma6.enable_ltd = "false",
+ receive_pma6.enable_ltr = "true",
+ receive_pma6.eq_dc_gain = 3,
+ receive_pma6.eqa_ctrl = 0,
+ receive_pma6.eqb_ctrl = 0,
+ receive_pma6.eqc_ctrl = 0,
+ receive_pma6.eqd_ctrl = 0,
+ receive_pma6.eqv_ctrl = 0,
+ receive_pma6.eyemon_bandwidth = 0,
+ receive_pma6.force_signal_detect = "false",
+ receive_pma6.logical_channel_address = (starting_channel_number + 6),
+ receive_pma6.low_speed_test_select = 0,
+ receive_pma6.offset_cancellation = 1,
+ receive_pma6.ppmselect = 32,
+ receive_pma6.protocol_hint = "pcie",
+ receive_pma6.send_direct_reverse_serial_loopback = "None",
+ receive_pma6.signal_detect_hysteresis = 4,
+ receive_pma6.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma6.signal_detect_loss_threshold = 3,
+ receive_pma6.termination = "OCT 100 Ohms",
+ receive_pma6.use_deser_double_data_width = "false",
+ receive_pma6.use_external_termination = "false",
+ receive_pma6.use_pma_direct = "false",
+ receive_pma6.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma7
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma7_analogtestbus),
+ .clockout(wire_receive_pma7_clockout),
+ .datain(rx_datain[7]),
+ .dataout(wire_receive_pma7_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[31:28]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pmadprioin_wire[2999:2700]),
+ .dprioout(wire_receive_pma7_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[7]),
+ .locktoref(rx_locktorefclk_wire[7]),
+ .locktorefout(wire_receive_pma7_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[7]),
+ .powerdn(cent_unit_rxibpowerdn[9]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[7]),
+ .recoverdatain(pll_ch_dataout_wire[15:14]),
+ .recoverdataout(wire_receive_pma7_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[9]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma7_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma7.adaptive_equalization_mode = "none",
+ receive_pma7.allow_serial_loopback = "false",
+ receive_pma7.channel_number = ((starting_channel_number + 7) % 4),
+ receive_pma7.channel_type = "auto",
+ receive_pma7.common_mode = "0.82V",
+ receive_pma7.deserialization_factor = 10,
+ receive_pma7.dprio_config_mode = 6'h01,
+ receive_pma7.enable_ltd = "false",
+ receive_pma7.enable_ltr = "true",
+ receive_pma7.eq_dc_gain = 3,
+ receive_pma7.eqa_ctrl = 0,
+ receive_pma7.eqb_ctrl = 0,
+ receive_pma7.eqc_ctrl = 0,
+ receive_pma7.eqd_ctrl = 0,
+ receive_pma7.eqv_ctrl = 0,
+ receive_pma7.eyemon_bandwidth = 0,
+ receive_pma7.force_signal_detect = "false",
+ receive_pma7.logical_channel_address = (starting_channel_number + 7),
+ receive_pma7.low_speed_test_select = 0,
+ receive_pma7.offset_cancellation = 1,
+ receive_pma7.ppmselect = 32,
+ receive_pma7.protocol_hint = "pcie",
+ receive_pma7.send_direct_reverse_serial_loopback = "None",
+ receive_pma7.signal_detect_hysteresis = 4,
+ receive_pma7.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma7.signal_detect_loss_threshold = 3,
+ receive_pma7.termination = "OCT 100 Ohms",
+ receive_pma7.use_deser_double_data_width = "false",
+ receive_pma7.use_external_termination = "false",
+ receive_pma7.use_pma_direct = "false",
+ receive_pma7.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
+ .datain({{32{1'b0}}, tx_datain_wire[7:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[0]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(wire_transmit_pcs0_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs0_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs0_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs0_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[1:0]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[1:0]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[1:0]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[1:0]),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "x8",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 8,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "false",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[1]}),
+ .datain({{32{1'b0}}, tx_datain_wire[15:8]}),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[1]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(wire_transmit_pcs1_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[1]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .forceelecidleout(wire_transmit_pcs1_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(wire_transmit_pcs1_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs1_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs1_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs1_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[3:2]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[3:2]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[3:2]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[3:2]),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[1]),
+ .pipetxdeemph(tx_pipedeemph[1]),
+ .pipetxmargin(tx_pipemargin[5:3]),
+ .pipetxswing(tx_pipeswing[1]),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.auto_spd_self_switch_enable = "false",
+ transmit_pcs1.bitslip_enable = "false",
+ transmit_pcs1.channel_bonding = "x8",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 8,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h01,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "false",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[2]}),
+ .datain({{32{1'b0}}, tx_datain_wire[23:16]}),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(tx_detectrxloop[2]),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[2]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(wire_transmit_pcs2_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[8:6]),
+ .enrevparallellpbk(tx_revparallellpbken[2]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .forceelecidleout(wire_transmit_pcs2_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(wire_transmit_pcs2_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs2_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs2_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs2_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[5:4]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[5:4]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[5:4]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[5:4]),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs2_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[2]),
+ .pipetxdeemph(tx_pipedeemph[2]),
+ .pipetxmargin(tx_pipemargin[8:6]),
+ .pipetxswing(tx_pipeswing[2]),
+ .powerdn(powerdn[5:4]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[59:40]),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "false",
+ transmit_pcs2.auto_spd_self_switch_enable = "false",
+ transmit_pcs2.bitslip_enable = "false",
+ transmit_pcs2.channel_bonding = "x8",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 8,
+ transmit_pcs2.core_clock_0ppm = "false",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "pipe",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "new",
+ transmit_pcs2.dprio_config_mode = 6'h01,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "true",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "pcie",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "false",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[3]}),
+ .datain({{32{1'b0}}, tx_datain_wire[31:24]}),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(tx_detectrxloop[3]),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[3]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(wire_transmit_pcs3_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[11:9]),
+ .enrevparallellpbk(tx_revparallellpbken[3]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[3]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .forceelecidleout(wire_transmit_pcs3_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(wire_transmit_pcs3_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs3_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs3_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs3_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[7:6]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[7:6]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[7:6]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[7:6]),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs3_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[3]),
+ .pipetxdeemph(tx_pipedeemph[3]),
+ .pipetxmargin(tx_pipemargin[11:9]),
+ .pipetxswing(tx_pipeswing[3]),
+ .powerdn(powerdn[7:6]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[79:60]),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "false",
+ transmit_pcs3.auto_spd_self_switch_enable = "false",
+ transmit_pcs3.bitslip_enable = "false",
+ transmit_pcs3.channel_bonding = "x8",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 8,
+ transmit_pcs3.core_clock_0ppm = "false",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "pipe",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "new",
+ transmit_pcs3.dprio_config_mode = 6'h01,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "true",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "pcie",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "false",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs4
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[4]),
+ .coreclkout(wire_transmit_pcs4_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[4]}),
+ .datain({{32{1'b0}}, tx_datain_wire[39:32]}),
+ .dataout(wire_transmit_pcs4_dataout),
+ .detectrxloop(tx_detectrxloop[4]),
+ .digitalreset(tx_digitalreset_out[4]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[4]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_dprioin_wire[749:600]),
+ .dprioout(wire_transmit_pcs4_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[14:12]),
+ .enrevparallellpbk(tx_revparallellpbken[4]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[4]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[4]),
+ .forceelecidleout(wire_transmit_pcs4_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs4_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[4]),
+ .iqpphfifobyteselout(wire_transmit_pcs4_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs4_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs4_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs4_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[9:8]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[9:8]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[9:8]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[9:8]),
+ .localrefclk(tx_localrefclk[4]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[4]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[4]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs4_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[4]),
+ .phfiforesetout(wire_transmit_pcs4_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs4_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[14:12]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[14:12]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[14:12]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[14:12]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs4_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs4_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs4_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[4]),
+ .pipetxdeemph(tx_pipedeemph[4]),
+ .pipetxmargin(tx_pipemargin[14:12]),
+ .pipetxswing(tx_pipeswing[4]),
+ .powerdn(powerdn[9:8]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[99:80]),
+ .txdetectrx(wire_transmit_pcs4_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[4]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[39:32]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs4.allow_polarity_inversion = "false",
+ transmit_pcs4.auto_spd_self_switch_enable = "false",
+ transmit_pcs4.bitslip_enable = "false",
+ transmit_pcs4.channel_bonding = "x8",
+ transmit_pcs4.channel_number = ((starting_channel_number + 4) % 4),
+ transmit_pcs4.channel_width = 8,
+ transmit_pcs4.core_clock_0ppm = "false",
+ transmit_pcs4.datapath_low_latency_mode = "false",
+ transmit_pcs4.datapath_protocol = "pipe",
+ transmit_pcs4.disable_ph_low_latency_mode = "false",
+ transmit_pcs4.disparity_mode = "new",
+ transmit_pcs4.dprio_config_mode = 6'h01,
+ transmit_pcs4.elec_idle_delay = 6,
+ transmit_pcs4.enable_bit_reversal = "false",
+ transmit_pcs4.enable_idle_selection = "false",
+ transmit_pcs4.enable_reverse_parallel_loopback = "true",
+ transmit_pcs4.enable_self_test_mode = "false",
+ transmit_pcs4.enable_symbol_swap = "false",
+ transmit_pcs4.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs4.enc_8b_10b_mode = "normal",
+ transmit_pcs4.force_echar = "false",
+ transmit_pcs4.force_kchar = "false",
+ transmit_pcs4.hip_enable = "false",
+ transmit_pcs4.iqp_ph_fifo_xn_select = 1,
+ transmit_pcs4.logical_channel_address = (starting_channel_number + 4),
+ transmit_pcs4.ph_fifo_reg_mode = "false",
+ transmit_pcs4.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs4.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs4.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs4.ph_fifo_xn_select = 1,
+ transmit_pcs4.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs4.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs4.prbs_cid_pattern = "false",
+ transmit_pcs4.protocol_hint = "pcie",
+ transmit_pcs4.refclk_select = "cmu_clock_divider",
+ transmit_pcs4.self_test_mode = "incremental",
+ transmit_pcs4.use_double_data_mode = "false",
+ transmit_pcs4.use_serializer_double_data_mode = "false",
+ transmit_pcs4.wr_clk_mux_select = "core_clk",
+ transmit_pcs4.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs5
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[5]),
+ .coreclkout(wire_transmit_pcs5_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[5]}),
+ .datain({{32{1'b0}}, tx_datain_wire[47:40]}),
+ .dataout(wire_transmit_pcs5_dataout),
+ .detectrxloop(tx_detectrxloop[5]),
+ .digitalreset(tx_digitalreset_out[5]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[5]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_dprioin_wire[899:750]),
+ .dprioout(wire_transmit_pcs5_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[17:15]),
+ .enrevparallellpbk(tx_revparallellpbken[5]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[5]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[5]),
+ .forceelecidleout(wire_transmit_pcs5_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs5_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[5]),
+ .iqpphfifobyteselout(wire_transmit_pcs5_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs5_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs5_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs5_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[11:10]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[11:10]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[11:10]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[11:10]),
+ .localrefclk(tx_localrefclk[5]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[5]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[5]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs5_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[5]),
+ .phfiforesetout(wire_transmit_pcs5_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs5_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[17:15]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[17:15]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[17:15]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[17:15]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs5_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs5_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs5_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[5]),
+ .pipetxdeemph(tx_pipedeemph[5]),
+ .pipetxmargin(tx_pipemargin[17:15]),
+ .pipetxswing(tx_pipeswing[5]),
+ .powerdn(powerdn[11:10]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[119:100]),
+ .txdetectrx(wire_transmit_pcs5_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[5]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[47:40]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs5.allow_polarity_inversion = "false",
+ transmit_pcs5.auto_spd_self_switch_enable = "false",
+ transmit_pcs5.bitslip_enable = "false",
+ transmit_pcs5.channel_bonding = "x8",
+ transmit_pcs5.channel_number = ((starting_channel_number + 5) % 4),
+ transmit_pcs5.channel_width = 8,
+ transmit_pcs5.core_clock_0ppm = "false",
+ transmit_pcs5.datapath_low_latency_mode = "false",
+ transmit_pcs5.datapath_protocol = "pipe",
+ transmit_pcs5.disable_ph_low_latency_mode = "false",
+ transmit_pcs5.disparity_mode = "new",
+ transmit_pcs5.dprio_config_mode = 6'h01,
+ transmit_pcs5.elec_idle_delay = 6,
+ transmit_pcs5.enable_bit_reversal = "false",
+ transmit_pcs5.enable_idle_selection = "false",
+ transmit_pcs5.enable_reverse_parallel_loopback = "true",
+ transmit_pcs5.enable_self_test_mode = "false",
+ transmit_pcs5.enable_symbol_swap = "false",
+ transmit_pcs5.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs5.enc_8b_10b_mode = "normal",
+ transmit_pcs5.force_echar = "false",
+ transmit_pcs5.force_kchar = "false",
+ transmit_pcs5.hip_enable = "false",
+ transmit_pcs5.logical_channel_address = (starting_channel_number + 5),
+ transmit_pcs5.ph_fifo_reg_mode = "false",
+ transmit_pcs5.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs5.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs5.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs5.ph_fifo_xn_select = 1,
+ transmit_pcs5.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs5.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs5.prbs_cid_pattern = "false",
+ transmit_pcs5.protocol_hint = "pcie",
+ transmit_pcs5.refclk_select = "cmu_clock_divider",
+ transmit_pcs5.self_test_mode = "incremental",
+ transmit_pcs5.use_double_data_mode = "false",
+ transmit_pcs5.use_serializer_double_data_mode = "false",
+ transmit_pcs5.wr_clk_mux_select = "core_clk",
+ transmit_pcs5.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs6
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[6]),
+ .coreclkout(wire_transmit_pcs6_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[6]}),
+ .datain({{32{1'b0}}, tx_datain_wire[55:48]}),
+ .dataout(wire_transmit_pcs6_dataout),
+ .detectrxloop(tx_detectrxloop[6]),
+ .digitalreset(tx_digitalreset_out[6]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[6]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_dprioin_wire[1049:900]),
+ .dprioout(wire_transmit_pcs6_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[20:18]),
+ .enrevparallellpbk(tx_revparallellpbken[6]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[6]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[6]),
+ .forceelecidleout(wire_transmit_pcs6_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs6_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[6]),
+ .iqpphfifobyteselout(wire_transmit_pcs6_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs6_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs6_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs6_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[13:12]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[13:12]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[13:12]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[13:12]),
+ .localrefclk(tx_localrefclk[6]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[6]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[6]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs6_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[6]),
+ .phfiforesetout(wire_transmit_pcs6_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs6_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[20:18]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[20:18]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[20:18]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[20:18]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs6_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs6_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs6_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[6]),
+ .pipetxdeemph(tx_pipedeemph[6]),
+ .pipetxmargin(tx_pipemargin[20:18]),
+ .pipetxswing(tx_pipeswing[6]),
+ .powerdn(powerdn[13:12]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[139:120]),
+ .txdetectrx(wire_transmit_pcs6_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[6]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[55:48]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs6.allow_polarity_inversion = "false",
+ transmit_pcs6.auto_spd_self_switch_enable = "false",
+ transmit_pcs6.bitslip_enable = "false",
+ transmit_pcs6.channel_bonding = "x8",
+ transmit_pcs6.channel_number = ((starting_channel_number + 6) % 4),
+ transmit_pcs6.channel_width = 8,
+ transmit_pcs6.core_clock_0ppm = "false",
+ transmit_pcs6.datapath_low_latency_mode = "false",
+ transmit_pcs6.datapath_protocol = "pipe",
+ transmit_pcs6.disable_ph_low_latency_mode = "false",
+ transmit_pcs6.disparity_mode = "new",
+ transmit_pcs6.dprio_config_mode = 6'h01,
+ transmit_pcs6.elec_idle_delay = 6,
+ transmit_pcs6.enable_bit_reversal = "false",
+ transmit_pcs6.enable_idle_selection = "false",
+ transmit_pcs6.enable_reverse_parallel_loopback = "true",
+ transmit_pcs6.enable_self_test_mode = "false",
+ transmit_pcs6.enable_symbol_swap = "false",
+ transmit_pcs6.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs6.enc_8b_10b_mode = "normal",
+ transmit_pcs6.force_echar = "false",
+ transmit_pcs6.force_kchar = "false",
+ transmit_pcs6.hip_enable = "false",
+ transmit_pcs6.logical_channel_address = (starting_channel_number + 6),
+ transmit_pcs6.ph_fifo_reg_mode = "false",
+ transmit_pcs6.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs6.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs6.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs6.ph_fifo_xn_select = 1,
+ transmit_pcs6.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs6.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs6.prbs_cid_pattern = "false",
+ transmit_pcs6.protocol_hint = "pcie",
+ transmit_pcs6.refclk_select = "cmu_clock_divider",
+ transmit_pcs6.self_test_mode = "incremental",
+ transmit_pcs6.use_double_data_mode = "false",
+ transmit_pcs6.use_serializer_double_data_mode = "false",
+ transmit_pcs6.wr_clk_mux_select = "core_clk",
+ transmit_pcs6.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs7
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[7]),
+ .coreclkout(wire_transmit_pcs7_coreclkout),
+ .ctrlenable({{3{1'b0}}, tx_ctrlenable[7]}),
+ .datain({{32{1'b0}}, tx_datain_wire[63:56]}),
+ .dataout(wire_transmit_pcs7_dataout),
+ .detectrxloop(tx_detectrxloop[7]),
+ .digitalreset(tx_digitalreset_out[7]),
+ .dispval({{3{1'b0}}, tx_forceelecidle[7]}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_dprioin_wire[1199:1050]),
+ .dprioout(wire_transmit_pcs7_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[23:21]),
+ .enrevparallellpbk(tx_revparallellpbken[7]),
+ .forcedisp({{3{1'b0}}, tx_forcedisp_wire[7]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[7]),
+ .forceelecidleout(wire_transmit_pcs7_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs7_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[7]),
+ .iqpphfifobyteselout(wire_transmit_pcs7_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs7_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs7_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs7_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[15:14]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[15:14]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[15:14]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[15:14]),
+ .localrefclk(tx_localrefclk[7]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[7]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[7]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs7_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[7]),
+ .phfiforesetout(wire_transmit_pcs7_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs7_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[23:21]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[23:21]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[23:21]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[23:21]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs7_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs7_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs7_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[7]),
+ .pipetxdeemph(tx_pipedeemph[7]),
+ .pipetxmargin(tx_pipemargin[23:21]),
+ .pipetxswing(tx_pipeswing[7]),
+ .powerdn(powerdn[15:14]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[159:140]),
+ .txdetectrx(wire_transmit_pcs7_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[7]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[63:56]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs7.allow_polarity_inversion = "false",
+ transmit_pcs7.auto_spd_self_switch_enable = "false",
+ transmit_pcs7.bitslip_enable = "false",
+ transmit_pcs7.channel_bonding = "x8",
+ transmit_pcs7.channel_number = ((starting_channel_number + 7) % 4),
+ transmit_pcs7.channel_width = 8,
+ transmit_pcs7.core_clock_0ppm = "false",
+ transmit_pcs7.datapath_low_latency_mode = "false",
+ transmit_pcs7.datapath_protocol = "pipe",
+ transmit_pcs7.disable_ph_low_latency_mode = "false",
+ transmit_pcs7.disparity_mode = "new",
+ transmit_pcs7.dprio_config_mode = 6'h01,
+ transmit_pcs7.elec_idle_delay = 6,
+ transmit_pcs7.enable_bit_reversal = "false",
+ transmit_pcs7.enable_idle_selection = "false",
+ transmit_pcs7.enable_reverse_parallel_loopback = "true",
+ transmit_pcs7.enable_self_test_mode = "false",
+ transmit_pcs7.enable_symbol_swap = "false",
+ transmit_pcs7.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs7.enc_8b_10b_mode = "normal",
+ transmit_pcs7.force_echar = "false",
+ transmit_pcs7.force_kchar = "false",
+ transmit_pcs7.hip_enable = "false",
+ transmit_pcs7.logical_channel_address = (starting_channel_number + 7),
+ transmit_pcs7.ph_fifo_reg_mode = "false",
+ transmit_pcs7.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs7.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs7.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs7.ph_fifo_xn_select = 1,
+ transmit_pcs7.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs7.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs7.prbs_cid_pattern = "false",
+ transmit_pcs7.protocol_hint = "pcie",
+ transmit_pcs7.refclk_select = "cmu_clock_divider",
+ transmit_pcs7.self_test_mode = "incremental",
+ transmit_pcs7.use_double_data_mode = "false",
+ transmit_pcs7.use_serializer_double_data_mode = "false",
+ transmit_pcs7.wr_clk_mux_select = "core_clk",
+ transmit_pcs7.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "auto",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.logical_protocol_hint_0 = "pcie",
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.physical_clkin1_mapping = "x4",
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 4,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(wire_transmit_pma1_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "auto",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h01,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.logical_protocol_hint_0 = "pcie",
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.physical_clkin1_mapping = "x4",
+ transmit_pma1.preemp_pretap = 0,
+ transmit_pma1.preemp_pretap_inv = "false",
+ transmit_pma1.preemp_tap_1 = 0,
+ transmit_pma1.preemp_tap_2 = 0,
+ transmit_pma1.preemp_tap_2_inv = "false",
+ transmit_pma1.protocol_hint = "pcie",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "off",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_external_termination = "false",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = 4,
+ transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(wire_transmit_pma2_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[2]),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma2_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[2])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "auto",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h01,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.logical_protocol_hint_0 = "pcie",
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.physical_clkin1_mapping = "x4",
+ transmit_pma2.preemp_pretap = 0,
+ transmit_pma2.preemp_pretap_inv = "false",
+ transmit_pma2.preemp_tap_1 = 0,
+ transmit_pma2.preemp_tap_2 = 0,
+ transmit_pma2.preemp_tap_2_inv = "false",
+ transmit_pma2.protocol_hint = "pcie",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "off",
+ transmit_pma2.termination = "OCT 100 Ohms",
+ transmit_pma2.use_external_termination = "false",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = 4,
+ transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_transmit_pma3_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[3]),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma3_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[3])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "auto",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h01,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.logical_protocol_hint_0 = "pcie",
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.physical_clkin1_mapping = "x4",
+ transmit_pma3.preemp_pretap = 0,
+ transmit_pma3.preemp_pretap_inv = "false",
+ transmit_pma3.preemp_tap_1 = 0,
+ transmit_pma3.preemp_tap_2 = 0,
+ transmit_pma3.preemp_tap_2_inv = "false",
+ transmit_pma3.protocol_hint = "pcie",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "off",
+ transmit_pma3.termination = "OCT 100 Ohms",
+ transmit_pma3.use_external_termination = "false",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = 4,
+ transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma4
+ (
+ .clockout(wire_transmit_pma4_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[99:80]}),
+ .dataout(wire_transmit_pma4_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[6]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_pmadprioin_wire[2099:1800]),
+ .dprioout(wire_transmit_pma4_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[4]),
+ .powerdn(cent_unit_txobpowerdn[6]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(cmu_analogrefclkout[1:0]),
+ .refclk2inpulse(cmu_analogrefclkpulse[0]),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[4]),
+ .rxdetectvalidout(wire_transmit_pma4_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma4_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[6])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma4.analog_power = "auto",
+ transmit_pma4.channel_number = ((starting_channel_number + 4) % 4),
+ transmit_pma4.channel_type = "auto",
+ transmit_pma4.clkin_select = 2,
+ transmit_pma4.clkmux_delay = "false",
+ transmit_pma4.common_mode = "0.65V",
+ transmit_pma4.dprio_config_mode = 6'h01,
+ transmit_pma4.enable_reverse_serial_loopback = "false",
+ transmit_pma4.logical_channel_address = (starting_channel_number + 4),
+ transmit_pma4.logical_protocol_hint_0 = "pcie",
+ transmit_pma4.low_speed_test_select = 0,
+ transmit_pma4.physical_clkin2_mapping = "xn_top",
+ transmit_pma4.preemp_pretap = 0,
+ transmit_pma4.preemp_pretap_inv = "false",
+ transmit_pma4.preemp_tap_1 = 0,
+ transmit_pma4.preemp_tap_2 = 0,
+ transmit_pma4.preemp_tap_2_inv = "false",
+ transmit_pma4.protocol_hint = "pcie",
+ transmit_pma4.rx_detect = 0,
+ transmit_pma4.serialization_factor = 10,
+ transmit_pma4.slew_rate = "off",
+ transmit_pma4.termination = "OCT 100 Ohms",
+ transmit_pma4.use_external_termination = "false",
+ transmit_pma4.use_pma_direct = "false",
+ transmit_pma4.use_ser_double_data_mode = "false",
+ transmit_pma4.vod_selection = 4,
+ transmit_pma4.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma5
+ (
+ .clockout(wire_transmit_pma5_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[119:100]}),
+ .dataout(wire_transmit_pma5_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[7]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_pmadprioin_wire[2399:2100]),
+ .dprioout(wire_transmit_pma5_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[5]),
+ .powerdn(cent_unit_txobpowerdn[7]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(cmu_analogrefclkout[1:0]),
+ .refclk2inpulse(cmu_analogrefclkpulse[0]),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[5]),
+ .rxdetectvalidout(wire_transmit_pma5_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma5_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[7])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma5.analog_power = "auto",
+ transmit_pma5.channel_number = ((starting_channel_number + 5) % 4),
+ transmit_pma5.channel_type = "auto",
+ transmit_pma5.clkin_select = 2,
+ transmit_pma5.clkmux_delay = "false",
+ transmit_pma5.common_mode = "0.65V",
+ transmit_pma5.dprio_config_mode = 6'h01,
+ transmit_pma5.enable_reverse_serial_loopback = "false",
+ transmit_pma5.logical_channel_address = (starting_channel_number + 5),
+ transmit_pma5.logical_protocol_hint_0 = "pcie",
+ transmit_pma5.low_speed_test_select = 0,
+ transmit_pma5.physical_clkin2_mapping = "xn_top",
+ transmit_pma5.preemp_pretap = 0,
+ transmit_pma5.preemp_pretap_inv = "false",
+ transmit_pma5.preemp_tap_1 = 0,
+ transmit_pma5.preemp_tap_2 = 0,
+ transmit_pma5.preemp_tap_2_inv = "false",
+ transmit_pma5.protocol_hint = "pcie",
+ transmit_pma5.rx_detect = 0,
+ transmit_pma5.serialization_factor = 10,
+ transmit_pma5.slew_rate = "off",
+ transmit_pma5.termination = "OCT 100 Ohms",
+ transmit_pma5.use_external_termination = "false",
+ transmit_pma5.use_pma_direct = "false",
+ transmit_pma5.use_ser_double_data_mode = "false",
+ transmit_pma5.vod_selection = 4,
+ transmit_pma5.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma6
+ (
+ .clockout(wire_transmit_pma6_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[139:120]}),
+ .dataout(wire_transmit_pma6_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[8]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_pmadprioin_wire[2699:2400]),
+ .dprioout(wire_transmit_pma6_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[6]),
+ .powerdn(cent_unit_txobpowerdn[8]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(cmu_analogrefclkout[1:0]),
+ .refclk2inpulse(cmu_analogrefclkpulse[0]),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[6]),
+ .rxdetectvalidout(wire_transmit_pma6_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma6_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[8])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma6.analog_power = "auto",
+ transmit_pma6.channel_number = ((starting_channel_number + 6) % 4),
+ transmit_pma6.channel_type = "auto",
+ transmit_pma6.clkin_select = 2,
+ transmit_pma6.clkmux_delay = "false",
+ transmit_pma6.common_mode = "0.65V",
+ transmit_pma6.dprio_config_mode = 6'h01,
+ transmit_pma6.enable_reverse_serial_loopback = "false",
+ transmit_pma6.logical_channel_address = (starting_channel_number + 6),
+ transmit_pma6.logical_protocol_hint_0 = "pcie",
+ transmit_pma6.low_speed_test_select = 0,
+ transmit_pma6.physical_clkin2_mapping = "xn_top",
+ transmit_pma6.preemp_pretap = 0,
+ transmit_pma6.preemp_pretap_inv = "false",
+ transmit_pma6.preemp_tap_1 = 0,
+ transmit_pma6.preemp_tap_2 = 0,
+ transmit_pma6.preemp_tap_2_inv = "false",
+ transmit_pma6.protocol_hint = "pcie",
+ transmit_pma6.rx_detect = 0,
+ transmit_pma6.serialization_factor = 10,
+ transmit_pma6.slew_rate = "off",
+ transmit_pma6.termination = "OCT 100 Ohms",
+ transmit_pma6.use_external_termination = "false",
+ transmit_pma6.use_pma_direct = "false",
+ transmit_pma6.use_ser_double_data_mode = "false",
+ transmit_pma6.vod_selection = 4,
+ transmit_pma6.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma7
+ (
+ .clockout(wire_transmit_pma7_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[159:140]}),
+ .dataout(wire_transmit_pma7_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[9]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_pmadprioin_wire[2999:2700]),
+ .dprioout(wire_transmit_pma7_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[7]),
+ .powerdn(cent_unit_txobpowerdn[9]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(cmu_analogrefclkout[1:0]),
+ .refclk2inpulse(cmu_analogrefclkpulse[0]),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[7]),
+ .rxdetectvalidout(wire_transmit_pma7_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma7_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[9])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma7.analog_power = "auto",
+ transmit_pma7.channel_number = ((starting_channel_number + 7) % 4),
+ transmit_pma7.channel_type = "auto",
+ transmit_pma7.clkin_select = 2,
+ transmit_pma7.clkmux_delay = "false",
+ transmit_pma7.common_mode = "0.65V",
+ transmit_pma7.dprio_config_mode = 6'h01,
+ transmit_pma7.enable_reverse_serial_loopback = "false",
+ transmit_pma7.logical_channel_address = (starting_channel_number + 7),
+ transmit_pma7.logical_protocol_hint_0 = "pcie",
+ transmit_pma7.low_speed_test_select = 0,
+ transmit_pma7.physical_clkin2_mapping = "xn_top",
+ transmit_pma7.preemp_pretap = 0,
+ transmit_pma7.preemp_pretap_inv = "false",
+ transmit_pma7.preemp_tap_1 = 0,
+ transmit_pma7.preemp_tap_2 = 0,
+ transmit_pma7.preemp_tap_2_inv = "false",
+ transmit_pma7.protocol_hint = "pcie",
+ transmit_pma7.rx_detect = 0,
+ transmit_pma7.serialization_factor = 10,
+ transmit_pma7.slew_rate = "off",
+ transmit_pma7.termination = "OCT 100 Ohms",
+ transmit_pma7.use_external_termination = "false",
+ transmit_pma7.use_pma_direct = "false",
+ transmit_pma7.use_ser_double_data_mode = "false",
+ transmit_pma7.vod_selection = 4,
+ transmit_pma7.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b0,
+ cent_unit_clkdivpowerdn = {wire_cent_unit1_clkdivpowerdn[0], wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_cmudividerdprioout = {wire_cent_unit1_cmudividerdprioout, wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit1_cmuplldprioout, wire_cent_unit0_cmuplldprioout},
+ cent_unit_pllpowerdn = {wire_cent_unit1_pllpowerdn[1:0], wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit1_pllresetout[1:0], wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit1_quadresetout, wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit1_rxcrupowerdown[5:0], wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit1_rxibpowerdown[5:0], wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {rx_pcsdprioout[3199:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit1_rxpcsdprioout[1599:0], wire_cent_unit0_rxpcsdprioout[1599:0]},
+ cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit1_rxpmadprioout[1799:0], wire_cent_unit0_rxpmadprioout[1799:0]},
+ cent_unit_tx_dprioin = {{1200{1'b0}}, tx_txdprioout[1199:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit1_txdataout[31:0], wire_cent_unit0_txdataout[31:0]},
+ cent_unit_txctrlout = {wire_cent_unit1_txctrlout, wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit1_txdetectrxpowerdown[5:0], wire_cent_unit0_txdetectrxpowerdown[5:0]},
+ cent_unit_txdprioout = {wire_cent_unit1_txpcsdprioout[599:0], wire_cent_unit0_txpcsdprioout[599:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit1_txobpowerdown[5:0], wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit1_txpmadprioout[1799:0], wire_cent_unit0_txpmadprioout[1799:0]},
+ clk_div_clk0in = {pll0_out[7:0]},
+ clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div1_dprioout, {400{1'b0}}, {100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
+ clk_div_pclkin = {refclk_pma[0], 1'b0},
+ cmu_analogfastrefclkout = {wire_central_clk_div1_analogfastrefclkout, wire_central_clk_div0_analogfastrefclkout},
+ cmu_analogrefclkout = {wire_central_clk_div1_analogrefclkout, wire_central_clk_div0_analogrefclkout},
+ cmu_analogrefclkpulse = {wire_central_clk_div1_analogrefclkpulse, wire_central_clk_div0_analogrefclkpulse},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_bi_quad_wire = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div1_coreclkout, wire_central_clk_div0_coreclkout},
+ fixedclk_to_cmu = {12{reconfig_clk}},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs7_grayelecidleinferselout, wire_transmit_pcs6_grayelecidleinferselout, wire_transmit_pcs5_grayelecidleinferselout, wire_transmit_pcs4_grayelecidleinferselout, wire_transmit_pcs3_grayelecidleinferselout, wire_transmit_pcs2_grayelecidleinferselout, wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
+ int_hiprateswtichdone = {wire_central_clk_div1_rateswitchdone, wire_central_clk_div0_rateswitchdone},
+ int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs7_pipeenrevparallellpbkout, wire_transmit_pcs6_pipeenrevparallellpbkout, wire_transmit_pcs5_pipeenrevparallellpbkout, wire_transmit_pcs4_pipeenrevparallellpbkout, wire_transmit_pcs3_pipeenrevparallellpbkout, wire_transmit_pcs2_pipeenrevparallellpbkout, wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
+ int_rx_coreclkout = {wire_receive_pcs7_coreclkout, wire_receive_pcs6_coreclkout, wire_receive_pcs5_coreclkout, wire_receive_pcs4_coreclkout, wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
+ int_rx_iqpphfifobyteselout = {wire_receive_pcs7_iqpphfifobyteselout, wire_receive_pcs6_iqpphfifobyteselout, wire_receive_pcs5_iqpphfifobyteselout, wire_receive_pcs4_iqpphfifobyteselout, wire_receive_pcs3_iqpphfifobyteselout, wire_receive_pcs2_iqpphfifobyteselout, wire_receive_pcs1_iqpphfifobyteselout, wire_receive_pcs0_iqpphfifobyteselout},
+ int_rx_iqpphfifordenableout = {wire_receive_pcs7_iqpphfifordenableout, wire_receive_pcs6_iqpphfifordenableout, wire_receive_pcs5_iqpphfifordenableout, wire_receive_pcs4_iqpphfifordenableout, wire_receive_pcs3_iqpphfifordenableout, wire_receive_pcs2_iqpphfifordenableout, wire_receive_pcs1_iqpphfifordenableout, wire_receive_pcs0_iqpphfifordenableout},
+ int_rx_iqpphfifowrclkout = {wire_receive_pcs7_iqpphfifowrclkout, wire_receive_pcs6_iqpphfifowrclkout, wire_receive_pcs5_iqpphfifowrclkout, wire_receive_pcs4_iqpphfifowrclkout, wire_receive_pcs3_iqpphfifowrclkout, wire_receive_pcs2_iqpphfifowrclkout, wire_receive_pcs1_iqpphfifowrclkout, wire_receive_pcs0_iqpphfifowrclkout},
+ int_rx_iqpphfifowrenableout = {wire_receive_pcs7_iqpphfifowrenableout, wire_receive_pcs6_iqpphfifowrenableout, wire_receive_pcs5_iqpphfifowrenableout, wire_receive_pcs4_iqpphfifowrenableout, wire_receive_pcs3_iqpphfifowrenableout, wire_receive_pcs2_iqpphfifowrenableout, wire_receive_pcs1_iqpphfifowrenableout, wire_receive_pcs0_iqpphfifowrenableout},
+ int_rx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_rx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_iqpphfifoxnwrclk = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrclkout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs7_phfifobyteserdisableout, wire_receive_pcs6_phfifobyteserdisableout, wire_receive_pcs5_phfifobyteserdisableout, wire_receive_pcs4_phfifobyteserdisableout, wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs7_phfifoptrsresetout, wire_receive_pcs6_phfifoptrsresetout, wire_receive_pcs5_phfifoptrsresetout, wire_receive_pcs4_phfifoptrsresetout, wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs7_phfifordenableout, wire_receive_pcs6_phfifordenableout, wire_receive_pcs5_phfifordenableout, wire_receive_pcs4_phfifordenableout, wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs7_phfiforesetout, wire_receive_pcs6_phfiforesetout, wire_receive_pcs5_phfiforesetout, wire_receive_pcs4_phfiforesetout, wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs7_phfifowrdisableout, wire_receive_pcs6_phfifowrdisableout, wire_receive_pcs5_phfifowrdisableout, wire_receive_pcs4_phfifowrdisableout, wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {1'b0, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], 1'b0, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
+ int_rx_phfifoxnrdenable = {1'b0, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], 1'b0, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrclk = {1'b0, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], 1'b0, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrenable = {1'b0, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], 1'b0, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
+ int_rxcoreclk = {1'b0, int_rx_coreclkout[0]},
+ int_rxpcs_cdrctrlearlyeios = {wire_receive_pcs7_cdrctrlearlyeios, wire_receive_pcs6_cdrctrlearlyeios, wire_receive_pcs5_cdrctrlearlyeios, wire_receive_pcs4_cdrctrlearlyeios, wire_receive_pcs3_cdrctrlearlyeios, wire_receive_pcs2_cdrctrlearlyeios, wire_receive_pcs1_cdrctrlearlyeios, wire_receive_pcs0_cdrctrlearlyeios},
+ int_rxphfifordenable = {1'b0, int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {1'b0, int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit1_rxphfifox4byteselout, wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit1_rxphfifox4rdenableout, wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit1_rxphfifox4wrclkout, wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit1_rxphfifox4wrenableout, wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs7_coreclkout, wire_transmit_pcs6_coreclkout, wire_transmit_pcs5_coreclkout, wire_transmit_pcs4_coreclkout, wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
+ int_tx_iqpphfifobyteselout = {wire_transmit_pcs7_iqpphfifobyteselout, wire_transmit_pcs6_iqpphfifobyteselout, wire_transmit_pcs5_iqpphfifobyteselout, wire_transmit_pcs4_iqpphfifobyteselout, wire_transmit_pcs3_iqpphfifobyteselout, wire_transmit_pcs2_iqpphfifobyteselout, wire_transmit_pcs1_iqpphfifobyteselout, wire_transmit_pcs0_iqpphfifobyteselout},
+ int_tx_iqpphfifordclkout = {wire_transmit_pcs7_iqpphfifordclkout, wire_transmit_pcs6_iqpphfifordclkout, wire_transmit_pcs5_iqpphfifordclkout, wire_transmit_pcs4_iqpphfifordclkout, wire_transmit_pcs3_iqpphfifordclkout, wire_transmit_pcs2_iqpphfifordclkout, wire_transmit_pcs1_iqpphfifordclkout, wire_transmit_pcs0_iqpphfifordclkout},
+ int_tx_iqpphfifordenableout = {wire_transmit_pcs7_iqpphfifordenableout, wire_transmit_pcs6_iqpphfifordenableout, wire_transmit_pcs5_iqpphfifordenableout, wire_transmit_pcs4_iqpphfifordenableout, wire_transmit_pcs3_iqpphfifordenableout, wire_transmit_pcs2_iqpphfifordenableout, wire_transmit_pcs1_iqpphfifordenableout, wire_transmit_pcs0_iqpphfifordenableout},
+ int_tx_iqpphfifowrenableout = {wire_transmit_pcs7_iqpphfifowrenableout, wire_transmit_pcs6_iqpphfifowrenableout, wire_transmit_pcs5_iqpphfifowrenableout, wire_transmit_pcs4_iqpphfifowrenableout, wire_transmit_pcs3_iqpphfifowrenableout, wire_transmit_pcs2_iqpphfifowrenableout, wire_transmit_pcs1_iqpphfifowrenableout, wire_transmit_pcs0_iqpphfifowrenableout},
+ int_tx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_tx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_tx_iqpphfifoxnrdclk = {{3{{2{1'b0}}}}, int_tx_iqpphfifordclkout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_tx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_tx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_tx_phfiforddisableout = {wire_transmit_pcs7_phfiforddisableout, wire_transmit_pcs6_phfiforddisableout, wire_transmit_pcs5_phfiforddisableout, wire_transmit_pcs4_phfiforddisableout, wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs7_phfiforesetout, wire_transmit_pcs6_phfiforesetout, wire_transmit_pcs5_phfiforesetout, wire_transmit_pcs4_phfiforesetout, wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs7_phfifowrenableout, wire_transmit_pcs6_phfifowrenableout, wire_transmit_pcs5_phfifowrenableout, wire_transmit_pcs4_phfifowrenableout, wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {1'b0, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], 1'b0, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdclk = {1'b0, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], 1'b0, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdenable = {1'b0, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], 1'b0, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
+ int_tx_phfifoxnwrenable = {1'b0, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], 1'b0, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
+ int_txcoreclk = {1'b0, int_tx_coreclkout[0]},
+ int_txphfiforddisable = {1'b0, int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {1'b0, int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {1'b0, int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit1_txphfifox4byteselout, wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit1_txphfifox4rdclkout, wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit1_txphfifox4rdenableout, wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit1_txphfifox4wrenableout, wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk1_nonusertocmu, wire_cal_blk0_nonusertocmu},
+ pipedatavalid = {pipedatavalid_out[7:0]},
+ pipedatavalid_out = {wire_receive_pcs7_pipedatavalid, wire_receive_pcs6_pipedatavalid, wire_receive_pcs5_pipedatavalid, wire_receive_pcs4_pipedatavalid, wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[7:0]},
+ pipeelecidle_out = {wire_receive_pcs7_pipeelecidle, wire_receive_pcs6_pipeelecidle, wire_receive_pcs5_pipeelecidle, wire_receive_pcs4_pipeelecidle, wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs7_pipephydonestatus, wire_receive_pcs6_pipephydonestatus, wire_receive_pcs5_pipephydonestatus, wire_receive_pcs4_pipephydonestatus, wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs7_pipestatus, wire_receive_pcs6_pipestatus, wire_receive_pcs5_pipestatus, wire_receive_pcs4_pipestatus, wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll0_clkin = {{10{1'b0}}, {9{1'b0}}, pll_inclk_wire[0]},
+ pll0_dprioin = {{300{1'b0}}, cent_unit_cmuplldprioout[1499:1200]},
+ pll0_dprioout = {{300{1'b0}}, wire_tx_pll0_dprioout},
+ pll0_out = {{4{1'b0}}, wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll7_dataout, wire_rx_cdr_pll6_dataout, wire_rx_cdr_pll5_dataout, wire_rx_cdr_pll4_dataout, wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll7_dprioout, wire_rx_cdr_pll6_dprioout, wire_rx_cdr_pll5_dprioout, wire_rx_cdr_pll4_dprioout, wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {{600{1'b0}}, pll_ch_dprioout[2399:1200], {300{1'b0}}, pll0_dprioout[299:0], pll_ch_dprioout[1199:0]},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {1'b0, wire_tx_pll0_locked},
+ pll_powerdown = 1'b0,
+ pllpowerdn_in = {{2{1'b0}}, 1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {{2{1'b0}}, 1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {rx_pma_analogtestbus[33:18], wire_cent_unit1_dprioout, rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ refclk_pma = {wire_central_clk_div1_refclkout, wire_central_clk_div0_refclkout},
+ rx_analogreset_in = {{4{1'b0}}, {8{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
+ rx_analogreset_out = {wire_cent_unit1_rxanalogresetout[5:0], wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_coreclk_in = {8{coreclkout_bi_quad_wire[0]}},
+ rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[7], {9{1'b0}}, rx_pldcruclk_in[6], {9{1'b0}}, rx_pldcruclk_in[5], {9{1'b0}}, rx_pldcruclk_in[4], {9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs7_ctrldetect[0], wire_receive_pcs6_ctrldetect[0], wire_receive_pcs5_ctrldetect[0], wire_receive_pcs4_ctrldetect[0], wire_receive_pcs3_ctrldetect[0], wire_receive_pcs2_ctrldetect[0], wire_receive_pcs1_ctrldetect[0], wire_receive_pcs0_ctrldetect[0]},
+ rx_dataout = {rx_out_wire[63:0]},
+ rx_deserclock_in = {rx_pll_clkout[31:0]},
+ rx_digitalreset_in = {8{int_rx_digitalreset_reg[0]}},
+ rx_digitalreset_out = {wire_cent_unit1_rxdigitalresetout[3:0], wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_elecidleinfersel = {24{1'b0}},
+ rx_enapatternalign = {8{1'b0}},
+ rx_freqlocked = {(rx_freqlocked_wire[7] & (~ rx_analogreset[0])), (rx_freqlocked_wire[6] & (~ rx_analogreset[0])), (rx_freqlocked_wire[5] & (~ rx_analogreset[0])), (rx_freqlocked_wire[4] & (~ rx_analogreset[0])), (rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_freqlocked_wire = {wire_rx_cdr_pll7_freqlocked, wire_rx_cdr_pll6_freqlocked, wire_rx_cdr_pll5_freqlocked, wire_rx_cdr_pll4_freqlocked, wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = {8{1'b0}},
+ rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[7]), ((~ reconfig_togxb_busy) & rx_locktodata[6]), ((~ reconfig_togxb_busy) & rx_locktodata[5]), ((~ reconfig_togxb_busy) & rx_locktodata[4]), ((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
+ rx_locktorefclk_wire = {wire_receive_pcs7_cdrctrllocktorefclkout, wire_receive_pcs6_cdrctrllocktorefclkout, wire_receive_pcs5_cdrctrllocktorefclkout, wire_receive_pcs4_cdrctrllocktorefclkout, wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs7_dataout[7:0], wire_receive_pcs6_dataout[7:0], wire_receive_pcs5_dataout[7:0], wire_receive_pcs4_dataout[7:0], wire_receive_pcs3_dataout[7:0], wire_receive_pcs2_dataout[7:0], wire_receive_pcs1_dataout[7:0], wire_receive_pcs0_dataout[7:0]},
+ rx_patterndetect = {wire_receive_pcs7_patterndetect[0], wire_receive_pcs6_patterndetect[0], wire_receive_pcs5_patterndetect[0], wire_receive_pcs4_patterndetect[0], wire_receive_pcs3_patterndetect[0], wire_receive_pcs2_patterndetect[0], wire_receive_pcs1_patterndetect[0], wire_receive_pcs0_patterndetect[0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[7], tx_rxfoundout[7], txdetectrxout[6], tx_rxfoundout[6], txdetectrxout[5], tx_rxfoundout[5], txdetectrxout[4], tx_rxfoundout[4], txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[3199:0]},
+ rx_pcsdprioout = {wire_receive_pcs7_dprioout, wire_receive_pcs6_dprioout, wire_receive_pcs5_dprioout, wire_receive_pcs4_dprioout, wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = {8{1'b1}},
+ rx_phfiforeset = {8{1'b0}},
+ rx_phfifowrdisable = {8{1'b0}},
+ rx_pipestatetransdoneout = {wire_receive_pcs7_pipestatetransdoneout, wire_receive_pcs6_pipestatetransdoneout, wire_receive_pcs5_pipestatetransdoneout, wire_receive_pcs4_pipestatetransdoneout, wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[7:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll7_clk, wire_rx_cdr_pll6_clk, wire_rx_cdr_pll5_clk, wire_rx_cdr_pll4_clk, wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {(rx_plllocked_wire[7] & (~ rx_analogreset[0])), (rx_plllocked_wire[6] & (~ rx_analogreset[0])), (rx_plllocked_wire[5] & (~ rx_analogreset[0])), (rx_plllocked_wire[4] & (~ rx_analogreset[0])), (rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll7_pfdrefclkout, wire_rx_cdr_pll6_pfdrefclkout, wire_rx_cdr_pll5_pfdrefclkout, wire_rx_cdr_pll4_pfdrefclkout, wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll7_locked, wire_rx_cdr_pll6_locked, wire_rx_cdr_pll5_locked, wire_rx_cdr_pll4_locked, wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_analogtestbus = {{102{1'b0}}, wire_receive_pma7_analogtestbus[5:2], wire_receive_pma6_analogtestbus[5:2], wire_receive_pma5_analogtestbus[5:2], wire_receive_pma4_analogtestbus[5:2], 1'b0, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
+ rx_pma_clockout = {wire_receive_pma7_clockout, wire_receive_pma6_clockout, wire_receive_pma5_clockout, wire_receive_pma4_clockout, wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma7_dataout, wire_receive_pma6_dataout, wire_receive_pma5_dataout, wire_receive_pma4_dataout, wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma7_locktorefout, wire_receive_pma6_locktorefout, wire_receive_pma5_locktorefout, wire_receive_pma4_locktorefout, wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma7_recoverdataout[19:0], wire_receive_pma6_recoverdataout[19:0], wire_receive_pma5_recoverdataout[19:0], wire_receive_pma4_recoverdataout[19:0], wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
+ rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma7_dprioout, wire_receive_pma6_dprioout, wire_receive_pma5_dprioout, wire_receive_pma4_dprioout, {2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
+ rx_powerdown = {8{1'b0}},
+ rx_powerdown_in = {{4{1'b0}}, rx_powerdown[7:0]},
+ rx_prbscidenable = {8{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs7_revparallelfdbkdata, wire_receive_pcs6_revparallelfdbkdata, wire_receive_pcs5_revparallelfdbkdata, wire_receive_pcs4_revparallelfdbkdata, wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {8{1'b0}},
+ rx_rxcruresetout = {wire_cent_unit1_rxcruresetout[5:0], wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma7_signaldetect, wire_receive_pma6_signaldetect, wire_receive_pma5_signaldetect, wire_receive_pma4_signaldetect, wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs7_syncstatus[0], wire_receive_pcs6_syncstatus[0], wire_receive_pcs5_syncstatus[0], wire_receive_pcs4_syncstatus[0], wire_receive_pcs3_syncstatus[0], wire_receive_pcs2_syncstatus[0], wire_receive_pcs1_syncstatus[0], wire_receive_pcs0_syncstatus[0]},
+ rxphfifowrdisable = {1'b0, int_rx_phfifowrdisableout[0]},
+ rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
+ tx_analogreset_out = {wire_cent_unit1_txanalogresetout[5:0], wire_cent_unit0_txanalogresetout[5:0]},
+ tx_coreclk_in = {8{coreclkout_bi_quad_wire[0]}},
+ tx_datain_wire = {tx_datain[63:0]},
+ tx_dataout = {wire_transmit_pma7_dataout, wire_transmit_pma6_dataout, wire_transmit_pma5_dataout, wire_transmit_pma4_dataout, wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs7_dataout, wire_transmit_pcs6_dataout, wire_transmit_pcs5_dataout, wire_transmit_pcs4_dataout, wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {8{int_tx_digitalreset_reg[0]}},
+ tx_digitalreset_out = {wire_cent_unit1_txdigitalresetout[3:0], wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_dprioin_wire = {{1200{1'b0}}, cent_unit_txdprioout[1199:0]},
+ tx_forcedisp_wire = {tx_forcedispcompliance[7:0]},
+ tx_invpolarity = {8{1'b0}},
+ tx_localrefclk = {wire_transmit_pma7_clockout, wire_transmit_pma6_clockout, wire_transmit_pma5_clockout, wire_transmit_pma4_clockout, wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs7_forceelecidleout, wire_transmit_pcs6_forceelecidleout, wire_transmit_pcs5_forceelecidleout, wire_transmit_pcs4_forceelecidleout, wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = {8{1'b0}},
+ tx_pipedeemph = {8{1'b0}},
+ tx_pipemargin = {24{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs7_pipepowerdownout, wire_transmit_pcs6_pipepowerdownout, wire_transmit_pcs5_pipepowerdownout, wire_transmit_pcs4_pipepowerdownout, wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs7_pipepowerstateout, wire_transmit_pcs6_pipepowerstateout, wire_transmit_pcs5_pipepowerstateout, wire_transmit_pcs4_pipepowerstateout, wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = {8{1'b0}},
+ tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
+ tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma7_dprioout, wire_transmit_pma6_dprioout, wire_transmit_pma5_dprioout, wire_transmit_pma4_dprioout, {2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = {8{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma7_rxdetectvalidout, wire_transmit_pma6_rxdetectvalidout, wire_transmit_pma5_rxdetectvalidout, wire_transmit_pma4_rxdetectvalidout, wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma7_rxfoundout, wire_transmit_pma6_rxfoundout, wire_transmit_pma5_rxfoundout, wire_transmit_pma4_rxfoundout, wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {wire_transmit_pcs7_dprioout, wire_transmit_pcs6_dprioout, wire_transmit_pcs5_dprioout, wire_transmit_pcs4_dprioout, wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
+ txdetectrxout = {wire_transmit_pcs7_txdetectrx, wire_transmit_pcs6_txdetectrx, wire_transmit_pcs5_txdetectrx, wire_transmit_pcs4_txdetectrx, wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit1_dpriodisableout, wire_cent_unit0_dpriodisableout};
+endmodule //altpcie_serdes_4sgx_x8d_gen1_08p_alt4gxb_ko7a
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_4sgx_x8d_gen1_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout);
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [7:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [15:0] powerdn;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [7:0] rx_cruclk;
+ input [7:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [7:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [7:0] tx_forcedispcompliance;
+ input [7:0] tx_forceelecidle;
+ output [0:0] coreclkout;
+ output [7:0] pipedatavalid;
+ output [7:0] pipeelecidle;
+ output [7:0] pipephydonestatus;
+ output [23:0] pipestatus;
+ output [0:0] pll_locked;
+ output [33:0] reconfig_fromgxb;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [7:0] rx_freqlocked;
+ output [7:0] rx_patterndetect;
+ output [7:0] rx_pll_locked;
+ output [7:0] rx_syncstatus;
+ output [7:0] tx_dataout;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [7:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+
+
+ wire [7:0] sub_wire0;
+ wire [7:0] sub_wire1;
+ wire [7:0] sub_wire2;
+ wire [0:0] sub_wire3;
+ wire [33:0] sub_wire4;
+ wire [7:0] sub_wire5;
+ wire [23:0] sub_wire6;
+ wire [7:0] sub_wire7;
+ wire [7:0] sub_wire8;
+ wire [0:0] sub_wire9;
+ wire [63:0] sub_wire10;
+ wire [7:0] sub_wire11;
+ wire [7:0] sub_wire12;
+ wire [7:0] sub_wire13;
+ wire [7:0] pipedatavalid = sub_wire0[7:0];
+ wire [7:0] rx_patterndetect = sub_wire1[7:0];
+ wire [7:0] pipephydonestatus = sub_wire2[7:0];
+ wire [0:0] pll_locked = sub_wire3[0:0];
+ wire [33:0] reconfig_fromgxb = sub_wire4[33:0];
+ wire [7:0] rx_freqlocked = sub_wire5[7:0];
+ wire [23:0] pipestatus = sub_wire6[23:0];
+ wire [7:0] rx_pll_locked = sub_wire7[7:0];
+ wire [7:0] rx_syncstatus = sub_wire8[7:0];
+ wire [0:0] coreclkout = sub_wire9[0:0];
+ wire [63:0] rx_dataout = sub_wire10[63:0];
+ wire [7:0] pipeelecidle = sub_wire11[7:0];
+ wire [7:0] tx_dataout = sub_wire12[7:0];
+ wire [7:0] rx_ctrldetect = sub_wire13[7:0];
+
+ altpcie_serdes_4sgx_x8d_gen1_08p_alt4gxb_ko7a altpcie_serdes_4sgx_x8d_gen1_08p_alt4gxb_ko7a_component (
+ .pll_inclk (pll_inclk),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_detectrxloop (tx_detectrxloop),
+ .cal_blk_clk (cal_blk_clk),
+ .tx_forceelecidle (tx_forceelecidle),
+ .rx_datain (rx_datain),
+ .rx_digitalreset (rx_digitalreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .tx_datain (tx_datain),
+ .tx_digitalreset (tx_digitalreset),
+ .gxb_powerdown (gxb_powerdown),
+ .rx_cruclk (rx_cruclk),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .reconfig_clk (reconfig_clk),
+ .rx_analogreset (rx_analogreset),
+ .powerdn (powerdn),
+ .tx_ctrlenable (tx_ctrlenable),
+ .pipedatavalid (sub_wire0),
+ .rx_patterndetect (sub_wire1),
+ .pipephydonestatus (sub_wire2),
+ .pll_locked (sub_wire3),
+ .reconfig_fromgxb (sub_wire4),
+ .rx_freqlocked (sub_wire5),
+ .pipestatus (sub_wire6),
+ .rx_pll_locked (sub_wire7),
+ .rx_syncstatus (sub_wire8),
+ .coreclkout (sub_wire9),
+ .rx_dataout (sub_wire10),
+ .pipeelecidle (sub_wire11),
+ .tx_dataout (sub_wire12),
+ .rx_ctrldetect (sub_wire13));
+ defparam
+ altpcie_serdes_4sgx_x8d_gen1_08p_alt4gxb_ko7a_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500.0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "1"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x8"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "2.5v"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x8"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x8"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "2"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "34"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 8 0 INPUT NODEFVAL "pipe8b10binvpolarity[7..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 8 0 OUTPUT NODEFVAL "pipedatavalid[7..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 8 0 OUTPUT NODEFVAL "pipeelecidle[7..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 8 0 OUTPUT NODEFVAL "pipephydonestatus[7..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 24 0 OUTPUT NODEFVAL "pipestatus[23..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 16 0 INPUT NODEFVAL "powerdn[15..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 34 0 OUTPUT NODEFVAL "reconfig_fromgxb[33..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 8 0 INPUT GND "rx_cruclk[7..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 8 0 INPUT NODEFVAL "rx_datain[7..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 8 0 OUTPUT NODEFVAL "rx_freqlocked[7..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 8 0 OUTPUT NODEFVAL "rx_pll_locked[7..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 8 0 OUTPUT NODEFVAL "tx_dataout[7..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 8 0 INPUT NODEFVAL "tx_detectrxloop[7..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 8 0 INPUT NODEFVAL "tx_forcedispcompliance[7..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 8 0 INPUT NODEFVAL "tx_forceelecidle[7..0]"
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 8 0 pipe8b10binvpolarity 0 0 8 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @powerdn 0 0 16 0 powerdn 0 0 16 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 8 0 rx_cruclk 0 0 8 0
+// Retrieval info: CONNECT: @rx_datain 0 0 8 0 rx_datain 0 0 8 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 8 0 tx_detectrxloop 0 0 8 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 8 0 tx_forcedispcompliance 0 0 8 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 8 0 tx_forceelecidle 0 0 8 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 8 0 @pipedatavalid 0 0 8 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 8 0 @pipeelecidle 0 0 8 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 8 0 @pipephydonestatus 0 0 8 0
+// Retrieval info: CONNECT: pipestatus 0 0 24 0 @pipestatus 0 0 24 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 34 0 @reconfig_fromgxb 0 0 34 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 8 0 @rx_freqlocked 0 0 8 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 8 0 @rx_pll_locked 0 0 8 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 8 0 @tx_dataout 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen1_08p.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen1_08p.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen1_08p.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen1_08p.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen1_08p.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen1_08p_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen1_08p_bb.v TRUE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v
new file mode 100644
index 0000000000000000000000000000000000000000..e9e445dae4cb6b464e2b0232b13b4d7e79396762
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v
@@ -0,0 +1,7367 @@
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: altpcie_serdes_4sgx_x8d_gen2_08p.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.0 Internal Build 118 02/15/2011 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="5000 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="true" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="3.0v" gxb_powerdown_width=1 input_clock_frequency="100.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="none" number_of_channels=8 number_of_quads=2 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="pcie2" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=34 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x8" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="auto" rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=1 rx_data_rate=5000 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x8" tx_channel_width=16 tx_clkout_width=8 tx_common_mode="0.65v" tx_data_rate=5000 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_n_divider=1 tx_pll_type="ATX" tx_pll_vco_post_scale_divider=1 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=3 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn rateswitch reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
+//VERSION_BEGIN 11.0 cbx_alt4gxb 2011:02:15:21:24:41:SJ cbx_mgl 2011:02:15:21:26:30:SJ cbx_tgx 2011:02:15:21:24:41:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = reg 46 stratixiv_hssi_calibration_block 3 stratixiv_hssi_clock_divider 3 stratixiv_hssi_cmu 3 stratixiv_hssi_pll 9 stratixiv_hssi_rx_pcs 8 stratixiv_hssi_rx_pma 8 stratixiv_hssi_tx_pcs 8 stratixiv_hssi_tx_pma 8
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
+module altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_nuda
+ (
+ cal_blk_clk,
+ coreclkout,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_inclk,
+ pll_locked,
+ powerdn,
+ rateswitch,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ tx_pipedeemph,
+ tx_pipemargin) /* synthesis synthesis_clearbox=2 */;
+ input cal_blk_clk;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input [7:0] pipe8b10binvpolarity;
+ output [7:0] pipedatavalid;
+ output [7:0] pipeelecidle;
+ output [7:0] pipephydonestatus;
+ output [23:0] pipestatus;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [15:0] powerdn;
+ input [0:0] rateswitch;
+ input reconfig_clk;
+ output [33:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [7:0] rx_cruclk;
+ output [15:0] rx_ctrldetect;
+ input [7:0] rx_datain;
+ output [127:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [7:0] rx_freqlocked;
+ output [15:0] rx_patterndetect;
+ output [7:0] rx_pll_locked;
+ output [15:0] rx_syncstatus;
+ input [15:0] tx_ctrlenable;
+ input [127:0] tx_datain;
+ output [7:0] tx_dataout;
+ input [7:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [7:0] tx_forcedispcompliance;
+ input [7:0] tx_forceelecidle;
+ input [7:0] tx_pipedeemph;
+ input [23:0] tx_pipemargin;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 [0:0] gxb_powerdown;
+ tri0 [7:0] pipe8b10binvpolarity;
+ tri0 pll_inclk;
+ tri0 [15:0] powerdn;
+ tri0 [0:0] rateswitch;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [7:0] rx_cruclk;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [15:0] tx_ctrlenable;
+ tri0 [127:0] tx_datain;
+ tri0 [7:0] tx_detectrxloop;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [7:0] tx_forcedispcompliance;
+ tri0 [7:0] tx_forceelecidle;
+ tri0 [7:0] tx_pipedeemph;
+ tri0 [23:0] tx_pipemargin;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+
+
+ wire [9:0] wire_pcie_sw_sel_delay_blk0c_d;
+ reg [9:0] pcie_sw_sel_delay_blk0c;
+ wire [9:0] wire_pcie_sw_sel_delay_blk0c_prn;
+ wire [9:0] wire_pcie_sw_sel_delay_blk1c_d;
+ reg [9:0] pcie_sw_sel_delay_blk1c;
+ wire [9:0] wire_pcie_sw_sel_delay_blk1c_prn;
+ wire [9:0] wire_pllreset_delay_blk0c_d;
+ reg [9:0] pllreset_delay_blk0c;
+ wire [9:0] wire_pllreset_delay_blk0c_prn;
+ wire [9:0] wire_pllreset_delay_blk1c_d;
+ reg [9:0] pllreset_delay_blk1c;
+ wire [9:0] wire_pllreset_delay_blk1c_prn;
+ wire [2:0] wire_rx_digitalreset_reg0c_d;
+ reg [2:0] rx_digitalreset_reg0c;
+ wire [2:0] wire_rx_digitalreset_reg0c_clk;
+ wire [2:0] wire_tx_digitalreset_reg0c_d;
+ reg [2:0] tx_digitalreset_reg0c;
+ wire [2:0] wire_tx_digitalreset_reg0c_clk;
+ wire wire_cal_blk0_nonusertocmu;
+ wire wire_cal_blk1_nonusertocmu;
+ wire wire_pll_cal_blk0_nonusertocmu;
+ wire [1:0] wire_atx_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_atx_clk_div0_analogrefclkout;
+ wire wire_atx_clk_div0_analogrefclkpulse;
+ wire wire_atx_clk_div0_rateswitchdone;
+ wire wire_atx_clk_div0_refclkout;
+ wire wire_central_clk_div0_coreclkout;
+ wire [99:0] wire_central_clk_div0_dprioout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_rateswitchout;
+ wire wire_central_clk_div0_refclkout;
+ wire wire_central_clk_div1_coreclkout;
+ wire [99:0] wire_central_clk_div1_dprioout;
+ wire wire_central_clk_div1_rateswitchdone;
+ wire wire_central_clk_div1_rateswitchout;
+ wire wire_central_clk_div1_refclkout;
+ wire [1:0] wire_atx_pll_cent_unit0_clkdivpowerdn;
+ wire [1:0] wire_atx_pll_cent_unit0_pllpowerdn;
+ wire [1:0] wire_atx_pll_cent_unit0_pllresetout;
+ wire wire_atx_pll_cent_unit0_quadresetout;
+ wire wire_cent_unit0_autospdx4configsel;
+ wire wire_cent_unit0_autospdx4rateswitchout;
+ wire wire_cent_unit0_autospdx4spdchg;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire [9:0] wire_cent_unit0_digitaltestout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire wire_cent_unit0_phfifiox4ptrsreset;
+ wire wire_cent_unit0_quadresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire wire_cent_unit1_autospdx4configsel;
+ wire wire_cent_unit1_autospdx4rateswitchout;
+ wire wire_cent_unit1_autospdx4spdchg;
+ wire [1:0] wire_cent_unit1_clkdivpowerdn;
+ wire [599:0] wire_cent_unit1_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit1_cmuplldprioout;
+ wire [9:0] wire_cent_unit1_digitaltestout;
+ wire wire_cent_unit1_dpriodisableout;
+ wire wire_cent_unit1_dprioout;
+ wire wire_cent_unit1_phfifiox4ptrsreset;
+ wire wire_cent_unit1_quadresetout;
+ wire [5:0] wire_cent_unit1_rxanalogresetout;
+ wire [5:0] wire_cent_unit1_rxcrupowerdown;
+ wire [5:0] wire_cent_unit1_rxcruresetout;
+ wire [3:0] wire_cent_unit1_rxdigitalresetout;
+ wire [5:0] wire_cent_unit1_rxibpowerdown;
+ wire [1599:0] wire_cent_unit1_rxpcsdprioout;
+ wire wire_cent_unit1_rxphfifox4byteselout;
+ wire wire_cent_unit1_rxphfifox4rdenableout;
+ wire wire_cent_unit1_rxphfifox4wrclkout;
+ wire wire_cent_unit1_rxphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit1_rxpmadprioout;
+ wire [5:0] wire_cent_unit1_txanalogresetout;
+ wire [3:0] wire_cent_unit1_txctrlout;
+ wire [31:0] wire_cent_unit1_txdataout;
+ wire [5:0] wire_cent_unit1_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit1_txdigitalresetout;
+ wire [5:0] wire_cent_unit1_txobpowerdown;
+ wire [599:0] wire_cent_unit1_txpcsdprioout;
+ wire wire_cent_unit1_txphfifox4byteselout;
+ wire wire_cent_unit1_txphfifox4rdclkout;
+ wire wire_cent_unit1_txphfifox4rdenableout;
+ wire wire_cent_unit1_txphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit1_txpmadprioout;
+ wire [3:0] wire_atx_pll0_clk;
+ wire wire_atx_pll0_locked;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire [299:0] wire_rx_cdr_pll1_dprioout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire [299:0] wire_rx_cdr_pll2_dprioout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire [299:0] wire_rx_cdr_pll3_dprioout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll4_clk;
+ wire [1:0] wire_rx_cdr_pll4_dataout;
+ wire [299:0] wire_rx_cdr_pll4_dprioout;
+ wire wire_rx_cdr_pll4_freqlocked;
+ wire wire_rx_cdr_pll4_locked;
+ wire wire_rx_cdr_pll4_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll5_clk;
+ wire [1:0] wire_rx_cdr_pll5_dataout;
+ wire [299:0] wire_rx_cdr_pll5_dprioout;
+ wire wire_rx_cdr_pll5_freqlocked;
+ wire wire_rx_cdr_pll5_locked;
+ wire wire_rx_cdr_pll5_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll6_clk;
+ wire [1:0] wire_rx_cdr_pll6_dataout;
+ wire [299:0] wire_rx_cdr_pll6_dprioout;
+ wire wire_rx_cdr_pll6_freqlocked;
+ wire wire_rx_cdr_pll6_locked;
+ wire wire_rx_cdr_pll6_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll7_clk;
+ wire [1:0] wire_rx_cdr_pll7_dataout;
+ wire [299:0] wire_rx_cdr_pll7_dprioout;
+ wire wire_rx_cdr_pll7_freqlocked;
+ wire wire_rx_cdr_pll7_locked;
+ wire wire_rx_cdr_pll7_pfdrefclkout;
+ wire wire_receive_pcs0_autospdrateswitchout;
+ wire wire_receive_pcs0_autospdspdchgout;
+ wire wire_receive_pcs0_cdrctrlearlyeios;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire wire_receive_pcs0_iqpphfifobyteselout;
+ wire wire_receive_pcs0_iqpphfifoptrsresetout;
+ wire wire_receive_pcs0_iqpphfifordenableout;
+ wire wire_receive_pcs0_iqpphfifowrclkout;
+ wire wire_receive_pcs0_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_pipedatavalid;
+ wire wire_receive_pcs0_pipeelecidle;
+ wire wire_receive_pcs0_pipephydonestatus;
+ wire wire_receive_pcs0_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs0_pipestatus;
+ wire wire_receive_pcs0_rateswitchout;
+ wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
+ wire wire_receive_pcs0_signaldetect;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs1_autospdrateswitchout;
+ wire wire_receive_pcs1_autospdspdchgout;
+ wire wire_receive_pcs1_cdrctrlearlyeios;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire [399:0] wire_receive_pcs1_dprioout;
+ wire wire_receive_pcs1_iqpphfifobyteselout;
+ wire wire_receive_pcs1_iqpphfifoptrsresetout;
+ wire wire_receive_pcs1_iqpphfifordenableout;
+ wire wire_receive_pcs1_iqpphfifowrclkout;
+ wire wire_receive_pcs1_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_pipedatavalid;
+ wire wire_receive_pcs1_pipeelecidle;
+ wire wire_receive_pcs1_pipephydonestatus;
+ wire wire_receive_pcs1_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs1_pipestatus;
+ wire wire_receive_pcs1_rateswitchout;
+ wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
+ wire wire_receive_pcs1_signaldetect;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs2_autospdrateswitchout;
+ wire wire_receive_pcs2_autospdspdchgout;
+ wire wire_receive_pcs2_cdrctrlearlyeios;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire [399:0] wire_receive_pcs2_dprioout;
+ wire wire_receive_pcs2_iqpphfifobyteselout;
+ wire wire_receive_pcs2_iqpphfifoptrsresetout;
+ wire wire_receive_pcs2_iqpphfifordenableout;
+ wire wire_receive_pcs2_iqpphfifowrclkout;
+ wire wire_receive_pcs2_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_pipedatavalid;
+ wire wire_receive_pcs2_pipeelecidle;
+ wire wire_receive_pcs2_pipephydonestatus;
+ wire wire_receive_pcs2_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs2_pipestatus;
+ wire wire_receive_pcs2_rateswitchout;
+ wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
+ wire wire_receive_pcs2_signaldetect;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs3_autospdrateswitchout;
+ wire wire_receive_pcs3_autospdspdchgout;
+ wire wire_receive_pcs3_cdrctrlearlyeios;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire [399:0] wire_receive_pcs3_dprioout;
+ wire wire_receive_pcs3_iqpphfifobyteselout;
+ wire wire_receive_pcs3_iqpphfifoptrsresetout;
+ wire wire_receive_pcs3_iqpphfifordenableout;
+ wire wire_receive_pcs3_iqpphfifowrclkout;
+ wire wire_receive_pcs3_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_pipedatavalid;
+ wire wire_receive_pcs3_pipeelecidle;
+ wire wire_receive_pcs3_pipephydonestatus;
+ wire wire_receive_pcs3_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs3_pipestatus;
+ wire wire_receive_pcs3_rateswitchout;
+ wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
+ wire wire_receive_pcs3_signaldetect;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire wire_receive_pcs4_autospdrateswitchout;
+ wire wire_receive_pcs4_autospdspdchgout;
+ wire wire_receive_pcs4_cdrctrlearlyeios;
+ wire wire_receive_pcs4_cdrctrllocktorefclkout;
+ wire wire_receive_pcs4_coreclkout;
+ wire [3:0] wire_receive_pcs4_ctrldetect;
+ wire [39:0] wire_receive_pcs4_dataout;
+ wire [399:0] wire_receive_pcs4_dprioout;
+ wire wire_receive_pcs4_iqpphfifobyteselout;
+ wire wire_receive_pcs4_iqpphfifoptrsresetout;
+ wire wire_receive_pcs4_iqpphfifordenableout;
+ wire wire_receive_pcs4_iqpphfifowrclkout;
+ wire wire_receive_pcs4_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs4_patterndetect;
+ wire wire_receive_pcs4_phfifobyteserdisableout;
+ wire wire_receive_pcs4_phfifoptrsresetout;
+ wire wire_receive_pcs4_phfifordenableout;
+ wire wire_receive_pcs4_phfiforesetout;
+ wire wire_receive_pcs4_phfifowrdisableout;
+ wire wire_receive_pcs4_pipedatavalid;
+ wire wire_receive_pcs4_pipeelecidle;
+ wire wire_receive_pcs4_pipephydonestatus;
+ wire wire_receive_pcs4_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs4_pipestatus;
+ wire wire_receive_pcs4_rateswitchout;
+ wire [19:0] wire_receive_pcs4_revparallelfdbkdata;
+ wire wire_receive_pcs4_signaldetect;
+ wire [3:0] wire_receive_pcs4_syncstatus;
+ wire wire_receive_pcs5_autospdrateswitchout;
+ wire wire_receive_pcs5_autospdspdchgout;
+ wire wire_receive_pcs5_cdrctrlearlyeios;
+ wire wire_receive_pcs5_cdrctrllocktorefclkout;
+ wire wire_receive_pcs5_coreclkout;
+ wire [3:0] wire_receive_pcs5_ctrldetect;
+ wire [39:0] wire_receive_pcs5_dataout;
+ wire [399:0] wire_receive_pcs5_dprioout;
+ wire wire_receive_pcs5_iqpphfifobyteselout;
+ wire wire_receive_pcs5_iqpphfifoptrsresetout;
+ wire wire_receive_pcs5_iqpphfifordenableout;
+ wire wire_receive_pcs5_iqpphfifowrclkout;
+ wire wire_receive_pcs5_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs5_patterndetect;
+ wire wire_receive_pcs5_phfifobyteserdisableout;
+ wire wire_receive_pcs5_phfifoptrsresetout;
+ wire wire_receive_pcs5_phfifordenableout;
+ wire wire_receive_pcs5_phfiforesetout;
+ wire wire_receive_pcs5_phfifowrdisableout;
+ wire wire_receive_pcs5_pipedatavalid;
+ wire wire_receive_pcs5_pipeelecidle;
+ wire wire_receive_pcs5_pipephydonestatus;
+ wire wire_receive_pcs5_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs5_pipestatus;
+ wire wire_receive_pcs5_rateswitchout;
+ wire [19:0] wire_receive_pcs5_revparallelfdbkdata;
+ wire wire_receive_pcs5_signaldetect;
+ wire [3:0] wire_receive_pcs5_syncstatus;
+ wire wire_receive_pcs6_autospdrateswitchout;
+ wire wire_receive_pcs6_autospdspdchgout;
+ wire wire_receive_pcs6_cdrctrlearlyeios;
+ wire wire_receive_pcs6_cdrctrllocktorefclkout;
+ wire wire_receive_pcs6_coreclkout;
+ wire [3:0] wire_receive_pcs6_ctrldetect;
+ wire [39:0] wire_receive_pcs6_dataout;
+ wire [399:0] wire_receive_pcs6_dprioout;
+ wire wire_receive_pcs6_iqpphfifobyteselout;
+ wire wire_receive_pcs6_iqpphfifoptrsresetout;
+ wire wire_receive_pcs6_iqpphfifordenableout;
+ wire wire_receive_pcs6_iqpphfifowrclkout;
+ wire wire_receive_pcs6_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs6_patterndetect;
+ wire wire_receive_pcs6_phfifobyteserdisableout;
+ wire wire_receive_pcs6_phfifoptrsresetout;
+ wire wire_receive_pcs6_phfifordenableout;
+ wire wire_receive_pcs6_phfiforesetout;
+ wire wire_receive_pcs6_phfifowrdisableout;
+ wire wire_receive_pcs6_pipedatavalid;
+ wire wire_receive_pcs6_pipeelecidle;
+ wire wire_receive_pcs6_pipephydonestatus;
+ wire wire_receive_pcs6_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs6_pipestatus;
+ wire wire_receive_pcs6_rateswitchout;
+ wire [19:0] wire_receive_pcs6_revparallelfdbkdata;
+ wire wire_receive_pcs6_signaldetect;
+ wire [3:0] wire_receive_pcs6_syncstatus;
+ wire wire_receive_pcs7_autospdrateswitchout;
+ wire wire_receive_pcs7_autospdspdchgout;
+ wire wire_receive_pcs7_cdrctrlearlyeios;
+ wire wire_receive_pcs7_cdrctrllocktorefclkout;
+ wire wire_receive_pcs7_coreclkout;
+ wire [3:0] wire_receive_pcs7_ctrldetect;
+ wire [39:0] wire_receive_pcs7_dataout;
+ wire [399:0] wire_receive_pcs7_dprioout;
+ wire wire_receive_pcs7_iqpphfifobyteselout;
+ wire wire_receive_pcs7_iqpphfifoptrsresetout;
+ wire wire_receive_pcs7_iqpphfifordenableout;
+ wire wire_receive_pcs7_iqpphfifowrclkout;
+ wire wire_receive_pcs7_iqpphfifowrenableout;
+ wire [3:0] wire_receive_pcs7_patterndetect;
+ wire wire_receive_pcs7_phfifobyteserdisableout;
+ wire wire_receive_pcs7_phfifoptrsresetout;
+ wire wire_receive_pcs7_phfifordenableout;
+ wire wire_receive_pcs7_phfiforesetout;
+ wire wire_receive_pcs7_phfifowrdisableout;
+ wire wire_receive_pcs7_pipedatavalid;
+ wire wire_receive_pcs7_pipeelecidle;
+ wire wire_receive_pcs7_pipephydonestatus;
+ wire wire_receive_pcs7_pipestatetransdoneout;
+ wire [2:0] wire_receive_pcs7_pipestatus;
+ wire wire_receive_pcs7_rateswitchout;
+ wire [19:0] wire_receive_pcs7_revparallelfdbkdata;
+ wire wire_receive_pcs7_signaldetect;
+ wire [3:0] wire_receive_pcs7_syncstatus;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire [7:0] wire_receive_pma1_analogtestbus;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire [299:0] wire_receive_pma1_dprioout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire [7:0] wire_receive_pma2_analogtestbus;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire [299:0] wire_receive_pma2_dprioout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire [7:0] wire_receive_pma3_analogtestbus;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire [299:0] wire_receive_pma3_dprioout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire [7:0] wire_receive_pma4_analogtestbus;
+ wire wire_receive_pma4_clockout;
+ wire wire_receive_pma4_dataout;
+ wire [299:0] wire_receive_pma4_dprioout;
+ wire wire_receive_pma4_locktorefout;
+ wire [63:0] wire_receive_pma4_recoverdataout;
+ wire wire_receive_pma4_signaldetect;
+ wire [7:0] wire_receive_pma5_analogtestbus;
+ wire wire_receive_pma5_clockout;
+ wire wire_receive_pma5_dataout;
+ wire [299:0] wire_receive_pma5_dprioout;
+ wire wire_receive_pma5_locktorefout;
+ wire [63:0] wire_receive_pma5_recoverdataout;
+ wire wire_receive_pma5_signaldetect;
+ wire [7:0] wire_receive_pma6_analogtestbus;
+ wire wire_receive_pma6_clockout;
+ wire wire_receive_pma6_dataout;
+ wire [299:0] wire_receive_pma6_dprioout;
+ wire wire_receive_pma6_locktorefout;
+ wire [63:0] wire_receive_pma6_recoverdataout;
+ wire wire_receive_pma6_signaldetect;
+ wire [7:0] wire_receive_pma7_analogtestbus;
+ wire wire_receive_pma7_clockout;
+ wire wire_receive_pma7_dataout;
+ wire [299:0] wire_receive_pma7_dprioout;
+ wire wire_receive_pma7_locktorefout;
+ wire [63:0] wire_receive_pma7_recoverdataout;
+ wire wire_receive_pma7_signaldetect;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
+ wire wire_transmit_pcs0_iqpphfifobyteselout;
+ wire wire_transmit_pcs0_iqpphfifordclkout;
+ wire wire_transmit_pcs0_iqpphfifordenableout;
+ wire wire_transmit_pcs0_iqpphfifowrenableout;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire wire_transmit_pcs0_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs0_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs0_pipepowerstateout;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire [149:0] wire_transmit_pcs1_dprioout;
+ wire wire_transmit_pcs1_forceelecidleout;
+ wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
+ wire wire_transmit_pcs1_iqpphfifobyteselout;
+ wire wire_transmit_pcs1_iqpphfifordclkout;
+ wire wire_transmit_pcs1_iqpphfifordenableout;
+ wire wire_transmit_pcs1_iqpphfifowrenableout;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire wire_transmit_pcs1_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs1_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs1_pipepowerstateout;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire [149:0] wire_transmit_pcs2_dprioout;
+ wire wire_transmit_pcs2_forceelecidleout;
+ wire [2:0] wire_transmit_pcs2_grayelecidleinferselout;
+ wire wire_transmit_pcs2_iqpphfifobyteselout;
+ wire wire_transmit_pcs2_iqpphfifordclkout;
+ wire wire_transmit_pcs2_iqpphfifordenableout;
+ wire wire_transmit_pcs2_iqpphfifowrenableout;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire wire_transmit_pcs2_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs2_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs2_pipepowerstateout;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire [149:0] wire_transmit_pcs3_dprioout;
+ wire wire_transmit_pcs3_forceelecidleout;
+ wire [2:0] wire_transmit_pcs3_grayelecidleinferselout;
+ wire wire_transmit_pcs3_iqpphfifobyteselout;
+ wire wire_transmit_pcs3_iqpphfifordclkout;
+ wire wire_transmit_pcs3_iqpphfifordenableout;
+ wire wire_transmit_pcs3_iqpphfifowrenableout;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire wire_transmit_pcs3_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs3_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs3_pipepowerstateout;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pcs4_coreclkout;
+ wire [19:0] wire_transmit_pcs4_dataout;
+ wire [149:0] wire_transmit_pcs4_dprioout;
+ wire wire_transmit_pcs4_forceelecidleout;
+ wire [2:0] wire_transmit_pcs4_grayelecidleinferselout;
+ wire wire_transmit_pcs4_iqpphfifobyteselout;
+ wire wire_transmit_pcs4_iqpphfifordclkout;
+ wire wire_transmit_pcs4_iqpphfifordenableout;
+ wire wire_transmit_pcs4_iqpphfifowrenableout;
+ wire wire_transmit_pcs4_phfiforddisableout;
+ wire wire_transmit_pcs4_phfiforesetout;
+ wire wire_transmit_pcs4_phfifowrenableout;
+ wire wire_transmit_pcs4_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs4_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs4_pipepowerstateout;
+ wire wire_transmit_pcs4_txdetectrx;
+ wire wire_transmit_pcs5_coreclkout;
+ wire [19:0] wire_transmit_pcs5_dataout;
+ wire [149:0] wire_transmit_pcs5_dprioout;
+ wire wire_transmit_pcs5_forceelecidleout;
+ wire [2:0] wire_transmit_pcs5_grayelecidleinferselout;
+ wire wire_transmit_pcs5_iqpphfifobyteselout;
+ wire wire_transmit_pcs5_iqpphfifordclkout;
+ wire wire_transmit_pcs5_iqpphfifordenableout;
+ wire wire_transmit_pcs5_iqpphfifowrenableout;
+ wire wire_transmit_pcs5_phfiforddisableout;
+ wire wire_transmit_pcs5_phfiforesetout;
+ wire wire_transmit_pcs5_phfifowrenableout;
+ wire wire_transmit_pcs5_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs5_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs5_pipepowerstateout;
+ wire wire_transmit_pcs5_txdetectrx;
+ wire wire_transmit_pcs6_coreclkout;
+ wire [19:0] wire_transmit_pcs6_dataout;
+ wire [149:0] wire_transmit_pcs6_dprioout;
+ wire wire_transmit_pcs6_forceelecidleout;
+ wire [2:0] wire_transmit_pcs6_grayelecidleinferselout;
+ wire wire_transmit_pcs6_iqpphfifobyteselout;
+ wire wire_transmit_pcs6_iqpphfifordclkout;
+ wire wire_transmit_pcs6_iqpphfifordenableout;
+ wire wire_transmit_pcs6_iqpphfifowrenableout;
+ wire wire_transmit_pcs6_phfiforddisableout;
+ wire wire_transmit_pcs6_phfiforesetout;
+ wire wire_transmit_pcs6_phfifowrenableout;
+ wire wire_transmit_pcs6_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs6_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs6_pipepowerstateout;
+ wire wire_transmit_pcs6_txdetectrx;
+ wire wire_transmit_pcs7_coreclkout;
+ wire [19:0] wire_transmit_pcs7_dataout;
+ wire [149:0] wire_transmit_pcs7_dprioout;
+ wire wire_transmit_pcs7_forceelecidleout;
+ wire [2:0] wire_transmit_pcs7_grayelecidleinferselout;
+ wire wire_transmit_pcs7_iqpphfifobyteselout;
+ wire wire_transmit_pcs7_iqpphfifordclkout;
+ wire wire_transmit_pcs7_iqpphfifordenableout;
+ wire wire_transmit_pcs7_iqpphfifowrenableout;
+ wire wire_transmit_pcs7_phfiforddisableout;
+ wire wire_transmit_pcs7_phfiforesetout;
+ wire wire_transmit_pcs7_phfifowrenableout;
+ wire wire_transmit_pcs7_pipeenrevparallellpbkout;
+ wire [1:0] wire_transmit_pcs7_pipepowerdownout;
+ wire [3:0] wire_transmit_pcs7_pipepowerstateout;
+ wire wire_transmit_pcs7_txdetectrx;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_rxdetectvalidout;
+ wire wire_transmit_pma0_rxfoundout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire [299:0] wire_transmit_pma1_dprioout;
+ wire wire_transmit_pma1_rxdetectvalidout;
+ wire wire_transmit_pma1_rxfoundout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire [299:0] wire_transmit_pma2_dprioout;
+ wire wire_transmit_pma2_rxdetectvalidout;
+ wire wire_transmit_pma2_rxfoundout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire [299:0] wire_transmit_pma3_dprioout;
+ wire wire_transmit_pma3_rxdetectvalidout;
+ wire wire_transmit_pma3_rxfoundout;
+ wire wire_transmit_pma4_clockout;
+ wire wire_transmit_pma4_dataout;
+ wire [299:0] wire_transmit_pma4_dprioout;
+ wire wire_transmit_pma4_rxdetectvalidout;
+ wire wire_transmit_pma4_rxfoundout;
+ wire wire_transmit_pma5_clockout;
+ wire wire_transmit_pma5_dataout;
+ wire [299:0] wire_transmit_pma5_dprioout;
+ wire wire_transmit_pma5_rxdetectvalidout;
+ wire wire_transmit_pma5_rxfoundout;
+ wire wire_transmit_pma6_clockout;
+ wire wire_transmit_pma6_dataout;
+ wire [299:0] wire_transmit_pma6_dprioout;
+ wire wire_transmit_pma6_rxdetectvalidout;
+ wire wire_transmit_pma6_rxfoundout;
+ wire wire_transmit_pma7_clockout;
+ wire wire_transmit_pma7_dataout;
+ wire [299:0] wire_transmit_pma7_dprioout;
+ wire wire_transmit_pma7_rxdetectvalidout;
+ wire wire_transmit_pma7_rxfoundout;
+ wire cal_blk_powerdown;
+ wire [1:0] cent_unit_clkdivpowerdn;
+ wire [1199:0] cent_unit_cmudividerdprioout;
+ wire [3599:0] cent_unit_cmuplldprioout;
+ wire [1:0] cent_unit_quadresetout;
+ wire [11:0] cent_unit_rxcrupowerdn;
+ wire [11:0] cent_unit_rxibpowerdn;
+ wire [3199:0] cent_unit_rxpcsdprioin;
+ wire [3199:0] cent_unit_rxpcsdprioout;
+ wire [3599:0] cent_unit_rxpmadprioin;
+ wire [3599:0] cent_unit_rxpmadprioout;
+ wire [2399:0] cent_unit_tx_dprioin;
+ wire [63:0] cent_unit_tx_xgmdataout;
+ wire [7:0] cent_unit_txctrlout;
+ wire [11:0] cent_unit_txdetectrxpowerdn;
+ wire [1199:0] cent_unit_txdprioout;
+ wire [11:0] cent_unit_txobpowerdn;
+ wire [3599:0] cent_unit_txpmadprioin;
+ wire [3599:0] cent_unit_txpmadprioout;
+ wire [1199:0] clk_div_cmudividerdprioin;
+ wire [1:0] clk_div_pclkin;
+ wire [3:0] clock_divider_clk0in;
+ wire [0:0] coreclkout_bi_quad_wire;
+ wire [1:0] coreclkout_wire;
+ wire [0:0] edge_cmu_clkdivpowerdn;
+ wire [0:0] edge_cmu_pllpowerdn;
+ wire [0:0] edge_cmu_pllresetout;
+ wire [0:0] edge_cmu_quadresetout;
+ wire [1:0] edge_pll_analogfastrefclkout;
+ wire [1:0] edge_pll_analogrefclkout;
+ wire [0:0] edge_pll_analogrefclkpulse;
+ wire [9:0] edge_pll_clkin;
+ wire [3:0] edge_pll_out;
+ wire [0:0] edge_pllpowerdn_in;
+ wire [0:0] edge_pllreset_in;
+ wire fixedclk;
+ wire [11:0] fixedclk_to_cmu;
+ wire [23:0] grayelecidleinfersel_from_tx;
+ wire [0:0] int_atx_hiprateswtichdone;
+ wire [1:0] int_autospdx4configsel;
+ wire [1:0] int_autospdx4spdchg;
+ wire [1:0] int_hiprateswtichdone;
+ wire [1:0] int_pcie_sw;
+ wire [1:0] int_pcie_sw_select;
+ wire [1:0] int_phfifiox4ptrsreset;
+ wire [7:0] int_pipeenrevparallellpbkfromtx;
+ wire [1:0] int_pll_reset_delayed;
+ wire [1:0] int_rateswitch;
+ wire [1:0] int_rateswitchout;
+ wire [7:0] int_rx_autospdspdchgout;
+ wire [23:0] int_rx_autospdxnconfigsel;
+ wire [23:0] int_rx_autospdxnspdchg;
+ wire [7:0] int_rx_coreclkout;
+ wire [0:0] int_rx_digitalreset_reg;
+ wire [15:0] int_rx_iqpautospdxnspgchg;
+ wire [7:0] int_rx_iqpphfifobyteselout;
+ wire [7:0] int_rx_iqpphfifoptrsresetout;
+ wire [7:0] int_rx_iqpphfifordenableout;
+ wire [7:0] int_rx_iqpphfifowrclkout;
+ wire [7:0] int_rx_iqpphfifowrenableout;
+ wire [15:0] int_rx_iqpphfifoxnbytesel;
+ wire [15:0] int_rx_iqpphfifoxnptrsreset;
+ wire [15:0] int_rx_iqpphfifoxnrdenable;
+ wire [15:0] int_rx_iqpphfifoxnwrclk;
+ wire [15:0] int_rx_iqpphfifoxnwrenable;
+ wire [23:0] int_rx_phfifioxnptrsreset;
+ wire [7:0] int_rx_phfifobyteserdisable;
+ wire [7:0] int_rx_phfifoptrsresetout;
+ wire [7:0] int_rx_phfifordenableout;
+ wire [7:0] int_rx_phfiforesetout;
+ wire [7:0] int_rx_phfifowrdisableout;
+ wire [23:0] int_rx_phfifoxnbytesel;
+ wire [23:0] int_rx_phfifoxnrdenable;
+ wire [23:0] int_rx_phfifoxnwrclk;
+ wire [23:0] int_rx_phfifoxnwrenable;
+ wire [7:0] int_rx_rateswitchout;
+ wire [1:0] int_rxcoreclk;
+ wire [7:0] int_rxpcs_cdrctrlearlyeios;
+ wire [1:0] int_rxphfifordenable;
+ wire [1:0] int_rxphfiforeset;
+ wire [1:0] int_rxphfifox4byteselout;
+ wire [1:0] int_rxphfifox4rdenableout;
+ wire [1:0] int_rxphfifox4wrclkout;
+ wire [1:0] int_rxphfifox4wrenableout;
+ wire [7:0] int_tx_coreclkout;
+ wire [0:0] int_tx_digitalreset_reg;
+ wire [7:0] int_tx_iqpphfifobyteselout;
+ wire [7:0] int_tx_iqpphfifordclkout;
+ wire [7:0] int_tx_iqpphfifordenableout;
+ wire [7:0] int_tx_iqpphfifowrenableout;
+ wire [15:0] int_tx_iqpphfifoxnbytesel;
+ wire [15:0] int_tx_iqpphfifoxnrdclk;
+ wire [15:0] int_tx_iqpphfifoxnrdenable;
+ wire [15:0] int_tx_iqpphfifoxnwrenable;
+ wire [23:0] int_tx_phfifioxnptrsreset;
+ wire [7:0] int_tx_phfiforddisableout;
+ wire [7:0] int_tx_phfiforesetout;
+ wire [7:0] int_tx_phfifowrenableout;
+ wire [23:0] int_tx_phfifoxnbytesel;
+ wire [23:0] int_tx_phfifoxnrdclk;
+ wire [23:0] int_tx_phfifoxnrdenable;
+ wire [23:0] int_tx_phfifoxnwrenable;
+ wire [1:0] int_txcoreclk;
+ wire [1:0] int_txphfiforddisable;
+ wire [1:0] int_txphfiforeset;
+ wire [1:0] int_txphfifowrenable;
+ wire [1:0] int_txphfifox4byteselout;
+ wire [1:0] int_txphfifox4rdclkout;
+ wire [1:0] int_txphfifox4rdenableout;
+ wire [1:0] int_txphfifox4wrenableout;
+ wire [1:0] nonusertocmu_out;
+ wire [0:0] nonusertocmu_out_pll;
+ wire [1:0] pcie_sw_wire;
+ wire [7:0] pipedatavalid_out;
+ wire [7:0] pipeelecidle_out;
+ wire [15:0] pll_ch_dataout_wire;
+ wire [2399:0] pll_ch_dprioout;
+ wire [3599:0] pll_cmuplldprioout;
+ wire [0:0] pll_edge_locked_out;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_powerdown;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [1:0] refclk_pma;
+ wire [0:0] refclk_pma_wire;
+ wire [11:0] rx_analogreset_in;
+ wire [11:0] rx_analogreset_out;
+ wire [7:0] rx_coreclk_in;
+ wire [79:0] rx_cruclk_in;
+ wire [31:0] rx_deserclock_in;
+ wire [7:0] rx_digitalreset_in;
+ wire [7:0] rx_digitalreset_out;
+ wire [23:0] rx_elecidleinfersel;
+ wire [7:0] rx_enapatternalign;
+ wire [7:0] rx_freqlocked_wire;
+ wire [7:0] rx_locktodata;
+ wire [7:0] rx_locktodata_wire;
+ wire [7:0] rx_locktorefclk_wire;
+ wire [127:0] rx_out_wire;
+ wire [15:0] rx_pcs_rxfound_wire;
+ wire [3199:0] rx_pcsdprioin_wire;
+ wire [3199:0] rx_pcsdprioout;
+ wire [7:0] rx_phfifordenable;
+ wire [7:0] rx_phfiforeset;
+ wire [7:0] rx_phfifowrdisable;
+ wire [7:0] rx_pipestatetransdoneout;
+ wire [7:0] rx_pldcruclk_in;
+ wire [31:0] rx_pll_clkout;
+ wire [7:0] rx_pll_pfdrefclkout_wire;
+ wire [7:0] rx_plllocked_wire;
+ wire [135:0] rx_pma_analogtestbus;
+ wire [7:0] rx_pma_clockout;
+ wire [7:0] rx_pma_dataout;
+ wire [7:0] rx_pma_locktorefout;
+ wire [159:0] rx_pma_recoverdataout_wire;
+ wire [3599:0] rx_pmadprioin_wire;
+ wire [3599:0] rx_pmadprioout;
+ wire [7:0] rx_powerdown;
+ wire [11:0] rx_powerdown_in;
+ wire [7:0] rx_prbscidenable;
+ wire [159:0] rx_revparallelfdbkdata;
+ wire [7:0] rx_rmfiforeset;
+ wire [11:0] rx_rxcruresetout;
+ wire [7:0] rx_signaldetect_wire;
+ wire [1:0] rxphfifowrdisable;
+ wire [3599:0] rxpll_dprioin;
+ wire [11:0] tx_analogreset_out;
+ wire [7:0] tx_clkout_int_wire;
+ wire [7:0] tx_coreclk_in;
+ wire [127:0] tx_datain_wire;
+ wire [159:0] tx_dataout_pcs_to_pma;
+ wire [7:0] tx_digitalreset_in;
+ wire [7:0] tx_digitalreset_out;
+ wire [2399:0] tx_dprioin_wire;
+ wire [15:0] tx_forcedisp_wire;
+ wire [7:0] tx_invpolarity;
+ wire [7:0] tx_localrefclk;
+ wire [7:0] tx_pcs_forceelecidleout;
+ wire [7:0] tx_phfiforeset;
+ wire [15:0] tx_pipepowerdownout;
+ wire [31:0] tx_pipepowerstateout;
+ wire [7:0] tx_pipeswing;
+ wire [3599:0] tx_pmadprioin_wire;
+ wire [3599:0] tx_pmadprioout;
+ wire [7:0] tx_revparallellpbken;
+ wire [7:0] tx_rxdetectvalidout;
+ wire [7:0] tx_rxfoundout;
+ wire [1199:0] tx_txdprioout;
+ wire [7:0] txdetectrxout;
+ wire [1:0] w_cent_unit_dpriodisableout1w;
+
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[0:0])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[0:0] == 1'b0) pcie_sw_sel_delay_blk0c[0:0] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[0:0] <= wire_pcie_sw_sel_delay_blk0c_d[0:0];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[1:1])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[1:1] == 1'b0) pcie_sw_sel_delay_blk0c[1:1] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[1:1] <= wire_pcie_sw_sel_delay_blk0c_d[1:1];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[2:2])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[2:2] == 1'b0) pcie_sw_sel_delay_blk0c[2:2] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[2:2] <= wire_pcie_sw_sel_delay_blk0c_d[2:2];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[3:3])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[3:3] == 1'b0) pcie_sw_sel_delay_blk0c[3:3] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[3:3] <= wire_pcie_sw_sel_delay_blk0c_d[3:3];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[4:4])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[4:4] == 1'b0) pcie_sw_sel_delay_blk0c[4:4] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[4:4] <= wire_pcie_sw_sel_delay_blk0c_d[4:4];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[5:5])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[5:5] == 1'b0) pcie_sw_sel_delay_blk0c[5:5] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[5:5] <= wire_pcie_sw_sel_delay_blk0c_d[5:5];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[6:6])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[6:6] == 1'b0) pcie_sw_sel_delay_blk0c[6:6] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[6:6] <= wire_pcie_sw_sel_delay_blk0c_d[6:6];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[7:7])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[7:7] == 1'b0) pcie_sw_sel_delay_blk0c[7:7] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[7:7] <= wire_pcie_sw_sel_delay_blk0c_d[7:7];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[8:8])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[8:8] == 1'b0) pcie_sw_sel_delay_blk0c[8:8] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[8:8] <= wire_pcie_sw_sel_delay_blk0c_d[8:8];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk0c[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk0c_prn[9:9])
+ if (wire_pcie_sw_sel_delay_blk0c_prn[9:9] == 1'b0) pcie_sw_sel_delay_blk0c[9:9] <= 1'b1;
+ else pcie_sw_sel_delay_blk0c[9:9] <= wire_pcie_sw_sel_delay_blk0c_d[9:9];
+ assign
+ wire_pcie_sw_sel_delay_blk0c_d = {pcie_sw_sel_delay_blk0c[8:0], pllreset_delay_blk0c[9]};
+ assign
+ wire_pcie_sw_sel_delay_blk0c_prn = {10{(~ pll_powerdown[0])}};
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[0:0])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[0:0] == 1'b0) pcie_sw_sel_delay_blk1c[0:0] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[0:0] <= wire_pcie_sw_sel_delay_blk1c_d[0:0];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[1:1])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[1:1] == 1'b0) pcie_sw_sel_delay_blk1c[1:1] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[1:1] <= wire_pcie_sw_sel_delay_blk1c_d[1:1];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[2:2])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[2:2] == 1'b0) pcie_sw_sel_delay_blk1c[2:2] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[2:2] <= wire_pcie_sw_sel_delay_blk1c_d[2:2];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[3:3])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[3:3] == 1'b0) pcie_sw_sel_delay_blk1c[3:3] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[3:3] <= wire_pcie_sw_sel_delay_blk1c_d[3:3];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[4:4])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[4:4] == 1'b0) pcie_sw_sel_delay_blk1c[4:4] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[4:4] <= wire_pcie_sw_sel_delay_blk1c_d[4:4];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[5:5])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[5:5] == 1'b0) pcie_sw_sel_delay_blk1c[5:5] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[5:5] <= wire_pcie_sw_sel_delay_blk1c_d[5:5];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[6:6])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[6:6] == 1'b0) pcie_sw_sel_delay_blk1c[6:6] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[6:6] <= wire_pcie_sw_sel_delay_blk1c_d[6:6];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[7:7])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[7:7] == 1'b0) pcie_sw_sel_delay_blk1c[7:7] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[7:7] <= wire_pcie_sw_sel_delay_blk1c_d[7:7];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[8:8])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[8:8] == 1'b0) pcie_sw_sel_delay_blk1c[8:8] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[8:8] <= wire_pcie_sw_sel_delay_blk1c_d[8:8];
+ // synopsys translate_off
+ initial
+ pcie_sw_sel_delay_blk1c[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pcie_sw_sel_delay_blk1c_prn[9:9])
+ if (wire_pcie_sw_sel_delay_blk1c_prn[9:9] == 1'b0) pcie_sw_sel_delay_blk1c[9:9] <= 1'b1;
+ else pcie_sw_sel_delay_blk1c[9:9] <= wire_pcie_sw_sel_delay_blk1c_d[9:9];
+ assign
+ wire_pcie_sw_sel_delay_blk1c_d = {pcie_sw_sel_delay_blk1c[8:0], pllreset_delay_blk1c[9]};
+ assign
+ wire_pcie_sw_sel_delay_blk1c_prn = {10{(~ pll_powerdown[0])}};
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[0:0])
+ if (wire_pllreset_delay_blk0c_prn[0:0] == 1'b0) pllreset_delay_blk0c[0:0] <= 1'b1;
+ else pllreset_delay_blk0c[0:0] <= wire_pllreset_delay_blk0c_d[0:0];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[1:1])
+ if (wire_pllreset_delay_blk0c_prn[1:1] == 1'b0) pllreset_delay_blk0c[1:1] <= 1'b1;
+ else pllreset_delay_blk0c[1:1] <= wire_pllreset_delay_blk0c_d[1:1];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[2:2])
+ if (wire_pllreset_delay_blk0c_prn[2:2] == 1'b0) pllreset_delay_blk0c[2:2] <= 1'b1;
+ else pllreset_delay_blk0c[2:2] <= wire_pllreset_delay_blk0c_d[2:2];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[3:3])
+ if (wire_pllreset_delay_blk0c_prn[3:3] == 1'b0) pllreset_delay_blk0c[3:3] <= 1'b1;
+ else pllreset_delay_blk0c[3:3] <= wire_pllreset_delay_blk0c_d[3:3];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[4:4])
+ if (wire_pllreset_delay_blk0c_prn[4:4] == 1'b0) pllreset_delay_blk0c[4:4] <= 1'b1;
+ else pllreset_delay_blk0c[4:4] <= wire_pllreset_delay_blk0c_d[4:4];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[5:5])
+ if (wire_pllreset_delay_blk0c_prn[5:5] == 1'b0) pllreset_delay_blk0c[5:5] <= 1'b1;
+ else pllreset_delay_blk0c[5:5] <= wire_pllreset_delay_blk0c_d[5:5];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[6:6])
+ if (wire_pllreset_delay_blk0c_prn[6:6] == 1'b0) pllreset_delay_blk0c[6:6] <= 1'b1;
+ else pllreset_delay_blk0c[6:6] <= wire_pllreset_delay_blk0c_d[6:6];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[7:7])
+ if (wire_pllreset_delay_blk0c_prn[7:7] == 1'b0) pllreset_delay_blk0c[7:7] <= 1'b1;
+ else pllreset_delay_blk0c[7:7] <= wire_pllreset_delay_blk0c_d[7:7];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[8:8])
+ if (wire_pllreset_delay_blk0c_prn[8:8] == 1'b0) pllreset_delay_blk0c[8:8] <= 1'b1;
+ else pllreset_delay_blk0c[8:8] <= wire_pllreset_delay_blk0c_d[8:8];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk0c[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk0c_prn[9:9])
+ if (wire_pllreset_delay_blk0c_prn[9:9] == 1'b0) pllreset_delay_blk0c[9:9] <= 1'b1;
+ else pllreset_delay_blk0c[9:9] <= wire_pllreset_delay_blk0c_d[9:9];
+ assign
+ wire_pllreset_delay_blk0c_d = {pllreset_delay_blk0c[8:0], (pll_powerdown[0] | (~ pll_edge_locked_out[0]))};
+ assign
+ wire_pllreset_delay_blk0c_prn = {10{(~ pll_powerdown[0])}};
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[0:0])
+ if (wire_pllreset_delay_blk1c_prn[0:0] == 1'b0) pllreset_delay_blk1c[0:0] <= 1'b1;
+ else pllreset_delay_blk1c[0:0] <= wire_pllreset_delay_blk1c_d[0:0];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[1:1])
+ if (wire_pllreset_delay_blk1c_prn[1:1] == 1'b0) pllreset_delay_blk1c[1:1] <= 1'b1;
+ else pllreset_delay_blk1c[1:1] <= wire_pllreset_delay_blk1c_d[1:1];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[2:2])
+ if (wire_pllreset_delay_blk1c_prn[2:2] == 1'b0) pllreset_delay_blk1c[2:2] <= 1'b1;
+ else pllreset_delay_blk1c[2:2] <= wire_pllreset_delay_blk1c_d[2:2];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[3:3] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[3:3])
+ if (wire_pllreset_delay_blk1c_prn[3:3] == 1'b0) pllreset_delay_blk1c[3:3] <= 1'b1;
+ else pllreset_delay_blk1c[3:3] <= wire_pllreset_delay_blk1c_d[3:3];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[4:4] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[4:4])
+ if (wire_pllreset_delay_blk1c_prn[4:4] == 1'b0) pllreset_delay_blk1c[4:4] <= 1'b1;
+ else pllreset_delay_blk1c[4:4] <= wire_pllreset_delay_blk1c_d[4:4];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[5:5] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[5:5])
+ if (wire_pllreset_delay_blk1c_prn[5:5] == 1'b0) pllreset_delay_blk1c[5:5] <= 1'b1;
+ else pllreset_delay_blk1c[5:5] <= wire_pllreset_delay_blk1c_d[5:5];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[6:6] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[6:6])
+ if (wire_pllreset_delay_blk1c_prn[6:6] == 1'b0) pllreset_delay_blk1c[6:6] <= 1'b1;
+ else pllreset_delay_blk1c[6:6] <= wire_pllreset_delay_blk1c_d[6:6];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[7:7] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[7:7])
+ if (wire_pllreset_delay_blk1c_prn[7:7] == 1'b0) pllreset_delay_blk1c[7:7] <= 1'b1;
+ else pllreset_delay_blk1c[7:7] <= wire_pllreset_delay_blk1c_d[7:7];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[8:8] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[8:8])
+ if (wire_pllreset_delay_blk1c_prn[8:8] == 1'b0) pllreset_delay_blk1c[8:8] <= 1'b1;
+ else pllreset_delay_blk1c[8:8] <= wire_pllreset_delay_blk1c_d[8:8];
+ // synopsys translate_off
+ initial
+ pllreset_delay_blk1c[9:9] = 0;
+ // synopsys translate_on
+ always @ ( posedge fixedclk or negedge wire_pllreset_delay_blk1c_prn[9:9])
+ if (wire_pllreset_delay_blk1c_prn[9:9] == 1'b0) pllreset_delay_blk1c[9:9] <= 1'b1;
+ else pllreset_delay_blk1c[9:9] <= wire_pllreset_delay_blk1c_d[9:9];
+ assign
+ wire_pllreset_delay_blk1c_d = {pllreset_delay_blk1c[8:0], (pll_powerdown[0] | (~ pll_edge_locked_out[0]))};
+ assign
+ wire_pllreset_delay_blk1c_prn = {10{(~ pll_powerdown[0])}};
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
+ rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
+ rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
+ rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
+ assign
+ wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
+ tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
+ tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
+ tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
+ assign
+ wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_calibration_block cal_blk1
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk1_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_calibration_block pll_cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_pll_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider atx_clk_div0
+ (
+ .analogfastrefclkout(wire_atx_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_atx_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_atx_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clock_divider_clk0in[3:0]),
+ .coreclkout(),
+ .dpriodisable(1'b1),
+ .dprioout(),
+ .powerdn(edge_cmu_clkdivpowerdn[0]),
+ .quadreset(edge_cmu_quadresetout[0]),
+ .rateswitch(int_rateswitchout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_atx_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkout(wire_atx_clk_div0_refclkout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .dprioin({100{1'b0}}),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ atx_clk_div0.divide_by = 5,
+ atx_clk_div0.divider_type = "ATX_REGULAR",
+ atx_clk_div0.effective_data_rate = "5000 Mbps",
+ atx_clk_div0.enable_dynamic_divider = "true",
+ atx_clk_div0.enable_refclk_out = "true",
+ atx_clk_div0.select_local_rate_switch_base_clock = "true",
+ atx_clk_div0.select_local_rate_switch_done = "true",
+ atx_clk_div0.select_local_refclk = "true",
+ atx_clk_div0.use_refclk_post_divider = "false",
+ atx_clk_div0.use_vco_bypass = "false",
+ atx_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(),
+ .analogrefclkpulseshifted(),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[499:400]),
+ .dprioout(wire_central_clk_div0_dprioout),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(int_pcie_sw[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchdonein({{1{1'b0}}, int_atx_hiprateswtichdone}),
+ .rateswitchout(wire_central_clk_div0_rateswitchout),
+ .refclkin({{1{1'b0}}, clk_div_pclkin[0]}),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk0in({4{1'b0}}),
+ .clk1in({4{1'b0}}),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .refclkdig(1'b0),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.effective_data_rate = "5000 Mbps",
+ central_clk_div0.enable_dynamic_divider = "true",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_rate_switch_done = "false",
+ central_clk_div0.select_local_refclk = "false",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "true",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_clock_divider central_clk_div1
+ (
+ .analogfastrefclkout(),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(),
+ .analogrefclkpulseshifted(),
+ .coreclkout(wire_central_clk_div1_coreclkout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(cent_unit_cmudividerdprioout[1099:1000]),
+ .dprioout(wire_central_clk_div1_dprioout),
+ .powerdn(cent_unit_clkdivpowerdn[1]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div1_rateswitchdone),
+ .rateswitchdonein({{1{1'b0}}, int_atx_hiprateswtichdone}),
+ .rateswitchout(wire_central_clk_div1_rateswitchout),
+ .refclkin({{1{1'b0}}, clk_div_pclkin[1]}),
+ .refclkout(wire_central_clk_div1_refclkout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk0in({4{1'b0}}),
+ .clk1in({4{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .refclkdig(1'b0),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div1.divide_by = 5,
+ central_clk_div1.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div1.effective_data_rate = "5000 Mbps",
+ central_clk_div1.enable_dynamic_divider = "true",
+ central_clk_div1.enable_refclk_out = "true",
+ central_clk_div1.inclk_select = 0,
+ central_clk_div1.logical_channel_address = 0,
+ central_clk_div1.pre_divide_by = 1,
+ central_clk_div1.refclkin_select = 0,
+ central_clk_div1.select_local_rate_switch_done = "false",
+ central_clk_div1.select_local_refclk = "false",
+ central_clk_div1.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div1.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div1.sim_coreclkout_phase_shift = 0,
+ central_clk_div1.sim_refclkout_phase_shift = 0,
+ central_clk_div1.use_coreclk_out_post_divider = "true",
+ central_clk_div1.use_refclk_post_divider = "false",
+ central_clk_div1.use_vco_bypass = "false",
+ central_clk_div1.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu atx_pll_cent_unit0
+ (
+ .alignstatus(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_atx_pll_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioout(),
+ .cmuplldprioout(),
+ .digitaltestout(),
+ .dpriodisableout(),
+ .dpriooe(),
+ .dprioout(),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out_pll[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_atx_pll_cent_unit0_pllpowerdn),
+ .pllresetout(wire_atx_pll_cent_unit0_pllresetout),
+ .quadreset(pll_powerdown[0]),
+ .quadresetout(wire_atx_pll_cent_unit0_quadresetout),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogresetout(),
+ .rxcrupowerdown(),
+ .rxcruresetout(),
+ .rxctrlout(),
+ .rxdataout(),
+ .rxdigitalresetout(),
+ .rxibpowerdown(),
+ .rxpcsdprioout(),
+ .rxphfifox4byteselout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4wrclkout(),
+ .rxphfifox4wrenableout(),
+ .rxpmadprioout(),
+ .scanout(),
+ .testout(),
+ .txanalogresetout(),
+ .txctrlout(),
+ .txdataout(),
+ .txdetectrxpowerdown(),
+ .txdigitalresetout(),
+ .txdividerpowerdown(),
+ .txobpowerdown(),
+ .txpcsdprioout(),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4wrenableout(),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adet({4{1'b0}}),
+ .cmudividerdprioin({600{1'b0}}),
+ .cmuplldprioin({1800{1'b0}}),
+ .dpclk(1'b0),
+ .dpriodisable(1'b1),
+ .dprioin(1'b0),
+ .dprioload(1'b0),
+ .extra10gin({7{1'b0}}),
+ .fixedclk({6{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchdonein(1'b0),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b1),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .rxanalogreset({6{1'b0}}),
+ .rxclk(1'b0),
+ .rxcoreclk(1'b0),
+ .rxctrl({4{1'b0}}),
+ .rxdatain({32{1'b0}}),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({4{1'b0}}),
+ .rxpcsdprioin({1600{1'b0}}),
+ .rxphfifordenable(1'b1),
+ .rxphfiforeset(1'b0),
+ .rxphfifowrdisable(1'b0),
+ .rxpmadprioin({1800{1'b0}}),
+ .rxpowerdown({6{1'b0}}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .syncstatus({4{1'b0}}),
+ .testin({10000{1'b0}}),
+ .txclk(1'b0),
+ .txcoreclk(1'b0),
+ .txctrl({4{1'b0}}),
+ .txdatain({32{1'b0}}),
+ .txdigitalreset({4{1'b0}}),
+ .txpcsdprioin({600{1'b0}}),
+ .txphfiforddisable(1'b0),
+ .txphfiforeset(1'b0),
+ .txphfifowrenable(1'b0),
+ .txpmadprioin({1800{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ atx_pll_cent_unit0.cmu_type = "atx",
+ atx_pll_cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(wire_cent_unit0_autospdx4configsel),
+ .autospdx4rateswitchout(wire_cent_unit0_autospdx4rateswitchout),
+ .autospdx4spdchg(wire_cent_unit0_autospdx4spdchg),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin(clk_div_cmudividerdprioin[599:0]),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(wire_cent_unit0_digitaltestout),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(wire_cent_unit0_phfifiox4ptrsreset),
+ .pllpowerdn(),
+ .pllresetout(),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitch(int_rateswitch[0]),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}}),
+ .txpllreset({2{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 14,
+ cent_unit0.bonded_quad_mode = "driver",
+ cent_unit0.central_test_bus_select = 0,
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "false",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "true",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 249950,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "true",
+ cent_unit0.rx0_channel_bonding = "x8",
+ cent_unit0.rx0_clk1_mux_select = "recovered clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "true",
+ cent_unit0.tx0_channel_bonding = "x8",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "false",
+ cent_unit0.vcceh_voltage = "3.0V",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_cmu cent_unit1
+ (
+ .adet({4{1'b0}}),
+ .alignstatus(),
+ .autospdx4configsel(wire_cent_unit1_autospdx4configsel),
+ .autospdx4rateswitchout(wire_cent_unit1_autospdx4rateswitchout),
+ .autospdx4spdchg(wire_cent_unit1_autospdx4spdchg),
+ .clkdivpowerdn(wire_cent_unit1_clkdivpowerdn),
+ .cmudividerdprioin(clk_div_cmudividerdprioin[1199:600]),
+ .cmudividerdprioout(wire_cent_unit1_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[3599:1800]),
+ .cmuplldprioout(wire_cent_unit1_cmuplldprioout),
+ .digitaltestout(wire_cent_unit1_digitaltestout),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit1_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit1_dprioout),
+ .enabledeskew(),
+ .extra10gout(),
+ .fiforesetrd(),
+ .fixedclk({{2{1'b0}}, fixedclk_to_cmu[9:6]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[1]),
+ .phfifiox4ptrsreset(wire_cent_unit1_phfifiox4ptrsreset),
+ .pllpowerdn(),
+ .pllresetout(),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit1_quadresetout),
+ .rateswitch(int_rateswitch[1]),
+ .rateswitchdonein(int_hiprateswtichdone[1]),
+ .rdalign({4{1'b0}}),
+ .rdenablesync(1'b0),
+ .recovclk(1'b0),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[7:4]}),
+ .rxanalogresetout(wire_cent_unit1_rxanalogresetout),
+ .rxclk(refclk_pma[1]),
+ .rxcoreclk(int_rxcoreclk[1]),
+ .rxcrupowerdown(wire_cent_unit1_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit1_rxcruresetout),
+ .rxctrl({4{1'b0}}),
+ .rxctrlout(),
+ .rxdatain({32{1'b0}}),
+ .rxdataout(),
+ .rxdatavalid({4{1'b0}}),
+ .rxdigitalreset({rx_digitalreset_in[7:4]}),
+ .rxdigitalresetout(wire_cent_unit1_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit1_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[3199:1600]}),
+ .rxpcsdprioout(wire_cent_unit1_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[1]),
+ .rxphfiforeset(int_rxphfiforeset[1]),
+ .rxphfifowrdisable(rxphfifowrdisable[1]),
+ .rxphfifox4byteselout(wire_cent_unit1_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit1_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit1_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit1_rxphfifox4wrenableout),
+ .rxpmadprioin({cent_unit_rxpmadprioin[3599:1800]}),
+ .rxpmadprioout(wire_cent_unit1_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[7:4]}),
+ .rxrunningdisp({4{1'b0}}),
+ .scanout(),
+ .syncstatus({4{1'b0}}),
+ .testout(),
+ .txanalogresetout(wire_cent_unit1_txanalogresetout),
+ .txclk(refclk_pma[1]),
+ .txcoreclk(int_txcoreclk[1]),
+ .txctrl({4{1'b0}}),
+ .txctrlout(wire_cent_unit1_txctrlout),
+ .txdatain({32{1'b0}}),
+ .txdataout(wire_cent_unit1_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit1_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[7:4]}),
+ .txdigitalresetout(wire_cent_unit1_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit1_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[1199:600]}),
+ .txpcsdprioout(wire_cent_unit1_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[1]),
+ .txphfiforeset(int_txphfiforeset[1]),
+ .txphfifowrenable(int_txphfifowrenable[1]),
+ .txphfifox4byteselout(wire_cent_unit1_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit1_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit1_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit1_txphfifox4wrenableout),
+ .txpmadprioin({cent_unit_txpmadprioin[3599:1800]}),
+ .txpmadprioout(wire_cent_unit1_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}}),
+ .txpllreset({2{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit1.auto_spd_phystatus_notify_count = 14,
+ cent_unit1.bonded_quad_mode = "receiver",
+ cent_unit1.central_test_bus_select = 0,
+ cent_unit1.devaddr = ((((starting_channel_number / 4) + 1) % 32) + 1),
+ cent_unit1.in_xaui_mode = "false",
+ cent_unit1.offset_all_errors_align = "false",
+ cent_unit1.pipe_auto_speed_nego_enable = "true",
+ cent_unit1.pipe_freq_scale_mode = "Frequency",
+ cent_unit1.pma_done_count = 249950,
+ cent_unit1.portaddr = (((starting_channel_number + 4) / 128) + 1),
+ cent_unit1.rx0_auto_spd_self_switch_enable = "true",
+ cent_unit1.rx0_channel_bonding = "x8",
+ cent_unit1.rx0_clk1_mux_select = "recovered clock",
+ cent_unit1.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit1.rx0_ph_fifo_reg_mode = "false",
+ cent_unit1.rx0_rd_clk_mux_select = "core clock",
+ cent_unit1.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit1.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit1.rx0_use_double_data_mode = "true",
+ cent_unit1.tx0_auto_spd_self_switch_enable = "true",
+ cent_unit1.tx0_channel_bonding = "x8",
+ cent_unit1.tx0_ph_fifo_reg_mode = "false",
+ cent_unit1.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit1.tx0_use_double_data_mode = "true",
+ cent_unit1.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit1.use_deskew_fifo = "false",
+ cent_unit1.vcceh_voltage = "3.0V",
+ cent_unit1.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll atx_pll0
+ (
+ .areset(edge_pllreset_in[0]),
+ .clk(wire_atx_pll0_clk),
+ .dataout(),
+ .dprioout(),
+ .freqlocked(),
+ .inclk({edge_pll_clkin[9:0]}),
+ .locked(wire_atx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(edge_pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .dpriodisable(1'b0),
+ .dprioin({300{1'b0}}),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ atx_pll0.bandwidth_type = "High",
+ atx_pll0.channel_num = 0,
+ atx_pll0.inclk0_input_period = 10000,
+ atx_pll0.input_clock_frequency = "100.0 MHz",
+ atx_pll0.m = 25,
+ atx_pll0.n = 1,
+ atx_pll0.pll_type = "ATX",
+ atx_pll0.vco_post_scale = 1,
+ atx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[0]),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({rx_cruclk_in[9:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .rateswitch(int_pcie_sw[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.bandwidth_type = "Auto",
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll0.enable_dynamic_divider = "true",
+ rx_cdr_pll0.fast_lock_control = "false",
+ rx_cdr_pll0.inclk0_input_period = 10000,
+ rx_cdr_pll0.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll0.m = 25,
+ rx_cdr_pll0.n = 1,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_post_scale = 1,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[599:300]),
+ .dprioout(wire_rx_cdr_pll1_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[1]),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({rx_cruclk_in[19:10]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .rateswitch(int_pcie_sw[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.bandwidth_type = "Auto",
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.dprio_config_mode = 6'h00,
+ rx_cdr_pll1.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll1.enable_dynamic_divider = "true",
+ rx_cdr_pll1.fast_lock_control = "false",
+ rx_cdr_pll1.inclk0_input_period = 10000,
+ rx_cdr_pll1.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll1.m = 25,
+ rx_cdr_pll1.n = 1,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_post_scale = 1,
+ rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[899:600]),
+ .dprioout(wire_rx_cdr_pll2_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[2]),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({rx_cruclk_in[29:20]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .rateswitch(int_pcie_sw[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.bandwidth_type = "Auto",
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.dprio_config_mode = 6'h00,
+ rx_cdr_pll2.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll2.enable_dynamic_divider = "true",
+ rx_cdr_pll2.fast_lock_control = "false",
+ rx_cdr_pll2.inclk0_input_period = 10000,
+ rx_cdr_pll2.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll2.m = 25,
+ rx_cdr_pll2.n = 1,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_post_scale = 1,
+ rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[1199:900]),
+ .dprioout(wire_rx_cdr_pll3_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[3]),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({rx_cruclk_in[39:30]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .rateswitch(int_pcie_sw[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.bandwidth_type = "Auto",
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.dprio_config_mode = 6'h00,
+ rx_cdr_pll3.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll3.enable_dynamic_divider = "true",
+ rx_cdr_pll3.fast_lock_control = "false",
+ rx_cdr_pll3.inclk0_input_period = 10000,
+ rx_cdr_pll3.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll3.m = 25,
+ rx_cdr_pll3.n = 1,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_post_scale = 1,
+ rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll4
+ (
+ .areset(rx_rxcruresetout[6]),
+ .clk(wire_rx_cdr_pll4_clk),
+ .datain(rx_pma_dataout[4]),
+ .dataout(wire_rx_cdr_pll4_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rxpll_dprioin[2099:1800]),
+ .dprioout(wire_rx_cdr_pll4_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[4]),
+ .freqlocked(wire_rx_cdr_pll4_freqlocked),
+ .inclk({rx_cruclk_in[49:40]}),
+ .locked(wire_rx_cdr_pll4_locked),
+ .locktorefclk(rx_pma_locktorefout[4]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll4_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[6]),
+ .rateswitch(int_pcie_sw[1]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll4.bandwidth_type = "Auto",
+ rx_cdr_pll4.channel_num = ((starting_channel_number + 4) % 4),
+ rx_cdr_pll4.dprio_config_mode = 6'h00,
+ rx_cdr_pll4.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll4.enable_dynamic_divider = "true",
+ rx_cdr_pll4.fast_lock_control = "false",
+ rx_cdr_pll4.inclk0_input_period = 10000,
+ rx_cdr_pll4.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll4.m = 25,
+ rx_cdr_pll4.n = 1,
+ rx_cdr_pll4.pll_type = "RX CDR",
+ rx_cdr_pll4.use_refclk_pin = "false",
+ rx_cdr_pll4.vco_post_scale = 1,
+ rx_cdr_pll4.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll5
+ (
+ .areset(rx_rxcruresetout[7]),
+ .clk(wire_rx_cdr_pll5_clk),
+ .datain(rx_pma_dataout[5]),
+ .dataout(wire_rx_cdr_pll5_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rxpll_dprioin[2399:2100]),
+ .dprioout(wire_rx_cdr_pll5_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[5]),
+ .freqlocked(wire_rx_cdr_pll5_freqlocked),
+ .inclk({rx_cruclk_in[59:50]}),
+ .locked(wire_rx_cdr_pll5_locked),
+ .locktorefclk(rx_pma_locktorefout[5]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll5_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[7]),
+ .rateswitch(int_pcie_sw[1]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll5.bandwidth_type = "Auto",
+ rx_cdr_pll5.channel_num = ((starting_channel_number + 5) % 4),
+ rx_cdr_pll5.dprio_config_mode = 6'h00,
+ rx_cdr_pll5.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll5.enable_dynamic_divider = "true",
+ rx_cdr_pll5.fast_lock_control = "false",
+ rx_cdr_pll5.inclk0_input_period = 10000,
+ rx_cdr_pll5.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll5.m = 25,
+ rx_cdr_pll5.n = 1,
+ rx_cdr_pll5.pll_type = "RX CDR",
+ rx_cdr_pll5.use_refclk_pin = "false",
+ rx_cdr_pll5.vco_post_scale = 1,
+ rx_cdr_pll5.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll6
+ (
+ .areset(rx_rxcruresetout[8]),
+ .clk(wire_rx_cdr_pll6_clk),
+ .datain(rx_pma_dataout[6]),
+ .dataout(wire_rx_cdr_pll6_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rxpll_dprioin[2699:2400]),
+ .dprioout(wire_rx_cdr_pll6_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[6]),
+ .freqlocked(wire_rx_cdr_pll6_freqlocked),
+ .inclk({rx_cruclk_in[69:60]}),
+ .locked(wire_rx_cdr_pll6_locked),
+ .locktorefclk(rx_pma_locktorefout[6]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll6_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[8]),
+ .rateswitch(int_pcie_sw[1]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll6.bandwidth_type = "Auto",
+ rx_cdr_pll6.channel_num = ((starting_channel_number + 6) % 4),
+ rx_cdr_pll6.dprio_config_mode = 6'h00,
+ rx_cdr_pll6.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll6.enable_dynamic_divider = "true",
+ rx_cdr_pll6.fast_lock_control = "false",
+ rx_cdr_pll6.inclk0_input_period = 10000,
+ rx_cdr_pll6.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll6.m = 25,
+ rx_cdr_pll6.n = 1,
+ rx_cdr_pll6.pll_type = "RX CDR",
+ rx_cdr_pll6.use_refclk_pin = "false",
+ rx_cdr_pll6.vco_post_scale = 1,
+ rx_cdr_pll6.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll7
+ (
+ .areset(rx_rxcruresetout[9]),
+ .clk(wire_rx_cdr_pll7_clk),
+ .datain(rx_pma_dataout[7]),
+ .dataout(wire_rx_cdr_pll7_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rxpll_dprioin[2999:2700]),
+ .dprioout(wire_rx_cdr_pll7_dprioout),
+ .earlyeios(int_rxpcs_cdrctrlearlyeios[7]),
+ .freqlocked(wire_rx_cdr_pll7_freqlocked),
+ .inclk({rx_cruclk_in[79:70]}),
+ .locked(wire_rx_cdr_pll7_locked),
+ .locktorefclk(rx_pma_locktorefout[7]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll7_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[9]),
+ .rateswitch(int_pcie_sw[1]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll7.bandwidth_type = "Auto",
+ rx_cdr_pll7.channel_num = ((starting_channel_number + 7) % 4),
+ rx_cdr_pll7.dprio_config_mode = 6'h00,
+ rx_cdr_pll7.effective_data_rate = "5000 Mbps",
+ rx_cdr_pll7.enable_dynamic_divider = "true",
+ rx_cdr_pll7.fast_lock_control = "false",
+ rx_cdr_pll7.inclk0_input_period = 10000,
+ rx_cdr_pll7.input_clock_frequency = "100.0 MHz",
+ rx_cdr_pll7.m = 25,
+ rx_cdr_pll7.n = 1,
+ rx_cdr_pll7.pll_type = "RX CDR",
+ rx_cdr_pll7.use_refclk_pin = "false",
+ rx_cdr_pll7.vco_post_scale = 1,
+ rx_cdr_pll7.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs0_autospdrateswitchout),
+ .autospdspdchgout(wire_receive_pcs0_autospdspdchgout),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[2:0]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[2:0]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[1:0]),
+ .iqpphfifobyteselout(wire_receive_pcs0_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(wire_receive_pcs0_iqpphfifoptrsresetout),
+ .iqpphfifordenableout(wire_receive_pcs0_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs0_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs0_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[1:0]),
+ .iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[1:0]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[1:0]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[1:0]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[1:0]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs0_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs0_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
+ .pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[1:0]),
+ .pipepowerstate(tx_pipepowerstateout[3:0]),
+ .pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs0_pipestatus),
+ .powerdn(powerdn[1:0]),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[0]),
+ .rxfound(rx_pcs_rxfound_wire[1:0]),
+ .signaldetect(wire_receive_pcs0_signaldetect),
+ .signaldetected(rx_signaldetect_wire[0]),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "false",
+ receive_pcs0.allow_pipe_polarity_inversion = "true",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 14,
+ receive_pcs0.auto_spd_self_switch_enable = "true",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_cid_mode_enable = "true",
+ receive_pcs0.cdrctrl_enable = "true",
+ receive_pcs0.cdrctrl_rxvalid_mask = "true",
+ receive_pcs0.channel_bonding = "x8",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "recovered clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "false",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "pipe",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs0.deskew_pattern = "0",
+ receive_pcs0.disable_auto_idle_insertion = "false",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 16,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 17,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "true",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 249950,
+ receive_pcs0.protocol_hint = "pcie2",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "false",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs0.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs0.rate_match_pattern_size = 20,
+ receive_pcs0.rate_match_pipe_enable = "true",
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "true",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 32,
+ receive_pcs0.rxstatus_error_report_mode = 1,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.test_bus_sel = 10,
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "false",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs1_autospdrateswitchout),
+ .autospdspdchgout(wire_receive_pcs1_autospdspdchgout),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[5:3]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[5:3]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(wire_receive_pcs1_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[3:2]),
+ .iqpphfifobyteselout(wire_receive_pcs1_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(wire_receive_pcs1_iqpphfifoptrsresetout),
+ .iqpphfifordenableout(wire_receive_pcs1_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs1_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs1_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[3:2]),
+ .iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[3:2]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[3:2]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[3:2]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[3:2]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs1_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs1_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
+ .pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[3:2]),
+ .pipepowerstate(tx_pipepowerstateout[7:4]),
+ .pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs1_pipestatus),
+ .powerdn(powerdn[3:2]),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[1]),
+ .rxfound(rx_pcs_rxfound_wire[3:2]),
+ .signaldetect(wire_receive_pcs1_signaldetect),
+ .signaldetected(rx_signaldetect_wire[1]),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "false",
+ receive_pcs1.allow_pipe_polarity_inversion = "true",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 14,
+ receive_pcs1.auto_spd_self_switch_enable = "true",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_cid_mode_enable = "true",
+ receive_pcs1.cdrctrl_enable = "true",
+ receive_pcs1.cdrctrl_rxvalid_mask = "true",
+ receive_pcs1.channel_bonding = "x8",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 16,
+ receive_pcs1.clk1_mux_select = "recovered clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "false",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "pipe",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs1.deskew_pattern = "0",
+ receive_pcs1.disable_auto_idle_insertion = "false",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h01,
+ receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 16,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 17,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "true",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 249950,
+ receive_pcs1.protocol_hint = "pcie2",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "false",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs1.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs1.rate_match_pattern_size = 20,
+ receive_pcs1.rate_match_pipe_enable = "true",
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "true",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rx_phfifo_wait_cnt = 32,
+ receive_pcs1.rxstatus_error_report_mode = 1,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.test_bus_sel = 10,
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "false",
+ receive_pcs1.use_double_data_mode = "true",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs2_autospdrateswitchout),
+ .autospdspdchgout(wire_receive_pcs2_autospdspdchgout),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[8:6]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[8:6]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs2_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(wire_receive_pcs2_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[8:6]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[5:4]),
+ .iqpphfifobyteselout(wire_receive_pcs2_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(wire_receive_pcs2_iqpphfifoptrsresetout),
+ .iqpphfifordenableout(wire_receive_pcs2_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs2_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs2_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[5:4]),
+ .iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[5:4]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[5:4]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[5:4]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[5:4]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs2_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs2_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[2]),
+ .pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[5:4]),
+ .pipepowerstate(tx_pipepowerstateout[11:8]),
+ .pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs2_pipestatus),
+ .powerdn(powerdn[5:4]),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[2]),
+ .rxfound(rx_pcs_rxfound_wire[5:4]),
+ .signaldetect(wire_receive_pcs2_signaldetect),
+ .signaldetected(rx_signaldetect_wire[2]),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "false",
+ receive_pcs2.allow_pipe_polarity_inversion = "true",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 14,
+ receive_pcs2.auto_spd_self_switch_enable = "true",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs2.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_cid_mode_enable = "true",
+ receive_pcs2.cdrctrl_enable = "true",
+ receive_pcs2.cdrctrl_rxvalid_mask = "true",
+ receive_pcs2.channel_bonding = "x8",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 16,
+ receive_pcs2.clk1_mux_select = "recovered clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "false",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "pipe",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs2.deskew_pattern = "0",
+ receive_pcs2.disable_auto_idle_insertion = "false",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h01,
+ receive_pcs2.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 16,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 17,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "true",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 249950,
+ receive_pcs2.protocol_hint = "pcie2",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "false",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs2.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs2.rate_match_pattern_size = 20,
+ receive_pcs2.rate_match_pipe_enable = "true",
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "true",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rx_phfifo_wait_cnt = 32,
+ receive_pcs2.rxstatus_error_report_mode = 1,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.test_bus_sel = 10,
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "false",
+ receive_pcs2.use_double_data_mode = "true",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs3_autospdrateswitchout),
+ .autospdspdchgout(wire_receive_pcs3_autospdspdchgout),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[11:9]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[11:9]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs3_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(wire_receive_pcs3_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[11:9]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[7:6]),
+ .iqpphfifobyteselout(wire_receive_pcs3_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(wire_receive_pcs3_iqpphfifoptrsresetout),
+ .iqpphfifordenableout(wire_receive_pcs3_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs3_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs3_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[7:6]),
+ .iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[7:6]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[7:6]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[7:6]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[7:6]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs3_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs3_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[3]),
+ .pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[7:6]),
+ .pipepowerstate(tx_pipepowerstateout[15:12]),
+ .pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs3_pipestatus),
+ .powerdn(powerdn[7:6]),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[3]),
+ .rxfound(rx_pcs_rxfound_wire[7:6]),
+ .signaldetect(wire_receive_pcs3_signaldetect),
+ .signaldetected(rx_signaldetect_wire[3]),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "false",
+ receive_pcs3.allow_pipe_polarity_inversion = "true",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 14,
+ receive_pcs3.auto_spd_self_switch_enable = "true",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs3.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_cid_mode_enable = "true",
+ receive_pcs3.cdrctrl_enable = "true",
+ receive_pcs3.cdrctrl_rxvalid_mask = "true",
+ receive_pcs3.channel_bonding = "x8",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 16,
+ receive_pcs3.clk1_mux_select = "recovered clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "false",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "pipe",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs3.deskew_pattern = "0",
+ receive_pcs3.disable_auto_idle_insertion = "false",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h01,
+ receive_pcs3.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 16,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 17,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "true",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 249950,
+ receive_pcs3.protocol_hint = "pcie2",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "false",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs3.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs3.rate_match_pattern_size = 20,
+ receive_pcs3.rate_match_pipe_enable = "true",
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "true",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rx_phfifo_wait_cnt = 32,
+ receive_pcs3.rxstatus_error_report_mode = 1,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.test_bus_sel = 10,
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "false",
+ receive_pcs3.use_double_data_mode = "true",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs4
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs4_autospdrateswitchout),
+ .autospdspdchgout(wire_receive_pcs4_autospdspdchgout),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[14:12]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[14:12]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs4_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs4_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[4]),
+ .coreclkout(wire_receive_pcs4_coreclkout),
+ .ctrldetect(wire_receive_pcs4_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[99:80]),
+ .dataout(wire_receive_pcs4_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[4]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pcsdprioin_wire[1999:1600]),
+ .dprioout(wire_receive_pcs4_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[4]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[14:12]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[9:8]),
+ .iqpphfifobyteselout(wire_receive_pcs4_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(wire_receive_pcs4_iqpphfifoptrsresetout),
+ .iqpphfifordenableout(wire_receive_pcs4_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs4_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs4_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[9:8]),
+ .iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[9:8]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[9:8]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[9:8]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[9:8]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs4_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs4_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs4_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[4]),
+ .phfifordenableout(wire_receive_pcs4_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[4]),
+ .phfiforesetout(wire_receive_pcs4_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[4]),
+ .phfifowrdisableout(wire_receive_pcs4_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[14:12]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[14:12]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[14:12]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[14:12]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[14:12]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[4]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs4_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs4_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[4]),
+ .pipephydonestatus(wire_receive_pcs4_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[9:8]),
+ .pipepowerstate(tx_pipepowerstateout[19:16]),
+ .pipestatetransdoneout(wire_receive_pcs4_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs4_pipestatus),
+ .powerdn(powerdn[9:8]),
+ .prbscidenable(rx_prbscidenable[4]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs4_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[4]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs4_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[4]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[4]),
+ .rxfound(rx_pcs_rxfound_wire[9:8]),
+ .signaldetect(wire_receive_pcs4_signaldetect),
+ .signaldetected(rx_signaldetect_wire[4]),
+ .syncstatus(wire_receive_pcs4_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs4.align_pattern = "0101111100",
+ receive_pcs4.align_pattern_length = 10,
+ receive_pcs4.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs4.allow_align_polarity_inversion = "false",
+ receive_pcs4.allow_pipe_polarity_inversion = "true",
+ receive_pcs4.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs4.auto_spd_phystatus_notify_count = 14,
+ receive_pcs4.auto_spd_self_switch_enable = "true",
+ receive_pcs4.bit_slip_enable = "false",
+ receive_pcs4.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs4.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs4.byte_order_mode = "none",
+ receive_pcs4.byte_order_pad_pattern = "0",
+ receive_pcs4.byte_order_pattern = "0",
+ receive_pcs4.byte_order_pld_ctrl_enable = "false",
+ receive_pcs4.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs4.cdrctrl_cid_mode_enable = "true",
+ receive_pcs4.cdrctrl_enable = "true",
+ receive_pcs4.cdrctrl_rxvalid_mask = "true",
+ receive_pcs4.channel_bonding = "x8",
+ receive_pcs4.channel_number = ((starting_channel_number + 4) % 4),
+ receive_pcs4.channel_width = 16,
+ receive_pcs4.clk1_mux_select = "recovered clock",
+ receive_pcs4.clk2_mux_select = "digital reference clock",
+ receive_pcs4.core_clock_0ppm = "false",
+ receive_pcs4.datapath_low_latency_mode = "false",
+ receive_pcs4.datapath_protocol = "pipe",
+ receive_pcs4.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs4.dec_8b_10b_mode = "normal",
+ receive_pcs4.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs4.deskew_pattern = "0",
+ receive_pcs4.disable_auto_idle_insertion = "false",
+ receive_pcs4.disable_running_disp_in_word_align = "false",
+ receive_pcs4.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs4.dprio_config_mode = 6'h01,
+ receive_pcs4.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs4.elec_idle_infer_enable = "false",
+ receive_pcs4.elec_idle_num_com_detect = 3,
+ receive_pcs4.enable_bit_reversal = "false",
+ receive_pcs4.enable_deep_align = "false",
+ receive_pcs4.enable_deep_align_byte_swap = "false",
+ receive_pcs4.enable_self_test_mode = "false",
+ receive_pcs4.enable_true_complement_match_in_word_align = "false",
+ receive_pcs4.force_signal_detect_dig = "true",
+ receive_pcs4.hip_enable = "false",
+ receive_pcs4.infiniband_invalid_code = 0,
+ receive_pcs4.insert_pad_on_underflow = "false",
+ receive_pcs4.iqp_ph_fifo_xn_select = 1,
+ receive_pcs4.logical_channel_address = (starting_channel_number + 4),
+ receive_pcs4.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs4.num_align_cons_good_data = 16,
+ receive_pcs4.num_align_cons_pat = 4,
+ receive_pcs4.num_align_loss_sync_error = 17,
+ receive_pcs4.ph_fifo_low_latency_enable = "true",
+ receive_pcs4.ph_fifo_reg_mode = "false",
+ receive_pcs4.ph_fifo_xn_mapping0 = "none",
+ receive_pcs4.ph_fifo_xn_mapping1 = "up",
+ receive_pcs4.ph_fifo_xn_mapping2 = "none",
+ receive_pcs4.ph_fifo_xn_select = 1,
+ receive_pcs4.pipe_auto_speed_nego_enable = "true",
+ receive_pcs4.pipe_freq_scale_mode = "Frequency",
+ receive_pcs4.pma_done_count = 249950,
+ receive_pcs4.protocol_hint = "pcie2",
+ receive_pcs4.rate_match_almost_empty_threshold = 11,
+ receive_pcs4.rate_match_almost_full_threshold = 13,
+ receive_pcs4.rate_match_back_to_back = "false",
+ receive_pcs4.rate_match_delete_threshold = 13,
+ receive_pcs4.rate_match_empty_threshold = 5,
+ receive_pcs4.rate_match_fifo_mode = "true",
+ receive_pcs4.rate_match_full_threshold = 20,
+ receive_pcs4.rate_match_insert_threshold = 11,
+ receive_pcs4.rate_match_ordered_set_based = "false",
+ receive_pcs4.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs4.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs4.rate_match_pattern_size = 20,
+ receive_pcs4.rate_match_pipe_enable = "true",
+ receive_pcs4.rate_match_reset_enable = "false",
+ receive_pcs4.rate_match_skip_set_based = "true",
+ receive_pcs4.rate_match_start_threshold = 7,
+ receive_pcs4.rd_clk_mux_select = "core clock",
+ receive_pcs4.recovered_clk_mux_select = "recovered clock",
+ receive_pcs4.run_length = 40,
+ receive_pcs4.run_length_enable = "true",
+ receive_pcs4.rx_detect_bypass = "false",
+ receive_pcs4.rx_phfifo_wait_cnt = 32,
+ receive_pcs4.rxstatus_error_report_mode = 1,
+ receive_pcs4.self_test_mode = "incremental",
+ receive_pcs4.test_bus_sel = 10,
+ receive_pcs4.use_alignment_state_machine = "true",
+ receive_pcs4.use_deserializer_double_data_mode = "false",
+ receive_pcs4.use_deskew_fifo = "false",
+ receive_pcs4.use_double_data_mode = "true",
+ receive_pcs4.use_parallel_loopback = "false",
+ receive_pcs4.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs4.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs5
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs5_autospdrateswitchout),
+ .autospdspdchgout(wire_receive_pcs5_autospdspdchgout),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[17:15]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[17:15]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs5_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs5_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[5]),
+ .coreclkout(wire_receive_pcs5_coreclkout),
+ .ctrldetect(wire_receive_pcs5_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[119:100]),
+ .dataout(wire_receive_pcs5_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[5]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pcsdprioin_wire[2399:2000]),
+ .dprioout(wire_receive_pcs5_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[5]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[17:15]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[11:10]),
+ .iqpphfifobyteselout(wire_receive_pcs5_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(wire_receive_pcs5_iqpphfifoptrsresetout),
+ .iqpphfifordenableout(wire_receive_pcs5_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs5_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs5_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[11:10]),
+ .iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[11:10]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[11:10]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[11:10]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[11:10]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs5_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs5_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs5_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[5]),
+ .phfifordenableout(wire_receive_pcs5_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[5]),
+ .phfiforesetout(wire_receive_pcs5_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[5]),
+ .phfifowrdisableout(wire_receive_pcs5_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[17:15]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[17:15]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[17:15]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[17:15]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[17:15]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[5]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs5_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs5_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[5]),
+ .pipephydonestatus(wire_receive_pcs5_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[11:10]),
+ .pipepowerstate(tx_pipepowerstateout[23:20]),
+ .pipestatetransdoneout(wire_receive_pcs5_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs5_pipestatus),
+ .powerdn(powerdn[11:10]),
+ .prbscidenable(rx_prbscidenable[5]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs5_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[5]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs5_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[5]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[5]),
+ .rxfound(rx_pcs_rxfound_wire[11:10]),
+ .signaldetect(wire_receive_pcs5_signaldetect),
+ .signaldetected(rx_signaldetect_wire[5]),
+ .syncstatus(wire_receive_pcs5_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs5.align_pattern = "0101111100",
+ receive_pcs5.align_pattern_length = 10,
+ receive_pcs5.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs5.allow_align_polarity_inversion = "false",
+ receive_pcs5.allow_pipe_polarity_inversion = "true",
+ receive_pcs5.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs5.auto_spd_phystatus_notify_count = 14,
+ receive_pcs5.auto_spd_self_switch_enable = "true",
+ receive_pcs5.bit_slip_enable = "false",
+ receive_pcs5.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs5.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs5.byte_order_mode = "none",
+ receive_pcs5.byte_order_pad_pattern = "0",
+ receive_pcs5.byte_order_pattern = "0",
+ receive_pcs5.byte_order_pld_ctrl_enable = "false",
+ receive_pcs5.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs5.cdrctrl_cid_mode_enable = "true",
+ receive_pcs5.cdrctrl_enable = "true",
+ receive_pcs5.cdrctrl_rxvalid_mask = "true",
+ receive_pcs5.channel_bonding = "x8",
+ receive_pcs5.channel_number = ((starting_channel_number + 5) % 4),
+ receive_pcs5.channel_width = 16,
+ receive_pcs5.clk1_mux_select = "recovered clock",
+ receive_pcs5.clk2_mux_select = "digital reference clock",
+ receive_pcs5.core_clock_0ppm = "false",
+ receive_pcs5.datapath_low_latency_mode = "false",
+ receive_pcs5.datapath_protocol = "pipe",
+ receive_pcs5.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs5.dec_8b_10b_mode = "normal",
+ receive_pcs5.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs5.deskew_pattern = "0",
+ receive_pcs5.disable_auto_idle_insertion = "false",
+ receive_pcs5.disable_running_disp_in_word_align = "false",
+ receive_pcs5.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs5.dprio_config_mode = 6'h01,
+ receive_pcs5.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs5.elec_idle_infer_enable = "false",
+ receive_pcs5.elec_idle_num_com_detect = 3,
+ receive_pcs5.enable_bit_reversal = "false",
+ receive_pcs5.enable_deep_align = "false",
+ receive_pcs5.enable_deep_align_byte_swap = "false",
+ receive_pcs5.enable_self_test_mode = "false",
+ receive_pcs5.enable_true_complement_match_in_word_align = "false",
+ receive_pcs5.force_signal_detect_dig = "true",
+ receive_pcs5.hip_enable = "false",
+ receive_pcs5.infiniband_invalid_code = 0,
+ receive_pcs5.insert_pad_on_underflow = "false",
+ receive_pcs5.logical_channel_address = (starting_channel_number + 5),
+ receive_pcs5.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs5.num_align_cons_good_data = 16,
+ receive_pcs5.num_align_cons_pat = 4,
+ receive_pcs5.num_align_loss_sync_error = 17,
+ receive_pcs5.ph_fifo_low_latency_enable = "true",
+ receive_pcs5.ph_fifo_reg_mode = "false",
+ receive_pcs5.ph_fifo_xn_mapping0 = "none",
+ receive_pcs5.ph_fifo_xn_mapping1 = "up",
+ receive_pcs5.ph_fifo_xn_mapping2 = "none",
+ receive_pcs5.ph_fifo_xn_select = 1,
+ receive_pcs5.pipe_auto_speed_nego_enable = "true",
+ receive_pcs5.pipe_freq_scale_mode = "Frequency",
+ receive_pcs5.pma_done_count = 249950,
+ receive_pcs5.protocol_hint = "pcie2",
+ receive_pcs5.rate_match_almost_empty_threshold = 11,
+ receive_pcs5.rate_match_almost_full_threshold = 13,
+ receive_pcs5.rate_match_back_to_back = "false",
+ receive_pcs5.rate_match_delete_threshold = 13,
+ receive_pcs5.rate_match_empty_threshold = 5,
+ receive_pcs5.rate_match_fifo_mode = "true",
+ receive_pcs5.rate_match_full_threshold = 20,
+ receive_pcs5.rate_match_insert_threshold = 11,
+ receive_pcs5.rate_match_ordered_set_based = "false",
+ receive_pcs5.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs5.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs5.rate_match_pattern_size = 20,
+ receive_pcs5.rate_match_pipe_enable = "true",
+ receive_pcs5.rate_match_reset_enable = "false",
+ receive_pcs5.rate_match_skip_set_based = "true",
+ receive_pcs5.rate_match_start_threshold = 7,
+ receive_pcs5.rd_clk_mux_select = "core clock",
+ receive_pcs5.recovered_clk_mux_select = "recovered clock",
+ receive_pcs5.run_length = 40,
+ receive_pcs5.run_length_enable = "true",
+ receive_pcs5.rx_detect_bypass = "false",
+ receive_pcs5.rx_phfifo_wait_cnt = 32,
+ receive_pcs5.rxstatus_error_report_mode = 1,
+ receive_pcs5.self_test_mode = "incremental",
+ receive_pcs5.test_bus_sel = 10,
+ receive_pcs5.use_alignment_state_machine = "true",
+ receive_pcs5.use_deserializer_double_data_mode = "false",
+ receive_pcs5.use_deskew_fifo = "false",
+ receive_pcs5.use_double_data_mode = "true",
+ receive_pcs5.use_parallel_loopback = "false",
+ receive_pcs5.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs5.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs6
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs6_autospdrateswitchout),
+ .autospdspdchgout(wire_receive_pcs6_autospdspdchgout),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[20:18]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[20:18]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs6_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs6_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[6]),
+ .coreclkout(wire_receive_pcs6_coreclkout),
+ .ctrldetect(wire_receive_pcs6_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[139:120]),
+ .dataout(wire_receive_pcs6_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[6]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pcsdprioin_wire[2799:2400]),
+ .dprioout(wire_receive_pcs6_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[6]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[20:18]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[13:12]),
+ .iqpphfifobyteselout(wire_receive_pcs6_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(wire_receive_pcs6_iqpphfifoptrsresetout),
+ .iqpphfifordenableout(wire_receive_pcs6_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs6_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs6_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[13:12]),
+ .iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[13:12]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[13:12]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[13:12]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[13:12]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs6_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs6_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs6_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[6]),
+ .phfifordenableout(wire_receive_pcs6_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[6]),
+ .phfiforesetout(wire_receive_pcs6_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[6]),
+ .phfifowrdisableout(wire_receive_pcs6_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[20:18]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[20:18]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[20:18]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[20:18]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[20:18]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[6]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs6_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs6_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[6]),
+ .pipephydonestatus(wire_receive_pcs6_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[13:12]),
+ .pipepowerstate(tx_pipepowerstateout[27:24]),
+ .pipestatetransdoneout(wire_receive_pcs6_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs6_pipestatus),
+ .powerdn(powerdn[13:12]),
+ .prbscidenable(rx_prbscidenable[6]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs6_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[6]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs6_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[6]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[6]),
+ .rxfound(rx_pcs_rxfound_wire[13:12]),
+ .signaldetect(wire_receive_pcs6_signaldetect),
+ .signaldetected(rx_signaldetect_wire[6]),
+ .syncstatus(wire_receive_pcs6_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs6.align_pattern = "0101111100",
+ receive_pcs6.align_pattern_length = 10,
+ receive_pcs6.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs6.allow_align_polarity_inversion = "false",
+ receive_pcs6.allow_pipe_polarity_inversion = "true",
+ receive_pcs6.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs6.auto_spd_phystatus_notify_count = 14,
+ receive_pcs6.auto_spd_self_switch_enable = "true",
+ receive_pcs6.bit_slip_enable = "false",
+ receive_pcs6.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs6.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs6.byte_order_mode = "none",
+ receive_pcs6.byte_order_pad_pattern = "0",
+ receive_pcs6.byte_order_pattern = "0",
+ receive_pcs6.byte_order_pld_ctrl_enable = "false",
+ receive_pcs6.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs6.cdrctrl_cid_mode_enable = "true",
+ receive_pcs6.cdrctrl_enable = "true",
+ receive_pcs6.cdrctrl_rxvalid_mask = "true",
+ receive_pcs6.channel_bonding = "x8",
+ receive_pcs6.channel_number = ((starting_channel_number + 6) % 4),
+ receive_pcs6.channel_width = 16,
+ receive_pcs6.clk1_mux_select = "recovered clock",
+ receive_pcs6.clk2_mux_select = "digital reference clock",
+ receive_pcs6.core_clock_0ppm = "false",
+ receive_pcs6.datapath_low_latency_mode = "false",
+ receive_pcs6.datapath_protocol = "pipe",
+ receive_pcs6.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs6.dec_8b_10b_mode = "normal",
+ receive_pcs6.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs6.deskew_pattern = "0",
+ receive_pcs6.disable_auto_idle_insertion = "false",
+ receive_pcs6.disable_running_disp_in_word_align = "false",
+ receive_pcs6.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs6.dprio_config_mode = 6'h01,
+ receive_pcs6.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs6.elec_idle_infer_enable = "false",
+ receive_pcs6.elec_idle_num_com_detect = 3,
+ receive_pcs6.enable_bit_reversal = "false",
+ receive_pcs6.enable_deep_align = "false",
+ receive_pcs6.enable_deep_align_byte_swap = "false",
+ receive_pcs6.enable_self_test_mode = "false",
+ receive_pcs6.enable_true_complement_match_in_word_align = "false",
+ receive_pcs6.force_signal_detect_dig = "true",
+ receive_pcs6.hip_enable = "false",
+ receive_pcs6.infiniband_invalid_code = 0,
+ receive_pcs6.insert_pad_on_underflow = "false",
+ receive_pcs6.logical_channel_address = (starting_channel_number + 6),
+ receive_pcs6.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs6.num_align_cons_good_data = 16,
+ receive_pcs6.num_align_cons_pat = 4,
+ receive_pcs6.num_align_loss_sync_error = 17,
+ receive_pcs6.ph_fifo_low_latency_enable = "true",
+ receive_pcs6.ph_fifo_reg_mode = "false",
+ receive_pcs6.ph_fifo_xn_mapping0 = "none",
+ receive_pcs6.ph_fifo_xn_mapping1 = "up",
+ receive_pcs6.ph_fifo_xn_mapping2 = "none",
+ receive_pcs6.ph_fifo_xn_select = 1,
+ receive_pcs6.pipe_auto_speed_nego_enable = "true",
+ receive_pcs6.pipe_freq_scale_mode = "Frequency",
+ receive_pcs6.pma_done_count = 249950,
+ receive_pcs6.protocol_hint = "pcie2",
+ receive_pcs6.rate_match_almost_empty_threshold = 11,
+ receive_pcs6.rate_match_almost_full_threshold = 13,
+ receive_pcs6.rate_match_back_to_back = "false",
+ receive_pcs6.rate_match_delete_threshold = 13,
+ receive_pcs6.rate_match_empty_threshold = 5,
+ receive_pcs6.rate_match_fifo_mode = "true",
+ receive_pcs6.rate_match_full_threshold = 20,
+ receive_pcs6.rate_match_insert_threshold = 11,
+ receive_pcs6.rate_match_ordered_set_based = "false",
+ receive_pcs6.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs6.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs6.rate_match_pattern_size = 20,
+ receive_pcs6.rate_match_pipe_enable = "true",
+ receive_pcs6.rate_match_reset_enable = "false",
+ receive_pcs6.rate_match_skip_set_based = "true",
+ receive_pcs6.rate_match_start_threshold = 7,
+ receive_pcs6.rd_clk_mux_select = "core clock",
+ receive_pcs6.recovered_clk_mux_select = "recovered clock",
+ receive_pcs6.run_length = 40,
+ receive_pcs6.run_length_enable = "true",
+ receive_pcs6.rx_detect_bypass = "false",
+ receive_pcs6.rx_phfifo_wait_cnt = 32,
+ receive_pcs6.rxstatus_error_report_mode = 1,
+ receive_pcs6.self_test_mode = "incremental",
+ receive_pcs6.test_bus_sel = 10,
+ receive_pcs6.use_alignment_state_machine = "true",
+ receive_pcs6.use_deserializer_double_data_mode = "false",
+ receive_pcs6.use_deskew_fifo = "false",
+ receive_pcs6.use_double_data_mode = "true",
+ receive_pcs6.use_parallel_loopback = "false",
+ receive_pcs6.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs6.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs7
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(),
+ .alignstatus(1'b0),
+ .alignstatussync(1'b0),
+ .alignstatussyncout(),
+ .autospdrateswitchout(wire_receive_pcs7_autospdrateswitchout),
+ .autospdspdchgout(wire_receive_pcs7_autospdspdchgout),
+ .autospdxnconfigsel(int_rx_autospdxnconfigsel[23:21]),
+ .autospdxnspdchg(int_rx_autospdxnspdchg[23:21]),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(wire_receive_pcs7_cdrctrlearlyeios),
+ .cdrctrllocktorefclkout(wire_receive_pcs7_cdrctrllocktorefclkout),
+ .clkout(),
+ .coreclk(rx_coreclk_in[7]),
+ .coreclkout(wire_receive_pcs7_coreclkout),
+ .ctrldetect(wire_receive_pcs7_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[159:140]),
+ .dataout(wire_receive_pcs7_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[7]),
+ .digitaltestout(),
+ .disablefifordin(1'b0),
+ .disablefifordout(),
+ .disablefifowrin(1'b0),
+ .disablefifowrout(),
+ .disperr(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pcsdprioin_wire[3199:2800]),
+ .dprioout(wire_receive_pcs7_dprioout),
+ .elecidleinfersel({3{1'b0}}),
+ .enabledeskew(1'b0),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[7]),
+ .errdetect(),
+ .fifordin(1'b0),
+ .fifordout(),
+ .fiforesetrd(1'b0),
+ .grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[23:21]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(1'b0),
+ .iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[15:14]),
+ .iqpphfifobyteselout(wire_receive_pcs7_iqpphfifobyteselout),
+ .iqpphfifoptrsresetout(wire_receive_pcs7_iqpphfifoptrsresetout),
+ .iqpphfifordenableout(wire_receive_pcs7_iqpphfifordenableout),
+ .iqpphfifowrclkout(wire_receive_pcs7_iqpphfifowrclkout),
+ .iqpphfifowrenableout(wire_receive_pcs7_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[15:14]),
+ .iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[15:14]),
+ .iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[15:14]),
+ .iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[15:14]),
+ .iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[15:14]),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(1'b0),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs7_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs7_phfifobyteserdisableout),
+ .phfifooverflow(),
+ .phfifoptrsresetout(wire_receive_pcs7_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[7]),
+ .phfifordenableout(wire_receive_pcs7_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[7]),
+ .phfiforesetout(wire_receive_pcs7_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[7]),
+ .phfifowrdisableout(wire_receive_pcs7_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[23:21]),
+ .phfifoxnptrsreset(int_rx_phfifioxnptrsreset[23:21]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[23:21]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[23:21]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[23:21]),
+ .pipe8b10binvpolarity(pipe8b10binvpolarity[7]),
+ .pipebufferstat(),
+ .pipedatavalid(wire_receive_pcs7_pipedatavalid),
+ .pipeelecidle(wire_receive_pcs7_pipeelecidle),
+ .pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[7]),
+ .pipephydonestatus(wire_receive_pcs7_pipephydonestatus),
+ .pipepowerdown(tx_pipepowerdownout[15:14]),
+ .pipepowerstate(tx_pipepowerstateout[31:28]),
+ .pipestatetransdoneout(wire_receive_pcs7_pipestatetransdoneout),
+ .pipestatus(wire_receive_pcs7_pipestatus),
+ .powerdn(powerdn[15:14]),
+ .prbscidenable(rx_prbscidenable[7]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitch(rateswitch[0]),
+ .rateswitchout(wire_receive_pcs7_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[1]),
+ .rdalign(),
+ .recoveredclk(rx_pma_clockout[7]),
+ .refclk(refclk_pma[1]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(wire_receive_pcs7_revparallelfdbkdata),
+ .rlv(),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(),
+ .rmfifodatainserted(),
+ .rmfifoempty(),
+ .rmfifofull(),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[7]),
+ .rmfifowrena(1'b0),
+ .runningdisp(),
+ .rxdetectvalid(tx_rxdetectvalidout[7]),
+ .rxfound(rx_pcs_rxfound_wire[15:14]),
+ .signaldetect(wire_receive_pcs7_signaldetect),
+ .signaldetected(rx_signaldetect_wire[7]),
+ .syncstatus(wire_receive_pcs7_syncstatus),
+ .syncstatusdeskew(),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(),
+ .xgmctrlin(1'b0),
+ .xgmdatain({8{1'b0}}),
+ .xgmdataout(),
+ .xgmdatavalid(),
+ .xgmrunningdisp()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslip(1'b0),
+ .cdrctrllocktorefcl(1'b0),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs7.align_pattern = "0101111100",
+ receive_pcs7.align_pattern_length = 10,
+ receive_pcs7.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs7.allow_align_polarity_inversion = "false",
+ receive_pcs7.allow_pipe_polarity_inversion = "true",
+ receive_pcs7.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs7.auto_spd_phystatus_notify_count = 14,
+ receive_pcs7.auto_spd_self_switch_enable = "true",
+ receive_pcs7.bit_slip_enable = "false",
+ receive_pcs7.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs7.byte_order_invalid_code_or_run_disp_error = "true",
+ receive_pcs7.byte_order_mode = "none",
+ receive_pcs7.byte_order_pad_pattern = "0",
+ receive_pcs7.byte_order_pattern = "0",
+ receive_pcs7.byte_order_pld_ctrl_enable = "false",
+ receive_pcs7.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs7.cdrctrl_cid_mode_enable = "true",
+ receive_pcs7.cdrctrl_enable = "true",
+ receive_pcs7.cdrctrl_rxvalid_mask = "true",
+ receive_pcs7.channel_bonding = "x8",
+ receive_pcs7.channel_number = ((starting_channel_number + 7) % 4),
+ receive_pcs7.channel_width = 16,
+ receive_pcs7.clk1_mux_select = "recovered clock",
+ receive_pcs7.clk2_mux_select = "digital reference clock",
+ receive_pcs7.core_clock_0ppm = "false",
+ receive_pcs7.datapath_low_latency_mode = "false",
+ receive_pcs7.datapath_protocol = "pipe",
+ receive_pcs7.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs7.dec_8b_10b_mode = "normal",
+ receive_pcs7.dec_8b_10b_polarity_inv_enable = "true",
+ receive_pcs7.deskew_pattern = "0",
+ receive_pcs7.disable_auto_idle_insertion = "false",
+ receive_pcs7.disable_running_disp_in_word_align = "false",
+ receive_pcs7.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs7.dprio_config_mode = 6'h01,
+ receive_pcs7.elec_idle_gen1_sigdet_enable = "true",
+ receive_pcs7.elec_idle_infer_enable = "false",
+ receive_pcs7.elec_idle_num_com_detect = 3,
+ receive_pcs7.enable_bit_reversal = "false",
+ receive_pcs7.enable_deep_align = "false",
+ receive_pcs7.enable_deep_align_byte_swap = "false",
+ receive_pcs7.enable_self_test_mode = "false",
+ receive_pcs7.enable_true_complement_match_in_word_align = "false",
+ receive_pcs7.force_signal_detect_dig = "true",
+ receive_pcs7.hip_enable = "false",
+ receive_pcs7.infiniband_invalid_code = 0,
+ receive_pcs7.insert_pad_on_underflow = "false",
+ receive_pcs7.logical_channel_address = (starting_channel_number + 7),
+ receive_pcs7.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs7.num_align_cons_good_data = 16,
+ receive_pcs7.num_align_cons_pat = 4,
+ receive_pcs7.num_align_loss_sync_error = 17,
+ receive_pcs7.ph_fifo_low_latency_enable = "true",
+ receive_pcs7.ph_fifo_reg_mode = "false",
+ receive_pcs7.ph_fifo_xn_mapping0 = "none",
+ receive_pcs7.ph_fifo_xn_mapping1 = "up",
+ receive_pcs7.ph_fifo_xn_mapping2 = "none",
+ receive_pcs7.ph_fifo_xn_select = 1,
+ receive_pcs7.pipe_auto_speed_nego_enable = "true",
+ receive_pcs7.pipe_freq_scale_mode = "Frequency",
+ receive_pcs7.pma_done_count = 249950,
+ receive_pcs7.protocol_hint = "pcie2",
+ receive_pcs7.rate_match_almost_empty_threshold = 11,
+ receive_pcs7.rate_match_almost_full_threshold = 13,
+ receive_pcs7.rate_match_back_to_back = "false",
+ receive_pcs7.rate_match_delete_threshold = 13,
+ receive_pcs7.rate_match_empty_threshold = 5,
+ receive_pcs7.rate_match_fifo_mode = "true",
+ receive_pcs7.rate_match_full_threshold = 20,
+ receive_pcs7.rate_match_insert_threshold = 11,
+ receive_pcs7.rate_match_ordered_set_based = "false",
+ receive_pcs7.rate_match_pattern1 = "11010000111010000011",
+ receive_pcs7.rate_match_pattern2 = "00101111000101111100",
+ receive_pcs7.rate_match_pattern_size = 20,
+ receive_pcs7.rate_match_pipe_enable = "true",
+ receive_pcs7.rate_match_reset_enable = "false",
+ receive_pcs7.rate_match_skip_set_based = "true",
+ receive_pcs7.rate_match_start_threshold = 7,
+ receive_pcs7.rd_clk_mux_select = "core clock",
+ receive_pcs7.recovered_clk_mux_select = "recovered clock",
+ receive_pcs7.run_length = 40,
+ receive_pcs7.run_length_enable = "true",
+ receive_pcs7.rx_detect_bypass = "false",
+ receive_pcs7.rx_phfifo_wait_cnt = 32,
+ receive_pcs7.rxstatus_error_report_mode = 1,
+ receive_pcs7.self_test_mode = "incremental",
+ receive_pcs7.test_bus_sel = 10,
+ receive_pcs7.use_alignment_state_machine = "true",
+ receive_pcs7.use_deserializer_double_data_mode = "false",
+ receive_pcs7.use_deskew_fifo = "false",
+ receive_pcs7.use_double_data_mode = "true",
+ receive_pcs7.use_parallel_loopback = "false",
+ receive_pcs7.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs7.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.adaptive_equalization_mode = "none",
+ receive_pma0.allow_serial_loopback = "false",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = "0.82V",
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.enable_ltd = "false",
+ receive_pma0.enable_ltr = "true",
+ receive_pma0.eq_dc_gain = 3,
+ receive_pma0.eqa_ctrl = 0,
+ receive_pma0.eqb_ctrl = 0,
+ receive_pma0.eqc_ctrl = 0,
+ receive_pma0.eqd_ctrl = 0,
+ receive_pma0.eqv_ctrl = 0,
+ receive_pma0.eyemon_bandwidth = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "pcie2",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis = 4,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma0.signal_detect_loss_threshold = 3,
+ receive_pma0.termination = "OCT 100 Ohms",
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma1_analogtestbus),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(wire_receive_pma1_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma1_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.adaptive_equalization_mode = "none",
+ receive_pma1.allow_serial_loopback = "false",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = "0.82V",
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h01,
+ receive_pma1.enable_ltd = "false",
+ receive_pma1.enable_ltr = "true",
+ receive_pma1.eq_dc_gain = 3,
+ receive_pma1.eqa_ctrl = 0,
+ receive_pma1.eqb_ctrl = 0,
+ receive_pma1.eqc_ctrl = 0,
+ receive_pma1.eqd_ctrl = 0,
+ receive_pma1.eqv_ctrl = 0,
+ receive_pma1.eyemon_bandwidth = 0,
+ receive_pma1.force_signal_detect = "true",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 1,
+ receive_pma1.ppmselect = 32,
+ receive_pma1.protocol_hint = "pcie2",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis = 4,
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma1.signal_detect_loss_threshold = 3,
+ receive_pma1.termination = "OCT 100 Ohms",
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_external_termination = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma2_analogtestbus),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(wire_receive_pma2_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma2_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.adaptive_equalization_mode = "none",
+ receive_pma2.allow_serial_loopback = "false",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = "0.82V",
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h01,
+ receive_pma2.enable_ltd = "false",
+ receive_pma2.enable_ltr = "true",
+ receive_pma2.eq_dc_gain = 3,
+ receive_pma2.eqa_ctrl = 0,
+ receive_pma2.eqb_ctrl = 0,
+ receive_pma2.eqc_ctrl = 0,
+ receive_pma2.eqd_ctrl = 0,
+ receive_pma2.eqv_ctrl = 0,
+ receive_pma2.eyemon_bandwidth = 0,
+ receive_pma2.force_signal_detect = "true",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 1,
+ receive_pma2.ppmselect = 32,
+ receive_pma2.protocol_hint = "pcie2",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis = 4,
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma2.signal_detect_loss_threshold = 3,
+ receive_pma2.termination = "OCT 100 Ohms",
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_external_termination = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma3_analogtestbus),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_receive_pma3_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma3_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.adaptive_equalization_mode = "none",
+ receive_pma3.allow_serial_loopback = "false",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = "0.82V",
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h01,
+ receive_pma3.enable_ltd = "false",
+ receive_pma3.enable_ltr = "true",
+ receive_pma3.eq_dc_gain = 3,
+ receive_pma3.eqa_ctrl = 0,
+ receive_pma3.eqb_ctrl = 0,
+ receive_pma3.eqc_ctrl = 0,
+ receive_pma3.eqd_ctrl = 0,
+ receive_pma3.eqv_ctrl = 0,
+ receive_pma3.eyemon_bandwidth = 0,
+ receive_pma3.force_signal_detect = "true",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 1,
+ receive_pma3.ppmselect = 32,
+ receive_pma3.protocol_hint = "pcie2",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis = 4,
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma3.signal_detect_loss_threshold = 3,
+ receive_pma3.termination = "OCT 100 Ohms",
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_external_termination = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma4
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma4_analogtestbus),
+ .clockout(wire_receive_pma4_clockout),
+ .datain(rx_datain[4]),
+ .dataout(wire_receive_pma4_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[19:16]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pmadprioin_wire[2099:1800]),
+ .dprioout(wire_receive_pma4_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[4]),
+ .locktoref(rx_locktorefclk_wire[4]),
+ .locktorefout(wire_receive_pma4_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[4]),
+ .powerdn(cent_unit_rxibpowerdn[6]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[4]),
+ .recoverdatain(pll_ch_dataout_wire[9:8]),
+ .recoverdataout(wire_receive_pma4_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[6]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma4_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma4.adaptive_equalization_mode = "none",
+ receive_pma4.allow_serial_loopback = "false",
+ receive_pma4.channel_number = ((starting_channel_number + 4) % 4),
+ receive_pma4.channel_type = "auto",
+ receive_pma4.common_mode = "0.82V",
+ receive_pma4.deserialization_factor = 10,
+ receive_pma4.dprio_config_mode = 6'h01,
+ receive_pma4.enable_ltd = "false",
+ receive_pma4.enable_ltr = "true",
+ receive_pma4.eq_dc_gain = 3,
+ receive_pma4.eqa_ctrl = 0,
+ receive_pma4.eqb_ctrl = 0,
+ receive_pma4.eqc_ctrl = 0,
+ receive_pma4.eqd_ctrl = 0,
+ receive_pma4.eqv_ctrl = 0,
+ receive_pma4.eyemon_bandwidth = 0,
+ receive_pma4.force_signal_detect = "true",
+ receive_pma4.logical_channel_address = (starting_channel_number + 4),
+ receive_pma4.low_speed_test_select = 0,
+ receive_pma4.offset_cancellation = 1,
+ receive_pma4.ppmselect = 32,
+ receive_pma4.protocol_hint = "pcie2",
+ receive_pma4.send_direct_reverse_serial_loopback = "None",
+ receive_pma4.signal_detect_hysteresis = 4,
+ receive_pma4.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma4.signal_detect_loss_threshold = 3,
+ receive_pma4.termination = "OCT 100 Ohms",
+ receive_pma4.use_deser_double_data_width = "false",
+ receive_pma4.use_external_termination = "false",
+ receive_pma4.use_pma_direct = "false",
+ receive_pma4.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma5
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma5_analogtestbus),
+ .clockout(wire_receive_pma5_clockout),
+ .datain(rx_datain[5]),
+ .dataout(wire_receive_pma5_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[23:20]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pmadprioin_wire[2399:2100]),
+ .dprioout(wire_receive_pma5_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[5]),
+ .locktoref(rx_locktorefclk_wire[5]),
+ .locktorefout(wire_receive_pma5_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[5]),
+ .powerdn(cent_unit_rxibpowerdn[7]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[5]),
+ .recoverdatain(pll_ch_dataout_wire[11:10]),
+ .recoverdataout(wire_receive_pma5_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[7]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma5_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma5.adaptive_equalization_mode = "none",
+ receive_pma5.allow_serial_loopback = "false",
+ receive_pma5.channel_number = ((starting_channel_number + 5) % 4),
+ receive_pma5.channel_type = "auto",
+ receive_pma5.common_mode = "0.82V",
+ receive_pma5.deserialization_factor = 10,
+ receive_pma5.dprio_config_mode = 6'h01,
+ receive_pma5.enable_ltd = "false",
+ receive_pma5.enable_ltr = "true",
+ receive_pma5.eq_dc_gain = 3,
+ receive_pma5.eqa_ctrl = 0,
+ receive_pma5.eqb_ctrl = 0,
+ receive_pma5.eqc_ctrl = 0,
+ receive_pma5.eqd_ctrl = 0,
+ receive_pma5.eqv_ctrl = 0,
+ receive_pma5.eyemon_bandwidth = 0,
+ receive_pma5.force_signal_detect = "true",
+ receive_pma5.logical_channel_address = (starting_channel_number + 5),
+ receive_pma5.low_speed_test_select = 0,
+ receive_pma5.offset_cancellation = 1,
+ receive_pma5.ppmselect = 32,
+ receive_pma5.protocol_hint = "pcie2",
+ receive_pma5.send_direct_reverse_serial_loopback = "None",
+ receive_pma5.signal_detect_hysteresis = 4,
+ receive_pma5.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma5.signal_detect_loss_threshold = 3,
+ receive_pma5.termination = "OCT 100 Ohms",
+ receive_pma5.use_deser_double_data_width = "false",
+ receive_pma5.use_external_termination = "false",
+ receive_pma5.use_pma_direct = "false",
+ receive_pma5.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma6
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma6_analogtestbus),
+ .clockout(wire_receive_pma6_clockout),
+ .datain(rx_datain[6]),
+ .dataout(wire_receive_pma6_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[27:24]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pmadprioin_wire[2699:2400]),
+ .dprioout(wire_receive_pma6_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[6]),
+ .locktoref(rx_locktorefclk_wire[6]),
+ .locktorefout(wire_receive_pma6_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[6]),
+ .powerdn(cent_unit_rxibpowerdn[8]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[6]),
+ .recoverdatain(pll_ch_dataout_wire[13:12]),
+ .recoverdataout(wire_receive_pma6_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[8]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma6_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma6.adaptive_equalization_mode = "none",
+ receive_pma6.allow_serial_loopback = "false",
+ receive_pma6.channel_number = ((starting_channel_number + 6) % 4),
+ receive_pma6.channel_type = "auto",
+ receive_pma6.common_mode = "0.82V",
+ receive_pma6.deserialization_factor = 10,
+ receive_pma6.dprio_config_mode = 6'h01,
+ receive_pma6.enable_ltd = "false",
+ receive_pma6.enable_ltr = "true",
+ receive_pma6.eq_dc_gain = 3,
+ receive_pma6.eqa_ctrl = 0,
+ receive_pma6.eqb_ctrl = 0,
+ receive_pma6.eqc_ctrl = 0,
+ receive_pma6.eqd_ctrl = 0,
+ receive_pma6.eqv_ctrl = 0,
+ receive_pma6.eyemon_bandwidth = 0,
+ receive_pma6.force_signal_detect = "true",
+ receive_pma6.logical_channel_address = (starting_channel_number + 6),
+ receive_pma6.low_speed_test_select = 0,
+ receive_pma6.offset_cancellation = 1,
+ receive_pma6.ppmselect = 32,
+ receive_pma6.protocol_hint = "pcie2",
+ receive_pma6.send_direct_reverse_serial_loopback = "None",
+ receive_pma6.signal_detect_hysteresis = 4,
+ receive_pma6.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma6.signal_detect_loss_threshold = 3,
+ receive_pma6.termination = "OCT 100 Ohms",
+ receive_pma6.use_deser_double_data_width = "false",
+ receive_pma6.use_external_termination = "false",
+ receive_pma6.use_pma_direct = "false",
+ receive_pma6.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma7
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma7_analogtestbus),
+ .clockout(wire_receive_pma7_clockout),
+ .datain(rx_datain[7]),
+ .dataout(wire_receive_pma7_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[31:28]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(rx_pmadprioin_wire[2999:2700]),
+ .dprioout(wire_receive_pma7_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[7]),
+ .locktoref(rx_locktorefclk_wire[7]),
+ .locktorefout(wire_receive_pma7_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[7]),
+ .powerdn(cent_unit_rxibpowerdn[9]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[7]),
+ .recoverdatain(pll_ch_dataout_wire[15:14]),
+ .recoverdataout(wire_receive_pma7_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[9]),
+ .seriallpbken(1'b0),
+ .seriallpbkin(1'b0),
+ .signaldetect(wire_receive_pma7_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma7.adaptive_equalization_mode = "none",
+ receive_pma7.allow_serial_loopback = "false",
+ receive_pma7.channel_number = ((starting_channel_number + 7) % 4),
+ receive_pma7.channel_type = "auto",
+ receive_pma7.common_mode = "0.82V",
+ receive_pma7.deserialization_factor = 10,
+ receive_pma7.dprio_config_mode = 6'h01,
+ receive_pma7.enable_ltd = "false",
+ receive_pma7.enable_ltr = "true",
+ receive_pma7.eq_dc_gain = 3,
+ receive_pma7.eqa_ctrl = 0,
+ receive_pma7.eqb_ctrl = 0,
+ receive_pma7.eqc_ctrl = 0,
+ receive_pma7.eqd_ctrl = 0,
+ receive_pma7.eqv_ctrl = 0,
+ receive_pma7.eyemon_bandwidth = 0,
+ receive_pma7.force_signal_detect = "true",
+ receive_pma7.logical_channel_address = (starting_channel_number + 7),
+ receive_pma7.low_speed_test_select = 0,
+ receive_pma7.offset_cancellation = 1,
+ receive_pma7.ppmselect = 32,
+ receive_pma7.protocol_hint = "pcie2",
+ receive_pma7.send_direct_reverse_serial_loopback = "None",
+ receive_pma7.signal_detect_hysteresis = 4,
+ receive_pma7.signal_detect_hysteresis_valid_threshold = 14,
+ receive_pma7.signal_detect_loss_threshold = 3,
+ receive_pma7.termination = "OCT 100 Ohms",
+ receive_pma7.use_deser_double_data_width = "false",
+ receive_pma7.use_external_termination = "false",
+ receive_pma7.use_pma_direct = "false",
+ receive_pma7.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
+ .datain({{24{1'b0}}, tx_datain_wire[15:0]}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(tx_detectrxloop[0]),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[0]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[2:0]),
+ .enrevparallellpbk(tx_revparallellpbken[0]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[0]),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(wire_transmit_pcs0_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs0_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs0_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs0_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[1:0]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[1:0]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[1:0]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[1:0]),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[0]),
+ .pipetxdeemph(tx_pipedeemph[0]),
+ .pipetxmargin(tx_pipemargin[2:0]),
+ .pipetxswing(tx_pipeswing[0]),
+ .powerdn(powerdn[1:0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[19:0]),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "false",
+ transmit_pcs0.auto_spd_self_switch_enable = "true",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "x8",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "false",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "pipe",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "new",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "true",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.pipe_voltage_swing_control = "false",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "pcie2",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
+ .datain({{24{1'b0}}, tx_datain_wire[31:16]}),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(tx_detectrxloop[1]),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[1]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(wire_transmit_pcs1_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[5:3]),
+ .enrevparallellpbk(tx_revparallellpbken[1]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[1]),
+ .forceelecidleout(wire_transmit_pcs1_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(wire_transmit_pcs1_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs1_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs1_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs1_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[3:2]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[3:2]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[3:2]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[3:2]),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[1]),
+ .pipetxdeemph(tx_pipedeemph[1]),
+ .pipetxmargin(tx_pipemargin[5:3]),
+ .pipetxswing(tx_pipeswing[1]),
+ .powerdn(powerdn[3:2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[39:20]),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "false",
+ transmit_pcs1.auto_spd_self_switch_enable = "true",
+ transmit_pcs1.bitslip_enable = "false",
+ transmit_pcs1.channel_bonding = "x8",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 16,
+ transmit_pcs1.core_clock_0ppm = "false",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "pipe",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "new",
+ transmit_pcs1.dprio_config_mode = 6'h01,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "true",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.pipe_voltage_swing_control = "false",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "pcie2",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "true",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[5:4]}),
+ .datain({{24{1'b0}}, tx_datain_wire[47:32]}),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(tx_detectrxloop[2]),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[2]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(wire_transmit_pcs2_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[8:6]),
+ .enrevparallellpbk(tx_revparallellpbken[2]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[5:4]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[2]),
+ .forceelecidleout(wire_transmit_pcs2_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(wire_transmit_pcs2_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs2_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs2_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs2_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[5:4]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[5:4]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[5:4]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[5:4]),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs2_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[2]),
+ .pipetxdeemph(tx_pipedeemph[2]),
+ .pipetxmargin(tx_pipemargin[8:6]),
+ .pipetxswing(tx_pipeswing[2]),
+ .powerdn(powerdn[5:4]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[59:40]),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "false",
+ transmit_pcs2.auto_spd_self_switch_enable = "true",
+ transmit_pcs2.bitslip_enable = "false",
+ transmit_pcs2.channel_bonding = "x8",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 16,
+ transmit_pcs2.core_clock_0ppm = "false",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "pipe",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "new",
+ transmit_pcs2.dprio_config_mode = 6'h01,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "true",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.pipe_voltage_swing_control = "false",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "pcie2",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "true",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[7:6]}),
+ .datain({{24{1'b0}}, tx_datain_wire[63:48]}),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(tx_detectrxloop[3]),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[3]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(wire_transmit_pcs3_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[11:9]),
+ .enrevparallellpbk(tx_revparallellpbken[3]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[7:6]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[3]),
+ .forceelecidleout(wire_transmit_pcs3_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(wire_transmit_pcs3_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs3_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs3_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs3_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[7:6]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[7:6]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[7:6]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[7:6]),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs3_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[3]),
+ .pipetxdeemph(tx_pipedeemph[3]),
+ .pipetxmargin(tx_pipemargin[11:9]),
+ .pipetxswing(tx_pipeswing[3]),
+ .powerdn(powerdn[7:6]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk(rx_revparallelfdbkdata[79:60]),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "false",
+ transmit_pcs3.auto_spd_self_switch_enable = "true",
+ transmit_pcs3.bitslip_enable = "false",
+ transmit_pcs3.channel_bonding = "x8",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 16,
+ transmit_pcs3.core_clock_0ppm = "false",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "pipe",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "new",
+ transmit_pcs3.dprio_config_mode = 6'h01,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "true",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.pipe_voltage_swing_control = "false",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "pcie2",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "true",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs4
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[4]),
+ .coreclkout(wire_transmit_pcs4_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[9:8]}),
+ .datain({{24{1'b0}}, tx_datain_wire[79:64]}),
+ .dataout(wire_transmit_pcs4_dataout),
+ .detectrxloop(tx_detectrxloop[4]),
+ .digitalreset(tx_digitalreset_out[4]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[4]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_dprioin_wire[749:600]),
+ .dprioout(wire_transmit_pcs4_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[14:12]),
+ .enrevparallellpbk(tx_revparallellpbken[4]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[9:8]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[4]),
+ .forceelecidleout(wire_transmit_pcs4_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs4_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[4]),
+ .iqpphfifobyteselout(wire_transmit_pcs4_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs4_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs4_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs4_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[9:8]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[9:8]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[9:8]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[9:8]),
+ .localrefclk(tx_localrefclk[4]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[4]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[4]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs4_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[4]),
+ .phfiforesetout(wire_transmit_pcs4_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs4_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[14:12]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[14:12]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[14:12]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[14:12]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[14:12]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs4_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs4_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs4_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[4]),
+ .pipetxdeemph(tx_pipedeemph[4]),
+ .pipetxmargin(tx_pipemargin[14:12]),
+ .pipetxswing(tx_pipeswing[4]),
+ .powerdn(powerdn[9:8]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[99:80]),
+ .txdetectrx(wire_transmit_pcs4_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[4]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[39:32]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs4.allow_polarity_inversion = "false",
+ transmit_pcs4.auto_spd_self_switch_enable = "true",
+ transmit_pcs4.bitslip_enable = "false",
+ transmit_pcs4.channel_bonding = "x8",
+ transmit_pcs4.channel_number = ((starting_channel_number + 4) % 4),
+ transmit_pcs4.channel_width = 16,
+ transmit_pcs4.core_clock_0ppm = "false",
+ transmit_pcs4.datapath_low_latency_mode = "false",
+ transmit_pcs4.datapath_protocol = "pipe",
+ transmit_pcs4.disable_ph_low_latency_mode = "false",
+ transmit_pcs4.disparity_mode = "new",
+ transmit_pcs4.dprio_config_mode = 6'h01,
+ transmit_pcs4.elec_idle_delay = 6,
+ transmit_pcs4.enable_bit_reversal = "false",
+ transmit_pcs4.enable_idle_selection = "false",
+ transmit_pcs4.enable_reverse_parallel_loopback = "true",
+ transmit_pcs4.enable_self_test_mode = "false",
+ transmit_pcs4.enable_symbol_swap = "false",
+ transmit_pcs4.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs4.enc_8b_10b_mode = "normal",
+ transmit_pcs4.force_echar = "false",
+ transmit_pcs4.force_kchar = "false",
+ transmit_pcs4.hip_enable = "false",
+ transmit_pcs4.iqp_ph_fifo_xn_select = 1,
+ transmit_pcs4.logical_channel_address = (starting_channel_number + 4),
+ transmit_pcs4.ph_fifo_reg_mode = "false",
+ transmit_pcs4.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs4.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs4.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs4.ph_fifo_xn_select = 1,
+ transmit_pcs4.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs4.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs4.pipe_voltage_swing_control = "false",
+ transmit_pcs4.prbs_cid_pattern = "false",
+ transmit_pcs4.protocol_hint = "pcie2",
+ transmit_pcs4.refclk_select = "cmu_clock_divider",
+ transmit_pcs4.self_test_mode = "incremental",
+ transmit_pcs4.use_double_data_mode = "true",
+ transmit_pcs4.use_serializer_double_data_mode = "false",
+ transmit_pcs4.wr_clk_mux_select = "core_clk",
+ transmit_pcs4.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs5
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[5]),
+ .coreclkout(wire_transmit_pcs5_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[11:10]}),
+ .datain({{24{1'b0}}, tx_datain_wire[95:80]}),
+ .dataout(wire_transmit_pcs5_dataout),
+ .detectrxloop(tx_detectrxloop[5]),
+ .digitalreset(tx_digitalreset_out[5]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[5]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_dprioin_wire[899:750]),
+ .dprioout(wire_transmit_pcs5_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[17:15]),
+ .enrevparallellpbk(tx_revparallellpbken[5]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[11:10]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[5]),
+ .forceelecidleout(wire_transmit_pcs5_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs5_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[5]),
+ .iqpphfifobyteselout(wire_transmit_pcs5_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs5_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs5_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs5_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[11:10]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[11:10]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[11:10]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[11:10]),
+ .localrefclk(tx_localrefclk[5]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[5]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[5]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs5_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[5]),
+ .phfiforesetout(wire_transmit_pcs5_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs5_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[17:15]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[17:15]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[17:15]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[17:15]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[17:15]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs5_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs5_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs5_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[5]),
+ .pipetxdeemph(tx_pipedeemph[5]),
+ .pipetxmargin(tx_pipemargin[17:15]),
+ .pipetxswing(tx_pipeswing[5]),
+ .powerdn(powerdn[11:10]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[119:100]),
+ .txdetectrx(wire_transmit_pcs5_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[5]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[47:40]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs5.allow_polarity_inversion = "false",
+ transmit_pcs5.auto_spd_self_switch_enable = "true",
+ transmit_pcs5.bitslip_enable = "false",
+ transmit_pcs5.channel_bonding = "x8",
+ transmit_pcs5.channel_number = ((starting_channel_number + 5) % 4),
+ transmit_pcs5.channel_width = 16,
+ transmit_pcs5.core_clock_0ppm = "false",
+ transmit_pcs5.datapath_low_latency_mode = "false",
+ transmit_pcs5.datapath_protocol = "pipe",
+ transmit_pcs5.disable_ph_low_latency_mode = "false",
+ transmit_pcs5.disparity_mode = "new",
+ transmit_pcs5.dprio_config_mode = 6'h01,
+ transmit_pcs5.elec_idle_delay = 6,
+ transmit_pcs5.enable_bit_reversal = "false",
+ transmit_pcs5.enable_idle_selection = "false",
+ transmit_pcs5.enable_reverse_parallel_loopback = "true",
+ transmit_pcs5.enable_self_test_mode = "false",
+ transmit_pcs5.enable_symbol_swap = "false",
+ transmit_pcs5.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs5.enc_8b_10b_mode = "normal",
+ transmit_pcs5.force_echar = "false",
+ transmit_pcs5.force_kchar = "false",
+ transmit_pcs5.hip_enable = "false",
+ transmit_pcs5.logical_channel_address = (starting_channel_number + 5),
+ transmit_pcs5.ph_fifo_reg_mode = "false",
+ transmit_pcs5.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs5.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs5.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs5.ph_fifo_xn_select = 1,
+ transmit_pcs5.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs5.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs5.pipe_voltage_swing_control = "false",
+ transmit_pcs5.prbs_cid_pattern = "false",
+ transmit_pcs5.protocol_hint = "pcie2",
+ transmit_pcs5.refclk_select = "cmu_clock_divider",
+ transmit_pcs5.self_test_mode = "incremental",
+ transmit_pcs5.use_double_data_mode = "true",
+ transmit_pcs5.use_serializer_double_data_mode = "false",
+ transmit_pcs5.wr_clk_mux_select = "core_clk",
+ transmit_pcs5.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs6
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[6]),
+ .coreclkout(wire_transmit_pcs6_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[13:12]}),
+ .datain({{24{1'b0}}, tx_datain_wire[111:96]}),
+ .dataout(wire_transmit_pcs6_dataout),
+ .detectrxloop(tx_detectrxloop[6]),
+ .digitalreset(tx_digitalreset_out[6]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[6]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_dprioin_wire[1049:900]),
+ .dprioout(wire_transmit_pcs6_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[20:18]),
+ .enrevparallellpbk(tx_revparallellpbken[6]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[13:12]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[6]),
+ .forceelecidleout(wire_transmit_pcs6_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs6_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[6]),
+ .iqpphfifobyteselout(wire_transmit_pcs6_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs6_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs6_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs6_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[13:12]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[13:12]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[13:12]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[13:12]),
+ .localrefclk(tx_localrefclk[6]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[6]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[6]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs6_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[6]),
+ .phfiforesetout(wire_transmit_pcs6_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs6_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[20:18]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[20:18]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[20:18]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[20:18]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[20:18]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs6_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs6_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs6_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[6]),
+ .pipetxdeemph(tx_pipedeemph[6]),
+ .pipetxmargin(tx_pipemargin[20:18]),
+ .pipetxswing(tx_pipeswing[6]),
+ .powerdn(powerdn[13:12]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[139:120]),
+ .txdetectrx(wire_transmit_pcs6_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[6]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[55:48]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs6.allow_polarity_inversion = "false",
+ transmit_pcs6.auto_spd_self_switch_enable = "true",
+ transmit_pcs6.bitslip_enable = "false",
+ transmit_pcs6.channel_bonding = "x8",
+ transmit_pcs6.channel_number = ((starting_channel_number + 6) % 4),
+ transmit_pcs6.channel_width = 16,
+ transmit_pcs6.core_clock_0ppm = "false",
+ transmit_pcs6.datapath_low_latency_mode = "false",
+ transmit_pcs6.datapath_protocol = "pipe",
+ transmit_pcs6.disable_ph_low_latency_mode = "false",
+ transmit_pcs6.disparity_mode = "new",
+ transmit_pcs6.dprio_config_mode = 6'h01,
+ transmit_pcs6.elec_idle_delay = 6,
+ transmit_pcs6.enable_bit_reversal = "false",
+ transmit_pcs6.enable_idle_selection = "false",
+ transmit_pcs6.enable_reverse_parallel_loopback = "true",
+ transmit_pcs6.enable_self_test_mode = "false",
+ transmit_pcs6.enable_symbol_swap = "false",
+ transmit_pcs6.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs6.enc_8b_10b_mode = "normal",
+ transmit_pcs6.force_echar = "false",
+ transmit_pcs6.force_kchar = "false",
+ transmit_pcs6.hip_enable = "false",
+ transmit_pcs6.logical_channel_address = (starting_channel_number + 6),
+ transmit_pcs6.ph_fifo_reg_mode = "false",
+ transmit_pcs6.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs6.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs6.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs6.ph_fifo_xn_select = 1,
+ transmit_pcs6.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs6.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs6.pipe_voltage_swing_control = "false",
+ transmit_pcs6.prbs_cid_pattern = "false",
+ transmit_pcs6.protocol_hint = "pcie2",
+ transmit_pcs6.refclk_select = "cmu_clock_divider",
+ transmit_pcs6.self_test_mode = "incremental",
+ transmit_pcs6.use_double_data_mode = "true",
+ transmit_pcs6.use_serializer_double_data_mode = "false",
+ transmit_pcs6.wr_clk_mux_select = "core_clk",
+ transmit_pcs6.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs7
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[7]),
+ .coreclkout(wire_transmit_pcs7_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[15:14]}),
+ .datain({{24{1'b0}}, tx_datain_wire[127:112]}),
+ .dataout(wire_transmit_pcs7_dataout),
+ .detectrxloop(tx_detectrxloop[7]),
+ .digitalreset(tx_digitalreset_out[7]),
+ .dispval({{2{1'b0}}, {2{tx_forceelecidle[7]}}}),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_dprioin_wire[1199:1050]),
+ .dprioout(wire_transmit_pcs7_dprioout),
+ .elecidleinfersel(rx_elecidleinfersel[23:21]),
+ .enrevparallellpbk(tx_revparallellpbken[7]),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[15:14]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidle(tx_forceelecidle[7]),
+ .forceelecidleout(wire_transmit_pcs7_forceelecidleout),
+ .grayelecidleinferselout(wire_transmit_pcs7_grayelecidleinferselout),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[7]),
+ .iqpphfifobyteselout(wire_transmit_pcs7_iqpphfifobyteselout),
+ .iqpphfifordclkout(wire_transmit_pcs7_iqpphfifordclkout),
+ .iqpphfifordenableout(wire_transmit_pcs7_iqpphfifordenableout),
+ .iqpphfifowrenableout(wire_transmit_pcs7_iqpphfifowrenableout),
+ .iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[15:14]),
+ .iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[15:14]),
+ .iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[15:14]),
+ .iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[15:14]),
+ .localrefclk(tx_localrefclk[7]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[7]),
+ .phfifooverflow(),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[7]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs7_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[7]),
+ .phfiforesetout(wire_transmit_pcs7_phfiforesetout),
+ .phfifounderflow(),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs7_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[23:21]),
+ .phfifoxnptrsreset(int_tx_phfifioxnptrsreset[23:21]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[23:21]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[23:21]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[23:21]),
+ .pipeenrevparallellpbkout(wire_transmit_pcs7_pipeenrevparallellpbkout),
+ .pipepowerdownout(wire_transmit_pcs7_pipepowerdownout),
+ .pipepowerstateout(wire_transmit_pcs7_pipepowerstateout),
+ .pipestatetransdone(rx_pipestatetransdoneout[7]),
+ .pipetxdeemph(tx_pipedeemph[7]),
+ .pipetxmargin(tx_pipemargin[23:21]),
+ .pipetxswing(tx_pipeswing[7]),
+ .powerdn(powerdn[15:14]),
+ .quadreset(cent_unit_quadresetout[1]),
+ .rateswitchout(),
+ .rdenablesync(),
+ .refclk(refclk_pma[1]),
+ .revparallelfdbk(rx_revparallelfdbkdata[159:140]),
+ .txdetectrx(wire_transmit_pcs7_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[7]),
+ .xgmctrlenable(),
+ .xgmdatain(cent_unit_tx_xgmdataout[63:56]),
+ .xgmdataout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .datainfull({44{1'b0}}),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs7.allow_polarity_inversion = "false",
+ transmit_pcs7.auto_spd_self_switch_enable = "true",
+ transmit_pcs7.bitslip_enable = "false",
+ transmit_pcs7.channel_bonding = "x8",
+ transmit_pcs7.channel_number = ((starting_channel_number + 7) % 4),
+ transmit_pcs7.channel_width = 16,
+ transmit_pcs7.core_clock_0ppm = "false",
+ transmit_pcs7.datapath_low_latency_mode = "false",
+ transmit_pcs7.datapath_protocol = "pipe",
+ transmit_pcs7.disable_ph_low_latency_mode = "false",
+ transmit_pcs7.disparity_mode = "new",
+ transmit_pcs7.dprio_config_mode = 6'h01,
+ transmit_pcs7.elec_idle_delay = 6,
+ transmit_pcs7.enable_bit_reversal = "false",
+ transmit_pcs7.enable_idle_selection = "false",
+ transmit_pcs7.enable_reverse_parallel_loopback = "true",
+ transmit_pcs7.enable_self_test_mode = "false",
+ transmit_pcs7.enable_symbol_swap = "false",
+ transmit_pcs7.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs7.enc_8b_10b_mode = "normal",
+ transmit_pcs7.force_echar = "false",
+ transmit_pcs7.force_kchar = "false",
+ transmit_pcs7.hip_enable = "false",
+ transmit_pcs7.logical_channel_address = (starting_channel_number + 7),
+ transmit_pcs7.ph_fifo_reg_mode = "false",
+ transmit_pcs7.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs7.ph_fifo_xn_mapping1 = "up",
+ transmit_pcs7.ph_fifo_xn_mapping2 = "none",
+ transmit_pcs7.ph_fifo_xn_select = 1,
+ transmit_pcs7.pipe_auto_speed_nego_enable = "true",
+ transmit_pcs7.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs7.pipe_voltage_swing_control = "false",
+ transmit_pcs7.prbs_cid_pattern = "false",
+ transmit_pcs7.protocol_hint = "pcie2",
+ transmit_pcs7.refclk_select = "cmu_clock_divider",
+ transmit_pcs7.self_test_mode = "incremental",
+ transmit_pcs7.use_double_data_mode = "true",
+ transmit_pcs7.use_serializer_double_data_mode = "false",
+ transmit_pcs7.wr_clk_mux_select = "core_clk",
+ transmit_pcs7.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(edge_pll_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[0]),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(edge_pll_analogrefclkout[1:0]),
+ .refclk1inpulse(edge_pll_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma0_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "auto",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.logical_protocol_hint_0 = "pcie2",
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.physical_clkin1_mapping = "x4",
+ transmit_pma0.preemp_pretap = 0,
+ transmit_pma0.preemp_pretap_inv = "false",
+ transmit_pma0.preemp_tap_1 = 0,
+ transmit_pma0.preemp_tap_1_a = 28,
+ transmit_pma0.preemp_tap_1_b = 22,
+ transmit_pma0.preemp_tap_1_c = 7,
+ transmit_pma0.preemp_tap_2 = 0,
+ transmit_pma0.preemp_tap_2_inv = "false",
+ transmit_pma0.protocol_hint = "pcie2",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "off",
+ transmit_pma0.termination = "OCT 100 Ohms",
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = 3,
+ transmit_pma0.vod_selection_a = 6,
+ transmit_pma0.vod_selection_c = 1,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(wire_transmit_pma1_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(edge_pll_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[1]),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(edge_pll_analogrefclkout[1:0]),
+ .refclk1inpulse(edge_pll_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma1_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[1])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "auto",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h01,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.logical_protocol_hint_0 = "pcie2",
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.physical_clkin1_mapping = "x4",
+ transmit_pma1.preemp_pretap = 0,
+ transmit_pma1.preemp_pretap_inv = "false",
+ transmit_pma1.preemp_tap_1 = 0,
+ transmit_pma1.preemp_tap_1_a = 28,
+ transmit_pma1.preemp_tap_1_b = 22,
+ transmit_pma1.preemp_tap_1_c = 7,
+ transmit_pma1.preemp_tap_2 = 0,
+ transmit_pma1.preemp_tap_2_inv = "false",
+ transmit_pma1.protocol_hint = "pcie2",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "off",
+ transmit_pma1.termination = "OCT 100 Ohms",
+ transmit_pma1.use_external_termination = "false",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = 3,
+ transmit_pma1.vod_selection_a = 6,
+ transmit_pma1.vod_selection_c = 1,
+ transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(wire_transmit_pma2_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(edge_pll_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[2]),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(edge_pll_analogrefclkout[1:0]),
+ .refclk1inpulse(edge_pll_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma2_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[2])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "auto",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h01,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.logical_protocol_hint_0 = "pcie2",
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.physical_clkin1_mapping = "x4",
+ transmit_pma2.preemp_pretap = 0,
+ transmit_pma2.preemp_pretap_inv = "false",
+ transmit_pma2.preemp_tap_1 = 0,
+ transmit_pma2.preemp_tap_1_a = 28,
+ transmit_pma2.preemp_tap_1_b = 22,
+ transmit_pma2.preemp_tap_1_c = 7,
+ transmit_pma2.preemp_tap_2 = 0,
+ transmit_pma2.preemp_tap_2_inv = "false",
+ transmit_pma2.protocol_hint = "pcie2",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "off",
+ transmit_pma2.termination = "OCT 100 Ohms",
+ transmit_pma2.use_external_termination = "false",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = 3,
+ transmit_pma2.vod_selection_a = 6,
+ transmit_pma2.vod_selection_c = 1,
+ transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_transmit_pma3_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(edge_pll_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[3]),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(edge_pll_analogrefclkout[1:0]),
+ .refclk1inpulse(edge_pll_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma3_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[3])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "auto",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h01,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.logical_protocol_hint_0 = "pcie2",
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.physical_clkin1_mapping = "x4",
+ transmit_pma3.preemp_pretap = 0,
+ transmit_pma3.preemp_pretap_inv = "false",
+ transmit_pma3.preemp_tap_1 = 0,
+ transmit_pma3.preemp_tap_1_a = 28,
+ transmit_pma3.preemp_tap_1_b = 22,
+ transmit_pma3.preemp_tap_1_c = 7,
+ transmit_pma3.preemp_tap_2 = 0,
+ transmit_pma3.preemp_tap_2_inv = "false",
+ transmit_pma3.protocol_hint = "pcie2",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "off",
+ transmit_pma3.termination = "OCT 100 Ohms",
+ transmit_pma3.use_external_termination = "false",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = 3,
+ transmit_pma3.vod_selection_a = 6,
+ transmit_pma3.vod_selection_c = 1,
+ transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma4
+ (
+ .clockout(wire_transmit_pma4_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[99:80]}),
+ .dataout(wire_transmit_pma4_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[6]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_pmadprioin_wire[2099:1800]),
+ .dprioout(wire_transmit_pma4_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(edge_pll_analogfastrefclkout[1:0]),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[4]),
+ .powerdn(cent_unit_txobpowerdn[6]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(edge_pll_analogrefclkout[1:0]),
+ .refclk2inpulse(edge_pll_analogrefclkpulse[0]),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[4]),
+ .rxdetectvalidout(wire_transmit_pma4_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma4_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[6])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma4.analog_power = "auto",
+ transmit_pma4.channel_number = ((starting_channel_number + 4) % 4),
+ transmit_pma4.channel_type = "auto",
+ transmit_pma4.clkin_select = 2,
+ transmit_pma4.clkmux_delay = "false",
+ transmit_pma4.common_mode = "0.65V",
+ transmit_pma4.dprio_config_mode = 6'h01,
+ transmit_pma4.enable_reverse_serial_loopback = "false",
+ transmit_pma4.logical_channel_address = (starting_channel_number + 4),
+ transmit_pma4.logical_protocol_hint_0 = "pcie2",
+ transmit_pma4.low_speed_test_select = 0,
+ transmit_pma4.physical_clkin2_mapping = "xn_top",
+ transmit_pma4.preemp_pretap = 0,
+ transmit_pma4.preemp_pretap_inv = "false",
+ transmit_pma4.preemp_tap_1 = 0,
+ transmit_pma4.preemp_tap_1_a = 28,
+ transmit_pma4.preemp_tap_1_b = 22,
+ transmit_pma4.preemp_tap_1_c = 7,
+ transmit_pma4.preemp_tap_2 = 0,
+ transmit_pma4.preemp_tap_2_inv = "false",
+ transmit_pma4.protocol_hint = "pcie2",
+ transmit_pma4.rx_detect = 0,
+ transmit_pma4.serialization_factor = 10,
+ transmit_pma4.slew_rate = "off",
+ transmit_pma4.termination = "OCT 100 Ohms",
+ transmit_pma4.use_external_termination = "false",
+ transmit_pma4.use_pma_direct = "false",
+ transmit_pma4.use_ser_double_data_mode = "false",
+ transmit_pma4.vod_selection = 3,
+ transmit_pma4.vod_selection_a = 6,
+ transmit_pma4.vod_selection_c = 1,
+ transmit_pma4.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma5
+ (
+ .clockout(wire_transmit_pma5_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[119:100]}),
+ .dataout(wire_transmit_pma5_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[7]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_pmadprioin_wire[2399:2100]),
+ .dprioout(wire_transmit_pma5_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(edge_pll_analogfastrefclkout[1:0]),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[5]),
+ .powerdn(cent_unit_txobpowerdn[7]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(edge_pll_analogrefclkout[1:0]),
+ .refclk2inpulse(edge_pll_analogrefclkpulse[0]),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[5]),
+ .rxdetectvalidout(wire_transmit_pma5_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma5_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[7])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma5.analog_power = "auto",
+ transmit_pma5.channel_number = ((starting_channel_number + 5) % 4),
+ transmit_pma5.channel_type = "auto",
+ transmit_pma5.clkin_select = 2,
+ transmit_pma5.clkmux_delay = "false",
+ transmit_pma5.common_mode = "0.65V",
+ transmit_pma5.dprio_config_mode = 6'h01,
+ transmit_pma5.enable_reverse_serial_loopback = "false",
+ transmit_pma5.logical_channel_address = (starting_channel_number + 5),
+ transmit_pma5.logical_protocol_hint_0 = "pcie2",
+ transmit_pma5.low_speed_test_select = 0,
+ transmit_pma5.physical_clkin2_mapping = "xn_top",
+ transmit_pma5.preemp_pretap = 0,
+ transmit_pma5.preemp_pretap_inv = "false",
+ transmit_pma5.preemp_tap_1 = 0,
+ transmit_pma5.preemp_tap_1_a = 28,
+ transmit_pma5.preemp_tap_1_b = 22,
+ transmit_pma5.preemp_tap_1_c = 7,
+ transmit_pma5.preemp_tap_2 = 0,
+ transmit_pma5.preemp_tap_2_inv = "false",
+ transmit_pma5.protocol_hint = "pcie2",
+ transmit_pma5.rx_detect = 0,
+ transmit_pma5.serialization_factor = 10,
+ transmit_pma5.slew_rate = "off",
+ transmit_pma5.termination = "OCT 100 Ohms",
+ transmit_pma5.use_external_termination = "false",
+ transmit_pma5.use_pma_direct = "false",
+ transmit_pma5.use_ser_double_data_mode = "false",
+ transmit_pma5.vod_selection = 3,
+ transmit_pma5.vod_selection_a = 6,
+ transmit_pma5.vod_selection_c = 1,
+ transmit_pma5.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma6
+ (
+ .clockout(wire_transmit_pma6_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[139:120]}),
+ .dataout(wire_transmit_pma6_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[8]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_pmadprioin_wire[2699:2400]),
+ .dprioout(wire_transmit_pma6_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(edge_pll_analogfastrefclkout[1:0]),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[6]),
+ .powerdn(cent_unit_txobpowerdn[8]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(edge_pll_analogrefclkout[1:0]),
+ .refclk2inpulse(edge_pll_analogrefclkpulse[0]),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[6]),
+ .rxdetectvalidout(wire_transmit_pma6_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma6_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[8])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma6.analog_power = "auto",
+ transmit_pma6.channel_number = ((starting_channel_number + 6) % 4),
+ transmit_pma6.channel_type = "auto",
+ transmit_pma6.clkin_select = 2,
+ transmit_pma6.clkmux_delay = "false",
+ transmit_pma6.common_mode = "0.65V",
+ transmit_pma6.dprio_config_mode = 6'h01,
+ transmit_pma6.enable_reverse_serial_loopback = "false",
+ transmit_pma6.logical_channel_address = (starting_channel_number + 6),
+ transmit_pma6.logical_protocol_hint_0 = "pcie2",
+ transmit_pma6.low_speed_test_select = 0,
+ transmit_pma6.physical_clkin2_mapping = "xn_top",
+ transmit_pma6.preemp_pretap = 0,
+ transmit_pma6.preemp_pretap_inv = "false",
+ transmit_pma6.preemp_tap_1 = 0,
+ transmit_pma6.preemp_tap_1_a = 28,
+ transmit_pma6.preemp_tap_1_b = 22,
+ transmit_pma6.preemp_tap_1_c = 7,
+ transmit_pma6.preemp_tap_2 = 0,
+ transmit_pma6.preemp_tap_2_inv = "false",
+ transmit_pma6.protocol_hint = "pcie2",
+ transmit_pma6.rx_detect = 0,
+ transmit_pma6.serialization_factor = 10,
+ transmit_pma6.slew_rate = "off",
+ transmit_pma6.termination = "OCT 100 Ohms",
+ transmit_pma6.use_external_termination = "false",
+ transmit_pma6.use_pma_direct = "false",
+ transmit_pma6.use_ser_double_data_mode = "false",
+ transmit_pma6.vod_selection = 3,
+ transmit_pma6.vod_selection_a = 6,
+ transmit_pma6.vod_selection_c = 1,
+ transmit_pma6.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma7
+ (
+ .clockout(wire_transmit_pma7_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[159:140]}),
+ .dataout(wire_transmit_pma7_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[9]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[1]),
+ .dprioin(tx_pmadprioin_wire[2999:2700]),
+ .dprioout(wire_transmit_pma7_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in({2{1'b0}}),
+ .fastrefclk2in(edge_pll_analogfastrefclkout[1:0]),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(tx_pcs_forceelecidleout[7]),
+ .powerdn(cent_unit_txobpowerdn[9]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in({2{1'b0}}),
+ .refclk1inpulse(1'b0),
+ .refclk2in(edge_pll_analogrefclkout[1:0]),
+ .refclk2inpulse(edge_pll_analogrefclkpulse[0]),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[7]),
+ .rxdetectvalidout(wire_transmit_pma7_rxdetectvalidout),
+ .rxfoundout(wire_transmit_pma7_rxfoundout),
+ .seriallpbkout(),
+ .txpmareset(tx_analogreset_out[9])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma7.analog_power = "auto",
+ transmit_pma7.channel_number = ((starting_channel_number + 7) % 4),
+ transmit_pma7.channel_type = "auto",
+ transmit_pma7.clkin_select = 2,
+ transmit_pma7.clkmux_delay = "false",
+ transmit_pma7.common_mode = "0.65V",
+ transmit_pma7.dprio_config_mode = 6'h01,
+ transmit_pma7.enable_reverse_serial_loopback = "false",
+ transmit_pma7.logical_channel_address = (starting_channel_number + 7),
+ transmit_pma7.logical_protocol_hint_0 = "pcie2",
+ transmit_pma7.low_speed_test_select = 0,
+ transmit_pma7.physical_clkin2_mapping = "xn_top",
+ transmit_pma7.preemp_pretap = 0,
+ transmit_pma7.preemp_pretap_inv = "false",
+ transmit_pma7.preemp_tap_1 = 0,
+ transmit_pma7.preemp_tap_1_a = 28,
+ transmit_pma7.preemp_tap_1_b = 22,
+ transmit_pma7.preemp_tap_1_c = 7,
+ transmit_pma7.preemp_tap_2 = 0,
+ transmit_pma7.preemp_tap_2_inv = "false",
+ transmit_pma7.protocol_hint = "pcie2",
+ transmit_pma7.rx_detect = 0,
+ transmit_pma7.serialization_factor = 10,
+ transmit_pma7.slew_rate = "off",
+ transmit_pma7.termination = "OCT 100 Ohms",
+ transmit_pma7.use_external_termination = "false",
+ transmit_pma7.use_pma_direct = "false",
+ transmit_pma7.use_ser_double_data_mode = "false",
+ transmit_pma7.vod_selection = 3,
+ transmit_pma7.vod_selection_a = 6,
+ transmit_pma7.vod_selection_c = 1,
+ transmit_pma7.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ cal_blk_powerdown = 1'b0,
+ cent_unit_clkdivpowerdn = {wire_cent_unit1_clkdivpowerdn[0], wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_cmudividerdprioout = {wire_cent_unit1_cmudividerdprioout, wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit1_cmuplldprioout, wire_cent_unit0_cmuplldprioout},
+ cent_unit_quadresetout = {wire_cent_unit1_quadresetout, wire_cent_unit0_quadresetout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit1_rxcrupowerdown[5:0], wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit1_rxibpowerdown[5:0], wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {rx_pcsdprioout[3199:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit1_rxpcsdprioout[1599:0], wire_cent_unit0_rxpcsdprioout[1599:0]},
+ cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit1_rxpmadprioout[1799:0], wire_cent_unit0_rxpmadprioout[1799:0]},
+ cent_unit_tx_dprioin = {{1200{1'b0}}, tx_txdprioout[1199:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit1_txdataout[31:0], wire_cent_unit0_txdataout[31:0]},
+ cent_unit_txctrlout = {wire_cent_unit1_txctrlout, wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit1_txdetectrxpowerdown[5:0], wire_cent_unit0_txdetectrxpowerdown[5:0]},
+ cent_unit_txdprioout = {wire_cent_unit1_txpcsdprioout[599:0], wire_cent_unit0_txpcsdprioout[599:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit1_txobpowerdown[5:0], wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit1_txpmadprioout[1799:0], wire_cent_unit0_txpmadprioout[1799:0]},
+ clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div1_dprioout, {400{1'b0}}, {100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
+ clk_div_pclkin = {2{refclk_pma_wire[0]}},
+ clock_divider_clk0in = {edge_pll_out[3:0]},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_bi_quad_wire = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div1_coreclkout, wire_central_clk_div0_coreclkout},
+ edge_cmu_clkdivpowerdn = {wire_atx_pll_cent_unit0_clkdivpowerdn[0]},
+ edge_cmu_pllpowerdn = {wire_atx_pll_cent_unit0_pllpowerdn[0]},
+ edge_cmu_pllresetout = {wire_atx_pll_cent_unit0_pllresetout[0]},
+ edge_cmu_quadresetout = {wire_atx_pll_cent_unit0_quadresetout},
+ edge_pll_analogfastrefclkout = {wire_atx_clk_div0_analogfastrefclkout},
+ edge_pll_analogrefclkout = {wire_atx_clk_div0_analogrefclkout},
+ edge_pll_analogrefclkpulse = {wire_atx_clk_div0_analogrefclkpulse},
+ edge_pll_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
+ edge_pll_out = {wire_atx_pll0_clk[3:0]},
+ edge_pllpowerdn_in = {edge_cmu_pllpowerdn[0]},
+ edge_pllreset_in = {edge_cmu_pllresetout[0]},
+ fixedclk = 1'b0,
+ fixedclk_to_cmu = {12{reconfig_clk}},
+ grayelecidleinfersel_from_tx = {wire_transmit_pcs7_grayelecidleinferselout, wire_transmit_pcs6_grayelecidleinferselout, wire_transmit_pcs5_grayelecidleinferselout, wire_transmit_pcs4_grayelecidleinferselout, wire_transmit_pcs3_grayelecidleinferselout, wire_transmit_pcs2_grayelecidleinferselout, wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
+ int_atx_hiprateswtichdone = wire_atx_clk_div0_rateswitchdone,
+ int_autospdx4configsel = {wire_cent_unit1_autospdx4configsel, wire_cent_unit0_autospdx4configsel},
+ int_autospdx4spdchg = {wire_cent_unit1_autospdx4spdchg, wire_cent_unit0_autospdx4spdchg},
+ int_hiprateswtichdone = {wire_central_clk_div1_rateswitchdone, wire_central_clk_div0_rateswitchdone},
+ int_pcie_sw = {((int_pcie_sw_select[1] & int_pll_reset_delayed[1]) | ((~ int_pcie_sw_select[1]) & pcie_sw_wire[1])), ((int_pcie_sw_select[0] & int_pll_reset_delayed[0]) | ((~ int_pcie_sw_select[0]) & pcie_sw_wire[0]))},
+ int_pcie_sw_select = {pcie_sw_sel_delay_blk1c[9], pcie_sw_sel_delay_blk0c[9]},
+ int_phfifiox4ptrsreset = {wire_cent_unit1_phfifiox4ptrsreset, wire_cent_unit0_phfifiox4ptrsreset},
+ int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs7_pipeenrevparallellpbkout, wire_transmit_pcs6_pipeenrevparallellpbkout, wire_transmit_pcs5_pipeenrevparallellpbkout, wire_transmit_pcs4_pipeenrevparallellpbkout, wire_transmit_pcs3_pipeenrevparallellpbkout, wire_transmit_pcs2_pipeenrevparallellpbkout, wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
+ int_pll_reset_delayed = {pllreset_delay_blk1c[9], pllreset_delay_blk0c[9]},
+ int_rateswitch = {int_rx_rateswitchout[4], int_rx_rateswitchout[0]},
+ int_rateswitchout = {wire_central_clk_div1_rateswitchout, wire_central_clk_div0_rateswitchout},
+ int_rx_autospdspdchgout = {wire_receive_pcs7_autospdspdchgout, wire_receive_pcs6_autospdspdchgout, wire_receive_pcs5_autospdspdchgout, wire_receive_pcs4_autospdspdchgout, wire_receive_pcs3_autospdspdchgout, wire_receive_pcs2_autospdspdchgout, wire_receive_pcs1_autospdspdchgout, wire_receive_pcs0_autospdspdchgout},
+ int_rx_autospdxnconfigsel = {1'b0, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], 1'b0, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}},
+ int_rx_autospdxnspdchg = {1'b0, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], 1'b0, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}},
+ int_rx_coreclkout = {wire_receive_pcs7_coreclkout, wire_receive_pcs6_coreclkout, wire_receive_pcs5_coreclkout, wire_receive_pcs4_coreclkout, wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
+ int_rx_iqpautospdxnspgchg = {{3{{2{1'b0}}}}, int_rx_autospdspdchgout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_iqpphfifobyteselout = {wire_receive_pcs7_iqpphfifobyteselout, wire_receive_pcs6_iqpphfifobyteselout, wire_receive_pcs5_iqpphfifobyteselout, wire_receive_pcs4_iqpphfifobyteselout, wire_receive_pcs3_iqpphfifobyteselout, wire_receive_pcs2_iqpphfifobyteselout, wire_receive_pcs1_iqpphfifobyteselout, wire_receive_pcs0_iqpphfifobyteselout},
+ int_rx_iqpphfifoptrsresetout = {wire_receive_pcs7_iqpphfifoptrsresetout, wire_receive_pcs6_iqpphfifoptrsresetout, wire_receive_pcs5_iqpphfifoptrsresetout, wire_receive_pcs4_iqpphfifoptrsresetout, wire_receive_pcs3_iqpphfifoptrsresetout, wire_receive_pcs2_iqpphfifoptrsresetout, wire_receive_pcs1_iqpphfifoptrsresetout, wire_receive_pcs0_iqpphfifoptrsresetout},
+ int_rx_iqpphfifordenableout = {wire_receive_pcs7_iqpphfifordenableout, wire_receive_pcs6_iqpphfifordenableout, wire_receive_pcs5_iqpphfifordenableout, wire_receive_pcs4_iqpphfifordenableout, wire_receive_pcs3_iqpphfifordenableout, wire_receive_pcs2_iqpphfifordenableout, wire_receive_pcs1_iqpphfifordenableout, wire_receive_pcs0_iqpphfifordenableout},
+ int_rx_iqpphfifowrclkout = {wire_receive_pcs7_iqpphfifowrclkout, wire_receive_pcs6_iqpphfifowrclkout, wire_receive_pcs5_iqpphfifowrclkout, wire_receive_pcs4_iqpphfifowrclkout, wire_receive_pcs3_iqpphfifowrclkout, wire_receive_pcs2_iqpphfifowrclkout, wire_receive_pcs1_iqpphfifowrclkout, wire_receive_pcs0_iqpphfifowrclkout},
+ int_rx_iqpphfifowrenableout = {wire_receive_pcs7_iqpphfifowrenableout, wire_receive_pcs6_iqpphfifowrenableout, wire_receive_pcs5_iqpphfifowrenableout, wire_receive_pcs4_iqpphfifowrenableout, wire_receive_pcs3_iqpphfifowrenableout, wire_receive_pcs2_iqpphfifowrenableout, wire_receive_pcs1_iqpphfifowrenableout, wire_receive_pcs0_iqpphfifowrenableout},
+ int_rx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_rx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_iqpphfifoxnptrsreset = {{3{{2{1'b0}}}}, int_rx_iqpphfifoptrsresetout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_iqpphfifoxnwrclk = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrclkout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_rx_phfifioxnptrsreset = {1'b0, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], 1'b0, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs7_phfifobyteserdisableout, wire_receive_pcs6_phfifobyteserdisableout, wire_receive_pcs5_phfifobyteserdisableout, wire_receive_pcs4_phfifobyteserdisableout, wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs7_phfifoptrsresetout, wire_receive_pcs6_phfifoptrsresetout, wire_receive_pcs5_phfifoptrsresetout, wire_receive_pcs4_phfifoptrsresetout, wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs7_phfifordenableout, wire_receive_pcs6_phfifordenableout, wire_receive_pcs5_phfifordenableout, wire_receive_pcs4_phfifordenableout, wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs7_phfiforesetout, wire_receive_pcs6_phfiforesetout, wire_receive_pcs5_phfiforesetout, wire_receive_pcs4_phfiforesetout, wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs7_phfifowrdisableout, wire_receive_pcs6_phfifowrdisableout, wire_receive_pcs5_phfifowrdisableout, wire_receive_pcs4_phfifowrdisableout, wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {1'b0, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], 1'b0, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
+ int_rx_phfifoxnrdenable = {1'b0, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], 1'b0, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrclk = {1'b0, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], 1'b0, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrenable = {1'b0, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], 1'b0, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
+ int_rx_rateswitchout = {wire_receive_pcs7_rateswitchout, wire_receive_pcs6_rateswitchout, wire_receive_pcs5_rateswitchout, wire_receive_pcs4_rateswitchout, wire_receive_pcs3_rateswitchout, wire_receive_pcs2_rateswitchout, wire_receive_pcs1_rateswitchout, wire_receive_pcs0_rateswitchout},
+ int_rxcoreclk = {1'b0, int_rx_coreclkout[0]},
+ int_rxpcs_cdrctrlearlyeios = {wire_receive_pcs7_cdrctrlearlyeios, wire_receive_pcs6_cdrctrlearlyeios, wire_receive_pcs5_cdrctrlearlyeios, wire_receive_pcs4_cdrctrlearlyeios, wire_receive_pcs3_cdrctrlearlyeios, wire_receive_pcs2_cdrctrlearlyeios, wire_receive_pcs1_cdrctrlearlyeios, wire_receive_pcs0_cdrctrlearlyeios},
+ int_rxphfifordenable = {1'b0, int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {1'b0, int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit1_rxphfifox4byteselout, wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit1_rxphfifox4rdenableout, wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit1_rxphfifox4wrclkout, wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit1_rxphfifox4wrenableout, wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs7_coreclkout, wire_transmit_pcs6_coreclkout, wire_transmit_pcs5_coreclkout, wire_transmit_pcs4_coreclkout, wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
+ int_tx_iqpphfifobyteselout = {wire_transmit_pcs7_iqpphfifobyteselout, wire_transmit_pcs6_iqpphfifobyteselout, wire_transmit_pcs5_iqpphfifobyteselout, wire_transmit_pcs4_iqpphfifobyteselout, wire_transmit_pcs3_iqpphfifobyteselout, wire_transmit_pcs2_iqpphfifobyteselout, wire_transmit_pcs1_iqpphfifobyteselout, wire_transmit_pcs0_iqpphfifobyteselout},
+ int_tx_iqpphfifordclkout = {wire_transmit_pcs7_iqpphfifordclkout, wire_transmit_pcs6_iqpphfifordclkout, wire_transmit_pcs5_iqpphfifordclkout, wire_transmit_pcs4_iqpphfifordclkout, wire_transmit_pcs3_iqpphfifordclkout, wire_transmit_pcs2_iqpphfifordclkout, wire_transmit_pcs1_iqpphfifordclkout, wire_transmit_pcs0_iqpphfifordclkout},
+ int_tx_iqpphfifordenableout = {wire_transmit_pcs7_iqpphfifordenableout, wire_transmit_pcs6_iqpphfifordenableout, wire_transmit_pcs5_iqpphfifordenableout, wire_transmit_pcs4_iqpphfifordenableout, wire_transmit_pcs3_iqpphfifordenableout, wire_transmit_pcs2_iqpphfifordenableout, wire_transmit_pcs1_iqpphfifordenableout, wire_transmit_pcs0_iqpphfifordenableout},
+ int_tx_iqpphfifowrenableout = {wire_transmit_pcs7_iqpphfifowrenableout, wire_transmit_pcs6_iqpphfifowrenableout, wire_transmit_pcs5_iqpphfifowrenableout, wire_transmit_pcs4_iqpphfifowrenableout, wire_transmit_pcs3_iqpphfifowrenableout, wire_transmit_pcs2_iqpphfifowrenableout, wire_transmit_pcs1_iqpphfifowrenableout, wire_transmit_pcs0_iqpphfifowrenableout},
+ int_tx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_tx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_tx_iqpphfifoxnrdclk = {{3{{2{1'b0}}}}, int_tx_iqpphfifordclkout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_tx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_tx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
+ int_tx_phfifioxnptrsreset = {1'b0, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], 1'b0, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
+ int_tx_phfiforddisableout = {wire_transmit_pcs7_phfiforddisableout, wire_transmit_pcs6_phfiforddisableout, wire_transmit_pcs5_phfiforddisableout, wire_transmit_pcs4_phfiforddisableout, wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs7_phfiforesetout, wire_transmit_pcs6_phfiforesetout, wire_transmit_pcs5_phfiforesetout, wire_transmit_pcs4_phfiforesetout, wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs7_phfifowrenableout, wire_transmit_pcs6_phfifowrenableout, wire_transmit_pcs5_phfifowrenableout, wire_transmit_pcs4_phfifowrenableout, wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {1'b0, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], 1'b0, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdclk = {1'b0, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], 1'b0, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdenable = {1'b0, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], 1'b0, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
+ int_tx_phfifoxnwrenable = {1'b0, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], 1'b0, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
+ int_txcoreclk = {1'b0, int_tx_coreclkout[0]},
+ int_txphfiforddisable = {1'b0, int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {1'b0, int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {1'b0, int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit1_txphfifox4byteselout, wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit1_txphfifox4rdclkout, wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit1_txphfifox4rdenableout, wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit1_txphfifox4wrenableout, wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk1_nonusertocmu, wire_cal_blk0_nonusertocmu},
+ nonusertocmu_out_pll = {wire_pll_cal_blk0_nonusertocmu},
+ pcie_sw_wire = {wire_cent_unit1_digitaltestout[2], wire_cent_unit0_digitaltestout[2]},
+ pipedatavalid = {pipedatavalid_out[7:0]},
+ pipedatavalid_out = {wire_receive_pcs7_pipedatavalid, wire_receive_pcs6_pipedatavalid, wire_receive_pcs5_pipedatavalid, wire_receive_pcs4_pipedatavalid, wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
+ pipeelecidle = {pipeelecidle_out[7:0]},
+ pipeelecidle_out = {wire_receive_pcs7_pipeelecidle, wire_receive_pcs6_pipeelecidle, wire_receive_pcs5_pipeelecidle, wire_receive_pcs4_pipeelecidle, wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
+ pipephydonestatus = {wire_receive_pcs7_pipephydonestatus, wire_receive_pcs6_pipephydonestatus, wire_receive_pcs5_pipephydonestatus, wire_receive_pcs4_pipephydonestatus, wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
+ pipestatus = {wire_receive_pcs7_pipestatus, wire_receive_pcs6_pipestatus, wire_receive_pcs5_pipestatus, wire_receive_pcs4_pipestatus, wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll7_dataout, wire_rx_cdr_pll6_dataout, wire_rx_cdr_pll5_dataout, wire_rx_cdr_pll4_dataout, wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll7_dprioout, wire_rx_cdr_pll6_dprioout, wire_rx_cdr_pll5_dprioout, wire_rx_cdr_pll4_dprioout, wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {{600{1'b0}}, pll_ch_dprioout[2399:1200], {600{1'b0}}, pll_ch_dprioout[1199:0]},
+ pll_edge_locked_out = {wire_atx_pll0_locked},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_edge_locked_out[0]},
+ pll_powerdown = 1'b0,
+ reconfig_fromgxb = {rx_pma_analogtestbus[33:18], wire_cent_unit1_dprioout, rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ refclk_pma = {wire_central_clk_div1_refclkout, wire_central_clk_div0_refclkout},
+ refclk_pma_wire = {wire_atx_clk_div0_refclkout},
+ rx_analogreset_in = {{4{1'b0}}, {8{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
+ rx_analogreset_out = {wire_cent_unit1_rxanalogresetout[5:0], wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_coreclk_in = {8{coreclkout_bi_quad_wire[0]}},
+ rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[7], {9{1'b0}}, rx_pldcruclk_in[6], {9{1'b0}}, rx_pldcruclk_in[5], {9{1'b0}}, rx_pldcruclk_in[4], {9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs7_ctrldetect[1:0], wire_receive_pcs6_ctrldetect[1:0], wire_receive_pcs5_ctrldetect[1:0], wire_receive_pcs4_ctrldetect[1:0], wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[127:0]},
+ rx_deserclock_in = {rx_pll_clkout[31:0]},
+ rx_digitalreset_in = {8{int_rx_digitalreset_reg[0]}},
+ rx_digitalreset_out = {wire_cent_unit1_rxdigitalresetout[3:0], wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_elecidleinfersel = {24{1'b0}},
+ rx_enapatternalign = {8{1'b0}},
+ rx_freqlocked = {(rx_freqlocked_wire[7] & (~ rx_analogreset[0])), (rx_freqlocked_wire[6] & (~ rx_analogreset[0])), (rx_freqlocked_wire[5] & (~ rx_analogreset[0])), (rx_freqlocked_wire[4] & (~ rx_analogreset[0])), (rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_freqlocked_wire = {wire_rx_cdr_pll7_freqlocked, wire_rx_cdr_pll6_freqlocked, wire_rx_cdr_pll5_freqlocked, wire_rx_cdr_pll4_freqlocked, wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata = {8{1'b0}},
+ rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[7]), ((~ reconfig_togxb_busy) & rx_locktodata[6]), ((~ reconfig_togxb_busy) & rx_locktodata[5]), ((~ reconfig_togxb_busy) & rx_locktodata[4]), ((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
+ rx_locktorefclk_wire = {wire_receive_pcs7_cdrctrllocktorefclkout, wire_receive_pcs6_cdrctrllocktorefclkout, wire_receive_pcs5_cdrctrllocktorefclkout, wire_receive_pcs4_cdrctrllocktorefclkout, wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_out_wire = {wire_receive_pcs7_dataout[15:0], wire_receive_pcs6_dataout[15:0], wire_receive_pcs5_dataout[15:0], wire_receive_pcs4_dataout[15:0], wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs7_patterndetect[1:0], wire_receive_pcs6_patterndetect[1:0], wire_receive_pcs5_patterndetect[1:0], wire_receive_pcs4_patterndetect[1:0], wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcs_rxfound_wire = {txdetectrxout[7], tx_rxfoundout[7], txdetectrxout[6], tx_rxfoundout[6], txdetectrxout[5], tx_rxfoundout[5], txdetectrxout[4], tx_rxfoundout[4], txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
+ rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[3199:0]},
+ rx_pcsdprioout = {wire_receive_pcs7_dprioout, wire_receive_pcs6_dprioout, wire_receive_pcs5_dprioout, wire_receive_pcs4_dprioout, wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
+ rx_phfifordenable = {8{1'b1}},
+ rx_phfiforeset = {8{1'b0}},
+ rx_phfifowrdisable = {8{1'b0}},
+ rx_pipestatetransdoneout = {wire_receive_pcs7_pipestatetransdoneout, wire_receive_pcs6_pipestatetransdoneout, wire_receive_pcs5_pipestatetransdoneout, wire_receive_pcs4_pipestatetransdoneout, wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
+ rx_pldcruclk_in = {rx_cruclk[7:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll7_clk, wire_rx_cdr_pll6_clk, wire_rx_cdr_pll5_clk, wire_rx_cdr_pll4_clk, wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {(rx_plllocked_wire[7] & (~ rx_analogreset[0])), (rx_plllocked_wire[6] & (~ rx_analogreset[0])), (rx_plllocked_wire[5] & (~ rx_analogreset[0])), (rx_plllocked_wire[4] & (~ rx_analogreset[0])), (rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll7_pfdrefclkout, wire_rx_cdr_pll6_pfdrefclkout, wire_rx_cdr_pll5_pfdrefclkout, wire_rx_cdr_pll4_pfdrefclkout, wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll7_locked, wire_rx_cdr_pll6_locked, wire_rx_cdr_pll5_locked, wire_rx_cdr_pll4_locked, wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_analogtestbus = {{102{1'b0}}, wire_receive_pma7_analogtestbus[5:2], wire_receive_pma6_analogtestbus[5:2], wire_receive_pma5_analogtestbus[5:2], wire_receive_pma4_analogtestbus[5:2], 1'b0, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
+ rx_pma_clockout = {wire_receive_pma7_clockout, wire_receive_pma6_clockout, wire_receive_pma5_clockout, wire_receive_pma4_clockout, wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma7_dataout, wire_receive_pma6_dataout, wire_receive_pma5_dataout, wire_receive_pma4_dataout, wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma7_locktorefout, wire_receive_pma6_locktorefout, wire_receive_pma5_locktorefout, wire_receive_pma4_locktorefout, wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma7_recoverdataout[19:0], wire_receive_pma6_recoverdataout[19:0], wire_receive_pma5_recoverdataout[19:0], wire_receive_pma4_recoverdataout[19:0], wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
+ rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma7_dprioout, wire_receive_pma6_dprioout, wire_receive_pma5_dprioout, wire_receive_pma4_dprioout, {2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
+ rx_powerdown = {8{1'b0}},
+ rx_powerdown_in = {{4{1'b0}}, rx_powerdown[7:0]},
+ rx_prbscidenable = {8{1'b0}},
+ rx_revparallelfdbkdata = {wire_receive_pcs7_revparallelfdbkdata, wire_receive_pcs6_revparallelfdbkdata, wire_receive_pcs5_revparallelfdbkdata, wire_receive_pcs4_revparallelfdbkdata, wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
+ rx_rmfiforeset = {8{1'b0}},
+ rx_rxcruresetout = {wire_cent_unit1_rxcruresetout[5:0], wire_cent_unit0_rxcruresetout[5:0]},
+ rx_signaldetect_wire = {wire_receive_pma7_signaldetect, wire_receive_pma6_signaldetect, wire_receive_pma5_signaldetect, wire_receive_pma4_signaldetect, wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
+ rx_syncstatus = {wire_receive_pcs7_syncstatus[1:0], wire_receive_pcs6_syncstatus[1:0], wire_receive_pcs5_syncstatus[1:0], wire_receive_pcs4_syncstatus[1:0], wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
+ rxphfifowrdisable = {1'b0, int_rx_phfifowrdisableout[0]},
+ rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
+ tx_analogreset_out = {wire_cent_unit1_txanalogresetout[5:0], wire_cent_unit0_txanalogresetout[5:0]},
+ tx_coreclk_in = {8{coreclkout_bi_quad_wire[0]}},
+ tx_datain_wire = {tx_datain[127:0]},
+ tx_dataout = {wire_transmit_pma7_dataout, wire_transmit_pma6_dataout, wire_transmit_pma5_dataout, wire_transmit_pma4_dataout, wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs7_dataout, wire_transmit_pcs6_dataout, wire_transmit_pcs5_dataout, wire_transmit_pcs4_dataout, wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {8{int_tx_digitalreset_reg[0]}},
+ tx_digitalreset_out = {wire_cent_unit1_txdigitalresetout[3:0], wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_dprioin_wire = {{1200{1'b0}}, cent_unit_txdprioout[1199:0]},
+ tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[7], 1'b0, tx_forcedispcompliance[6], 1'b0, tx_forcedispcompliance[5], 1'b0, tx_forcedispcompliance[4], 1'b0, tx_forcedispcompliance[3], 1'b0, tx_forcedispcompliance[2], 1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
+ tx_invpolarity = {8{1'b0}},
+ tx_localrefclk = {wire_transmit_pma7_clockout, wire_transmit_pma6_clockout, wire_transmit_pma5_clockout, wire_transmit_pma4_clockout, wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_pcs_forceelecidleout = {wire_transmit_pcs7_forceelecidleout, wire_transmit_pcs6_forceelecidleout, wire_transmit_pcs5_forceelecidleout, wire_transmit_pcs4_forceelecidleout, wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
+ tx_phfiforeset = {8{1'b0}},
+ tx_pipepowerdownout = {wire_transmit_pcs7_pipepowerdownout, wire_transmit_pcs6_pipepowerdownout, wire_transmit_pcs5_pipepowerdownout, wire_transmit_pcs4_pipepowerdownout, wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
+ tx_pipepowerstateout = {wire_transmit_pcs7_pipepowerstateout, wire_transmit_pcs6_pipepowerstateout, wire_transmit_pcs5_pipepowerstateout, wire_transmit_pcs4_pipepowerstateout, wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
+ tx_pipeswing = {8{1'b0}},
+ tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
+ tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma7_dprioout, wire_transmit_pma6_dprioout, wire_transmit_pma5_dprioout, wire_transmit_pma4_dprioout, {2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
+ tx_revparallellpbken = {8{1'b0}},
+ tx_rxdetectvalidout = {wire_transmit_pma7_rxdetectvalidout, wire_transmit_pma6_rxdetectvalidout, wire_transmit_pma5_rxdetectvalidout, wire_transmit_pma4_rxdetectvalidout, wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
+ tx_rxfoundout = {wire_transmit_pma7_rxfoundout, wire_transmit_pma6_rxfoundout, wire_transmit_pma5_rxfoundout, wire_transmit_pma4_rxfoundout, wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
+ tx_txdprioout = {wire_transmit_pcs7_dprioout, wire_transmit_pcs6_dprioout, wire_transmit_pcs5_dprioout, wire_transmit_pcs4_dprioout, wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
+ txdetectrxout = {wire_transmit_pcs7_txdetectrx, wire_transmit_pcs6_txdetectrx, wire_transmit_pcs5_txdetectrx, wire_transmit_pcs4_txdetectrx, wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit1_dpriodisableout, wire_cent_unit0_dpriodisableout};
+endmodule //altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_nuda
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcie_serdes_4sgx_x8d_gen2_08p (
+ cal_blk_clk,
+ gxb_powerdown,
+ pipe8b10binvpolarity,
+ pll_inclk,
+ powerdn,
+ rateswitch,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ tx_ctrlenable,
+ tx_datain,
+ tx_detectrxloop,
+ tx_digitalreset,
+ tx_forcedispcompliance,
+ tx_forceelecidle,
+ tx_pipedeemph,
+ tx_pipemargin,
+ coreclkout,
+ pipedatavalid,
+ pipeelecidle,
+ pipephydonestatus,
+ pipestatus,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_pll_locked,
+ rx_syncstatus,
+ tx_dataout)/* synthesis synthesis_clearbox = 2 */;
+
+ input cal_blk_clk;
+ input [0:0] gxb_powerdown;
+ input [7:0] pipe8b10binvpolarity;
+ input pll_inclk;
+ input [15:0] powerdn;
+ input [0:0] rateswitch;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ input [7:0] rx_cruclk;
+ input [7:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [15:0] tx_ctrlenable;
+ input [127:0] tx_datain;
+ input [7:0] tx_detectrxloop;
+ input [0:0] tx_digitalreset;
+ input [7:0] tx_forcedispcompliance;
+ input [7:0] tx_forceelecidle;
+ input [7:0] tx_pipedeemph;
+ input [23:0] tx_pipemargin;
+ output [0:0] coreclkout;
+ output [7:0] pipedatavalid;
+ output [7:0] pipeelecidle;
+ output [7:0] pipephydonestatus;
+ output [23:0] pipestatus;
+ output [0:0] pll_locked;
+ output [33:0] reconfig_fromgxb;
+ output [15:0] rx_ctrldetect;
+ output [127:0] rx_dataout;
+ output [7:0] rx_freqlocked;
+ output [15:0] rx_patterndetect;
+ output [7:0] rx_pll_locked;
+ output [15:0] rx_syncstatus;
+ output [7:0] tx_dataout;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [7:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+
+
+ wire [15:0] sub_wire0;
+ wire [7:0] sub_wire1;
+ wire [0:0] sub_wire2;
+ wire [33:0] sub_wire3;
+ wire [7:0] sub_wire4;
+ wire [23:0] sub_wire5;
+ wire [7:0] sub_wire6;
+ wire [15:0] sub_wire7;
+ wire [0:0] sub_wire8;
+ wire [127:0] sub_wire9;
+ wire [7:0] sub_wire10;
+ wire [7:0] sub_wire11;
+ wire [15:0] sub_wire12;
+ wire [7:0] sub_wire13;
+ wire [15:0] rx_patterndetect = sub_wire0[15:0];
+ wire [7:0] pipephydonestatus = sub_wire1[7:0];
+ wire [0:0] pll_locked = sub_wire2[0:0];
+ wire [33:0] reconfig_fromgxb = sub_wire3[33:0];
+ wire [7:0] rx_freqlocked = sub_wire4[7:0];
+ wire [23:0] pipestatus = sub_wire5[23:0];
+ wire [7:0] rx_pll_locked = sub_wire6[7:0];
+ wire [15:0] rx_syncstatus = sub_wire7[15:0];
+ wire [0:0] coreclkout = sub_wire8[0:0];
+ wire [127:0] rx_dataout = sub_wire9[127:0];
+ wire [7:0] pipeelecidle = sub_wire10[7:0];
+ wire [7:0] tx_dataout = sub_wire11[7:0];
+ wire [15:0] rx_ctrldetect = sub_wire12[15:0];
+ wire [7:0] pipedatavalid = sub_wire13[7:0];
+
+ altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_nuda altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_nuda_component (
+ .reconfig_togxb (reconfig_togxb),
+ .cal_blk_clk (cal_blk_clk),
+ .tx_forceelecidle (tx_forceelecidle),
+ .rx_datain (rx_datain),
+ .rx_digitalreset (rx_digitalreset),
+ .pipe8b10binvpolarity (pipe8b10binvpolarity),
+ .tx_datain (tx_datain),
+ .tx_digitalreset (tx_digitalreset),
+ .tx_pipedeemph (tx_pipedeemph),
+ .gxb_powerdown (gxb_powerdown),
+ .rx_cruclk (rx_cruclk),
+ .tx_forcedispcompliance (tx_forcedispcompliance),
+ .rateswitch (rateswitch),
+ .reconfig_clk (reconfig_clk),
+ .rx_analogreset (rx_analogreset),
+ .powerdn (powerdn),
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_pipemargin (tx_pipemargin),
+ .pll_inclk (pll_inclk),
+ .tx_detectrxloop (tx_detectrxloop),
+ .rx_patterndetect (sub_wire0),
+ .pipephydonestatus (sub_wire1),
+ .pll_locked (sub_wire2),
+ .reconfig_fromgxb (sub_wire3),
+ .rx_freqlocked (sub_wire4),
+ .pipestatus (sub_wire5),
+ .rx_pll_locked (sub_wire6),
+ .rx_syncstatus (sub_wire7),
+ .coreclkout (sub_wire8),
+ .rx_dataout (sub_wire9),
+ .pipeelecidle (sub_wire10),
+ .tx_dataout (sub_wire11),
+ .rx_ctrldetect (sub_wire12),
+ .pipedatavalid (sub_wire13))/* synthesis synthesis_clearbox=2
+ clearbox_macroname = alt4gxb
+ clearbox_defparam = "effective_data_rate=5000 Mbps;enable_lc_tx_pll=true;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gxb_analog_power=3.0v;gx_channel_type=AUTO;input_clock_frequency=100.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=none;lpm_type=alt4gxb;number_of_channels=8;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;protocol=pcie2;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=x8;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_bandwidth_type=Auto;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=5000;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;
+ rx_use_clkout=false;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=true;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_bonding=x8;tx_channel_width=16;tx_clkout_width=8;tx_common_mode=0.65v;tx_data_rate=5000;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=10000;tx_pll_type=ATX;tx_slew_rate=off;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=true;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=3;coreclkout_control_width=1;elec_idle_infer_enable=false;enable_0ppm=false;gxb_powerdown_width=1;number_of_quads=2;rateswitch_control_width=1;reconfig_calibration=true;reconfig_fromgxb_port_width=34;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_cru_m_divider=25;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=1;rx_dwidth_factor=2;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=2;tx_pll_clock_post_divider=1;tx_pll_m_divider=25;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=1;tx_use_external_termination=false;" */;
+ defparam
+ altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_nuda_component.starting_channel_number = starting_channel_number;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "5000.0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "5000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "5000"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 2-x8"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "5000 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "true"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "3.0v"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "pcie2"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x8"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "5000"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x8"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "5000"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "ATX"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
+// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
+// Retrieval info: CONSTANT: enable_0ppm STRING "false"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "2"
+// Retrieval info: CONSTANT: rateswitch_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "34"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 8 0 INPUT NODEFVAL "pipe8b10binvpolarity[7..0]"
+// Retrieval info: USED_PORT: pipedatavalid 0 0 8 0 OUTPUT NODEFVAL "pipedatavalid[7..0]"
+// Retrieval info: USED_PORT: pipeelecidle 0 0 8 0 OUTPUT NODEFVAL "pipeelecidle[7..0]"
+// Retrieval info: USED_PORT: pipephydonestatus 0 0 8 0 OUTPUT NODEFVAL "pipephydonestatus[7..0]"
+// Retrieval info: USED_PORT: pipestatus 0 0 24 0 OUTPUT NODEFVAL "pipestatus[23..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: powerdn 0 0 16 0 INPUT NODEFVAL "powerdn[15..0]"
+// Retrieval info: USED_PORT: rateswitch 0 0 1 0 INPUT NODEFVAL "rateswitch[0..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 34 0 OUTPUT NODEFVAL "reconfig_fromgxb[33..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 8 0 INPUT GND "rx_cruclk[7..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 16 0 OUTPUT NODEFVAL "rx_ctrldetect[15..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 8 0 INPUT NODEFVAL "rx_datain[7..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 128 0 OUTPUT NODEFVAL "rx_dataout[127..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 8 0 OUTPUT NODEFVAL "rx_freqlocked[7..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 16 0 OUTPUT NODEFVAL "rx_patterndetect[15..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 8 0 OUTPUT NODEFVAL "rx_pll_locked[7..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 16 0 OUTPUT NODEFVAL "rx_syncstatus[15..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 16 0 INPUT NODEFVAL "tx_ctrlenable[15..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 128 0 INPUT NODEFVAL "tx_datain[127..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 8 0 OUTPUT NODEFVAL "tx_dataout[7..0]"
+// Retrieval info: USED_PORT: tx_detectrxloop 0 0 8 0 INPUT NODEFVAL "tx_detectrxloop[7..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 8 0 INPUT NODEFVAL "tx_forcedispcompliance[7..0]"
+// Retrieval info: USED_PORT: tx_forceelecidle 0 0 8 0 INPUT NODEFVAL "tx_forceelecidle[7..0]"
+// Retrieval info: USED_PORT: tx_pipedeemph 0 0 8 0 INPUT NODEFVAL "tx_pipedeemph[7..0]"
+// Retrieval info: USED_PORT: tx_pipemargin 0 0 24 0 INPUT NODEFVAL "tx_pipemargin[23..0]"
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 8 0 pipe8b10binvpolarity 0 0 8 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @powerdn 0 0 16 0 powerdn 0 0 16 0
+// Retrieval info: CONNECT: @rateswitch 0 0 1 0 rateswitch 0 0 1 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 8 0 rx_cruclk 0 0 8 0
+// Retrieval info: CONNECT: @rx_datain 0 0 8 0 rx_datain 0 0 8 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 16 0 tx_ctrlenable 0 0 16 0
+// Retrieval info: CONNECT: @tx_datain 0 0 128 0 tx_datain 0 0 128 0
+// Retrieval info: CONNECT: @tx_detectrxloop 0 0 8 0 tx_detectrxloop 0 0 8 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 8 0 tx_forcedispcompliance 0 0 8 0
+// Retrieval info: CONNECT: @tx_forceelecidle 0 0 8 0 tx_forceelecidle 0 0 8 0
+// Retrieval info: CONNECT: @tx_pipedeemph 0 0 8 0 tx_pipedeemph 0 0 8 0
+// Retrieval info: CONNECT: @tx_pipemargin 0 0 24 0 tx_pipemargin 0 0 24 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: pipedatavalid 0 0 8 0 @pipedatavalid 0 0 8 0
+// Retrieval info: CONNECT: pipeelecidle 0 0 8 0 @pipeelecidle 0 0 8 0
+// Retrieval info: CONNECT: pipephydonestatus 0 0 8 0 @pipephydonestatus 0 0 8 0
+// Retrieval info: CONNECT: pipestatus 0 0 24 0 @pipestatus 0 0 24 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 34 0 @reconfig_fromgxb 0 0 34 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 16 0 @rx_ctrldetect 0 0 16 0
+// Retrieval info: CONNECT: rx_dataout 0 0 128 0 @rx_dataout 0 0 128 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 8 0 @rx_freqlocked 0 0 8 0
+// Retrieval info: CONNECT: rx_patterndetect 0 0 16 0 @rx_patterndetect 0 0 16 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 8 0 @rx_pll_locked 0 0 8 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 16 0 @rx_syncstatus 0 0 16 0
+// Retrieval info: CONNECT: tx_dataout 0 0 8 0 @tx_dataout 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p_bb.v TRUE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v b/ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v
new file mode 100644
index 0000000000000000000000000000000000000000..3ca68ac95f68931a984a571092f214f71e048efc
--- /dev/null
+++ b/ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v
@@ -0,0 +1,336 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: altpcierd_reconfig_clk_pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+//
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.1 Internal Build 132 10/11/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altpcierd_reconfig_clk_pll (
+ inclk0,
+ c0,
+ c1,
+ locked);
+
+ input inclk0;
+ output c0;
+ output c1;
+ output locked;
+
+ wire [9:0] sub_wire0;
+ wire sub_wire2;
+ wire [0:0] sub_wire6 = 1'h0;
+ wire [0:0] sub_wire3 = sub_wire0[0:0];
+ wire [1:1] sub_wire1 = sub_wire0[1:1];
+ wire c1 = sub_wire1;
+ wire locked = sub_wire2;
+ wire c0 = sub_wire3;
+ wire sub_wire4 = inclk0;
+ wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+ altpll altpll_component (
+ .inclk (sub_wire5),
+ .clk (sub_wire0),
+ .locked (sub_wire2),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 2,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 4,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 5,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 10000,
+ altpll_component.intended_device_family = "Stratix IV",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altpcierd_reconfig_clk_pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_fbout = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clk6 = "PORT_UNUSED",
+ altpll_component.port_clk7 = "PORT_UNUSED",
+ altpll_component.port_clk8 = "PORT_UNUSED",
+ altpll_component.port_clk9 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.self_reset_on_loss_lock = "OFF",
+ altpll_component.using_fbmimicbidir_port = "OFF",
+ altpll_component.width_clock = 10;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_reconfig_clk_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
+// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_reconfig_clk_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_reconfig_clk_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_reconfig_clk_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_reconfig_clk_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_reconfig_clk_pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_reconfig_clk_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL altpcierd_reconfig_clk_pll_bb.v FALSE
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp b/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp
new file mode 100644
index 0000000000000000000000000000000000000000..7c6199b88b9757e7bd2afcc0e4ed002c6246edae
Binary files /dev/null and b/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp differ
diff --git a/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp b/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp
new file mode 100644
index 0000000000000000000000000000000000000000..50800a37083a10c93df1468e2e2d00c406356b54
Binary files /dev/null and b/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp differ
diff --git a/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp b/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp
new file mode 100644
index 0000000000000000000000000000000000000000..b7612cb9dc9c3022efde20dff8e6688a6645f4be
Binary files /dev/null and b/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp differ
diff --git a/ip_compiler_for_pci_express-library/pciexp64_dlink.v b/ip_compiler_for_pci_express-library/pciexp64_dlink.v
new file mode 100644
index 0000000000000000000000000000000000000000..5d1e77af915715f55ea7867861389714564cc17f
Binary files /dev/null and b/ip_compiler_for_pci_express-library/pciexp64_dlink.v differ
diff --git a/ip_compiler_for_pci_express-library/pciexp64_trans.v b/ip_compiler_for_pci_express-library/pciexp64_trans.v
new file mode 100644
index 0000000000000000000000000000000000000000..c9f3e76da208e882db14c7219a7c87410418aa2d
Binary files /dev/null and b/ip_compiler_for_pci_express-library/pciexp64_trans.v differ
diff --git a/ip_compiler_for_pci_express-library/pciexp_dcram.v b/ip_compiler_for_pci_express-library/pciexp_dcram.v
new file mode 100644
index 0000000000000000000000000000000000000000..def0ff4d5b1ffb2c403c47d76aff988ab422fa10
Binary files /dev/null and b/ip_compiler_for_pci_express-library/pciexp_dcram.v differ
diff --git a/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v b/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v
new file mode 100644
index 0000000000000000000000000000000000000000..8cb8cdd8d6bde6919c634f332f3044afa3f38a3e
Binary files /dev/null and b/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v differ
diff --git a/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp b/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp
new file mode 100644
index 0000000000000000000000000000000000000000..61c556643d9807c4fa36eb8b9d3da1b2a8812296
Binary files /dev/null and b/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp differ
diff --git a/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp b/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp
new file mode 100644
index 0000000000000000000000000000000000000000..073be79a26e0b1b396ce582193e9b1ad17df3c8a
Binary files /dev/null and b/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp differ