Issues · Projects / VME FMC Carrier VFC · Open Hardware Repository

TTLBunchClk and TTLTClk signals on the P0 are forced as input for the carrier.

#36 · opened Oct 20, 2010 by Andrea Boccardi feature
- CLOSED
- 2
updated Feb 12, 2019
Name inversion between the control signals of the P0 HWHIGHBYTE and HWLOWBYTE

#35 · opened Oct 20, 2010 by Andrea Boccardi feature
- CLOSED
- 1
updated Feb 12, 2019
Missing connection to control the output enable of the VMEP0_LVDSTCLK and VMEP0_LVDSBUNCHCLK

#34 · opened Oct 20, 2010 by Andrea Boccardi bug
- CLOSED
- 2
updated Feb 12, 2019
Inverted polarity of DDS_OUT LVDS signal

#33 · opened Oct 20, 2010 by Andrea Boccardi bug
- CLOSED
- 1
updated Feb 12, 2019
Design out RAKON IVT3205CR 25.0 MHz as too difficult to obtain.

#32 · opened Nov 02, 2010 by Erik van der Bij bug
- CLOSED
- 2
updated Feb 12, 2019
NUMONYX M25P128-VMF6G difficult to find

#31 · opened Nov 02, 2010 by Erik van der Bij bug
- CLOSED
- 1
updated Feb 12, 2019
Do not mount PT6914 and PT6915 negative supplies

#30 · opened Nov 16, 2010 by Erik van der Bij feature
- CLOSED
- 2
updated Feb 12, 2019
Add configuration jumpers to SFPGA's HSWAPEN

#28 · opened Feb 11, 2011 by Pablo Alvarez bug
- CLOSED
- 1
updated Feb 12, 2019
A 100nF on the Vref of the AD5666 would improve the reference stability

#27 · opened Feb 15, 2011 by Andrea Boccardi bug
- CLOSED
- 1
updated Feb 12, 2019
1-wire chip package should be changed

#26 · opened Mar 15, 2011 by Andrea Boccardi feature
- CLOSED
- 2
updated Feb 12, 2019
Difficulties in soldering the FMC connectors

#25 · opened Mar 25, 2011 by Andrea Boccardi bug
- CLOSED
- 1
updated Feb 12, 2019
place pull ups and down on the pin modes of the S-FPGA

#24 · opened Jun 06, 2011 by Andrea Boccardi bug
- CLOSED
- 0
updated Feb 12, 2019
AC couple the SFP

#23 · opened Jun 06, 2011 by Andrea Boccardi bug
- CLOSED
- 1
updated Feb 12, 2019
Place the VME-ADDR buffers by default in BUS to Carrier direction

#22 · opened Jun 06, 2011 by Andrea Boccardi bug
- CLOSED
- 0
updated Feb 12, 2019
Replace the on off indication (serigraphy) on the manual address switch with 1 and 0

#21 · opened Jun 06, 2011 by Andrea Boccardi bug
- CLOSED
- 0
updated Feb 12, 2019
Foresee the possibility to have the BST signals (2 bytes) and clocks either from the P0 or from the S-FPGA (jumpers?)

#20 · opened Jun 06, 2011 by Andrea Boccardi feature
- CLOSED
- 1
updated Feb 12, 2019
Add a CDR chip optionally connected (AC coupling switch) to one of the 2 SFP

#19 · opened Jun 06, 2011 by Andrea Boccardi bug
- CLOSED
- 1
updated Feb 12, 2019
Missing RZQ calibration resistor for DDR termination

#18 · opened Jun 07, 2011 by Projects bug
- CLOSED
- 1
updated Feb 12, 2019
Connect ddr3 address pin 14

#17 · opened Jun 07, 2011 by Projects feature
- CLOSED
- 1
updated Feb 12, 2019
P2 user defined connections

#15 · opened Jun 14, 2011 by Andrea Boccardi bug
- CLOSED
- 1
updated Feb 12, 2019