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VME FMC Carrier VFC
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  • VME FMC Carrier VFC
  • Issues

  • Open 6
  • Closed 30
  • All 36
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  • Priority Created date Last updated Milestone Due date Popularity Label priority
  • V2-0: Front-panel BOM wrong
    #1 · opened Dec 12, 2012 by Erik van der Bij   bug
    • 0
    updated Feb 12, 2019
  • Design files in Repository old
    #2 · opened Jun 01, 2012 by Erik van der Bij   support
    • 0
    updated Feb 12, 2019
  • VMEPX_DS lines swaped on vme connector
    #3 · opened Jun 28, 2011 by Pablo Alvarez   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • DDS not debugged
    #4 · opened Jun 24, 2011 by Erik van der Bij   feature
    • CLOSED
    • 1
    updated Feb 12, 2019
  • DDR3 access problems
    #5 · opened Jun 24, 2011 by Erik van der Bij   bug
    • 0
    updated Feb 12, 2019
  • VME 2eSST cycles not proven to work
    #6 · opened Jun 24, 2011 by Erik van der Bij   feature
    • 0
    updated Feb 12, 2019
  • Solve JTAG problems
    #7 · opened Jun 24, 2011 by Projects   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • Unreliable PTH04T230W soldering
    #8 · opened Jun 23, 2011 by Projects   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • Follow PCB layout guidelines for DDR3 routing.
    #9 · opened Jun 22, 2011 by Projects   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • Review inter-FPGA GTP clocking
    #10 · opened Jun 22, 2011 by Projects   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • Programming the system FPGA crashes/reboots the MEN-A20
    #11 · opened Jun 21, 2011 by Projects   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • Oscillators for WR
    #12 · opened Jun 17, 2011 by Tomasz Wlostowski   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • PLL oscillators
    #13 · opened Jun 17, 2011 by Tomasz Wlostowski   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • [CRITICAL] Tx/Rx pairs swapped in SFP1 and SFP2
    #14 · opened Jun 17, 2011 by Tomasz Wlostowski   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • P2 user defined connections
    #15 · opened Jun 14, 2011 by Andrea Boccardi   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • eSATA connector
    #16 · opened Jun 14, 2011 by Andrea Boccardi   feature
    • 0
    updated Feb 12, 2019
  • Connect ddr3 address pin 14
    #17 · opened Jun 07, 2011 by Projects   feature
    • CLOSED
    • 1
    updated Feb 12, 2019
  • Missing RZQ calibration resistor for DDR termination
    #18 · opened Jun 07, 2011 by Projects   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • Add a CDR chip optionally connected (AC coupling switch) to one of the 2 SFP
    #19 · opened Jun 06, 2011 by Andrea Boccardi   bug
    • CLOSED
    • 1
    updated Feb 12, 2019
  • Foresee the possibility to have the BST signals (2 bytes) and clocks either from the P0 or from the S-FPGA (jumpers?)
    #20 · opened Jun 06, 2011 by Andrea Boccardi   feature
    • CLOSED
    • 1
    updated Feb 12, 2019
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