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VME FMC Carrier VFC
Commits
f7146861
Commit
f7146861
authored
Jan 28, 2011
by
Andrea Boccardi
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parent
0b0fcfdb
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2 changed files
with
12 additions
and
12 deletions
+12
-12
SystemFpga.v
trunk/hdl/design/SystemFpga.v
+2
-2
VmeToWishBone.v
trunk/hdl/design/VmeToWishBone.v
+10
-10
No files found.
trunk/hdl/design/SystemFpga.v
View file @
f7146861
...
...
@@ -433,8 +433,8 @@ assign FpGpIo34OutputMode_o = 1'b1;
// Clock
//####################################
assign
Clk_k
=
Si57x_ik
;
//
assign Clk_k= VcTcXo_ik;
//
assign Clk_k= Si57x_ik;
assign
Clk_k
=
VcTcXo_ik
;
//#####################################
...
...
trunk/hdl/design/VmeToWishBone.v
View file @
f7146861
...
...
@@ -76,7 +76,7 @@ end
// State Machine
reg
[
29
:
0
]
TimoutCounter_cb30
;
reg
[
7
:
0
]
TimeoutCounter_cb8
;
reg
[
1
:
0
]
State_q
,
NextState_a
;
localparam
s_Idle
=
2'b00
,
...
...
@@ -93,11 +93,11 @@ always @* begin
if
(
VmeRWAccess_a
)
NextState_a
=
VmeWr_in
?
s_Read
:
s_Write
;
else
if
(
VmeIntAckAccess_a
)
NextState_a
=
s_IntAck
;
s_Write:
if
((
~
Ack_i
&&
~
Stb_oq
&&
~
VmeRWAccess_a
)
||
&
TimoutCounter_cb30
)
NextState_a
=
s_Idle
;
if
((
~
Ack_i
&&
~
Stb_oq
&&
~
VmeRWAccess_a
)
||
&
TimeoutCounter_cb8
)
NextState_a
=
s_Idle
;
s_Read:
if
((
~
Ack_i
&&
~
Stb_oq
&&
~
VmeRWAccess_a
)
||
&
TimoutCounter_cb30
)
NextState_a
=
s_Idle
;
if
((
~
Ack_i
&&
~
Stb_oq
&&
~
VmeRWAccess_a
)
||
&
TimeoutCounter_cb8
)
NextState_a
=
s_Idle
;
s_IntAck:
if
((
a_Ds1_q
&&
a_IAckIn_q
)
||
&
TimoutCounter_cb30
)
NextState_a
=
s_Idle
;
if
((
a_Ds1_q
&&
a_IAckIn_q
)
||
&
TimeoutCounter_cb8
)
NextState_a
=
s_Idle
;
default:
NextState_a
=
s_Idle
;
endcase
...
...
@@ -122,10 +122,10 @@ always @(posedge Clk_ik) begin
VmeDataDir_oq
<=
1'b0
;
ClearInt_op
<=
1'b0
;
VmeIAckOutn_oqn
<=
1'b1
;
TimoutCounter_cb30
<=
30
'h0
;
TimeoutCounter_cb8
<=
8
'h0
;
end
else
case
(
State_q
)
s_Idle:
begin
TimoutCounter_cb30
<=
30
'h0
;
TimeoutCounter_cb8
<=
8
'h0
;
Adr_obq22
<=
22'h0
;
Dat_obq32
<=
32'h0
;
We_oq
<=
1'b0
;
...
...
@@ -161,7 +161,7 @@ always @(posedge Clk_ik) begin
end
end
s_Write:
begin
TimoutCounter_cb30
<=
TimoutCounter_cb30
+
1'b1
;
TimeoutCounter_cb8
<=
TimeoutCounter_cb8
+
1'b1
;
if
(
Ack_i
)
begin
Stb_oq
<=
1'b0
;
Cyc_oq
<=
1'b0
;
...
...
@@ -170,7 +170,7 @@ always @(posedge Clk_ik) begin
end
end
s_Read:
begin
TimoutCounter_cb30
<=
TimoutCounter_cb30
+
1'b1
;
TimeoutCounter_cb8
<=
TimeoutCounter_cb8
+
1'b1
;
if
(
Ack_i
&&
Stb_oq
)
begin
Stb_oq
<=
1'b0
;
Cyc_oq
<=
1'b0
;
...
...
@@ -181,7 +181,7 @@ always @(posedge Clk_ik) begin
if
(
NextState_a
==
s_Idle
)
VmeDataRegOe
<=
1'b0
;
end
s_IntAck:
begin
TimoutCounter_cb30
<=
TimoutCounter_cb30
+
1'b1
;
TimeoutCounter_cb8
<=
TimeoutCounter_cb8
+
1'b1
;
ClearInt_op
<=
1'b0
;
VmeDataRegOe
<=
1'b1
;
VmeDtAck_oqn
<=
~
VmeDataRegOe
;
...
...
@@ -191,7 +191,7 @@ always @(posedge Clk_ik) begin
end
end
default:
begin
TimoutCounter_cb30
<=
30
'h0
;
TimeoutCounter_cb8
<=
8
'h0
;
Adr_obq22
<=
22'h0
;
Dat_obq32
<=
32'h0
;
We_oq
<=
1'b0
;
...
...
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