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Commit c3d17ad2 authored by Andrea Boccardi's avatar Andrea Boccardi
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Small changes in the files

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trunk/firmware/XilinxISE/SystemFpga/SFpga.bld
View file @ c3d17ad2
Release 12.3 ngdbuild M.70d (nt) Release 12.3 ngdbuild M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3
SFpga.ngd SFpga.ngc SFpga.ngd
Reading NGO file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" ... Reading NGO file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" ...
Gathering constraint information from source properties... Gathering constraint information from source properties...
...@@ -41,10 +41,10 @@ NGDBUILD Design Results Summary: ...@@ -41,10 +41,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 14 Number of warnings: 14
Total memory usage is 88036 kilobytes Total memory usage is 155980 kilobytes
Writing NGD file "SFpga.ngd" ... Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec Total REAL time to NGDBUILD completion: 4 sec
Total CPU time to NGDBUILD completion: 5 sec Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"... Writing NGDBUILD log file "SFpga.bld"...
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log
View file @ c3d17ad2
...@@ -69,3 +69,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -69,3 +69,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.pad
View file @ c3d17ad2
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 10:02:33 2010 Fri Dec 17 11:12:54 2010
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
...@@ -296,7 +296,7 @@ E14||IOBS|IO_L40N_0|UNUSED||0||||||||| ...@@ -296,7 +296,7 @@ E14||IOBS|IO_L40N_0|UNUSED||0|||||||||
E15|||GND|||||||||||| E15|||GND||||||||||||
E16|VmeP0HwLowByteOe_o|IOB|IO_L49N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE| E16|VmeP0HwLowByteOe_o|IOB|IO_L49N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E17|||VCCAUX||||||||2.5|||| E17|||VCCAUX||||||||2.5||||
E18||IOBS|IO_L51N_0|UNUSED||0||||||||| E18|Si57xOe_o|IOB|IO_L51N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E19|||GND|||||||||||| E19|||GND||||||||||||
E20|VmeWrite_in|IOB|IO_L57N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| E20|VmeWrite_in|IOB|IO_L57N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
E21|||VCCO_0|||0|||||3.30|||| E21|||VCCO_0|||0|||||3.30||||
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.par
View file @ c3d17ad2
Release 12.3 par M.70d (nt) Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Fri Dec 17 10:01:26 2010 PCBE13225:: Fri Dec 17 11:12:22 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
...@@ -26,11 +26,11 @@ Slice Logic Utilization: ...@@ -26,11 +26,11 @@ Slice Logic Utilization:
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 941 out of 92,152 1% Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 899 out of 92,152 1% Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 587 Number using O6 output only: 571
Number using O5 output only: 154 Number using O5 output only: 154
Number using O5 and O6: 158 Number using O5 and O6: 166
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -42,17 +42,17 @@ Slice Logic Utilization: ...@@ -42,17 +42,17 @@ Slice Logic Utilization:
Number using O6 output only: 3 Number using O6 output only: 3
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 31 Number used exclusively as route-thrus: 32
Number with same-slice register load: 22 Number with same-slice register load: 23
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 363 out of 23,038 1% Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,084 Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 369 out of 1,084 34% Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 143 out of 1,084 13% Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 572 out of 1,084 52% Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0% to control set restrictions: 0 out of 184,304 0%
...@@ -63,8 +63,8 @@ Slice Logic Distribution: ...@@ -63,8 +63,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
IO Utilization: IO Utilization:
Number of bonded IOBs: 329 out of 396 83% Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 327 out of 329 99% Number of LOCed IOBs: 328 out of 330 99%
IOB Master Pads: 2 IOB Master Pads: 2
IOB Slave Pads: 2 IOB Slave Pads: 2
...@@ -99,8 +99,8 @@ Specific Feature Utilization: ...@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High Overall effort level (-ol): High
Router effort level (-rl): High Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 22 secs Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 22 secs Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
...@@ -152,29 +152,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O ...@@ -152,29 +152,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router Starting Router
Phase 1 : 5204 unrouted; REAL time: 25 secs Phase 1 : 5227 unrouted; REAL time: 12 secs
Phase 2 : 4597 unrouted; REAL time: 31 secs Phase 2 : 4601 unrouted; REAL time: 15 secs
Phase 3 : 1889 unrouted; REAL time: 44 secs Phase 3 : 1750 unrouted; REAL time: 21 secs
Phase 4 : 1889 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 56 secs Phase 4 : 1750 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Updating file: SFpga.ncd with current fully routed design. Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 30 secs
Total REAL time to Router completion: 1 mins 4 secs Total REAL time to Router completion: 30 secs
Total CPU time to Router completion: 1 mins 2 secs Total CPU time to Router completion: 29 secs
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
...@@ -192,18 +192,18 @@ Generating Clock Report ...@@ -192,18 +192,18 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 217 | 0.248 | 1.696 | | Si57x_BUFG | BUFGMUX_X2Y4| No | 229 | 0.260 | 1.710 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.083 | 1.644 | | VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.009 | 1.640 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 | | VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 15 | 0.009 | 1.515 | | SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.186 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 213 | 0.000 | 6.628 | | i_Core/Rst_rq | Local| | 223 | 0.000 | 7.868 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | | |i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.448 | | e/stb_o | Local| | 19 | 0.000 | 4.686 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing * Net Skew is the difference between the minimum and maximum routing
...@@ -220,11 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met. ...@@ -220,11 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score | | Slack | Achievable | Errors | Score
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.399ns| 7.934ns| 0| 0 TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.435ns| 7.898ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.347ns| | 0| 0 20 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 5.459ns| 2.874ns| 0| 0 TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.464ns| 3.869ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.459ns| | 0| 0 lk_ik" 120 MHz HIGH 50% | HOLD | 0.442ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
...@@ -237,10 +237,10 @@ All signals are completely routed. ...@@ -237,10 +237,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 8 secs Total REAL time to PAR completion: 32 secs
Total CPU time to PAR completion: 1 mins 7 secs Total CPU time to PAR completion: 32 secs
Peak Memory Usage: 369 MB Peak Memory Usage: 546 MB
Placer: Placement generated during map. Placer: Placement generated during map.
Routing: Completed - No errors found. Routing: Completed - No errors found.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf
View file @ c3d17ad2
//! ************************************************************************** //! **************************************************************************
// Written by: Map M.70d on Fri Dec 17 10:01:22 2010 // Written by: Map M.70d on Fri Dec 17 11:12:18 2010
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
...@@ -255,6 +255,7 @@ COMP "DdsF_ob2<1>" LOCATE = SITE "A2" LEVEL 1; ...@@ -255,6 +255,7 @@ COMP "DdsF_ob2<1>" LOCATE = SITE "A2" LEVEL 1;
COMP "DdsDrOver_i" LOCATE = SITE "G13" LEVEL 1; COMP "DdsDrOver_i" LOCATE = SITE "G13" LEVEL 1;
COMP "PllFmc2Synch_on" LOCATE = SITE "V12" LEVEL 1; COMP "PllFmc2Synch_on" LOCATE = SITE "V12" LEVEL 1;
COMP "DdsTxEnable_o" LOCATE = SITE "G8" LEVEL 1; COMP "DdsTxEnable_o" LOCATE = SITE "G8" LEVEL 1;
COMP "Si57xOe_o" LOCATE = SITE "E18" LEVEL 1;
COMP "VmeP0BunchSelectDir_o" LOCATE = SITE "G15" LEVEL 1; COMP "VmeP0BunchSelectDir_o" LOCATE = SITE "G15" LEVEL 1;
COMP "VAdjSClk_ok" LOCATE = SITE "J2" LEVEL 1; COMP "VAdjSClk_ok" LOCATE = SITE "J2" LEVEL 1;
COMP "PllDacClrn_orn" LOCATE = SITE "Y21" LEVEL 1; COMP "PllDacClrn_orn" LOCATE = SITE "Y21" LEVEL 1;
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx
View file @ c3d17ad2
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.399" best="7.934" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.347" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="5.459" best="2.874" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.459" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.435" best="7.898" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.464" best="3.869" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.442" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.twx
View file @ c3d17ad2
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes
View file @ c3d17ad2
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 10:02:34 2010 Fri Dec 17 11:12:54 2010
All signals are completely routed. All signals are completely routed.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_envsettings.html
View file @ c3d17ad2
...@@ -15,17 +15,17 @@ ...@@ -15,17 +15,17 @@
</tr> </tr>
<tr> <tr>
<td>PATHEXT</td> <td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr> </tr>
<tr> <tr>
<td>Path</td> <td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
</tr> </tr>
<tr> <tr>
<td>XILINX</td> <td>XILINX</td>
...@@ -35,13 +35,6 @@ ...@@ -35,13 +35,6 @@
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
</tr> </tr>
<tr> <tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td> <td>XILINX_DSP</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td> <td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td> <td>C:\Xilinx\12.3\ISE_DS\ISE</td>
...@@ -515,31 +508,31 @@ ...@@ -515,31 +508,31 @@
</tr> </tr>
<tr> <tr>
<td>CPU Architecture/Speed</td> <td>CPU Architecture/Speed</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
</tr> </tr>
<tr> <tr>
<td>Host</td> <td>Host</td>
<td>bqplv2</td> <td>PCBE13225</td>
<td>bqplv2</td> <td>PCBE13225</td>
<td>bqplv2</td> <td>PCBE13225</td>
<td>bqplv2</td> <td>PCBE13225</td>
</tr> </tr>
<tr> <tr>
<td>OS Name</td> <td>OS Name</td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
</tr> </tr>
<tr> <tr>
<td>OS Release</td> <td>OS Release</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
</tr> </tr>
</TABLE> </TABLE>
</BODY> </HTML> </BODY> </HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.map
View file @ c3d17ad2
Release 12.3 Map M.70d (nt) Release 12.3 Map M.70d (nt64)
Xilinx Map Application Log File for Design 'SFpga' Xilinx Map Application Log File for Design 'SFpga'
Design Information Design Information
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 09:59:57 2010 Mapped Date : Fri Dec 17 11:11:25 2010
Mapping design into LUTs... Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
...@@ -79,8 +79,6 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io ...@@ -79,8 +79,6 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed. has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed. has been removed.
WARNING:MapLib:701 - Signal Si57xOe_o connected to top level port Si57xOe_o has
been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed. AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
...@@ -91,20 +89,20 @@ Updating timing models... ...@@ -91,20 +89,20 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 26 secs Total REAL time at the beginning of Placer: 16 secs
Total CPU time at the beginning of Placer: 26 secs Total CPU time at the beginning of Placer: 12 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:f1e9a8bb) REAL time: 34 secs Phase 1.1 Initial Placement Analysis (Checksum:fbd9bf1c) REAL time: 21 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 329 IOs, 327 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
and 2 are not locked. If you would like to print the names of these IOs, and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:f1e9a8bb) REAL time: 34 secs Phase 2.7 Design Feasibility Check (Checksum:fbd9bf1c) REAL time: 22 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:f1e9a8bb) REAL time: 34 secs Phase 3.31 Local Placement Optimization (Checksum:fbd9bf1c) REAL time: 22 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
... ...
...@@ -122,42 +120,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found ...@@ -122,42 +120,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
discouraged as it may lead to very poor timing results. It is recommended discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design. that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:2c046bcb) REAL time: 47 secs (Checksum:b9a90c54) REAL time: 29 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:2c046bcb) REAL time: 47 secs Phase 5.36 Local Placement Optimization (Checksum:b9a90c54) REAL time: 29 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:2c046bcb) REAL time: 47 secs Phase 6.30 Global Clock Region Assignment (Checksum:b9a90c54) REAL time: 29 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
... ...
Phase 7.3 Local Placement Optimization (Checksum:e20e3683) REAL time: 48 secs Phase 7.3 Local Placement Optimization (Checksum:5a4374ed) REAL time: 30 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:2c14b62b) REAL time: 49 secs Phase 8.5 Local Placement Optimization (Checksum:b9b9c566) REAL time: 30 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
............. ...
................
....................... .......................
..... ................
Phase 9.8 Global Placement (Checksum:ae7774fb) REAL time: 1 mins ......
Phase 9.8 Global Placement (Checksum:94595592) REAL time: 36 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:ae7774fb) REAL time: 1 mins 1 secs Phase 10.5 Local Placement Optimization (Checksum:94595592) REAL time: 36 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:fe895bce) REAL time: 1 mins 14 secs Phase 11.18 Placement Optimization (Checksum:df505277) REAL time: 47 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:fe895bce) REAL time: 1 mins 14 secs Phase 12.5 Local Placement Optimization (Checksum:df505277) REAL time: 47 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:b38174ec) REAL time: 1 mins 14 secs Phase 13.34 Placement Validation (Checksum:967c17e4) REAL time: 47 secs
Total REAL time to Placer completion: 1 mins 23 secs Total REAL time to Placer completion: 52 secs
Total CPU time to Placer completion: 1 mins 22 secs Total CPU time to Placer completion: 47 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
...@@ -261,18 +259,18 @@ Design Summary ...@@ -261,18 +259,18 @@ Design Summary
Design Summary: Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 84 Number of warnings: 83
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 796
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 941 out of 92,152 1% Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 899 out of 92,152 1% Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 587 Number using O6 output only: 571
Number using O5 output only: 154 Number using O5 output only: 154
Number using O5 and O6: 158 Number using O5 and O6: 166
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -284,17 +282,17 @@ Slice Logic Utilization: ...@@ -284,17 +282,17 @@ Slice Logic Utilization:
Number using O6 output only: 3 Number using O6 output only: 3
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 31 Number used exclusively as route-thrus: 32
Number with same-slice register load: 22 Number with same-slice register load: 23
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 363 out of 23,038 1% Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,084 Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 369 out of 1,084 34% Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 143 out of 1,084 13% Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 572 out of 1,084 52% Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of unique control sets: 32 Number of unique control sets: 32
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1% to control set restrictions: 85 out of 184,304 1%
...@@ -306,8 +304,8 @@ Slice Logic Distribution: ...@@ -306,8 +304,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
IO Utilization: IO Utilization:
Number of bonded IOBs: 329 out of 396 83% Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 327 out of 329 99% Number of LOCed IOBs: 328 out of 330 99%
IOB Master Pads: 2 IOB Master Pads: 2
IOB Slave Pads: 2 IOB Slave Pads: 2
...@@ -338,11 +336,11 @@ Specific Feature Utilization: ...@@ -338,11 +336,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.03 Average Fanout of Non-Clock Nets: 3.02
Peak Memory Usage: 406 MB Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 1 mins 26 secs Total REAL time to MAP completion: 54 secs
Total CPU time to MAP completion: 1 mins 25 secs Total CPU time to MAP completion: 49 secs
Mapping completed. Mapping completed.
See MAP report file "SFpga_map.mrp" for details. See MAP report file "SFpga_map.mrp" for details.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.mrp
View file @ c3d17ad2
Release 12.3 Map M.70d (nt) Release 12.3 Map M.70d (nt64)
Xilinx Mapping Report File for Design 'SFpga' Xilinx Mapping Report File for Design 'SFpga'
Design Information Design Information
...@@ -10,23 +10,23 @@ Target Device : xc6slx150t ...@@ -10,23 +10,23 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 09:59:57 2010 Mapped Date : Fri Dec 17 11:11:25 2010
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 84 Number of warnings: 83
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 796
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 941 out of 92,152 1% Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 899 out of 92,152 1% Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 587 Number using O6 output only: 571
Number using O5 output only: 154 Number using O5 output only: 154
Number using O5 and O6: 158 Number using O5 and O6: 166
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -38,17 +38,17 @@ Slice Logic Utilization: ...@@ -38,17 +38,17 @@ Slice Logic Utilization:
Number using O6 output only: 3 Number using O6 output only: 3
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 31 Number used exclusively as route-thrus: 32
Number with same-slice register load: 22 Number with same-slice register load: 23
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 363 out of 23,038 1% Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,084 Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 369 out of 1,084 34% Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 143 out of 1,084 13% Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 572 out of 1,084 52% Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of unique control sets: 32 Number of unique control sets: 32
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1% to control set restrictions: 85 out of 184,304 1%
...@@ -60,8 +60,8 @@ Slice Logic Distribution: ...@@ -60,8 +60,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
IO Utilization: IO Utilization:
Number of bonded IOBs: 329 out of 396 83% Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 327 out of 329 99% Number of LOCed IOBs: 328 out of 330 99%
IOB Master Pads: 2 IOB Master Pads: 2
IOB Slave Pads: 2 IOB Slave Pads: 2
...@@ -92,11 +92,11 @@ Specific Feature Utilization: ...@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.03 Average Fanout of Non-Clock Nets: 3.02
Peak Memory Usage: 406 MB Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 1 mins 26 secs Total REAL time to MAP completion: 54 secs
Total CPU time to MAP completion: 1 mins 25 secs Total CPU time to MAP completion: 49 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -185,8 +185,6 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io ...@@ -185,8 +185,6 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed. has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed. has been removed.
WARNING:MapLib:701 - Signal Si57xOe_o connected to top level port Si57xOe_o has
been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed. AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
...@@ -320,16 +318,16 @@ INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to ...@@ -320,16 +318,16 @@ INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts) 1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 329 IOs, 327 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
and 2 are not locked. If you would like to print the names of these IOs, and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
INFO:Pack:1650 - Map created a placed design. INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary Section 4 - Removed Logic Summary
--------------------------------- ---------------------------------
69 block(s) removed 67 block(s) removed
2 block(s) optimized away 2 block(s) optimized away
38 signal(s) removed 37 signal(s) removed
Section 5 - Removed Logic Section 5 - Removed Logic
------------------------- -------------------------
...@@ -411,8 +409,6 @@ The signal "DdrDQ_iob16<0>" is unused and has been removed. ...@@ -411,8 +409,6 @@ The signal "DdrDQ_iob16<0>" is unused and has been removed.
Unused block "DdrDQ_iob16_0_OBUFT" (TRI) removed. Unused block "DdrDQ_iob16_0_OBUFT" (TRI) removed.
The signal "Si57xSDa_io" is unused and has been removed. The signal "Si57xSDa_io" is unused and has been removed.
Unused block "Si57xSDa_io_OBUFT" (TRI) removed. Unused block "Si57xSDa_io_OBUFT" (TRI) removed.
The signal "Si57xOe_o" is unused and has been removed.
Unused block "Si57xOe_o_OBUFT" (TRI) removed.
The signal "AFpgaProgDone_io" is unused and has been removed. The signal "AFpgaProgDone_io" is unused and has been removed.
Unused block "AFpgaProgDone_io_OBUFT" (TRI) removed. Unused block "AFpgaProgDone_io_OBUFT" (TRI) removed.
The signal "AFpgaProgProgram_o" is unused and has been removed. The signal "AFpgaProgProgram_o" is unused and has been removed.
...@@ -451,7 +447,6 @@ Unused block "DdsIOUpdate_io" (PAD) removed. ...@@ -451,7 +447,6 @@ Unused block "DdsIOUpdate_io" (PAD) removed.
Unused block "Fmc1SDa_io" (PAD) removed. Unused block "Fmc1SDa_io" (PAD) removed.
Unused block "Fmc2SDa_io" (PAD) removed. Unused block "Fmc2SDa_io" (PAD) removed.
Unused block "Sfp2ModeDef2_io" (PAD) removed. Unused block "Sfp2ModeDef2_io" (PAD) removed.
Unused block "Si57xOe_o" (PAD) removed.
Unused block "Si57xSDa_io" (PAD) removed. Unused block "Si57xSDa_io" (PAD) removed.
Unused block "VAdjInhibit_ozn" (PAD) removed. Unused block "VAdjInhibit_ozn" (PAD) removed.
Unused block "WRModeDef2_io" (PAD) removed. Unused block "WRModeDef2_io" (PAD) removed.
...@@ -657,6 +652,7 @@ Section 6 - IOB Properties ...@@ -657,6 +652,7 @@ Section 6 - IOB Properties
| Sfp2RateSelect | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | Sfp2RateSelect | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sfp2TxDisable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | Sfp2TxDisable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sfp2TxFault_i | IOB | INPUT | LVCMOS33 | | | | | | | | Sfp2TxFault_i | IOB | INPUT | LVCMOS33 | | | | | | |
| Si57xOe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Si57xSCl_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | Si57xSCl_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Si57x_ik | IOB | INPUT | LVDS_33 | TRUE | | | | | | | Si57x_ik | IOB | INPUT | LVDS_33 | TRUE | | | | | |
| Si57x_ikn | IOB | INPUT | LVDS_33 | TRUE | | | | | | | Si57x_ikn | IOB | INPUT | LVDS_33 | TRUE | | | | | |
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_ngdbuild.xrpt
View file @ c3d17ad2
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3"> <document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Fri Dec 17 09:59:56 2010"> <application stringID="NgdBuild" timeStamp="Fri Dec 17 11:11:22 2010">
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<item stringID="variable" value="XILINX"/> <item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
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</row> </row>
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<item stringID="variable" value="XILINX_PLANAHEAD"/> <item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row> </row>
</table> </table>
<item stringID="User_EnvOs" value="OS Information"> <item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/> <item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/> <item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item> </item>
<item stringID="User_EnvHost" value="bqplv2"/> <item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu"> <table stringID="User_EnvCpu">
<column stringID="arch"/> <column stringID="arch"/>
<column stringID="speed"/> <column stringID="speed"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/> <item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3389 MHz"/> <item stringID="speed" value="3158 MHz"/>
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...@@ -93,9 +89,9 @@ ...@@ -93,9 +89,9 @@
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="151"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="34"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
...@@ -125,9 +121,9 @@ ...@@ -125,9 +121,9 @@
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="151"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="66"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="65"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv
View file @ c3d17ad2
#Release 12.3 - par M.70d (nt) #Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Fri Dec 17 10:02:33 2010 #Fri Dec 17 11:12:54 2010
# #
## NOTE: This file is designed to be imported into a spreadsheet program ## NOTE: This file is designed to be imported into a spreadsheet program
...@@ -296,7 +296,7 @@ E14,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,, ...@@ -296,7 +296,7 @@ E14,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,,
E15,,,GND,,,,,,,,,,,, E15,,,GND,,,,,,,,,,,,
E16,VmeP0HwLowByteOe_o,IOB,IO_L49N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE, E16,VmeP0HwLowByteOe_o,IOB,IO_L49N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E17,,,VCCAUX,,,,,,,,2.5,,,, E17,,,VCCAUX,,,,,,,,2.5,,,,
E18,,IOBS,IO_L51N_0,UNUSED,,0,,,,,,,,, E18,Si57xOe_o,IOB,IO_L51N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E19,,,GND,,,,,,,,,,,, E19,,,GND,,,,,,,,,,,,
E20,VmeWrite_in,IOB,IO_L57N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, E20,VmeWrite_in,IOB,IO_L57N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
E21,,,VCCO_0,,,0,,,,,3.30,,,, E21,,,VCCO_0,,,0,,,,,3.30,,,,
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt
View file @ c3d17ad2
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 10:02:34 2010 Fri Dec 17 11:12:54 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
...@@ -297,7 +297,7 @@ Pinout by Pin Number: ...@@ -297,7 +297,7 @@ Pinout by Pin Number:
|E15 | | |GND | | | | | | | | | | | | |E15 | | |GND | | | | | | | | | | | |
|E16 |VmeP0HwLowByteOe_o |IOB |IO_L49N_0 |OUTPUT |LVCMOS33 |0 |12 | | | | |LOCATED |NO |NONE | |E16 |VmeP0HwLowByteOe_o |IOB |IO_L49N_0 |OUTPUT |LVCMOS33 |0 |12 | | | | |LOCATED |NO |NONE |
|E17 | | |VCCAUX | | | | | | | |2.5 | | | | |E17 | | |VCCAUX | | | | | | | |2.5 | | | |
|E18 | |IOBS |IO_L51N_0 |UNUSED | |0 | | | | | | | | | |E18 |Si57xOe_o |IOB |IO_L51N_0 |OUTPUT |LVCMOS33 |0 |12 | | | | |LOCATED |NO |NONE |
|E19 | | |GND | | | | | | | | | | | | |E19 | | |GND | | | | | | | | | | | |
|E20 |VmeWrite_in |IOB |IO_L57N_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | |E20 |VmeWrite_in |IOB |IO_L57N_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE |
|E21 | | |VCCO_0 | | |0 | | | | |3.30 | | | | |E21 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml
View file @ c3d17ad2
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DesignSummary rev="13"> <DesignSummary rev="15">
<CmdHistory> <CmdHistory>
</CmdHistory> </CmdHistory>
</DesignSummary> </DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_xst.xrpt
View file @ c3d17ad2
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3"> <document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Fri Dec 17 09:49:53 2010"> <application stringID="Xst" timeStamp="Fri Dec 17 11:10:57 2010">
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</table> </table>
<item stringID="User_EnvOs" value="OS Information"> <item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/> <item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/> <item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item> </item>
<item stringID="User_EnvHost" value="bqplv2"/> <item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu"> <table stringID="User_EnvCpu">
<column stringID="arch"/> <column stringID="arch"/>
<column stringID="speed"/> <column stringID="speed"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/> <item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3389 MHz"/> <item stringID="speed" value="3158 MHz"/>
</row> </row>
</table> </table>
</section> </section>
...@@ -137,8 +133,8 @@ ...@@ -137,8 +133,8 @@
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/> <item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="1"/> <item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_TRISTATES" value="66"> <item dataType="int" stringID="XST_TRISTATES" value="65">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="66"/> <item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="65"/>
</item> </item>
<item dataType="int" stringID="XST_FSMS" value="2"/> <item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_XORS" value="4"> <item dataType="int" stringID="XST_XORS" value="4">
...@@ -233,8 +229,8 @@ ...@@ -233,8 +229,8 @@
<item dataType="int" stringID="XST_IO_BUFFERS" value="305"> <item dataType="int" stringID="XST_IO_BUFFERS" value="305">
<item dataType="int" stringID="XST_IBUF" value="77"/> <item dataType="int" stringID="XST_IBUF" value="77"/>
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="32"/> <item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="32"/>
<item dataType="int" stringID="XST_OBUF" value="151"/> <item dataType="int" stringID="XST_OBUF" value="152"/>
<item dataType="int" stringID="XST_OBUFT" value="34"/> <item dataType="int" stringID="XST_OBUFT" value="33"/>
</item> </item>
</section> </section>
</section> </section>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.gise
View file @ c3d17ad2
...@@ -107,7 +107,7 @@ ...@@ -107,7 +107,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292575819" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292575791"> <transform xil_pn:end_ts="1292580677" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292580654">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -129,7 +129,7 @@ ...@@ -129,7 +129,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292576396" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292576389"> <transform xil_pn:end_ts="1292580684" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292580677">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -139,7 +139,7 @@ ...@@ -139,7 +139,7 @@
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292576485" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292576396"> <transform xil_pn:end_ts="1292580741" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292580684">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -155,7 +155,7 @@ ...@@ -155,7 +155,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/> <outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292576581" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292576485"> <transform xil_pn:end_ts="1292580788" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292580741">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -170,7 +170,7 @@ ...@@ -170,7 +170,7 @@
<outfile xil_pn:name="SFpga_par.xrpt"/> <outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292576632" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292576581"> <transform xil_pn:end_ts="1292580816" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292580788">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -183,6 +183,10 @@ ...@@ -183,6 +183,10 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1292580983" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292580980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570"> <transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -193,7 +197,7 @@ ...@@ -193,7 +197,7 @@
<status xil_pn:value="InputRemoved"/> <status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/> <status xil_pn:value="OutputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1292576581" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292576556"> <transform xil_pn:end_ts="1292580788" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292580776">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SFpga.twr"/> <outfile xil_pn:name="SFpga.twr"/>
......
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst
View file @ c3d17ad2
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292575819 C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292580676
OK OK
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/map.xmsgs
View file @ c3d17ad2
...@@ -119,9 +119,6 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please ...@@ -119,9 +119,6 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Fmc2SDa_io</arg> connected to top level port <arg fmt="%s" index="2">Fmc2SDa_io</arg> has been removed. <msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Fmc2SDa_io</arg> connected to top level port <arg fmt="%s" index="2">Fmc2SDa_io</arg> has been removed.
</msg> </msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Si57xOe_o</arg> connected to top level port <arg fmt="%s" index="2">Si57xOe_o</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">AFpgaProgProgram_o</arg> connected to top level port <arg fmt="%s" index="2">AFpgaProgProgram_o</arg> has been removed. <msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">AFpgaProgProgram_o</arg> connected to top level port <arg fmt="%s" index="2">AFpgaProgProgram_o</arg> has been removed.
</msg> </msg>
...@@ -140,7 +137,7 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please ...@@ -140,7 +137,7 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp). <msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg> </msg>
<msg type="info" file="Place" num="834" delta="old" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">329</arg> IOs, <arg fmt="%d" index="2">327</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg> <msg type="info" file="Place" num="834" delta="new" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">330</arg> IOs, <arg fmt="%d" index="2">328</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg> </msg>
<msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y9</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. <msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y9</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/pn_parser.xmsgs
View file @ c3d17ad2
...@@ -8,5 +8,8 @@ ...@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SystemFpga.v\&quot; into library work</arg>
</msg>
</messages> </messages>
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport
View file @ c3d17ad2
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2010-12-17T09:49:40</DateModified> <DateModified>2010-12-17T11:09:45</DateModified>
<ModuleName>SFpga</ModuleName> <ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-15T15:17:10</SummaryTimeStamp> <SummaryTimeStamp>2010-12-15T15:17:10</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath> <SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SystemFpga.projectmgr
View file @ c3d17ad2
...@@ -57,7 +57,6 @@ ...@@ -57,7 +57,6 @@
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes> <ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion> <ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode> <ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode> <ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode> <ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
...@@ -65,13 +64,13 @@ ...@@ -65,13 +64,13 @@
<ClosedNode>Implement Design/Translate</ClosedNode> <ClosedNode>Implement Design/Translate</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>Generate Programming File</SelectedItem> <SelectedItem>Generate Target PROM/ACE File</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >1</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >14</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000191000000010000000100000000000000000000000064ffffffff000000810000000000000001000001910000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Programming File</CurrentItem> <CurrentItem>Generate Target PROM/ACE File</CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes> <ClosedNodes>
......
trunk/firmware/XilinxISE/SystemFpga/par_usage_statistics.html
View file @ c3d17ad2
...@@ -2,30 +2,30 @@ ...@@ -2,30 +2,30 @@
<xtag-section name="ParStatistics"> <xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1486</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1486</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4724</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4740</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4724</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4740</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4258</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4274</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>25.0 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>31.4 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>15.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>43.9 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>21.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>55.5 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>26.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>62.8 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>29.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>15.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>16.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>6.7</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>9.5</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>8.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.7</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.6</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>4.6</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.1180</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0984</xtag-par-property-value></TD></TR>
</xtag-section> </xtag-section>
</TABLE> </TABLE>
trunk/firmware/XilinxISE/SystemFpga/sfpga.bgn
View file @ c3d17ad2
Release 12.3 - Bitgen M.70d (nt) Release 12.3 - Bitgen M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx150t.nph' in environment Loading device for application Rf_Device from file '6slx150t.nph' in environment
C:\Xilinx\12.3\ISE_DS\ISE\. C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3 "SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf. Opened constraints file SFpga.pcf.
Fri Dec 17 10:03:13 2010 Fri Dec 17 11:13:13 2010
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
Summary of Bitgen Options: Summary of Bitgen Options:
+----------------------+----------------------+ +----------------------+----------------------+
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.drc
View file @ c3d17ad2
Release 12.3 Drc M.70d (nt) Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 10:03:13 2010 Fri Dec 17 11:13:13 2010
drc -z SFpga.ncd SFpga.pcf drc -z SFpga.ncd SFpga.pcf
......
trunk/firmware/XilinxISE/SystemFpga/webtalk.log
View file @ c3d17ad2
...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information Project Information
-------------------- --------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=5 ProjectIteration=6
WebTalk Summary WebTalk Summary
---------------- ----------------
...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled. ...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON. INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON. INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-17T10:03:52. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-17T11:13:36. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/SystemFpga/webtalk_pn.xml
View file @ c3d17ad2
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Dec 17 10:03:02 2010"> <application name="pn" timeStamp="Fri Dec 17 11:13:08 2010">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/> <property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="5" type="project"/> <property name="ProjectIteration" value="6" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/> <property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/> <property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section> </section>
...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq ...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/> <property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/> <property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="5" type="process"/> <property name="PROP_intWbtProjectIteration" value="6" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> <property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
trunk/hdl/design/SystemFpga.v
View file @ c3d17ad2
...@@ -336,7 +336,7 @@ assign VmeP0BunchSelectOe_o= 1'b0; ...@@ -336,7 +336,7 @@ assign VmeP0BunchSelectOe_o= 1'b0;
assign Si57xSCl_ok= 1'b0; assign Si57xSCl_ok= 1'b0;
assign Si57xSDa_io= 1'bz; assign Si57xSDa_io= 1'bz;
assign Si57xOe_o= 1'bz; assign Si57xOe_o= 1'b1;
assign DdsF_ob2= 2'b0; assign DdsF_ob2= 2'b0;
assign DdsProfile_ob3= 3'b0; assign DdsProfile_ob3= 3'b0;
......
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