Commit 9763573c authored by Andrea Boccardi's avatar Andrea Boccardi

..

parent 2e4547c8
......@@ -27,7 +27,7 @@ wire WriteCycle_a = Cyc_i && Stb_i && We_i;
always @(posedge Clk_ik) ReadCycle_d <= #1 {ReadCycle_d[3:0], ReadCycle_a};
assign Ack_oa = WriteCycle_a || (ReadCycle_a && ReadCycle_d[3]);
assign SramOe_on = SramWe_d[1];
assign SramOe_on = |SramWe_d[1:0];
always @(posedge Clk_ik) SramAddress_ob21 <= #1 Adr_ib21;
......@@ -35,7 +35,7 @@ always @(posedge Clk_ik) WriteCycle_d <= #1 {WriteCycle_d[0], WriteCycle_a};
always @(negedge Clk_ik) SramWe_on <= #1 ~(WriteCycle_d[1:0]==2'b01);
always @(negedge Clk_ik) SramWe_d <= #1 {SramWe_d[0], ~SramWe_on};
always @(posedge Clk_ik) SramWe_d <= #1 {SramWe_d[0], ~SramWe_on};
always @(posedge Clk_ik) begin
DatI_db32[2] <= #1 DatI_db32[1];
......
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