Commit 914e4c5d authored by Andrea Boccardi's avatar Andrea Boccardi

Adding the functional specs

parent 1de5f566
VmeInterface
contains: VME connectors (P0, P1, P2), VME buffers, VME GA bypass
connected to: SystemFpga, PowerSupplies
EthernetInterface
contains: SFP socket, PHY, PLL
connected to : SystemFpga, ClockGeneration, PowerSupplies
DdrMemory
contains: the DDR module
connected to: SystemFpga, PowerSupplies
EepromMemory
contains: the EEPROM module
connected to: SystemFpga, PowerSupplies
SystemFpga
contains: FPGA, EEPROM
conected to: VmeInterface, EthernetInterface, DdrMemory, EepromMemory,
ApplicationFpga, ClockGeneration, Fmc1, Fmc2, PowerSupplies
ApplicationFpga
contains: FPGA
connected to: SystemFpga, Fmc1, Fmc2, ZbtMemory, ClockGeneration,
PowerSupplies
ZbtMemory
contains: ZBT memories
connected to: ApplicationFpga, PowerSupplies
ClockGeneration:
contains: PLL chips, quartz cristal, clock buffers
connected to: SystemFpga, EthernetInterface, ApplicationFpga, Fmc1,
Fmc2, PowerSupplies
Fmc1/2
contains: FMC conector
connected to: ApplicationFpga,SystemFpga, ClockGeneration, PowerSuppliesPowerSupplies
contains: DC/DC switcting converters, filtering components, bypass logic
Connected to: ALL the modules
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