Commit 803158d3 authored by Andrea Boccardi's avatar Andrea Boccardi

Synthesized Appl and Syst FPGA for the control of the SRAMs

parent 88e03536
...@@ -40,7 +40,7 @@ NGDBUILD Design Results Summary: ...@@ -40,7 +40,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 12 Number of warnings: 12
Total memory usage is 146700 kilobytes Total memory usage is 148816 kilobytes
Writing NGD file "ApplicationFpga.ngd" ... Writing NGD file "ApplicationFpga.ngd" ...
Total REAL time to NGDBUILD completion: 2 sec Total REAL time to NGDBUILD completion: 2 sec
......
...@@ -30,3 +30,32 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -30,3 +30,32 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
...@@ -107,7 +107,7 @@ ...@@ -107,7 +107,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292855052" xil_pn:in_ck="4072638633301905625" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="6138376139572991401" xil_pn:start_ts="1292855045"> <transform xil_pn:end_ts="1294743513" xil_pn:in_ck="5192584784990505676" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="6138376139572991401" xil_pn:start_ts="1294743504">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -125,27 +125,23 @@ ...@@ -125,27 +125,23 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1292839127" xil_pn:in_ck="-4700563312770453794" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-149139164536860460" xil_pn:start_ts="1292839127"> <transform xil_pn:end_ts="1294732675" xil_pn:in_ck="-4700563312770453794" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-149139164536860460" xil_pn:start_ts="1294732675">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292855056" xil_pn:in_ck="-2234839937575114378" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1018860157679998437" xil_pn:start_ts="1292855052"> <transform xil_pn:end_ts="1294743516" xil_pn:in_ck="-2234839937575114378" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1018860157679998437" xil_pn:start_ts="1294743513">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ApplicationFpga.bld"/> <outfile xil_pn:name="ApplicationFpga.bld"/>
<outfile xil_pn:name="ApplicationFpga.ngd"/> <outfile xil_pn:name="ApplicationFpga.ngd"/>
<outfile xil_pn:name="ApplicationFpga_ngdbuild.xrpt"/> <outfile xil_pn:name="ApplicationFpga_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292855079" xil_pn:in_ck="-7949697330576238633" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292855056"> <transform xil_pn:end_ts="1294743543" xil_pn:in_ck="-7949697330576238633" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1294743516">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ApplicationFpga.pcf"/> <outfile xil_pn:name="ApplicationFpga.pcf"/>
<outfile xil_pn:name="ApplicationFpga_map.map"/> <outfile xil_pn:name="ApplicationFpga_map.map"/>
<outfile xil_pn:name="ApplicationFpga_map.mrp"/> <outfile xil_pn:name="ApplicationFpga_map.mrp"/>
...@@ -156,7 +152,7 @@ ...@@ -156,7 +152,7 @@
<outfile xil_pn:name="ApplicationFpga_usage.xml"/> <outfile xil_pn:name="ApplicationFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292855116" xil_pn:in_ck="4718546783015930448" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292855079"> <transform xil_pn:end_ts="1294743582" xil_pn:in_ck="4718546783015930448" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1294743543">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -171,7 +167,7 @@ ...@@ -171,7 +167,7 @@
<outfile xil_pn:name="ApplicationFpga_par.xrpt"/> <outfile xil_pn:name="ApplicationFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292855146" xil_pn:in_ck="-4700563312770461419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1292855116"> <transform xil_pn:end_ts="1294743613" xil_pn:in_ck="-4700563312770461419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1294743582">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -187,23 +183,26 @@ ...@@ -187,23 +183,26 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1292855153" xil_pn:in_ck="4850548760538546975" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1292855146"> <transform xil_pn:end_ts="1294732851" xil_pn:in_ck="4850548760538546975" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1294732849">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="applicationfpga.isc"/> <outfile xil_pn:name="applicationfpga.isc"/>
</transform> </transform>
<transform xil_pn:end_ts="1292855116" xil_pn:in_ck="8541715597190098387" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292855105"> <transform xil_pn:end_ts="1294743582" xil_pn:in_ck="8541715597190098387" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1294743572">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ApplicationFpga.twr"/> <outfile xil_pn:name="ApplicationFpga.twr"/>
<outfile xil_pn:name="ApplicationFpga.twx"/> <outfile xil_pn:name="ApplicationFpga.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292838687" xil_pn:in_ck="-4700563312770461287" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1292838685"> <transform xil_pn:end_ts="1294741808" xil_pn:in_ck="-7949697330576238633" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1294741808">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
</transform> </transform>
</transforms> </transforms>
......
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 12.3 par M.70d (nt64) Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Mon Dec 20 15:24:39 2010 PCBE13225:: Tue Jan 11 11:59:03 2011
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd
ApplicationFpga.ncd ApplicationFpga.pcf ApplicationFpga.ncd ApplicationFpga.pcf
...@@ -22,35 +22,35 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15". ...@@ -22,35 +22,35 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary: Device Utilization Summary:
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 330 out of 184,304 1% Number of Slice Registers: 492 out of 184,304 1%
Number used as Flip Flops: 330 Number used as Flip Flops: 492
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 264 out of 92,152 1% Number of Slice LUTs: 201 out of 92,152 1%
Number used as logic: 238 out of 92,152 1% Number used as logic: 160 out of 92,152 1%
Number using O6 output only: 222 Number using O6 output only: 123
Number using O5 output only: 14 Number using O5 output only: 14
Number using O5 and O6: 2 Number using O5 and O6: 23
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 5 out of 21,680 1% Number used as Memory: 23 out of 21,680 1%
Number used as Dual Port RAM: 0 Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 5 Number used as Shift Register: 23
Number using O6 output only: 5 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 18
Number used exclusively as route-thrus: 21 Number used exclusively as route-thrus: 18
Number with same-slice register load: 20 Number with same-slice register load: 17
Number with same-slice carry load: 1 Number with same-slice carry load: 1
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1% Number of occupied Slices: 143 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355 Number of LUT Flip Flop pairs used: 479
Number with an unused Flip Flop: 46 out of 355 12% Number with an unused Flip Flop: 25 out of 479 5%
Number with an unused LUT: 91 out of 355 25% Number with an unused LUT: 278 out of 479 58%
Number of fully used LUT-FF pairs: 218 out of 355 61% Number of fully used LUT-FF pairs: 176 out of 479 36%
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0% to control set restrictions: 0 out of 184,304 0%
...@@ -61,8 +61,8 @@ Slice Logic Distribution: ...@@ -61,8 +61,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
IO Utilization: IO Utilization:
Number of bonded IOBs: 23 out of 396 5% Number of bonded IOBs: 151 out of 396 38%
Number of LOCed IOBs: 23 out of 23 100% Number of LOCed IOBs: 151 out of 151 100%
Specific Feature Utilization: Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 268 0% Number of RAMB16BWERs: 0 out of 268 0%
...@@ -113,29 +113,29 @@ WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not ...@@ -113,29 +113,29 @@ WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not
Starting Router Starting Router
Phase 1 : 1691 unrouted; REAL time: 10 secs Phase 1 : 1676 unrouted; REAL time: 11 secs
Phase 2 : 1560 unrouted; REAL time: 13 secs Phase 2 : 1401 unrouted; REAL time: 14 secs
Phase 3 : 730 unrouted; REAL time: 15 secs Phase 3 : 400 unrouted; REAL time: 18 secs
Phase 4 : 730 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 21 secs Phase 4 : 400 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 23 secs
Updating file: ApplicationFpga.ncd with current fully routed design. Updating file: ApplicationFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 24 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 24 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 24 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 24 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 24 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 24 secs
Total REAL time to Router completion: 22 secs Total REAL time to Router completion: 24 secs
Total CPU time to Router completion: 22 secs Total CPU time to Router completion: 24 secs
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
...@@ -154,7 +154,7 @@ Generating Clock Report ...@@ -154,7 +154,7 @@ Generating Clock Report
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
|FpGpIo_iob4_4_OBUF_B | | | | | | |FpGpIo_iob4_4_OBUF_B | | | | | |
| UFG | BUFGMUX_X2Y1| No | 84 | 0.138 | 1.640 | | UFG | BUFGMUX_X2Y1| No | 127 | 0.191 | 1.695 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing * Net Skew is the difference between the minimum and maximum routing
...@@ -171,8 +171,8 @@ Asterisk (*) preceding a constraint indicates it was not met. ...@@ -171,8 +171,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score | | Slack | Achievable | Errors | Score
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 0.419ns| 7.914ns| 0| 0 TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 1.401ns| 6.932ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.383ns| | 0| 0 lk_ik" 120 MHz HIGH 50% | HOLD | 0.244ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
...@@ -185,10 +185,10 @@ All signals are completely routed. ...@@ -185,10 +185,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 24 secs Total REAL time to PAR completion: 26 secs
Total CPU time to PAR completion: 24 secs Total CPU time to PAR completion: 26 secs
Peak Memory Usage: 521 MB Peak Memory Usage: 533 MB
Placer: Placement generated during map. Placer: Placement generated during map.
Routing: Completed - No errors found. Routing: Completed - No errors found.
......
verilog work "../../../hdl/design/WbToCy7c1470.v"
verilog work "../../../hdl/design/Ser2MstWB.v" verilog work "../../../hdl/design/Ser2MstWB.v"
verilog work "../../../hdl/design/Generic4OutputRegs.v" verilog work "../../../hdl/design/Generic4OutputRegs.v"
verilog work "../../../hdl/design/Debouncer.v" verilog work "../../../hdl/design/Debouncer.v"
......
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.419" best="7.914" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.383" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="1.401" best="6.932" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.244" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
...@@ -3,7 +3,6 @@ ...@@ -3,7 +3,6 @@
NET "SysAppClk_ik" TNM_NET = "SysAppClk_ik"; NET "SysAppClk_ik" TNM_NET = "SysAppClk_ik";
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50 %; TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50 %;
# PlanAhead Generated physical constraints
NET "AFpgaProgClk_io" LOC = AE24; NET "AFpgaProgClk_io" LOC = AE24;
NET "AFpgaProgCsi_io" LOC = AF23; NET "AFpgaProgCsi_io" LOC = AF23;
...@@ -28,3 +27,134 @@ NET "SysAppClk_ik" LOC = U23; ...@@ -28,3 +27,134 @@ NET "SysAppClk_ik" LOC = U23;
NET "SysAppClk_ok" LOC = U24; NET "SysAppClk_ok" LOC = U24;
NET "SysAppSlow_iob2[1]" LOC = AF22; NET "SysAppSlow_iob2[1]" LOC = AF22;
NET "SysAppSlow_iob2[2]" LOC = AF3; NET "SysAppSlow_iob2[2]" LOC = AF3;
# PlanAhead Generated physical constraints
NET "Sram1Address_b21[0]" LOC = P17;
NET "Sram1Address_b21[1]" LOC = P19;
NET "Sram1Address_b21[2]" LOC = R18;
NET "Sram1Address_b21[3]" LOC = V20;
NET "Sram1Address_b21[4]" LOC = V21;
NET "Sram1Address_b21[5]" LOC = T19;
NET "Sram1Address_b21[6]" LOC = U20;
NET "Sram1Address_b21[7]" LOC = U21;
NET "Sram1Address_b21[8]" LOC = R19;
NET "Sram1Address_b21[9]" LOC = N3;
NET "Sram1Address_b21[10]" LOC = L3;
NET "Sram1Address_b21[11]" LOC = M4;
NET "Sram1Address_b21[12]" LOC = L4;
NET "Sram1Address_b21[13]" LOC = K1;
NET "Sram1Address_b21[14]" LOC = N2;
NET "Sram1Address_b21[15]" LOC = L2;
NET "Sram1Address_b21[16]" LOC = M3;
NET "Sram1Address_b21[17]" LOC = H1;
NET "Sram1Address_b21[18]" LOC = J1;
NET "Sram1Address_b21[19]" LOC = K3;
NET "Sram1Address_b21[20]" LOC = J3;
NET "Sram1Bws_nb4[0]" LOC = AD26;
NET "Sram1Bws_nb4[1]" LOC = AC25;
NET "Sram1Bws_nb4[2]" LOC = AE26;
NET "Sram1Bws_nb4[3]" LOC = AE25;
NET "Sram1Clk_k" LOC = U19;
NET "Sram1Data_b36[0]" LOC = T24;
NET "Sram1Data_b36[1]" LOC = U22;
NET "Sram1Data_b36[2]" LOC = T20;
NET "Sram1Data_b36[3]" LOC = T22;
NET "Sram1Data_b36[4]" LOC = R21;
NET "Sram1Data_b36[5]" LOC = R23;
NET "Sram1Data_b36[6]" LOC = R20;
NET "Sram1Data_b36[7]" LOC = P21;
NET "Sram1Data_b36[8]" LOC = AA26;
NET "Sram1Data_b36[9]" LOC = Y26;
NET "Sram1Data_b36[10]" LOC = V26;
NET "Sram1Data_b36[11]" LOC = U25;
NET "Sram1Data_b36[12]" LOC = U26;
NET "Sram1Data_b36[13]" LOC = T26;
NET "Sram1Data_b36[14]" LOC = W25;
NET "Sram1Data_b36[15]" LOC = W26;
NET "Sram1Data_b36[16]" LOC = AC23;
NET "Sram1Data_b36[17]" LOC = AD24;
NET "Sram1Data_b36[18]" LOC = AC24;
NET "Sram1Data_b36[19]" LOC = AB24;
NET "Sram1Data_b36[20]" LOC = AA24;
NET "Sram1Data_b36[21]" LOC = Y24;
NET "Sram1Data_b36[22]" LOC = W24;
NET "Sram1Data_b36[23]" LOC = V23;
NET "Sram1Data_b36[24]" LOC = V24;
NET "Sram1Data_b36[25]" LOC = D1;
NET "Sram1Data_b36[26]" LOC = D3;
NET "Sram1Data_b36[27]" LOC = T23;
NET "Sram1Data_b36[28]" LOC = R24;
NET "Sram1Data_b36[29]" LOC = E3;
NET "Sram1Data_b36[30]" LOC = E4;
NET "Sram1Data_b36[31]" LOC = P22;
NET "Sram1Data_b36[32]" LOC = P26;
NET "Sram1Data_b36[33]" LOC = AA25;
NET "Sram1Data_b36[34]" LOC = AA23;
NET "Sram1Data_b36[35]" LOC = P24;
NET "Sram1Oe_n" LOC = AB26;
NET "Sram1We_n" LOC = AC26;
NET "Sram2Address_b21[0]" LOC = N6;
NET "Sram2Address_b21[1]" LOC = N7;
NET "Sram2Address_b21[2]" LOC = V6;
NET "Sram2Address_b21[3]" LOC = U8;
NET "Sram2Address_b21[4]" LOC = R10;
NET "Sram2Address_b21[5]" LOC = V7;
NET "Sram2Address_b21[6]" LOC = T9;
NET "Sram2Address_b21[7]" LOC = U9;
NET "Sram2Address_b21[8]" LOC = C1;
NET "Sram2Address_b21[9]" LOC = N4;
NET "Sram2Address_b21[10]" LOC = M9;
NET "Sram2Address_b21[11]" LOC = N9;
NET "Sram2Address_b21[12]" LOC = P8;
NET "Sram2Address_b21[13]" LOC = R8;
NET "Sram2Address_b21[14]" LOC = B1;
NET "Sram2Address_b21[15]" LOC = N5;
NET "Sram2Address_b21[16]" LOC = M10;
NET "Sram2Address_b21[17]" LOC = N8;
NET "Sram2Address_b21[18]" LOC = P10;
NET "Sram2Address_b21[19]" LOC = R9;
NET "Sram2Address_b21[20]" LOC = R6;
NET "Sram2Bws_nb4[0]" LOC = AC2;
NET "Sram2Bws_nb4[1]" LOC = AD1;
NET "Sram2Bws_nb4[2]" LOC = AC1;
NET "Sram2Bws_nb4[3]" LOC = AB1;
NET "Sram2Clk_k" LOC = Y6;
NET "Sram2Data_b36[0]" LOC = P3;
NET "Sram2Data_b36[1]" LOC = Y3;
NET "Sram2Data_b36[2]" LOC = P1;
NET "Sram2Data_b36[3]" LOC = W5;
NET "Sram2Data_b36[4]" LOC = U3;
NET "Sram2Data_b36[5]" LOC = U4;
NET "Sram2Data_b36[6]" LOC = B2;
NET "Sram2Data_b36[7]" LOC = T4;
NET "Sram2Data_b36[8]" LOC = AC3;
NET "Sram2Data_b36[9]" LOC = AB5;
NET "Sram2Data_b36[10]" LOC = AA4;
NET "Sram2Data_b36[11]" LOC = AB3;
NET "Sram2Data_b36[12]" LOC = Y5;
NET "Sram2Data_b36[13]" LOC = AA3;
NET "Sram2Data_b36[14]" LOC = AB4;
NET "Sram2Data_b36[15]" LOC = AD3;
NET "Sram2Data_b36[16]" LOC = Y1;
NET "Sram2Data_b36[17]" LOC = AA1;
NET "Sram2Data_b36[18]" LOC = W1;
NET "Sram2Data_b36[19]" LOC = W2;
NET "Sram2Data_b36[20]" LOC = U2;
NET "Sram2Data_b36[21]" LOC = V1;
NET "Sram2Data_b36[22]" LOC = E1;
NET "Sram2Data_b36[23]" LOC = U1;
NET "Sram2Data_b36[24]" LOC = U5;
NET "Sram2Data_b36[25]" LOC = V3;
NET "Sram2Data_b36[26]" LOC = T6;
NET "Sram2Data_b36[27]" LOC = T8;
NET "Sram2Data_b36[28]" LOC = R4;
NET "Sram2Data_b36[29]" LOC = R5;
NET "Sram2Data_b36[30]" LOC = P5;
NET "Sram2Data_b36[31]" LOC = P6;
NET "Sram2Data_b36[32]" LOC = R3;
NET "Sram2Data_b36[33]" LOC = AC4;
NET "Sram2Data_b36[34]" LOC = AA2;
NET "Sram2Data_b36[35]" LOC = E2;
NET "Sram2Oe_n" LOC = AE2;
NET "Sram2We_n" LOC = AE1;
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 15:25:04 2010 Tue Jan 11 11:59:30 2011
All signals are completely routed. All signals are completely routed.
......
...@@ -38,6 +38,10 @@ ...@@ -38,6 +38,10 @@
<file xil_pn:name="ApplicationFpga.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="ApplicationFpga.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/> <association xil_pn:name="Implementation"/>
</file> </file>
<file xil_pn:name="../../../hdl/design/WbToCy7c1470.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
</files> </files>
<properties> <properties>
......
...@@ -11,7 +11,7 @@ Target Device : xc6slx150t ...@@ -11,7 +11,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 15:24:16 2010 Mapped Date : Tue Jan 11 11:58:37 2011
Mapping design into LUTs... Mapping design into LUTs...
Running directed packing... Running directed packing...
...@@ -20,54 +20,55 @@ Updating timing models... ...@@ -20,54 +20,55 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 10 secs Total REAL time at the beginning of Placer: 11 secs
Total CPU time at the beginning of Placer: 10 secs Total CPU time at the beginning of Placer: 10 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:22fc371c) REAL time: 13 secs Phase 1.1 Initial Placement Analysis (Checksum:5f73f5f6) REAL time: 14 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:22fc371c) REAL time: 14 secs Phase 2.7 Design Feasibility Check (Checksum:5f73f5f6) REAL time: 14 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:22fc371c) REAL time: 14 secs Phase 3.31 Local Placement Optimization (Checksum:5f73f5f6) REAL time: 14 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:92c6284) REAL time: 17 secs (Checksum:af4a4b86) REAL time: 19 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:92c6284) REAL time: 17 secs Phase 5.36 Local Placement Optimization (Checksum:af4a4b86) REAL time: 19 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:92c6284) REAL time: 17 secs Phase 6.30 Global Clock Region Assignment (Checksum:af4a4b86) REAL time: 19 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:92c6284) REAL time: 17 secs Phase 7.3 Local Placement Optimization (Checksum:af4a4b86) REAL time: 19 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:92c6284) REAL time: 17 secs Phase 8.5 Local Placement Optimization (Checksum:af4a4b86) REAL time: 19 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
............................. ......
........ .......................
Phase 9.8 Global Placement (Checksum:ac53ebd5) REAL time: 19 secs ....
Phase 9.8 Global Placement (Checksum:8f31ff0f) REAL time: 20 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:ac53ebd5) REAL time: 19 secs Phase 10.5 Local Placement Optimization (Checksum:8f31ff0f) REAL time: 21 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:2eb3148e) REAL time: 19 secs Phase 11.18 Placement Optimization (Checksum:e76ac3e7) REAL time: 21 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:2eb3148e) REAL time: 19 secs Phase 12.5 Local Placement Optimization (Checksum:e76ac3e7) REAL time: 21 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:85180713) REAL time: 19 secs Phase 13.34 Placement Validation (Checksum:c0db5f12) REAL time: 21 secs
Total REAL time to Placer completion: 21 secs Total REAL time to Placer completion: 23 secs
Total CPU time to Placer completion: 20 secs Total CPU time to Placer completion: 23 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
...@@ -102,38 +103,38 @@ Design Summary: ...@@ -102,38 +103,38 @@ Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 12 Number of warnings: 12
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 330 out of 184,304 1% Number of Slice Registers: 492 out of 184,304 1%
Number used as Flip Flops: 330 Number used as Flip Flops: 492
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 264 out of 92,152 1% Number of Slice LUTs: 201 out of 92,152 1%
Number used as logic: 238 out of 92,152 1% Number used as logic: 160 out of 92,152 1%
Number using O6 output only: 222 Number using O6 output only: 123
Number using O5 output only: 14 Number using O5 output only: 14
Number using O5 and O6: 2 Number using O5 and O6: 23
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 5 out of 21,680 1% Number used as Memory: 23 out of 21,680 1%
Number used as Dual Port RAM: 0 Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 5 Number used as Shift Register: 23
Number using O6 output only: 5 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 18
Number used exclusively as route-thrus: 21 Number used exclusively as route-thrus: 18
Number with same-slice register load: 20 Number with same-slice register load: 17
Number with same-slice carry load: 1 Number with same-slice carry load: 1
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1% Number of occupied Slices: 143 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355 Number of LUT Flip Flop pairs used: 479
Number with an unused Flip Flop: 46 out of 355 12% Number with an unused Flip Flop: 25 out of 479 5%
Number with an unused LUT: 91 out of 355 25% Number with an unused LUT: 278 out of 479 58%
Number of fully used LUT-FF pairs: 218 out of 355 61% Number of fully used LUT-FF pairs: 176 out of 479 36%
Number of unique control sets: 10 Number of unique control sets: 12
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 25 out of 184,304 1% to control set restrictions: 27 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -142,8 +143,8 @@ Slice Logic Distribution: ...@@ -142,8 +143,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
IO Utilization: IO Utilization:
Number of bonded IOBs: 23 out of 396 5% Number of bonded IOBs: 151 out of 396 38%
Number of LOCed IOBs: 23 out of 23 100% Number of LOCed IOBs: 151 out of 151 100%
Specific Feature Utilization: Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 268 0% Number of RAMB16BWERs: 0 out of 268 0%
...@@ -172,11 +173,11 @@ Specific Feature Utilization: ...@@ -172,11 +173,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.49 Average Fanout of Non-Clock Nets: 2.35
Peak Memory Usage: 583 MB Peak Memory Usage: 585 MB
Total REAL time to MAP completion: 21 secs Total REAL time to MAP completion: 24 secs
Total CPU time to MAP completion: 21 secs Total CPU time to MAP completion: 24 secs
Mapping completed. Mapping completed.
See MAP report file "ApplicationFpga_map.mrp" for details. See MAP report file "ApplicationFpga_map.mrp" for details.
This source diff could not be displayed because it is too large. You can view the blob instead.
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Mon Dec 20 15:24:14 2010"> <application stringID="NgdBuild" timeStamp="Tue Jan 11 11:58:35 2011">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -67,50 +67,49 @@ ...@@ -67,50 +67,49 @@
</section> </section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY"> <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="92"/> <item dataType="int" stringID="NGDBUILD_NUM_FD" value="153"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="60"/> <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="289"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="20"/> <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="20"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="147"/> <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="5"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_INV" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="64"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="15"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="5"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="206"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="75"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="15"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="62"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="4"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="16"/> <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="16"/>
</section> </section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY"> <section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="92"/> <item dataType="int" stringID="NGDBUILD_NUM_FD" value="153"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="60"/> <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="289"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="20"/> <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="20"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="147"/> <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="17"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="81"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_INV" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="15"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="5"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="206"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="75"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="15"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="15"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="62"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="72"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="4"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC32E" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DesignSummary rev="10"> <DesignSummary rev="20">
<CmdHistory> <CmdHistory>
</CmdHistory> </CmdHistory>
</DesignSummary> </DesignSummary>
C:\VFC_SVN\firmware\XilinxISE\ApplicationFpga\ApplicationFpga.ngc 1292855051 C:\VFC_SVN\firmware\XilinxISE\ApplicationFpga\ApplicationFpga.ngc 1294743511
OK OK
...@@ -8,26 +8,8 @@ ...@@ -8,26 +8,8 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<<<<<<< .mine
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/AddrDecoderWBApp.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/ApplicationFpga.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Debouncer.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Ser2MstWB.v\&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Ser2MstWB.v\&quot; into library work</arg>
</msg> </msg>
=======
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\&quot; into library work</arg>
</msg>
>>>>>>> .r43
</messages> </messages>
...@@ -6,7 +6,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\. ...@@ -6,7 +6,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\.
speed -3 speed -3
Opened constraints file ApplicationFpga.pcf. Opened constraints file ApplicationFpga.pcf.
Mon Dec 20 15:25:21 2010 Tue Jan 11 11:59:47 2011
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 ApplicationFpga.ncd C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 ApplicationFpga.ncd
......
Release 12.3 Drc M.70d (nt64) Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 15:25:21 2010 Tue Jan 11 11:59:47 2011
drc -z ApplicationFpga.ncd ApplicationFpga.pcf drc -z ApplicationFpga.ncd ApplicationFpga.pcf
......
<TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics"> <xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>396</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>655</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>1640</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>1472</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>1640</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>1472</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>1622</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>1211</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>10.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>10.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>13.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>14.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>15.6 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>17.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>21.0 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>23.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>24.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>24.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>24.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>24.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>22.2 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>24.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>22.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>24.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>7.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>13.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>0.5</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>19.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>1.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>1.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>12.2</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>19.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>13.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>15.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>40.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>4.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>7.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0180</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0102</xtag-par-property-value></TD></TR>
</xtag-section> </xtag-section>
</TABLE> </TABLE>
...@@ -16,3 +16,33 @@ WARNING:NetListWriters:306 - Signal bus i_Ser2MstWB/AckI_d31<30 : 0> on block ...@@ -16,3 +16,33 @@ WARNING:NetListWriters:306 - Signal bus i_Ser2MstWB/AckI_d31<30 : 0> on block
Writing EDIF netlist file ApplicationFpga.edif ... Writing EDIF netlist file ApplicationFpga.edif ...
ngc2edif: Total memory usage is 37440 kilobytes ngc2edif: Total memory usage is 37440 kilobytes
Release 12.3 - ngc2edif M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Reading design ApplicationFpga.ngc ...
WARNING:NetListWriters:298 - No output is written to ApplicationFpga.xncf,
ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus i_Sram2Controller/ReadCycle_d<3 : 0> on
block ApplicationFpga is not reconstructed, because there are some missing
bus signals.
WARNING:NetListWriters:306 - Signal bus i_Sram2Controller/WriteCycle_d<2 : 0> on
block ApplicationFpga is not reconstructed, because there are some missing
bus signals.
WARNING:NetListWriters:306 - Signal bus i_Sram1Controller/ReadCycle_d<3 : 0> on
block ApplicationFpga is not reconstructed, because there are some missing
bus signals.
WARNING:NetListWriters:306 - Signal bus i_Sram1Controller/WriteCycle_d<2 : 0> on
block ApplicationFpga is not reconstructed, because there are some missing
bus signals.
WARNING:NetListWriters:306 - Signal bus i_Ser2MstWB/SerCntrlIShReg_b32<31 : 0>
on block ApplicationFpga is not reconstructed, because there are some missing
bus signals.
WARNING:NetListWriters:306 - Signal bus i_Ser2MstWB/AckI_d31<30 : 0> on block
ApplicationFpga is not reconstructed, because there are some missing bus
signals.
finished :Prep
Writing EDIF netlist file ApplicationFpga.edif ...
ngc2edif: Total memory usage is 73052 kilobytes
...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information Project Information
-------------------- --------------------
ProjectID=E95F264691074EB59A186285E0ED1DCA ProjectID=E95F264691074EB59A186285E0ED1DCA
ProjectIteration=5 ProjectIteration=10
WebTalk Summary WebTalk Summary
---------------- ----------------
...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled. ...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON. INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON. INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-20T15:25:46. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2011-01-11T12:00:13. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Mon Dec 20 15:25:16 2010"> <application name="pn" timeStamp="Tue Jan 11 11:59:43 2011">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="E95F264691074EB59A186285E0ED1DCA" type="project"/> <property name="ProjectID" value="E95F264691074EB59A186285E0ED1DCA" type="project"/>
<property name="ProjectIteration" value="5" type="project"/> <property name="ProjectIteration" value="10" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xise" type="project"/> <property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-20T10:26:08" type="project"/> <property name="ProjectCreationTimestamp" value="2010-12-20T10:26:08" type="project"/>
</section> </section>
...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq ...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-20T10:26:08" type="design"/> <property name="PROP_intProjectCreationTimestamp" value="2010-12-20T10:26:08" type="design"/>
<property name="PROP_intWbtProjectID" value="E95F264691074EB59A186285E0ED1DCA" type="design"/> <property name="PROP_intWbtProjectID" value="E95F264691074EB59A186285E0ED1DCA" type="design"/>
<property name="PROP_intWbtProjectIteration" value="5" type="process"/> <property name="PROP_intWbtProjectIteration" value="10" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> <property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
...@@ -40,7 +40,7 @@ This means code written to parse this file will need to be revisited each subseq ...@@ -40,7 +40,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_DevSpeed" value="-3" type="design"/> <property name="PROP_DevSpeed" value="-3" type="design"/>
<property name="PROP_PreferredLanguage" value="Verilog" type="design"/> <property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
<property name="FILE_UCF" value="1" type="source"/> <property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_VERILOG" value="5" type="source"/> <property name="FILE_VERILOG" value="6" type="source"/>
</section> </section>
</application> </application>
</document> </document>
...@@ -57,7 +57,7 @@ NGDBUILD Design Results Summary: ...@@ -57,7 +57,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 18 Number of warnings: 18
Total memory usage is 150888 kilobytes Total memory usage is 155280 kilobytes
Writing NGD file "SFpga.ngd" ... Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec Total REAL time to NGDBUILD completion: 3 sec
......
...@@ -187,3 +187,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -187,3 +187,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Jan 06 13:57:44 2011 Tue Jan 11 12:02:01 2011
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment