Commit 6ee3e428 authored by Andrea Boccardi's avatar Andrea Boccardi

changed the clk_ik to be a proper input in Ser2MstWB

parent 265c6bd0
module Ser2MstWB (
output Rst_orq,
output Clk_ik,
input Clk_ik,
output reg Cyc_o,
output reg We_o,
output reg [20:0] Adr_ob21,
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