Commit 3887fd24 authored by Andrea Boccardi's avatar Andrea Boccardi

added the readout of some regs I forgot

parent c4f5c9f5
......@@ -28,7 +28,7 @@ module AddressDecoderWBSys(
always @(posedge Clk_ik) begin
Ack_o <= AckIntMAnager_i || AckGenericOutputRegs_i || AckGenericOutputRegs_i || AckSlv2SerWB_i || AckSpiMaster_i;
Ack_o <= AckIntMAnager_i || AckGenericOutputRegs_i || AckGenericInputRegs_i || AckSlv2SerWB_i || AckSpiMaster_i;
Dat_ob32 <= 32'h0;
StbIntManager_o <= 1'b0;
StbGenericOutputRegs_o <= 1'b0;
......
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