Commit 22a718f4 authored by Andrea Boccardi's avatar Andrea Boccardi

fixed the simulation afetr the changes needed for the ISE project

parent 23b1b4b5
`timescale 1ns/1ns
module si57x (
inout oe,
inout sda,
......@@ -5,4 +7,11 @@ module si57x (
inout clk_p,
inout clk_n);
reg Clk_s = 1'b0;
always #5 Clk_s = ~Clk_s;
assign clk_p = Clk_s;
assign clk_n = ~clk_p;
endmodule
......@@ -42,7 +42,7 @@ pullup i_Irq0(VmeIrq_b7[0]);
// VME master
//####################################
VmeMaster #(.g_VerboseAccesses(1'b0)) i_VmeMaster(
VmeMaster #(.g_VerboseAccesses(1'b1)) i_VmeMaster(
.Trst_o(VmeTrst),
.Tck_o(VmeTck),
.Tdo_i(VmeTdo),
......
......@@ -8,7 +8,7 @@ os.system('clear')
MyBoard = VFCInstance(4, 3, 4)
#StartDumping()
StartDumping()
WaitSimulation('1000')
VmeReset()
......
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