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Commit 0895a9f9 authored by Andrea Boccardi's avatar Andrea Boccardi
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rerun of ISE with added timing constraints

parent 36769977
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Showing with 1822 additions and 1456 deletions
trunk/firmware/XilinxISE/SystemFpga/SFpga.bld
View file @ 0895a9f9
...@@ -44,7 +44,7 @@ NGDBUILD Design Results Summary: ...@@ -44,7 +44,7 @@ NGDBUILD Design Results Summary:
Total memory usage is 88036 kilobytes Total memory usage is 88036 kilobytes
Writing NGD file "SFpga.ngd" ... Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 6 sec Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 5 sec Total CPU time to NGDBUILD completion: 5 sec
Writing NGDBUILD log file "SFpga.bld"... Writing NGDBUILD log file "SFpga.bld"...
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log
View file @ 0895a9f9
...@@ -58,3 +58,14 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -58,3 +58,14 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.pad
View file @ 0895a9f9
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Dec 16 18:44:09 2010 Fri Dec 17 10:02:33 2010
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
...@@ -296,7 +296,7 @@ E14||IOBS|IO_L40N_0|UNUSED||0||||||||| ...@@ -296,7 +296,7 @@ E14||IOBS|IO_L40N_0|UNUSED||0|||||||||
E15|||GND|||||||||||| E15|||GND||||||||||||
E16|VmeP0HwLowByteOe_o|IOB|IO_L49N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE| E16|VmeP0HwLowByteOe_o|IOB|IO_L49N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E17|||VCCAUX||||||||2.5|||| E17|||VCCAUX||||||||2.5||||
E18|Si57xOe_o|IOB|IO_L51N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE| E18||IOBS|IO_L51N_0|UNUSED||0|||||||||
E19|||GND|||||||||||| E19|||GND||||||||||||
E20|VmeWrite_in|IOB|IO_L57N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| E20|VmeWrite_in|IOB|IO_L57N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
E21|||VCCO_0|||0|||||3.30|||| E21|||VCCO_0|||0|||||3.30||||
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.par
View file @ 0895a9f9
Release 12.3 par M.70d (nt) Release 12.3 par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Thu Dec 16 18:43:02 2010 BQPLV2:: Fri Dec 17 10:01:26 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
...@@ -26,11 +26,11 @@ Slice Logic Utilization: ...@@ -26,11 +26,11 @@ Slice Logic Utilization:
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 917 out of 92,152 1% Number of Slice LUTs: 941 out of 92,152 1%
Number used as logic: 891 out of 92,152 1% Number used as logic: 899 out of 92,152 1%
Number using O6 output only: 571 Number using O6 output only: 587
Number using O5 output only: 154 Number using O5 output only: 154
Number using O5 and O6: 166 Number using O5 and O6: 158
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -42,17 +42,17 @@ Slice Logic Utilization: ...@@ -42,17 +42,17 @@ Slice Logic Utilization:
Number using O6 output only: 3 Number using O6 output only: 3
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 15 Number used exclusively as route-thrus: 31
Number with same-slice register load: 6 Number with same-slice register load: 22
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 371 out of 23,038 1% Number of occupied Slices: 363 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,113 Number of LUT Flip Flop pairs used: 1,084
Number with an unused Flip Flop: 382 out of 1,113 34% Number with an unused Flip Flop: 369 out of 1,084 34%
Number with an unused LUT: 196 out of 1,113 17% Number with an unused LUT: 143 out of 1,084 13%
Number of fully used LUT-FF pairs: 535 out of 1,113 48% Number of fully used LUT-FF pairs: 572 out of 1,084 52%
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0% to control set restrictions: 0 out of 184,304 0%
...@@ -63,8 +63,8 @@ Slice Logic Distribution: ...@@ -63,8 +63,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
IO Utilization: IO Utilization:
Number of bonded IOBs: 330 out of 396 83% Number of bonded IOBs: 329 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99% Number of LOCed IOBs: 327 out of 329 99%
IOB Master Pads: 2 IOB Master Pads: 2
IOB Slave Pads: 2 IOB Slave Pads: 2
...@@ -99,8 +99,8 @@ Specific Feature Utilization: ...@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High Overall effort level (-ol): High
Router effort level (-rl): High Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 24 secs Starting initial Timing Analysis. REAL time: 22 secs
Finished initial Timing Analysis. REAL time: 24 secs Finished initial Timing Analysis. REAL time: 22 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
...@@ -152,27 +152,27 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O ...@@ -152,27 +152,27 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router Starting Router
Phase 1 : 5215 unrouted; REAL time: 27 secs Phase 1 : 5204 unrouted; REAL time: 25 secs
Phase 2 : 4592 unrouted; REAL time: 34 secs Phase 2 : 4597 unrouted; REAL time: 31 secs
Phase 3 : 1753 unrouted; REAL time: 46 secs Phase 3 : 1889 unrouted; REAL time: 44 secs
Phase 4 : 1753 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 57 secs Phase 4 : 1889 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 56 secs
Updating file: SFpga.ncd with current fully routed design. Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 4 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Total REAL time to Router completion: 1 mins 4 secs Total REAL time to Router completion: 1 mins 4 secs
Total CPU time to Router completion: 1 mins 2 secs Total CPU time to Router completion: 1 mins 2 secs
...@@ -192,18 +192,18 @@ Generating Clock Report ...@@ -192,18 +192,18 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 221 | 0.247 | 1.696 | | Si57x_BUFG | BUFGMUX_X2Y4| No | 217 | 0.248 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.083 | 1.644 | | VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 | | VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 18 | 0.186 | 1.688 | | SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 15 | 0.009 | 1.515 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 217 | 0.000 | 4.055 | | i_Core/Rst_rq | Local| | 213 | 0.000 | 6.628 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | | |i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.159 | | e/stb_o | Local| | 19 | 0.000 | 4.448 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing * Net Skew is the difference between the minimum and maximum routing
...@@ -220,8 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met. ...@@ -220,8 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score | | Slack | Achievable | Errors | Score
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.189ns| 8.144ns| 0| 0 TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.399ns| 7.934ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.321ns| | 0| 0 20 MHz HIGH 50% | HOLD | 0.347ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 5.459ns| 2.874ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.459ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
...@@ -235,9 +238,9 @@ All signals are completely routed. ...@@ -235,9 +238,9 @@ All signals are completely routed.
WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 8 secs Total REAL time to PAR completion: 1 mins 8 secs
Total CPU time to PAR completion: 1 mins 6 secs Total CPU time to PAR completion: 1 mins 7 secs
Peak Memory Usage: 371 MB Peak Memory Usage: 369 MB
Placer: Placement generated during map. Placer: Placement generated during map.
Routing: Completed - No errors found. Routing: Completed - No errors found.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf
View file @ 0895a9f9
//! ************************************************************************** //! **************************************************************************
// Written by: Map M.70d on Thu Dec 16 18:42:57 2010 // Written by: Map M.70d on Fri Dec 17 10:01:22 2010
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
...@@ -255,7 +255,6 @@ COMP "DdsF_ob2<1>" LOCATE = SITE "A2" LEVEL 1; ...@@ -255,7 +255,6 @@ COMP "DdsF_ob2<1>" LOCATE = SITE "A2" LEVEL 1;
COMP "DdsDrOver_i" LOCATE = SITE "G13" LEVEL 1; COMP "DdsDrOver_i" LOCATE = SITE "G13" LEVEL 1;
COMP "PllFmc2Synch_on" LOCATE = SITE "V12" LEVEL 1; COMP "PllFmc2Synch_on" LOCATE = SITE "V12" LEVEL 1;
COMP "DdsTxEnable_o" LOCATE = SITE "G8" LEVEL 1; COMP "DdsTxEnable_o" LOCATE = SITE "G8" LEVEL 1;
COMP "Si57xOe_o" LOCATE = SITE "E18" LEVEL 1;
COMP "VmeP0BunchSelectDir_o" LOCATE = SITE "G15" LEVEL 1; COMP "VmeP0BunchSelectDir_o" LOCATE = SITE "G15" LEVEL 1;
COMP "VAdjSClk_ok" LOCATE = SITE "J2" LEVEL 1; COMP "VAdjSClk_ok" LOCATE = SITE "J2" LEVEL 1;
COMP "PllDacClrn_orn" LOCATE = SITE "Y21" LEVEL 1; COMP "PllDacClrn_orn" LOCATE = SITE "Y21" LEVEL 1;
...@@ -978,6 +977,63 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL ...@@ -978,6 +977,63 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL "i_Core/i_InterruptManager/Mram_int_fifo1_RAMC" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL "i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1" BEL
"i_Core/i_InterruptManager/Mram_int_fifo1_RAMD"; "i_Core/i_InterruptManager/Mram_int_fifo1_RAMD";
TIMEGRP SysAppClk_ik = BEL "i_Core/i_Slv2SerWB/Dat_xb32_31" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_30" BEL "i_Core/i_Slv2SerWB/Dat_xb32_29"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_28" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_27" BEL "i_Core/i_Slv2SerWB/Dat_xb32_26"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_25" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_24" BEL "i_Core/i_Slv2SerWB/Dat_xb32_23"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_22" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_21" BEL "i_Core/i_Slv2SerWB/Dat_xb32_20"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_19" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_18" BEL "i_Core/i_Slv2SerWB/Dat_xb32_17"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_16" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_15" BEL "i_Core/i_Slv2SerWB/Dat_xb32_14"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_13" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_12" BEL "i_Core/i_Slv2SerWB/Dat_xb32_11"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_10" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_9" BEL "i_Core/i_Slv2SerWB/Dat_xb32_8"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_7" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_6" BEL "i_Core/i_Slv2SerWB/Dat_xb32_5"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_4" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_3" BEL "i_Core/i_Slv2SerWB/Dat_xb32_2"
BEL "i_Core/i_Slv2SerWB/Dat_xb32_1" BEL
"i_Core/i_Slv2SerWB/Dat_xb32_0" BEL "i_Core/i_Slv2SerWB/AckI_xb3_2"
BEL "i_Core/i_Slv2SerWB/DatInShReg_b32_31" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_30" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_29" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_28" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_27" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_26" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_25" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_24" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_23" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_22" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_21" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_20" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_19" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_18" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_17" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_16" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_15" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_14" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_13" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_12" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_11" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_10" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_9" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_8" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_7" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_6" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_5" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_4" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_3" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_2" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_1" BEL
"i_Core/i_Slv2SerWB/DatInShReg_b32_0" BEL
"i_Core/i_Slv2SerWB/AckI_d3_2" BEL "i_Core/i_Slv2SerWB/AckI_d3_1" BEL
"i_Core/i_Slv2SerWB/AckI_d3_0" BEL "SysAppClk_ik_BUFGP/BUFG";
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%; TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
SCHEMATIC END; SCHEMATIC END;
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx
View file @ 0895a9f9
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.189" best="8.144" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.321" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.399" best="7.934" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.347" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="5.459" best="2.874" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.459" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.syr
View file @ 0895a9f9
...@@ -10,7 +10,7 @@ Total CPU time to Xst completion: 0.16 secs ...@@ -10,7 +10,7 @@ Total CPU time to Xst completion: 0.16 secs
Total REAL time to Xst completion: 0.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs Total CPU time to Xst completion: 0.16 secs
--> Reading design: SFpga.prj --> Reading design: SFpga.prj
...@@ -303,6 +303,7 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc ...@@ -303,6 +303,7 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
Found 1-bit tristate buffer for signal <DdrDQ_iob16<1>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<1>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 315 Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 315
Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 338 Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 338
Found 1-bit tristate buffer for signal <Si57xOe_o> created at line 339
Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 347 Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 347
Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 374 Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 374
Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 375 Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 375
...@@ -319,7 +320,7 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc ...@@ -319,7 +320,7 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
inferred 3 Adder/Subtractor(s). inferred 3 Adder/Subtractor(s).
inferred 69 D-type flip-flop(s). inferred 69 D-type flip-flop(s).
inferred 1 Multiplexer(s). inferred 1 Multiplexer(s).
inferred 33 Tristate(s). inferred 34 Tristate(s).
Unit <SystemFpga> synthesized. Unit <SystemFpga> synthesized.
Synthesizing Unit <Monostable>. Synthesizing Unit <Monostable>.
...@@ -329,7 +330,7 @@ Synthesizing Unit <Monostable>. ...@@ -329,7 +330,7 @@ Synthesizing Unit <Monostable>.
Found 20-bit register for signal <Counter_c>. Found 20-bit register for signal <Counter_c>.
Found 1-bit register for signal <SynchOutput_oq>. Found 1-bit register for signal <SynchOutput_oq>.
Found 1-bit register for signal <AsynchIn_ax>. Found 1-bit register for signal <AsynchIn_ax>.
Found 20-bit adder for signal <Counter_c[19]_GND_25_o_add_6_OUT> created at line 20. Found 20-bit adder for signal <Counter_c[19]_GND_26_o_add_6_OUT> created at line 20.
Summary: Summary:
inferred 1 Adder/Subtractor(s). inferred 1 Adder/Subtractor(s).
inferred 25 D-type flip-flop(s). inferred 25 D-type flip-flop(s).
...@@ -343,7 +344,7 @@ Synthesizing Unit <Debouncer>. ...@@ -343,7 +344,7 @@ Synthesizing Unit <Debouncer>.
Found 16-bit register for signal <Counter_c>. Found 16-bit register for signal <Counter_c>.
Found 1-bit register for signal <DebouncedSignal_oq>. Found 1-bit register for signal <DebouncedSignal_oq>.
Found 3-bit register for signal <BouncingSignal_x>. Found 3-bit register for signal <BouncingSignal_x>.
Found 16-bit adder for signal <Counter_c[15]_GND_34_o_add_7_OUT> created at line 38. Found 16-bit adder for signal <Counter_c[15]_GND_35_o_add_7_OUT> created at line 38.
Found 1-bit comparator equal for signal <n0003> created at line 31 Found 1-bit comparator equal for signal <n0003> created at line 31
Summary: Summary:
inferred 1 Adder/Subtractor(s). inferred 1 Adder/Subtractor(s).
...@@ -393,9 +394,9 @@ Synthesizing Unit <VmeInterfaceWB>. ...@@ -393,9 +394,9 @@ Synthesizing Unit <VmeInterfaceWB>.
| Encoding | auto | | Encoding | auto |
| Implementation | LUT | | Implementation | LUT |
----------------------------------------------------------------------- -----------------------------------------------------------------------
Found 9-bit adder for signal <AckTimeout_c[8]_GND_35_o_add_16_OUT> created at line 100. Found 9-bit adder for signal <AckTimeout_c[8]_GND_36_o_add_16_OUT> created at line 100.
Found 22-bit adder for signal <adr_o[21]_GND_35_o_add_48_OUT> created at line 200. Found 22-bit adder for signal <adr_o[21]_GND_36_o_add_48_OUT> created at line 200.
Found 1-bit 4-to-1 multiplexer for signal <_n0284> created at line 148. Found 1-bit 4-to-1 multiplexer for signal <_n0291> created at line 148.
Found 1-bit 4-to-1 multiplexer for signal <_n0316> created at line 148. Found 1-bit 4-to-1 multiplexer for signal <_n0316> created at line 148.
Found 1-bit tristate buffer for signal <vme_data<31>> created at line 110 Found 1-bit tristate buffer for signal <vme_data<31>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<30>> created at line 110 Found 1-bit tristate buffer for signal <vme_data<30>> created at line 110
...@@ -429,7 +430,7 @@ Synthesizing Unit <VmeInterfaceWB>. ...@@ -429,7 +430,7 @@ Synthesizing Unit <VmeInterfaceWB>.
Found 1-bit tristate buffer for signal <vme_data<2>> created at line 110 Found 1-bit tristate buffer for signal <vme_data<2>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<1>> created at line 110 Found 1-bit tristate buffer for signal <vme_data<1>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<0>> created at line 110 Found 1-bit tristate buffer for signal <vme_data<0>> created at line 110
Found 8-bit comparator equal for signal <VmeBaseAddr[7]_GND_35_o_equal_12_o> created at line 75 Found 8-bit comparator equal for signal <VmeBaseAddr[7]_GND_36_o_equal_12_o> created at line 75
Found 3-bit comparator equal for signal <vme_addr[3]_intlev_reg[2]_equal_43_o> created at line 178 Found 3-bit comparator equal for signal <vme_addr[3]_intlev_reg[2]_equal_43_o> created at line 178
Summary: Summary:
inferred 2 Adder/Subtractor(s). inferred 2 Adder/Subtractor(s).
...@@ -461,10 +462,10 @@ WARNING:Xst:647 - Input <Dat_ib32<30:11>> is never used. This port will be prese ...@@ -461,10 +462,10 @@ WARNING:Xst:647 - Input <Dat_ib32<30:11>> is never used. This port will be prese
Found 1-bit register for signal <fifo_empty>. Found 1-bit register for signal <fifo_empty>.
Found 1-bit register for signal <Stb_d>. Found 1-bit register for signal <Stb_d>.
Found 1-bit register for signal <osc_clk>. Found 1-bit register for signal <osc_clk>.
Found 4-bit subtractor for signal <int_counter[3]_GND_68_o_sub_23_OUT> created at line 101. Found 4-bit subtractor for signal <int_counter[3]_GND_69_o_sub_23_OUT> created at line 101.
Found 4-bit adder for signal <int_counter[3]_GND_68_o_add_20_OUT> created at line 99. Found 4-bit adder for signal <int_counter[3]_GND_69_o_add_20_OUT> created at line 99.
Found 3-bit adder for signal <int_pointer_w[2]_GND_68_o_add_29_OUT> created at line 115. Found 3-bit adder for signal <int_pointer_w[2]_GND_69_o_add_29_OUT> created at line 115.
Found 3-bit adder for signal <int_pointer_r[2]_GND_68_o_add_31_OUT> created at line 118. Found 3-bit adder for signal <int_pointer_r[2]_GND_69_o_add_31_OUT> created at line 118.
Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 165. Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 165.
Found 3-bit comparator equal for signal <int_pointer_w[2]_int_pointer_r[2]_equal_42_o> created at line 132 Found 3-bit comparator equal for signal <int_pointer_w[2]_int_pointer_r[2]_equal_42_o> created at line 132
Found 3-bit comparator equal for signal <n0078> created at line 134 Found 3-bit comparator equal for signal <n0078> created at line 134
...@@ -587,8 +588,8 @@ Synthesizing Unit <SpiMasterWB>. ...@@ -587,8 +588,8 @@ Synthesizing Unit <SpiMasterWB>.
| Encoding | auto | | Encoding | auto |
| Implementation | LUT | | Implementation | LUT |
----------------------------------------------------------------------- -----------------------------------------------------------------------
Found 12-bit adder for signal <TxCounter_cb12[11]_GND_77_o_add_40_OUT> created at line 138. Found 12-bit adder for signal <TxCounter_cb12[11]_GND_78_o_add_40_OUT> created at line 138.
Found 16-bit adder for signal <TimeCounter_cb16[15]_GND_77_o_add_67_OUT> created at line 163. Found 16-bit adder for signal <TimeCounter_cb16[15]_GND_78_o_add_67_OUT> created at line 163.
Found 1-bit 32-to-1 multiplexer for signal <a_SpiChannel_b5[4]_MiSo_ib32[31]_Mux_56_o> created at line 150. Found 1-bit 32-to-1 multiplexer for signal <a_SpiChannel_b5[4]_MiSo_ib32[31]_Mux_56_o> created at line 150.
Found 32-bit 7-to-1 multiplexer for signal <Dat_oab32> created at line 185. Found 32-bit 7-to-1 multiplexer for signal <Dat_oab32> created at line 185.
Found 16-bit comparator equal for signal <TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o> created at line 77 Found 16-bit comparator equal for signal <TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o> created at line 77
...@@ -649,8 +650,8 @@ Macro Statistics ...@@ -649,8 +650,8 @@ Macro Statistics
5-bit 2-to-1 multiplexer : 1 5-bit 2-to-1 multiplexer : 1
7-bit 2-to-1 multiplexer : 1 7-bit 2-to-1 multiplexer : 1
9-bit 2-to-1 multiplexer : 1 9-bit 2-to-1 multiplexer : 1
# Tristates : 65 # Tristates : 66
1-bit tristate buffer : 65 1-bit tristate buffer : 66
# FSMs : 2 # FSMs : 2
# Xors : 4 # Xors : 4
1-bit xor3 : 2 1-bit xor3 : 2
...@@ -901,9 +902,9 @@ Primitive and Black Box Usage: ...@@ -901,9 +902,9 @@ Primitive and Black Box Usage:
# IBUFGDS : 6 # IBUFGDS : 6
# IOBUF : 32 # IOBUF : 32
# IOBUFDS : 2 # IOBUFDS : 2
# OBUF : 152 # OBUF : 151
# OBUFDS : 3 # OBUFDS : 3
# OBUFT : 33 # OBUFT : 34
Device utilization summary: Device utilization summary:
--------------------------- ---------------------------
...@@ -996,8 +997,8 @@ Delay: 8.328ns (Levels of Logic = 5) ...@@ -996,8 +997,8 @@ Delay: 8.328ns (Levels of Logic = 5)
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
FDRE:C->Q 2 0.525 1.047 i_Core/i_VmeInterface/adr_o_21_1 (i_Core/i_VmeInterface/adr_o_21_1) FDRE:C->Q 2 0.525 1.047 i_Core/i_VmeInterface/adr_o_21_1 (i_Core/i_VmeInterface/adr_o_21_1)
LUT6:I1->O 4 0.254 0.912 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o13 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12) LUT6:I1->O 4 0.254 0.912 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o13 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o12)
LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1) LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_4_o1)
LUT5:I3->O 5 0.250 0.715 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster) LUT5:I3->O 5 0.250 0.715 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster)
LUT6:I5->O 58 0.254 1.601 i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster) LUT6:I5->O 58 0.254 1.601 i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster)
LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o) LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o)
...@@ -1175,8 +1176,8 @@ Offset: 8.362ns (Levels of Logic = 6) ...@@ -1175,8 +1176,8 @@ Offset: 8.362ns (Levels of Logic = 6)
---------------------------------------- ------------ ---------------------------------------- ------------
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF) IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.943 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error) LUT6:I1->O 5 0.254 0.943 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o311 (N5) LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o311 (N5)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N259) LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o87_SW0 (N259)
LUT6:I3->O 12 0.235 0.909 i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected) LUT6:I3->O 12 0.235 0.909 i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected)
LUT5:I4->O 24 0.254 1.172 i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv) LUT5:I4->O 24 0.254 1.172 i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv)
FDRE:CE 0.302 i_Core/i_VmeInterface/adr_o_0 FDRE:CE 0.302 i_Core/i_VmeInterface/adr_o_0
...@@ -1343,12 +1344,12 @@ i_Core/i_VmeInterface/stb_o| 2.049| | | | ...@@ -1343,12 +1344,12 @@ i_Core/i_VmeInterface/stb_o| 2.049| | | |
========================================================================= =========================================================================
Total REAL time to Xst completion: 28.00 secs Total REAL time to Xst completion: 27.00 secs
Total CPU time to Xst completion: 28.30 secs Total CPU time to Xst completion: 26.61 secs
--> -->
Total memory usage is 154916 kilobytes Total memory usage is 154724 kilobytes
Number of errors : 0 ( 0 filtered) Number of errors : 0 ( 0 filtered)
Number of warnings : 126 ( 0 filtered) Number of warnings : 126 ( 0 filtered)
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.twx
View file @ 0895a9f9
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.ucf
View file @ 0895a9f9
...@@ -696,3 +696,6 @@ NET "VmeSysClk_ik" CLOCK_DEDICATED_ROUTE = "FALSE"; ...@@ -696,3 +696,6 @@ NET "VmeSysClk_ik" CLOCK_DEDICATED_ROUTE = "FALSE";
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/16 #Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/16
NET "Si57x_ik" TNM_NET = "Si57x_ik"; NET "Si57x_ik" TNM_NET = "Si57x_ik";
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 120 MHz HIGH 50 %; TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 120 MHz HIGH 50 %;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/17
NET "SysAppClk_ik" TNM_NET = SysAppClk_ik;
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50%;
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes
View file @ 0895a9f9
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Dec 16 18:44:10 2010 Fri Dec 17 10:02:34 2010
All signals are completely routed. All signals are completely routed.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.map
View file @ 0895a9f9
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Thu Dec 16 18:41:28 2010 Mapped Date : Fri Dec 17 09:59:57 2010
Mapping design into LUTs... Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
...@@ -79,6 +79,8 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io ...@@ -79,6 +79,8 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed. has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed. has been removed.
WARNING:MapLib:701 - Signal Si57xOe_o connected to top level port Si57xOe_o has
been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed. AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
...@@ -89,20 +91,20 @@ Updating timing models... ...@@ -89,20 +91,20 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 28 secs Total REAL time at the beginning of Placer: 26 secs
Total CPU time at the beginning of Placer: 26 secs Total CPU time at the beginning of Placer: 26 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:fbd9bf1c) REAL time: 36 secs Phase 1.1 Initial Placement Analysis (Checksum:f1e9a8bb) REAL time: 34 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 329 IOs, 327 are locked
and 2 are not locked. If you would like to print the names of these IOs, and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:fbd9bf1c) REAL time: 36 secs Phase 2.7 Design Feasibility Check (Checksum:f1e9a8bb) REAL time: 34 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:fbd9bf1c) REAL time: 36 secs Phase 3.31 Local Placement Optimization (Checksum:f1e9a8bb) REAL time: 34 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
... ...
...@@ -120,42 +122,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found ...@@ -120,42 +122,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
discouraged as it may lead to very poor timing results. It is recommended discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design. that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:b9a90c54) REAL time: 50 secs (Checksum:2c046bcb) REAL time: 47 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:b9a90c54) REAL time: 50 secs Phase 5.36 Local Placement Optimization (Checksum:2c046bcb) REAL time: 47 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:b9a90c54) REAL time: 50 secs Phase 6.30 Global Clock Region Assignment (Checksum:2c046bcb) REAL time: 47 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
... ...
Phase 7.3 Local Placement Optimization (Checksum:5a4374ed) REAL time: 52 secs Phase 7.3 Local Placement Optimization (Checksum:e20e3683) REAL time: 48 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:b9b9c566) REAL time: 52 secs Phase 8.5 Local Placement Optimization (Checksum:2c14b62b) REAL time: 49 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
........... .............
................ ................
.............................. .......................
..... .....
Phase 9.8 Global Placement (Checksum:1b243f66) REAL time: 1 mins 3 secs Phase 9.8 Global Placement (Checksum:ae7774fb) REAL time: 1 mins
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:1b243f66) REAL time: 1 mins 3 secs Phase 10.5 Local Placement Optimization (Checksum:ae7774fb) REAL time: 1 mins 1 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:3389a4d6) REAL time: 1 mins 18 secs Phase 11.18 Placement Optimization (Checksum:fe895bce) REAL time: 1 mins 14 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:3389a4d6) REAL time: 1 mins 18 secs Phase 12.5 Local Placement Optimization (Checksum:fe895bce) REAL time: 1 mins 14 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:bed3755b) REAL time: 1 mins 19 secs Phase 13.34 Placement Validation (Checksum:b38174ec) REAL time: 1 mins 14 secs
Total REAL time to Placer completion: 1 mins 28 secs Total REAL time to Placer completion: 1 mins 23 secs
Total CPU time to Placer completion: 1 mins 24 secs Total CPU time to Placer completion: 1 mins 22 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
...@@ -259,18 +261,18 @@ Design Summary ...@@ -259,18 +261,18 @@ Design Summary
Design Summary: Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 83 Number of warnings: 84
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 796
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 917 out of 92,152 1% Number of Slice LUTs: 941 out of 92,152 1%
Number used as logic: 891 out of 92,152 1% Number used as logic: 899 out of 92,152 1%
Number using O6 output only: 571 Number using O6 output only: 587
Number using O5 output only: 154 Number using O5 output only: 154
Number using O5 and O6: 166 Number using O5 and O6: 158
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -282,17 +284,17 @@ Slice Logic Utilization: ...@@ -282,17 +284,17 @@ Slice Logic Utilization:
Number using O6 output only: 3 Number using O6 output only: 3
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 15 Number used exclusively as route-thrus: 31
Number with same-slice register load: 6 Number with same-slice register load: 22
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 371 out of 23,038 1% Number of occupied Slices: 363 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,113 Number of LUT Flip Flop pairs used: 1,084
Number with an unused Flip Flop: 382 out of 1,113 34% Number with an unused Flip Flop: 369 out of 1,084 34%
Number with an unused LUT: 196 out of 1,113 17% Number with an unused LUT: 143 out of 1,084 13%
Number of fully used LUT-FF pairs: 535 out of 1,113 48% Number of fully used LUT-FF pairs: 572 out of 1,084 52%
Number of unique control sets: 32 Number of unique control sets: 32
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1% to control set restrictions: 85 out of 184,304 1%
...@@ -304,8 +306,8 @@ Slice Logic Distribution: ...@@ -304,8 +306,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
IO Utilization: IO Utilization:
Number of bonded IOBs: 330 out of 396 83% Number of bonded IOBs: 329 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99% Number of LOCed IOBs: 327 out of 329 99%
IOB Master Pads: 2 IOB Master Pads: 2
IOB Slave Pads: 2 IOB Slave Pads: 2
...@@ -336,11 +338,11 @@ Specific Feature Utilization: ...@@ -336,11 +338,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02 Average Fanout of Non-Clock Nets: 3.03
Peak Memory Usage: 406 MB Peak Memory Usage: 406 MB
Total REAL time to MAP completion: 1 mins 31 secs Total REAL time to MAP completion: 1 mins 26 secs
Total CPU time to MAP completion: 1 mins 28 secs Total CPU time to MAP completion: 1 mins 25 secs
Mapping completed. Mapping completed.
See MAP report file "SFpga_map.mrp" for details. See MAP report file "SFpga_map.mrp" for details.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.mrp
View file @ 0895a9f9
...@@ -10,23 +10,23 @@ Target Device : xc6slx150t ...@@ -10,23 +10,23 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Thu Dec 16 18:41:28 2010 Mapped Date : Fri Dec 17 09:59:57 2010
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 83 Number of warnings: 84
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 796
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 917 out of 92,152 1% Number of Slice LUTs: 941 out of 92,152 1%
Number used as logic: 891 out of 92,152 1% Number used as logic: 899 out of 92,152 1%
Number using O6 output only: 571 Number using O6 output only: 587
Number using O5 output only: 154 Number using O5 output only: 154
Number using O5 and O6: 166 Number using O5 and O6: 158
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
...@@ -38,17 +38,17 @@ Slice Logic Utilization: ...@@ -38,17 +38,17 @@ Slice Logic Utilization:
Number using O6 output only: 3 Number using O6 output only: 3
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 15 Number used exclusively as route-thrus: 31
Number with same-slice register load: 6 Number with same-slice register load: 22
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 371 out of 23,038 1% Number of occupied Slices: 363 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,113 Number of LUT Flip Flop pairs used: 1,084
Number with an unused Flip Flop: 382 out of 1,113 34% Number with an unused Flip Flop: 369 out of 1,084 34%
Number with an unused LUT: 196 out of 1,113 17% Number with an unused LUT: 143 out of 1,084 13%
Number of fully used LUT-FF pairs: 535 out of 1,113 48% Number of fully used LUT-FF pairs: 572 out of 1,084 52%
Number of unique control sets: 32 Number of unique control sets: 32
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1% to control set restrictions: 85 out of 184,304 1%
...@@ -60,8 +60,8 @@ Slice Logic Distribution: ...@@ -60,8 +60,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
IO Utilization: IO Utilization:
Number of bonded IOBs: 330 out of 396 83% Number of bonded IOBs: 329 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99% Number of LOCed IOBs: 327 out of 329 99%
IOB Master Pads: 2 IOB Master Pads: 2
IOB Slave Pads: 2 IOB Slave Pads: 2
...@@ -92,11 +92,11 @@ Specific Feature Utilization: ...@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02 Average Fanout of Non-Clock Nets: 3.03
Peak Memory Usage: 406 MB Peak Memory Usage: 406 MB
Total REAL time to MAP completion: 1 mins 31 secs Total REAL time to MAP completion: 1 mins 26 secs
Total CPU time to MAP completion: 1 mins 28 secs Total CPU time to MAP completion: 1 mins 25 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -185,6 +185,8 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io ...@@ -185,6 +185,8 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed. has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed. has been removed.
WARNING:MapLib:701 - Signal Si57xOe_o connected to top level port Si57xOe_o has
been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed. AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
...@@ -318,16 +320,16 @@ INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to ...@@ -318,16 +320,16 @@ INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts) 1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 329 IOs, 327 are locked
and 2 are not locked. If you would like to print the names of these IOs, and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
INFO:Pack:1650 - Map created a placed design. INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary Section 4 - Removed Logic Summary
--------------------------------- ---------------------------------
67 block(s) removed 69 block(s) removed
2 block(s) optimized away 2 block(s) optimized away
37 signal(s) removed 38 signal(s) removed
Section 5 - Removed Logic Section 5 - Removed Logic
------------------------- -------------------------
...@@ -409,6 +411,8 @@ The signal "DdrDQ_iob16<0>" is unused and has been removed. ...@@ -409,6 +411,8 @@ The signal "DdrDQ_iob16<0>" is unused and has been removed.
Unused block "DdrDQ_iob16_0_OBUFT" (TRI) removed. Unused block "DdrDQ_iob16_0_OBUFT" (TRI) removed.
The signal "Si57xSDa_io" is unused and has been removed. The signal "Si57xSDa_io" is unused and has been removed.
Unused block "Si57xSDa_io_OBUFT" (TRI) removed. Unused block "Si57xSDa_io_OBUFT" (TRI) removed.
The signal "Si57xOe_o" is unused and has been removed.
Unused block "Si57xOe_o_OBUFT" (TRI) removed.
The signal "AFpgaProgDone_io" is unused and has been removed. The signal "AFpgaProgDone_io" is unused and has been removed.
Unused block "AFpgaProgDone_io_OBUFT" (TRI) removed. Unused block "AFpgaProgDone_io_OBUFT" (TRI) removed.
The signal "AFpgaProgProgram_o" is unused and has been removed. The signal "AFpgaProgProgram_o" is unused and has been removed.
...@@ -447,6 +451,7 @@ Unused block "DdsIOUpdate_io" (PAD) removed. ...@@ -447,6 +451,7 @@ Unused block "DdsIOUpdate_io" (PAD) removed.
Unused block "Fmc1SDa_io" (PAD) removed. Unused block "Fmc1SDa_io" (PAD) removed.
Unused block "Fmc2SDa_io" (PAD) removed. Unused block "Fmc2SDa_io" (PAD) removed.
Unused block "Sfp2ModeDef2_io" (PAD) removed. Unused block "Sfp2ModeDef2_io" (PAD) removed.
Unused block "Si57xOe_o" (PAD) removed.
Unused block "Si57xSDa_io" (PAD) removed. Unused block "Si57xSDa_io" (PAD) removed.
Unused block "VAdjInhibit_ozn" (PAD) removed. Unused block "VAdjInhibit_ozn" (PAD) removed.
Unused block "WRModeDef2_io" (PAD) removed. Unused block "WRModeDef2_io" (PAD) removed.
...@@ -652,7 +657,6 @@ Section 6 - IOB Properties ...@@ -652,7 +657,6 @@ Section 6 - IOB Properties
| Sfp2RateSelect | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | Sfp2RateSelect | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sfp2TxDisable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | Sfp2TxDisable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sfp2TxFault_i | IOB | INPUT | LVCMOS33 | | | | | | | | Sfp2TxFault_i | IOB | INPUT | LVCMOS33 | | | | | | |
| Si57xOe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Si57xSCl_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | Si57xSCl_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Si57x_ik | IOB | INPUT | LVDS_33 | TRUE | | | | | | | Si57x_ik | IOB | INPUT | LVDS_33 | TRUE | | | | | |
| Si57x_ikn | IOB | INPUT | LVDS_33 | TRUE | | | | | | | Si57x_ikn | IOB | INPUT | LVDS_33 | TRUE | | | | | |
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_ngdbuild.xrpt
View file @ 0895a9f9
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Thu Dec 16 18:41:24 2010"> <application stringID="NgdBuild" timeStamp="Fri Dec 17 09:59:56 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -93,9 +93,9 @@ ...@@ -93,9 +93,9 @@
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="151"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="33"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
...@@ -125,9 +125,9 @@ ...@@ -125,9 +125,9 @@
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="151"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="65"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="66"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv
View file @ 0895a9f9
#Release 12.3 - par M.70d (nt) #Release 12.3 - par M.70d (nt)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Thu Dec 16 18:44:09 2010 #Fri Dec 17 10:02:33 2010
# #
## NOTE: This file is designed to be imported into a spreadsheet program ## NOTE: This file is designed to be imported into a spreadsheet program
...@@ -296,7 +296,7 @@ E14,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,, ...@@ -296,7 +296,7 @@ E14,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,,
E15,,,GND,,,,,,,,,,,, E15,,,GND,,,,,,,,,,,,
E16,VmeP0HwLowByteOe_o,IOB,IO_L49N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE, E16,VmeP0HwLowByteOe_o,IOB,IO_L49N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E17,,,VCCAUX,,,,,,,,2.5,,,, E17,,,VCCAUX,,,,,,,,2.5,,,,
E18,Si57xOe_o,IOB,IO_L51N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE, E18,,IOBS,IO_L51N_0,UNUSED,,0,,,,,,,,,
E19,,,GND,,,,,,,,,,,, E19,,,GND,,,,,,,,,,,,
E20,VmeWrite_in,IOB,IO_L57N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, E20,VmeWrite_in,IOB,IO_L57N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
E21,,,VCCO_0,,,0,,,,,3.30,,,, E21,,,VCCO_0,,,0,,,,,3.30,,,,
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt
View file @ 0895a9f9
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Dec 16 18:44:10 2010 Fri Dec 17 10:02:34 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
...@@ -297,7 +297,7 @@ Pinout by Pin Number: ...@@ -297,7 +297,7 @@ Pinout by Pin Number:
|E15 | | |GND | | | | | | | | | | | | |E15 | | |GND | | | | | | | | | | | |
|E16 |VmeP0HwLowByteOe_o |IOB |IO_L49N_0 |OUTPUT |LVCMOS33 |0 |12 | | | | |LOCATED |NO |NONE | |E16 |VmeP0HwLowByteOe_o |IOB |IO_L49N_0 |OUTPUT |LVCMOS33 |0 |12 | | | | |LOCATED |NO |NONE |
|E17 | | |VCCAUX | | | | | | | |2.5 | | | | |E17 | | |VCCAUX | | | | | | | |2.5 | | | |
|E18 |Si57xOe_o |IOB |IO_L51N_0 |OUTPUT |LVCMOS33 |0 |12 | | | | |LOCATED |NO |NONE | |E18 | |IOBS |IO_L51N_0 |UNUSED | |0 | | | | | | | | |
|E19 | | |GND | | | | | | | | | | | | |E19 | | |GND | | | | | | | | | | | |
|E20 |VmeWrite_in |IOB |IO_L57N_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | |E20 |VmeWrite_in |IOB |IO_L57N_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE |
|E21 | | |VCCO_0 | | |0 | | | | |3.30 | | | | |E21 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_par.xrpt
View file @ 0895a9f9
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Thu Dec 16 18:43:24 2010"> <application stringID="par" timeStamp="Fri Dec 17 10:01:46 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -68,7 +68,7 @@ ...@@ -68,7 +68,7 @@
<item dataType="int" stringID="PAR_UNROUTES" value="0"/> <item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/> <item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="1 mins 8 secs "/> <item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="1 mins 8 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="1 mins 6 secs "/> <item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="1 mins 7 secs "/>
</section> </section>
</task> </task>
<task stringID="PAR_par"> <task stringID="PAR_par">
...@@ -87,8 +87,8 @@ ...@@ -87,8 +87,8 @@
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/> <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/>
<item label="Locked" stringID="LOCKED" value="No"/> <item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="221.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="217.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.247000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.248000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.696000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.696000"/>
</row> </row>
<row stringID="row" value="2"> <row stringID="row" value="2">
...@@ -114,17 +114,17 @@ ...@@ -114,17 +114,17 @@
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/> <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/>
<item label="Locked" stringID="LOCKED" value="No"/> <item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="18.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="15.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.186000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.009000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.688000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.515000"/>
</row> </row>
<row stringID="row" value="5"> <row stringID="row" value="5">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/Rst_rq"/> <item label="Clock Net" stringID="CLOCK_NET" value="i_Core/Rst_rq"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/> <item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="217.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="213.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.055000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="6.628000"/>
</row> </row>
<row stringID="row" value="6"> <row stringID="row" value="6">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/stb_o"/> <item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/stb_o"/>
...@@ -132,7 +132,7 @@ ...@@ -132,7 +132,7 @@
<item label="Resource" stringID="RESOURCE" value="Local"/> <item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="19.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="19.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.159000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.448000"/>
</row> </row>
</table> </table>
</section> </section>
...@@ -2469,16 +2469,10 @@ ...@@ -2469,16 +2469,10 @@
</row> </row>
<row stringID="row" value="278"> <row stringID="row" value="278">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="E18"/> <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="E18"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="Si57xOe_o"/> <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L51N_0"/> <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L51N_0"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="UNUSED"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/> <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row> </row>
<row stringID="row" value="279"> <row stringID="row" value="279">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="E19"/> <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="E19"/>
...@@ -6285,7 +6279,7 @@ ...@@ -6285,7 +6279,7 @@
</task> </task>
</application> </application>
<application stringID="Par" timeStamp="Thu Dec 16 18:43:24 2010"> <application stringID="Par" timeStamp="Fri Dec 17 10:01:47 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -6341,10 +6335,10 @@ ...@@ -6341,10 +6335,10 @@
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="917"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="941">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="154"/> <item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="154"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="571"/> <item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="587"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="166"/> <item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="158"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
...@@ -6358,25 +6352,25 @@ ...@@ -6358,25 +6352,25 @@
<item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="3"/> <item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="3"/>
<item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="9"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="9"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="6"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="22"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="6"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="22"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="9"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="9"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item> </item>
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="371"> <item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="363">
<item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="70"/> <item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="70"/>
<item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/> <item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="297"/> <item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="289"/>
</item> </item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1113"> <item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1084">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="382"/> <item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="369"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="196"/> <item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="143"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="535"/> <item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="572"/>
</item> </item>
</section> </section>
<section stringID="PAR_IOB_REPORTING"> <section stringID="PAR_IOB_REPORTING">
<item AVAILABLE="396" dataType="int" stringID="PAR_AGG_BONDED_IO" value="330"/> <item AVAILABLE="396" dataType="int" stringID="PAR_AGG_BONDED_IO" value="329"/>
<item AVAILABLE="180" dataType="int" stringID="PAR_AGG_UNBONDED_IO" value="0"/> <item AVAILABLE="180" dataType="int" stringID="PAR_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_FF" value="0"/> <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_LATCH" value="0"/> <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_LATCH" value="0"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml
View file @ 0895a9f9
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DesignSummary rev="9"> <DesignSummary rev="13">
<CmdHistory> <CmdHistory>
</CmdHistory> </CmdHistory>
</DesignSummary> </DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_xst.xrpt
View file @ 0895a9f9
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Thu Dec 16 18:40:47 2010"> <application stringID="Xst" timeStamp="Fri Dec 17 09:49:53 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
...@@ -137,8 +137,8 @@ ...@@ -137,8 +137,8 @@
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/> <item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="1"/> <item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_TRISTATES" value="65"> <item dataType="int" stringID="XST_TRISTATES" value="66">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="65"/> <item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="66"/>
</item> </item>
<item dataType="int" stringID="XST_FSMS" value="2"/> <item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_XORS" value="4"> <item dataType="int" stringID="XST_XORS" value="4">
...@@ -233,8 +233,8 @@ ...@@ -233,8 +233,8 @@
<item dataType="int" stringID="XST_IO_BUFFERS" value="305"> <item dataType="int" stringID="XST_IO_BUFFERS" value="305">
<item dataType="int" stringID="XST_IBUF" value="77"/> <item dataType="int" stringID="XST_IBUF" value="77"/>
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="32"/> <item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="32"/>
<item dataType="int" stringID="XST_OBUF" value="152"/> <item dataType="int" stringID="XST_OBUF" value="151"/>
<item dataType="int" stringID="XST_OBUFT" value="33"/> <item dataType="int" stringID="XST_OBUFT" value="34"/>
</item> </item>
</section> </section>
</section> </section>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.gise
View file @ 0895a9f9
...@@ -81,6 +81,7 @@ ...@@ -81,6 +81,7 @@
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1292421807" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1292421807"> <transform xil_pn:end_ts="1292421807" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1292421807">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292421807" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6605284883178938042" xil_pn:start_ts="1292421807"> <transform xil_pn:end_ts="1292421807" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6605284883178938042" xil_pn:start_ts="1292421807">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
...@@ -106,7 +107,7 @@ ...@@ -106,7 +107,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292521276" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292521245"> <transform xil_pn:end_ts="1292575819" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292575791">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -124,11 +125,11 @@ ...@@ -124,11 +125,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1292520620" xil_pn:in_ck="119863998498621" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4066557905353815859" xil_pn:start_ts="1292520620"> <transform xil_pn:end_ts="1292576389" xil_pn:in_ck="119863998498621" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4066557905353815859" xil_pn:start_ts="1292576389">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292521285" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292521276"> <transform xil_pn:end_ts="1292576396" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292576389">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -138,7 +139,7 @@ ...@@ -138,7 +139,7 @@
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292521380" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292521285"> <transform xil_pn:end_ts="1292576485" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292576396">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -152,7 +153,7 @@ ...@@ -152,7 +153,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/> <outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292521476" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292521380"> <transform xil_pn:end_ts="1292576581" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292576485">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -167,7 +168,7 @@ ...@@ -167,7 +168,7 @@
<outfile xil_pn:name="SFpga_par.xrpt"/> <outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292521527" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292521476"> <transform xil_pn:end_ts="1292576632" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292576581">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -190,7 +191,7 @@ ...@@ -190,7 +191,7 @@
<status xil_pn:value="InputRemoved"/> <status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/> <status xil_pn:value="OutputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1292521476" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292521451"> <transform xil_pn:end_ts="1292576581" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292576556">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SFpga.twr"/> <outfile xil_pn:name="SFpga.twr"/>
...@@ -208,7 +209,7 @@ ...@@ -208,7 +209,7 @@
<outfile xil_pn:name="SFpga_preroute.twx"/> <outfile xil_pn:name="SFpga_preroute.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292518697" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1292518697"> <transform xil_pn:end_ts="1292576356" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1292576356">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
......
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst
View file @ 0895a9f9
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292521275 C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292575819
OK OK
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/map.xmsgs
View file @ 0895a9f9
...@@ -119,6 +119,9 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please ...@@ -119,6 +119,9 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Fmc2SDa_io</arg> connected to top level port <arg fmt="%s" index="2">Fmc2SDa_io</arg> has been removed. <msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Fmc2SDa_io</arg> connected to top level port <arg fmt="%s" index="2">Fmc2SDa_io</arg> has been removed.
</msg> </msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Si57xOe_o</arg> connected to top level port <arg fmt="%s" index="2">Si57xOe_o</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">AFpgaProgProgram_o</arg> connected to top level port <arg fmt="%s" index="2">AFpgaProgProgram_o</arg> has been removed. <msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">AFpgaProgProgram_o</arg> connected to top level port <arg fmt="%s" index="2">AFpgaProgProgram_o</arg> has been removed.
</msg> </msg>
...@@ -137,7 +140,7 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please ...@@ -137,7 +140,7 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp). <msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg> </msg>
<msg type="info" file="Place" num="834" delta="old" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">330</arg> IOs, <arg fmt="%d" index="2">328</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg> <msg type="info" file="Place" num="834" delta="old" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">329</arg> IOs, <arg fmt="%d" index="2">327</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg> </msg>
<msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y9</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. <msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y9</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/pn_parser.xmsgs
View file @ 0895a9f9
...@@ -8,8 +8,5 @@ ...@@ -8,8 +8,5 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SystemFpga.v\&quot; into library work</arg>
</msg>
</messages> </messages>
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/xst.xmsgs
View file @ 0895a9f9
...@@ -266,10 +266,10 @@ ...@@ -266,10 +266,10 @@
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">Gbit34RefClk_ik</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg> </msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">485</arg>: Output port &lt;<arg fmt="%s" index="3">osc_clk</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_InterruptManager</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">485</arg>: Output port &lt;<arg fmt="%s" index="3">osc_clk</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_InterruptManager</arg>&gt; is unconnected or connected to loadless signal.
</msg> </msg>
<msg type="info" file="Xst" num="3010" delta="new" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">533</arg>: Output port &lt;<arg fmt="%s" index="3">Reg3Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Generic4OutputRegs</arg>&gt; is unconnected or connected to loadless signal. <msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/vfc_svn/hdl/design/systemfpga.v</arg>&quot; line <arg fmt="%d" index="2">533</arg>: Output port &lt;<arg fmt="%s" index="3">Reg3Value_ob32</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">i_Generic4OutputRegs</arg>&gt; is unconnected or connected to loadless signal.
</msg> </msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">GenericInputReg1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>. <msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">GenericInputReg1</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport
View file @ 0895a9f9
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2010-12-15T15:18:57</DateModified> <DateModified>2010-12-17T09:49:40</DateModified>
<ModuleName>SFpga</ModuleName> <ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-15T15:17:10</SummaryTimeStamp> <SummaryTimeStamp>2010-12-15T15:17:10</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath> <SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/VFC_SVN/firmware/XilinxISE/SystemFpga</ImplementationReportsDirectory> <ImplementationReportsDirectory>C:/VFC_SVN/firmware/XilinxISE/SystemFpga\</ImplementationReportsDirectory>
<DateInitialized>2010-12-15T15:02:31</DateInitialized> <DateInitialized>2010-12-15T15:02:31</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering> <EnableMessageFiltering>false</EnableMessageFiltering>
</header> </header>
......
trunk/firmware/XilinxISE/SystemFpga/par_usage_statistics.html
View file @ 0895a9f9
...@@ -2,30 +2,30 @@ ...@@ -2,30 +2,30 @@
<xtag-section name="ParStatistics"> <xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1486</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1486</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4726</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4724</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4726</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4724</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4167</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4258</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>25.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>25.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>32.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>31.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>44.6 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>43.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>55.9 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>55.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>61.4 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>62.4 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>62.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>15.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>15.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>6.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.8</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>8.8</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>9.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.6</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.8</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>4.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.1119</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.1180</xtag-par-property-value></TD></TR>
</xtag-section> </xtag-section>
</TABLE> </TABLE>
trunk/firmware/XilinxISE/SystemFpga/sfpga.bgn
View file @ 0895a9f9
...@@ -5,7 +5,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\. ...@@ -5,7 +5,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3 "SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf. Opened constraints file SFpga.pcf.
Thu Dec 16 18:44:48 2010 Fri Dec 17 10:03:13 2010
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.drc
View file @ 0895a9f9
Release 12.3 Drc M.70d (nt) Release 12.3 Drc M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Thu Dec 16 18:44:48 2010 Fri Dec 17 10:03:13 2010
drc -z SFpga.ncd SFpga.pcf drc -z SFpga.ncd SFpga.pcf
......
trunk/firmware/XilinxISE/SystemFpga/webtalk.log
View file @ 0895a9f9
...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information Project Information
-------------------- --------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=3 ProjectIteration=5
WebTalk Summary WebTalk Summary
---------------- ----------------
...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled. ...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON. INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON. INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-16T18:45:27. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-17T10:03:52. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/SystemFpga/webtalk_pn.xml
View file @ 0895a9f9
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Dec 16 18:44:36 2010"> <application name="pn" timeStamp="Fri Dec 17 10:03:02 2010">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/> <property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="3" type="project"/> <property name="ProjectIteration" value="5" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/> <property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/> <property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section> </section>
...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq ...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/> <property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/> <property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="3" type="process"/> <property name="PROP_intWbtProjectIteration" value="5" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> <property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
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