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--------------------------------------------------------------------------------
Release 12.3 Trace  (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o
ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf

Design file:              ApplicationFpga.ncd
Physical constraint file: ApplicationFpga.pcf
Device,package,speed:     xc6slx150t,fgg676,C,-3 (PRODUCTION 1.12c 2010-09-15)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 
50%;

 2806 paths analyzed, 1069 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   6.457ns.
--------------------------------------------------------------------------------

Paths for end point i_Sram1Controller/Dat_ob32_6 (SLICE_X89Y96.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.876ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Sram1Controller/ReadCycle_d_2 (FF)
  Destination:          i_Sram1Controller/Dat_ob32_6 (FF)
  Requirement:          8.333ns
  Data Path Delay:      6.213ns (Levels of Logic = 1)
  Clock Path Skew:      -0.209ns (0.864 - 1.073)
  Source Clock:         SysAppClk_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    SysAppClk_ik_IBUF_BUFG rising at 8.333ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Sram1Controller/ReadCycle_d_2 to i_Sram1Controller/Dat_ob32_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y82.BQ      Tcko                  0.525   i_Ser2MstWB/StbI_d3<1>
                                                       i_Sram1Controller/ReadCycle_d_2
    SLICE_X51Y82.D4      net (fanout=2)        1.207   i_Sram1Controller/ReadCycle_d<2>
    SLICE_X51Y82.D       Tilo                  0.259   i_AddressDecoderWB/Ack_o
                                                       i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o<3>1
    SLICE_X89Y96.CE      net (fanout=8)        3.814   i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o
    SLICE_X89Y96.CLK     Tceck                 0.408   i_Sram1Controller/Dat_ob32<7>
                                                       i_Sram1Controller/Dat_ob32_6
    -------------------------------------------------  ---------------------------
    Total                                      6.213ns (1.192ns logic, 5.021ns route)
                                                       (19.2% logic, 80.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.092ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Sram1Controller/ReadCycle_d_3 (FF)
  Destination:          i_Sram1Controller/Dat_ob32_6 (FF)
  Requirement:          8.333ns
  Data Path Delay:      5.994ns (Levels of Logic = 1)
  Clock Path Skew:      -0.212ns (0.864 - 1.076)
  Source Clock:         SysAppClk_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    SysAppClk_ik_IBUF_BUFG rising at 8.333ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Sram1Controller/ReadCycle_d_3 to i_Sram1Controller/Dat_ob32_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X59Y82.BQ      Tcko                  0.430   i_Sram1Controller/WriteCycle_d<3>
                                                       i_Sram1Controller/ReadCycle_d_3
    SLICE_X51Y82.D1      net (fanout=1)        1.083   i_Sram1Controller/ReadCycle_d<3>
    SLICE_X51Y82.D       Tilo                  0.259   i_AddressDecoderWB/Ack_o
                                                       i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o<3>1
    SLICE_X89Y96.CE      net (fanout=8)        3.814   i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o
    SLICE_X89Y96.CLK     Tceck                 0.408   i_Sram1Controller/Dat_ob32<7>
                                                       i_Sram1Controller/Dat_ob32_6
    -------------------------------------------------  ---------------------------
    Total                                      5.994ns (1.097ns logic, 4.897ns route)
                                                       (18.3% logic, 81.7% route)

--------------------------------------------------------------------------------

Paths for end point i_Sram1Controller/Dat_ob32_5 (SLICE_X89Y96.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.894ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Sram1Controller/ReadCycle_d_2 (FF)
  Destination:          i_Sram1Controller/Dat_ob32_5 (FF)
  Requirement:          8.333ns
  Data Path Delay:      6.195ns (Levels of Logic = 1)
  Clock Path Skew:      -0.209ns (0.864 - 1.073)
  Source Clock:         SysAppClk_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    SysAppClk_ik_IBUF_BUFG rising at 8.333ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Sram1Controller/ReadCycle_d_2 to i_Sram1Controller/Dat_ob32_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y82.BQ      Tcko                  0.525   i_Ser2MstWB/StbI_d3<1>
                                                       i_Sram1Controller/ReadCycle_d_2
    SLICE_X51Y82.D4      net (fanout=2)        1.207   i_Sram1Controller/ReadCycle_d<2>
    SLICE_X51Y82.D       Tilo                  0.259   i_AddressDecoderWB/Ack_o
                                                       i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o<3>1
    SLICE_X89Y96.CE      net (fanout=8)        3.814   i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o
    SLICE_X89Y96.CLK     Tceck                 0.390   i_Sram1Controller/Dat_ob32<7>
                                                       i_Sram1Controller/Dat_ob32_5
    -------------------------------------------------  ---------------------------
    Total                                      6.195ns (1.174ns logic, 5.021ns route)
                                                       (19.0% logic, 81.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.110ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Sram1Controller/ReadCycle_d_3 (FF)
  Destination:          i_Sram1Controller/Dat_ob32_5 (FF)
  Requirement:          8.333ns
  Data Path Delay:      5.976ns (Levels of Logic = 1)
  Clock Path Skew:      -0.212ns (0.864 - 1.076)
  Source Clock:         SysAppClk_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    SysAppClk_ik_IBUF_BUFG rising at 8.333ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Sram1Controller/ReadCycle_d_3 to i_Sram1Controller/Dat_ob32_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X59Y82.BQ      Tcko                  0.430   i_Sram1Controller/WriteCycle_d<3>
                                                       i_Sram1Controller/ReadCycle_d_3
    SLICE_X51Y82.D1      net (fanout=1)        1.083   i_Sram1Controller/ReadCycle_d<3>
    SLICE_X51Y82.D       Tilo                  0.259   i_AddressDecoderWB/Ack_o
                                                       i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o<3>1
    SLICE_X89Y96.CE      net (fanout=8)        3.814   i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o
    SLICE_X89Y96.CLK     Tceck                 0.390   i_Sram1Controller/Dat_ob32<7>
                                                       i_Sram1Controller/Dat_ob32_5
    -------------------------------------------------  ---------------------------
    Total                                      5.976ns (1.079ns logic, 4.897ns route)
                                                       (18.1% logic, 81.9% route)

--------------------------------------------------------------------------------

Paths for end point i_Sram1Controller/Dat_ob32_7 (SLICE_X89Y96.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     1.902ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Sram1Controller/ReadCycle_d_2 (FF)
  Destination:          i_Sram1Controller/Dat_ob32_7 (FF)
  Requirement:          8.333ns
  Data Path Delay:      6.187ns (Levels of Logic = 1)
  Clock Path Skew:      -0.209ns (0.864 - 1.073)
  Source Clock:         SysAppClk_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    SysAppClk_ik_IBUF_BUFG rising at 8.333ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Sram1Controller/ReadCycle_d_2 to i_Sram1Controller/Dat_ob32_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y82.BQ      Tcko                  0.525   i_Ser2MstWB/StbI_d3<1>
                                                       i_Sram1Controller/ReadCycle_d_2
    SLICE_X51Y82.D4      net (fanout=2)        1.207   i_Sram1Controller/ReadCycle_d<2>
    SLICE_X51Y82.D       Tilo                  0.259   i_AddressDecoderWB/Ack_o
                                                       i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o<3>1
    SLICE_X89Y96.CE      net (fanout=8)        3.814   i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o
    SLICE_X89Y96.CLK     Tceck                 0.382   i_Sram1Controller/Dat_ob32<7>
                                                       i_Sram1Controller/Dat_ob32_7
    -------------------------------------------------  ---------------------------
    Total                                      6.187ns (1.166ns logic, 5.021ns route)
                                                       (18.8% logic, 81.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.118ns (requirement - (data path - clock path skew + uncertainty))
  Source:               i_Sram1Controller/ReadCycle_d_3 (FF)
  Destination:          i_Sram1Controller/Dat_ob32_7 (FF)
  Requirement:          8.333ns
  Data Path Delay:      5.968ns (Levels of Logic = 1)
  Clock Path Skew:      -0.212ns (0.864 - 1.076)
  Source Clock:         SysAppClk_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    SysAppClk_ik_IBUF_BUFG rising at 8.333ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: i_Sram1Controller/ReadCycle_d_3 to i_Sram1Controller/Dat_ob32_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X59Y82.BQ      Tcko                  0.430   i_Sram1Controller/WriteCycle_d<3>
                                                       i_Sram1Controller/ReadCycle_d_3
    SLICE_X51Y82.D1      net (fanout=1)        1.083   i_Sram1Controller/ReadCycle_d<3>
    SLICE_X51Y82.D       Tilo                  0.259   i_AddressDecoderWB/Ack_o
                                                       i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o<3>1
    SLICE_X89Y96.CE      net (fanout=8)        3.814   i_Sram1Controller/ReadCycle_d[3]_GND_7_o_equal_13_o
    SLICE_X89Y96.CLK     Tceck                 0.382   i_Sram1Controller/Dat_ob32<7>
                                                       i_Sram1Controller/Dat_ob32_7
    -------------------------------------------------  ---------------------------
    Total                                      5.968ns (1.071ns logic, 4.897ns route)
                                                       (17.9% logic, 82.1% route)

--------------------------------------------------------------------------------

Hold Paths: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point i_Ser2MstWB/Mshreg_SerCntrlIShReg_b32_20 (SLICE_X40Y75.AI), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.375ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Ser2MstWB/SerCntrlIShReg_b32_29 (FF)
  Destination:          i_Ser2MstWB/Mshreg_SerCntrlIShReg_b32_20 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.375ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         SysAppClk_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    SysAppClk_ik_IBUF_BUFG rising at 8.333ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Ser2MstWB/SerCntrlIShReg_b32_29 to i_Ser2MstWB/Mshreg_SerCntrlIShReg_b32_20
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y75.BQ      Tcko                  0.234   i_Ser2MstWB/SerCntrlIShReg_b32<31>
                                                       i_Ser2MstWB/SerCntrlIShReg_b32_29
    SLICE_X40Y75.AI      net (fanout=2)        0.111   i_Ser2MstWB/SerCntrlIShReg_b32<29>
    SLICE_X40Y75.CLK     Tdh         (-Th)    -0.030   i_Ser2MstWB/SerCntrlIShReg_b32<31>
                                                       i_Ser2MstWB/Mshreg_SerCntrlIShReg_b32_20
    -------------------------------------------------  ---------------------------
    Total                                      0.375ns (0.264ns logic, 0.111ns route)
                                                       (70.4% logic, 29.6% route)

--------------------------------------------------------------------------------

Paths for end point i_Ser2MstWB/StbI_xb2_1 (SLICE_X39Y82.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.385ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Ser2MstWB/Rst_xb3_2 (FF)
  Destination:          i_Ser2MstWB/StbI_xb2_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.389ns (Levels of Logic = 0)
  Clock Path Skew:      0.004ns (0.075 - 0.071)
  Source Clock:         SysAppClk_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    SysAppClk_ik_IBUF_BUFG rising at 8.333ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Ser2MstWB/Rst_xb3_2 to i_Ser2MstWB/StbI_xb2_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X36Y82.CQ      Tcko                  0.234   i_Ser2MstWB/StbI_d3<1>
                                                       i_Ser2MstWB/Rst_xb3_2
    SLICE_X39Y82.SR      net (fanout=8)        0.282   i_Ser2MstWB/Rst_xb3_2
    SLICE_X39Y82.CLK     Tcksr       (-Th)     0.127   i_Ser2MstWB/StbI_xb2<1>
                                                       i_Ser2MstWB/StbI_xb2_1
    -------------------------------------------------  ---------------------------
    Total                                      0.389ns (0.107ns logic, 0.282ns route)
                                                       (27.5% logic, 72.5% route)

--------------------------------------------------------------------------------

Paths for end point i_Ser2MstWB/Rst_xb3_2_shift4 (SLICE_X42Y70.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.385ns (requirement - (clock path skew + uncertainty - data path))
  Source:               i_Ser2MstWB/Rst_xb3_2_shift3 (FF)
  Destination:          i_Ser2MstWB/Rst_xb3_2_shift4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.385ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         SysAppClk_ik_IBUF_BUFG rising at 0.000ns
  Destination Clock:    SysAppClk_ik_IBUF_BUFG rising at 8.333ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: i_Ser2MstWB/Rst_xb3_2_shift3 to i_Ser2MstWB/Rst_xb3_2_shift4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X42Y70.CQ      Tcko                  0.200   i_Ser2MstWB/Rst_xb3_2_shift4
                                                       i_Ser2MstWB/Rst_xb3_2_shift3
    SLICE_X42Y70.DX      net (fanout=1)        0.137   i_Ser2MstWB/Rst_xb3_2_shift3
    SLICE_X42Y70.CLK     Tckdi       (-Th)    -0.048   i_Ser2MstWB/Rst_xb3_2_shift4
                                                       i_Ser2MstWB/Rst_xb3_2_shift4
    -------------------------------------------------  ---------------------------
    Total                                      0.385ns (0.248ns logic, 0.137ns route)
                                                       (64.4% logic, 35.6% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 5.833ns (period - min period limit)
  Period: 8.333ns
  Min period limit: 2.500ns (400.000MHz) (Tbcper_I)
  Physical resource: SysAppClk_ik_IBUF_BUFG/I0
  Logical resource: SysAppClk_ik_IBUF_BUFG/I0
  Location pin: BUFGMUX_X2Y1.I0
  Clock network: SysAppClk_ik_IBUF
--------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit)
  Period: 8.333ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: i_Ser2MstWB/StbI_d3<1>/CLK
  Logical resource: i_Sram2Controller/Mshreg_ReadCycle_d_2/CLK
  Location pin: SLICE_X36Y82.CLK
  Clock network: SysAppClk_ik_IBUF_BUFG
--------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit)
  Period: 8.333ns
  Min period limit: 1.399ns (714.796MHz) (Tcp)
  Physical resource: i_Ser2MstWB/StbI_d3<1>/CLK
  Logical resource: i_Sram1Controller/Mshreg_ReadCycle_d_2/CLK
  Location pin: SLICE_X36Y82.CLK
  Clock network: SysAppClk_ik_IBUF_BUFG
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock SysAppClk_ik
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SysAppClk_ik   |    6.457|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 2806 paths, 0 nets, and 1213 connections

Design statistics:
   Minimum period:   6.457ns{1}   (Maximum frequency: 154.871MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Tue Feb 01 08:50:13 2011 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 386 MB