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Release 12.3 - xst M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Reading design: ApplicationFpga.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "ApplicationFpga.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "ApplicationFpga"
Output Format                      : NGC
Target Device                      : xc6slx150t-3-fgg676

---- Source Options
Top Module Name                    : ApplicationFpga
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/WbToCy7c1470.v\" into library work
Parsing module <WbToCy7c1470>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/Ser2MstWB.v\" into library work
Parsing module <Ser2MstWB>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/Generic4OutputRegs.v\" into library work
Parsing module <Generic4OutputRegs>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/Debouncer.v\" into library work
Parsing module <Debouncer>.
WARNING:HDLCompiler:572 - "\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/Debouncer.v" Line 14: Macro <dly> is redefined.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/AddrDecoderWBApp.v\" into library work
Parsing module <AddressDecoderWBApp>.
Analyzing Verilog file \"\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v\" into library work
Parsing module <ApplicationFpga>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <ApplicationFpga>.

Elaborating module <Debouncer(g_CounterWidth=16,g_SynchDepth=3)>.

Elaborating module <Ser2MstWB>.

Elaborating module <AddressDecoderWBApp>.

Elaborating module <Generic4OutputRegs(Reg0Default=32'b01010,Reg1Default=32'b01011,Reg2Default=32'b01100,Reg3Default=32'b01101)>.
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 133: Assignment to DebugReg0 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 134: Assignment to DebugReg1 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 135: Assignment to DebugReg2 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/ApplicationFpga.v" Line 136: Assignment to DebugReg3 ignored, since the identifier is never used

Elaborating module <WbToCy7c1470>.
WARNING:HDLCompiler:413 - "\VFC_SVN\firmware\XilinxISE\ApplicationFpga\../../../hdl/design/WbToCy7c1470.v" Line 45: Result of 36-bit expression is truncated to fit in 32-bit target.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ApplicationFpga>.
    Related source file is "/vfc_svn/hdl/design/applicationfpga.v".
INFO:Xst:3010 - "/vfc_svn/hdl/design/applicationfpga.v" line 123: Output port <Reg0Value_ob32> of the instance <i_DebugRegs> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/applicationfpga.v" line 123: Output port <Reg1Value_ob32> of the instance <i_DebugRegs> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/applicationfpga.v" line 123: Output port <Reg2Value_ob32> of the instance <i_DebugRegs> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/vfc_svn/hdl/design/applicationfpga.v" line 123: Output port <Reg3Value_ob32> of the instance <i_DebugRegs> is unconnected or connected to loadless signal.
Always blocking tristate driving signal <FpGpIo_iob4<1>> is removed.
    Found 1-bit register for signal <Rst_rq>.
INFO:Xst:2774 - HDL ADVISOR - KEEP property attached to signal Sram1Data_b36<31:0> may hinder XST clustering optimizations.
INFO:Xst:2774 - HDL ADVISOR - KEEP property attached to signal Sram2Data_b36<31:0> may hinder XST clustering optimizations.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ApplicationFpga> synthesized.

Synthesizing Unit <Debouncer>.
    Related source file is "/vfc_svn/hdl/design/debouncer.v".
        g_CounterWidth = 16
        g_SynchDepth = 3
    Found 1-bit register for signal <State_q>.
    Found 16-bit register for signal <Counter_c>.
    Found 1-bit register for signal <DebouncedSignal_oq>.
    Found 3-bit register for signal <BouncingSignal_x>.
    Found 16-bit adder for signal <Counter_c[15]_GND_2_o_add_7_OUT> created at line 38.
    Found 1-bit comparator equal for signal <n0003> created at line 31
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  21 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <Debouncer> synthesized.

Synthesizing Unit <Ser2MstWB>.
    Related source file is "/vfc_svn/hdl/design/ser2mstwb.v".
    Found 1-bit register for signal <Rst_xb3<0>>.
    Found 32-bit register for signal <SerDatIShReg_b32>.
    Found 32-bit register for signal <Dat_ob32>.
    Found 32-bit register for signal <SerCntrlIShReg_b32>.
    Found 1-bit register for signal <Cyc_o>.
    Found 1-bit register for signal <We_o>.
    Found 21-bit register for signal <Adr_ob21>.
    Found 1-bit register for signal <Rst_xb3<2>>.
    Found 1-bit register for signal <Rst_xb3<1>>.
    Found 2-bit register for signal <StbI_xb2>.
    Found 31-bit register for signal <AckI_d31>.
    Found 1-bit register for signal <Ack_o>.
    Found 32-bit register for signal <DatInShReg_b32>.
    Found 3-bit register for signal <StbI_d3>.
    Summary:
	inferred 191 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <Ser2MstWB> synthesized.

Synthesizing Unit <AddressDecoderWBApp>.
    Related source file is "/vfc_svn/hdl/design/addrdecoderwbapp.v".
WARNING:Xst:647 - Input <Adr_ib21<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <Dat_ob32>.
    Found 1-bit register for signal <StbDebugRegs_o>.
    Found 1-bit register for signal <StbSram1Controller_o>.
    Found 1-bit register for signal <StbSram2Controller_o>.
    Found 1-bit register for signal <Ack_o>.
    Found 32-bit 4-to-1 multiplexer for signal <GND_5_o_DatSram1Controller_ib32[31]_mux_5_OUT> created at line 32.
    Summary:
	inferred  36 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <AddressDecoderWBApp> synthesized.

Synthesizing Unit <Generic4OutputRegs>.
    Related source file is "/vfc_svn/hdl/design/generic4outputregs.v".
        Reg0Default = 32'b00000000000000000000000000001010
        Reg1Default = 32'b00000000000000000000000000001011
        Reg2Default = 32'b00000000000000000000000000001100
        Reg3Default = 32'b00000000000000000000000000001101
    Found 32-bit register for signal <Reg1Value_ob32>.
    Found 32-bit register for signal <Reg2Value_ob32>.
    Found 32-bit register for signal <Reg3Value_ob32>.
    Found 32-bit register for signal <Reg0Value_ob32>.
    Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 40.
    Summary:
	inferred 128 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
Unit <Generic4OutputRegs> synthesized.

Synthesizing Unit <WbToCy7c1470>.
    Related source file is "/vfc_svn/hdl/design/wbtocy7c1470.v".
WARNING:Xst:647 - Input <Rst_irq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 21-bit register for signal <SramAddress_ob21>.
    Found 4-bit register for signal <WriteCycle_d>.
    Found 96-bit register for signal <n0061>.
    Found 32-bit register for signal <Dat_ob32>.
    Found 4-bit register for signal <ReadCycle_d<3:0>>.
    Found 1-bit tristate buffer for signal <SramData_iob36<35>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<34>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<33>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<32>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<31>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<30>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<29>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<28>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<27>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<26>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<25>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<24>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<23>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<22>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<21>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<20>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<19>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<18>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<17>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<16>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<15>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<14>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<13>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<12>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<11>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<10>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<9>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<8>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<7>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<6>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<5>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<4>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<3>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<2>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<1>> created at line 43
    Found 1-bit tristate buffer for signal <SramData_iob36<0>> created at line 43
    Summary:
	inferred 157 D-type flip-flop(s).
	inferred  36 Tristate(s).
Unit <WbToCy7c1470> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 16-bit adder                                          : 1
# Registers                                            : 38
 1-bit register                                        : 13
 16-bit register                                       : 1
 2-bit register                                        : 1
 21-bit register                                       : 3
 3-bit register                                        : 2
 31-bit register                                       : 1
 32-bit register                                       : 11
 4-bit register                                        : 4
 96-bit register                                       : 2
# Comparators                                          : 1
 1-bit comparator equal                                : 1
# Multiplexers                                         : 10
 1-bit 2-to-1 multiplexer                              : 2
 32-bit 2-to-1 multiplexer                             : 6
 32-bit 4-to-1 multiplexer                             : 2
# Tristates                                            : 72
 1-bit tristate buffer                                 : 72

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1710 - FF/Latch <SramAddress_ob21_19> (without init value) has a constant value of 0 in block <i_Sram1Controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <SramAddress_ob21_20> (without init value) has a constant value of 0 in block <i_Sram1Controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <SramAddress_ob21_19> (without init value) has a constant value of 0 in block <i_Sram2Controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <SramAddress_ob21_20> (without init value) has a constant value of 0 in block <i_Sram2Controller>. This FF/Latch will be trimmed during the optimization process.

Synthesizing (advanced) Unit <Debouncer>.
The following registers are absorbed into counter <Counter_c>: 1 register on signal <Counter_c>.
Unit <Debouncer> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 16-bit up counter                                     : 1
# Registers                                            : 675
 Flip-Flops                                            : 675
# Comparators                                          : 1
 1-bit comparator equal                                : 1
# Multiplexers                                         : 41
 1-bit 2-to-1 multiplexer                              : 2
 1-bit 4-to-1 multiplexer                              : 32
 32-bit 2-to-1 multiplexer                             : 6
 32-bit 4-to-1 multiplexer                             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_16> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_16> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_17> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_17> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_18> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_18> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_0> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_0> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_1> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_1> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_2> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_2> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_3> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_3> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_4> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_4> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_5> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_5> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_6> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_6> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_20> in Unit <ApplicationFpga> is equivalent to the following 3 FFs/Latches, which will be removed : <i_Sram2Controller/SramAddress_ob21_19> <i_Sram1Controller/SramAddress_ob21_20> <i_Sram1Controller/SramAddress_ob21_19> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_7> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_7> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_8> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_8> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_9> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_9> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_0> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_0> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_1> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_1> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_10> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_10> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_2> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_2> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_11> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_11> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_3> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_3> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_12> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_12> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_4> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_4> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_13> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_13> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_5> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_5> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_14> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_14> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_6> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_6> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_20> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_20> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_15> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_15> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_7> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_7> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_21> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_21> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_16> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_16> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_8> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_8> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_22> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_22> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_17> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_17> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_9> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_9> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_23> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_23> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_18> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_18> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_24> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_24> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_19> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_19> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_30> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_30> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_25> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_25> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_31> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_31> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_26> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_26> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_27> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_27> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_10> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_10> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_28> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_28> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_11> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_11> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_29> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_29> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_12> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_12> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_13> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_13> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_14> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_14> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/SramAddress_ob21_15> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/SramAddress_ob21_15> 
WARNING:Xst:1710 - FF/Latch <i_Sram2Controller/SramAddress_ob21_20> (without init value) has a constant value of 0 in block <ApplicationFpga>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_42> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_42> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_43> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_43> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_44> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_44> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_45> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_45> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_46> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_46> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_52> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_52> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_47> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_47> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_53> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_53> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_48> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_48> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_54> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_54> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_49> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_49> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_55> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_55> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_50> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_50> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_56> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_56> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_51> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_51> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_62> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_62> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_57> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_57> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_63> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_63> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_58> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_58> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_59> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_59> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_60> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_60> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_61> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_61> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_32> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_32> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_33> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_33> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_34> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_34> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_35> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_35> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_36> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_36> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_37> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_37> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_38> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_38> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_39> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_39> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_40> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_40> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_41> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_41> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_64> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_64> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_65> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_65> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_66> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_66> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_72> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_72> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_67> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_67> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_73> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_73> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_68> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_68> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_74> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_74> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_69> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_69> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_75> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_75> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_70> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_70> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_76> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_76> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_71> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_71> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_82> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_82> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_77> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_77> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_83> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_83> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_78> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_78> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_84> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_84> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_79> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_79> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_85> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_85> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_80> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_80> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_86> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_86> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_81> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_81> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_92> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_92> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_87> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_87> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_93> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_93> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_88> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_88> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_94> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_94> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_89> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_89> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_95> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_95> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_90> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_90> 
INFO:Xst:2261 - The FF/Latch <i_Sram2Controller/DatI_db32_0_91> in Unit <ApplicationFpga> is equivalent to the following FF/Latch, which will be removed : <i_Sram1Controller/DatI_db32_0_91> 

Optimizing unit <ApplicationFpga> ...

Optimizing unit <Ser2MstWB> ...

Optimizing unit <Debouncer> ...

Optimizing unit <AddressDecoderWBApp> ...

Optimizing unit <Generic4OutputRegs> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ApplicationFpga, actual ratio is 0.
FlipFlop i_Ser2MstWB/Adr_ob21_19 has been replicated 1 time(s)

Final Macro Processing ...

Processing Unit <ApplicationFpga> :
	Found 2-bit shift register for signal <i_Sram2Controller/ReadCycle_d_2>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_95>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_94>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_93>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_92>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_91>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_90>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_89>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_88>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_87>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_86>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_85>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_84>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_83>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_82>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_81>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_80>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_79>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_78>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_77>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_76>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_75>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_74>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_73>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_72>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_71>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_70>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_69>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_68>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_67>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_66>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_65>.
	Found 3-bit shift register for signal <i_Sram2Controller/DatI_db32_0_64>.
	Found 2-bit shift register for signal <i_Sram1Controller/ReadCycle_d_2>.
	Found 29-bit shift register for signal <i_Ser2MstWB/AckI_d31_30>.
	Found 2-bit shift register for signal <i_Ser2MstWB/Rst_xb3_2>.
	Found 2-bit shift register for signal <i_Ser2MstWB/StbI_d3_1>.
	Found 9-bit shift register for signal <i_Ser2MstWB/SerCntrlIShReg_b32_20>.
	Found 3-bit shift register for signal <i_Debouncer/BouncingSignal_x_2>.
Unit <ApplicationFpga> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 428
 Flip-Flops                                            : 428
# Shift Registers                                      : 39
 2-bit shift register                                  : 4
 29-bit shift register                                 : 1
 3-bit shift register                                  : 33
 9-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : ApplicationFpga.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 215
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 15
#      LUT2                        : 46
#      LUT3                        : 7
#      LUT4                        : 35
#      LUT5                        : 2
#      LUT6                        : 75
#      MUXCY                       : 15
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 496
#      FD                          : 159
#      FDCE                        : 1
#      FDE                         : 287
#      FDR                         : 20
#      FDRE                        : 29
# Shift Registers                  : 39
#      SRLC16E                     : 38
#      SRLC32E                     : 1
# Clock Buffers                    : 1
#      BUFG                        : 1
# IO Buffers                       : 144
#      IBUF                        : 9
#      IOBUF                       : 64
#      OBUF                        : 63
#      OBUFT                       : 8

Device utilization summary:
---------------------------

Selected Device : 6slx150tfgg676-3 


Slice Logic Utilization: 
 Number of Slice Registers:             496  out of  184304     0%  
 Number of Slice LUTs:                  221  out of  92152     0%  
    Number used as Logic:               182  out of  92152     0%  
    Number used as Memory:               39  out of  21680     0%  
       Number used as SRL:               39

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    541
   Number with an unused Flip Flop:      45  out of    541     8%  
   Number with an unused LUT:           320  out of    541    59%  
   Number of fully used LUT-FF pairs:   176  out of    541    32%  
   Number of unique control sets:        13

IO Utilization: 
 Number of IOs:                         151
 Number of bonded IOBs:                 144  out of    396    36%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
SysAppClk_ik                       | IBUF+BUFG              | 535   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 4.329ns (Maximum Frequency: 231.022MHz)
   Minimum input arrival time before clock: 1.881ns
   Maximum output required time after clock: 5.526ns
   Maximum combinational path delay: 4.593ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'SysAppClk_ik'
  Clock period: 4.329ns (frequency: 231.022MHz)
  Total number of paths / destination ports: 2844 / 764
-------------------------------------------------------------------------
Delay:               4.329ns (Levels of Logic = 3)
  Source:            i_Ser2MstWB/Adr_ob21_18 (FF)
  Destination:       i_AddressDecoderWB/Dat_ob32_31 (FF)
  Source Clock:      SysAppClk_ik rising
  Destination Clock: SysAppClk_ik rising

  Data Path: i_Ser2MstWB/Adr_ob21_18 to i_AddressDecoderWB/Dat_ob32_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.525   1.047  i_Ser2MstWB/Adr_ob21_18 (i_Ser2MstWB/Adr_ob21_18)
     LUT6:I1->O            4   0.254   0.912  i_AddressDecoderWB/GND_5_o_GND_5_o_equal_2_o<20>3 (i_AddressDecoderWB/GND_5_o_GND_5_o_equal_2_o<20>2)
     LUT4:I1->O           17   0.235   1.028  i_AddressDecoderWB/GND_5_o_GND_5_o_equal_2_o<20>4 (i_AddressDecoderWB/GND_5_o_GND_5_o_equal_2_o)
     LUT6:I5->O            1   0.254   0.000  i_AddressDecoderWB/Mmux_GND_5_o_DatDebugRegs_ib32[31]_mux_6_OUT9 (i_AddressDecoderWB/GND_5_o_DatDebugRegs_ib32[31]_mux_6_OUT<17>)
     FD:D                      0.074          i_AddressDecoderWB/Dat_ob32_17
    ----------------------------------------
    Total                      4.329ns (1.342ns logic, 2.987ns route)
                                       (31.0% logic, 69.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SysAppClk_ik'
  Total number of paths / destination ports: 68 / 68
-------------------------------------------------------------------------
Offset:              1.881ns (Levels of Logic = 1)
  Source:            Sram2Data_b36<31> (PAD)
  Destination:       i_Sram2Controller/Dat_ob32_31 (FF)
  Destination Clock: SysAppClk_ik rising

  Data Path: Sram2Data_b36<31> to i_Sram2Controller/Dat_ob32_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           1   1.228   0.579  Sram2Data_b36_31_IOBUF (N100)
     FDE:D                     0.074          i_Sram2Controller/Dat_ob32_31
    ----------------------------------------
    Total                      1.881ns (1.302ns logic, 0.579ns route)
                                       (69.2% logic, 30.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'SysAppClk_ik'
  Total number of paths / destination ports: 252 / 114
-------------------------------------------------------------------------
Offset:              5.526ns (Levels of Logic = 2)
  Source:            i_Sram1Controller/WriteCycle_d_3 (FF)
  Destination:       Sram1Data_b36<35> (PAD)
  Source Clock:      SysAppClk_ik rising

  Data Path: i_Sram1Controller/WriteCycle_d_3 to Sram1Data_b36<35>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.525   0.688  i_Sram1Controller/WriteCycle_d_3 (i_Sram1Controller/WriteCycle_d_3)
     LUT2:I0->O           36   0.250   1.348  i_Sram1Controller/WriteCycle_d[3]_GND_7_o_equal_10_o_inv1 (i_Sram1Controller/WriteCycle_d[3]_GND_7_o_equal_10_o_inv)
     OBUFT:T->O                2.715          Sram1Data_b36_35_OBUFT (Sram1Data_b36<35>)
    ----------------------------------------
    Total                      5.526ns (3.490ns logic, 2.036ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Delay:               4.593ns (Levels of Logic = 2)
  Source:            SysAppClk_ik (PAD)
  Destination:       SysAppClk_ok (PAD)

  Data Path: SysAppClk_ik to SysAppClk_ok
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   1.228   0.650  SysAppClk_ik_IBUF (SysAppClk_ik_IBUF)
     OBUF:I->O                 2.715          SysAppClk_ok_OBUF (SysAppClk_ok)
    ----------------------------------------
    Total                      4.593ns (3.943ns logic, 0.650ns route)
                                       (85.8% logic, 14.2% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock SysAppClk_ik
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SysAppClk_ik   |    4.329|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.96 secs
 
--> 

Total memory usage is 252696 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   13 (   0 filtered)
Number of infos    :  122 (   0 filtered)