The FMC TDC 1ns 5cha Time to Digital Converter mezzanine board houses 5
input channels. It can calculate time differences between pulses
arriving to the channels with a precision of ±700 ps.
It can be carried by any of the carrier boards:
SVEC. It is implemented using a
dedicated time-to-digital converter chip from the European company
SVEC carrier with two slots for TDC mezzanines and SPEC carrier with
one slot for a TDC mezzanine
5 channels TTL with software selectable 50 Ohm termination.
Inputs need to be protected against +15V pulses with a pulse width of at least 10us at 50Hz
Software controlled switch that enables/ disables all 5 channels
Circular buffer that keeps the last 128 pulses (256 rising and falling edges);
programmable interrupts implemented based on the number of accumulated timestamps or the amount of elapsed time
Timestamps precision (deviation)
± 700 ps
With White Rabbit: *< 1ns*
Without White Rabbit: ± 4 ppm from a local TCXO on the FMC card
Maximum input pulse rate
31.25 MHz from all 5 channels
Timestamps apply to both rising and falling edges of incoming pulses;
on the software level the falling edges are only used for the calculation of the pulse width, ignoring pulses < 100 ns;
With White Rabbit, the TDC offers absolute timestamping and timestamps from different boards in the same White Rabbit network can be correlated.
Without White Rabbit the timestamps from one board need to be always subtracted between them, to calculate time differences
Minimum input pulse width
100 ns, narrower pulses are ignored on software level by subtracting a falling edge from the previous rising one
I-mode, 81ps resolution, +/- 500ps precision (6σ)
Low Pin Count
The FMC TDC development consists of the following sub-projects; each
sub-project has its corresponding release.