FMC Time to Digital Converter: FMC TDC 1ns 5cha
FMC_TDC_small.jpg
System specifications
- 5 inputs, TTL with software selectable 50 Ohm termination.
- Time tags apply to rising edges of inputs. They are made of two parts: 32 bits for the UTC second and as many bits as needed for the fractional part within the second (will depend on final choice of resolution).
- 500 ps resolution or better.
- Accuracy (of time-tag differences between channels): /- (250 ps timebase accuracy).
- Timebase accuracy: +/- 4ppm.
- Implementation details: timebase from a local TCXO on FMC card and needs calibration. Much better accuracy will be reached when used on a White Rabbit enabled FMC carrier.
- External inputs need to be protected against +15V pulses with a pulse width of at least 10us @ 50Hz (with protection diodes if possible).
- LEMO 00 connectors for all inputs. SMC connectors may be mounted instead.
- Minimum input pulse width: 100 ns. Narrower pulses should be ignored.
- A circular buffer will contain time tags for at least the last 100 input pulses. These time tags will at first be rough UTC (counter initialized by SW) giving ~ms accuracy. Later, with a WR-enabled solution, they can be much more accurate. Differences between channels will not suffer from this accuracy problem because the offset with respect to UTC will cancel.
- Programmable (enable/disable) host interrupts on all 5 channels.
- 6-layer PCB.
- FMC mezzanine using a Low Pin Count (LPC) connector.
- Vadj 2.5V or higher.
Project documents
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-02290
- FMC TDC SW support project
- Literature
- CERN specific information
- First, outdated system specification
Project Status
Date | Event |
06-12-2010 | Project start. |
14-12-2010 | First specification available for comments. |
09-03-2011 | First schematic available. (need to replace LEDs) |
18-03-2011 | Second schematics design review held. |
08-04-2011 | First layout made. Review made, needs moving of components Review08042011. |
11-04-2011 | Layout being modified. Planning: 3 assembled prototypes by 16 May. |
19-04-2011 | New layout received. Design review on 20-04-2011. |
20-04-2011 | Review held Review20042011. Layout office modifies the design. |
29-04-2011 | Layout office finalised the design. |
30-05-2011 | Three prototypes ready. |
01-06-2011 | Start of writing firmware. |
05-08-2011 | Design specification review held. https://www.ohwr.org/documents/91 |
08-08-2011 | Basic functionality OK. Several issues found that need a new PCB layout. |
16-12-2011 | New PCB layout made. Production files will be generated. |
02-02-2012 | V2 schematics and PCB made. Will be reviewed on 7 February. Foresee production 8 boards for 23 March. |
07-02-2012 | Schematics reviewed: (review07022012. Improved schematics ready by 21-02-2012 for new review. |
30-05-2012 | V2 boards received. |
30-08-2012 | V3 schematics and PCB being made. Input circuit modified. |
23-10-2012 | V3 schematics and PCB ready. |
Contacts
Commercial producers
- This card is not yet commercially available.
General questions
- Erik van der Bij - CERN
- Nicolas Voumard - lead hardware designer
- Gonzalo Penacoba, Eva Gousiou - firmware developers
Javier Serrano, Erik van der Bij - 25 October 2012