FMC Time to Digital Converter: FMC TDC 1ns 5cha
The Time to Digital Converter mezzanine board houses 5 input channels.
It can calculate time differences between pulses arriving to the
channels with a precision of +-700 ps.
It can be plugged on any of the carrier boards:
SPEC or
SVEC. It is using the ACAM
TDC-GPX chip in
I-mode.
Top view of TDC mezzanine board
System specifications
Input Channels |
5 channels TTL with software selectable 50 Ohm termination. Inputs need to be protected against +15V pulses with a pulse width of at least 10us at 50Hz |
Channels enable | Possibility to enable/ disable all 5 channels |
Timestamps buffer |
Circular buffer that keeps the last 128 pulses (256 rising and falling edges); programmable interrupts implemented based on the number of accumulated timestamps or the amount of elapsed time |
Timestamps precision (deviation) | +/- 700 ps |
Timebase accuracy | +/- 4 ppm from a local TCXO on FMC card; much better accuracy will be reached when used on a White Rabbit enabled FMC carrier |
Maximum input pulse rate | 31.25 MHz from all 5 channels |
Timestamps | Timestamps apply to both rising and falling edges of incoming pulses; on the software level the falling edges are only used for the calculation of the pulse width, ignoring pulses < 100 ns; the rising edges are always subtracted between them |
Minimum input pulse width | 100 ns, narrower pulses should be ignored on software level by subtracting a falling edge from the previous rising one |
ACAM mode | I-mode, 81ps resolution, +/- 500ps precision (6σ) |
Connectors | LEMO 00 |
FMC connector | Low Pin Count |
PCB | 6 layers |
Project documents
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-02290
- FMC TDC SW support project
- Literature
- CERN specific information
- First, outdated system specification
Contacts
Commercial producers
- FMC TDC Seven Solutions, Spain
General questions
- Erik van der Bij - CERN
- Nicolas Voumard - lead hardware designer
- Eva Gousiou, Gonzalo Penacoba - firmware developers
Project Status
Date | Event |
06-12-2010 | Project start. |
14-12-2010 | First specification available for comments. |
09-03-2011 | First schematic available. (need to replace LEDs) |
18-03-2011 | Second schematics design review held. |
08-04-2011 | First layout made. Review made, needs moving of components Review08042011. |
11-04-2011 | Layout being modified. Planning: 3 assembled prototypes by 16 May. |
19-04-2011 | New layout received. Design review on 20-04-2011. |
20-04-2011 | Review held Review20042011. Layout office modifies the design. |
29-04-2011 | Layout office finalised the design. |
30-05-2011 | Three prototypes ready. |
01-06-2011 | Start of writing firmware. |
05-08-2011 | Design specification review held. https://www.ohwr.org/documents/91 |
08-08-2011 | Basic functionality OK. Several issues found that need a new PCB layout. |
16-12-2011 | New PCB layout made. Production files will be generated. |
02-02-2012 | V2 schematics and PCB made. Will be reviewed on 7 February. Foresee production 8 boards for 23 March. |
07-02-2012 | Schematics reviewed: (review07022012. Improved schematics ready by 21-02-2012 for new review. |
30-05-2012 | V2 boards received. |
30-08-2012 | V3 schematics and PCB being made. Input circuit modified. |
23-10-2012 | V3 schematics and PCB ready. |
15-11-2012 | Ordered 60 V3 boards (10 for delivery by |
04-12-2012 | Feedback on design received. Can use same PCB. Other changes may be handled in a V4. |
25-03-2013 | Will make V3-1 design (only change of BOM) to handle five issues. |
08-04-2013 | Working on: correcting two firmware bugs, writing documentation, writing software to test firmware. |
26-04-2013 | No known firmware bugs left. Writing calibration test program. |
06-05-2013 | V3-1 design ready (only change of BOM) to handle five issues. |
13-05-2013 | CERN received 9 pre-series V3-1 boards. |
Javier Serrano, Erik van der Bij - 13 May 2013