- 16 Nov, 2020 1 commit
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Federico Vaga authored
Signed-off-by:Federico Vaga <federico.vaga@cern.ch>
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- 28 Apr, 2020 1 commit
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Federico Vaga authored
Signed-off-by:
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- 08 Oct, 2019 1 commit
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Federico Vaga authored
Signed-off-by:
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- 30 Sep, 2019 1 commit
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Evangelia Gousiou authored
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- 27 Sep, 2019 1 commit
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Evangelia Gousiou authored
updated submodules; added missing sim files
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- 24 Jun, 2019 1 commit
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Tomasz Wlostowski authored
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- 24 May, 2019 1 commit
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Dimitris Lampridis authoredThe following changes were done: 1. Point all submodules to new OHWR 2. update ddr3-sp6-core to latest master because the previous commit (8618c1e154c322be34cb069b62d8293527744dda) was not available in OHWR. Please test! 3. remove etherbone-core 4. update general-cores to latest master and use the updated gc_ds182x_readout module
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- 07 Sep, 2018 1 commit
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Federico Vaga authored
Signed-off-by:
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- 06 Aug, 2018 1 commit
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Tomasz Wlostowski authored
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- 11 Dec, 2017 1 commit
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Grzegorz Daniluk authored
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- 28 Nov, 2017 1 commit
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Federico Vaga authored
Signed-off-by:
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- 20 Mar, 2015 1 commit
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Tomasz Wlostowski authored
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- 06 Aug, 2014 1 commit
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Tomasz Wlostowski authored
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- 19 Jul, 2013 1 commit
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Tomasz Wlostowski authored
Done as the evil twin brother of the fine-delay driver. Still a bit incomplete and lacking documentation. Supports only SPEC carrier so far.
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