testbench/spec: adjust Manifest.py

e4906dab · Tristan Gingold · 9fbbe697 · e4906dab
Commit e4906dab authored Oct 15, 2020 by Tristan Gingold
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Showing with 30 additions and 3 deletions

Manifest.py hdl/testbench/spec/Manifest.py +30 -3

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--- a/hdl/testbench/spec/Manifest.py
+++ b/hdl/testbench/spec/Manifest.py
@@ -3,12 +3,17 @@ top_module="main"
 syn_device="xc6slx45t"
 sim_top="main"

+if locals().get('fetchto', None) is None:
+  fetchto = "../../ip_cores"
+
 action = "simulation"
 target = "xilinx"
-fetchto = "../../ip_cores"
 include_dirs=[ "../../sim", "../include"  ]
 vcom_opt = "-mixedsvvh l"

+# For wr-cores
+board='spec'
+
 include_dirs = [
    "../include",
    "../../sim",
@@ -23,10 +28,23 @@ include_dirs = [
 files = [
    "main.sv",
    "buildinfo_pkg.vhd",
+    "sourceid_wr_spec_tdc_pkg.vhd",
 ]


-modules = { "local" :  [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/sim/gn4124_bfm" ] }
+modules = {
+  "local" :  [
+    "../../top/spec",
+    fetchto + "/gn4124-core/hdl/sim/gn4124_bfm"
+  ],
+  "git" : [
+    "https://ohwr.org/project/wr-cores.git",
+    "https://ohwr.org/project/general-cores.git",
+    "https://ohwr.org/project/gn4124-core.git",
+    "https://ohwr.org/project/ddr3-sp6-core.git",
+  ],
+  "system": ['xilinx']
+}

 ctrls = ["bank3_32b_32b"]

@@ -34,4 +52,13 @@ ctrls = ["bank3_32b_32b"]
 try:
  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
 except:
-  pass
\ No newline at end of file
+  pass
+
+try:
+    # Assume this module is in fact a git submodule of a main project that
+    # is in the same directory as general-cores...
+    exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
+         None, {'project': 'wr_spec_tdc'})
+except Exception as e:
+    print("Error: cannot generate source id file")
+    raise