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FMC TDC 1ns 5cha
Commit d928d757 authored by Tristan Gingold's avatar Tristan Gingold
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hdl: remove unused declarations.

parent 9e320175
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Showing with 3 additions and 56 deletions
hdl/rtl/fmc_tdc_core.vhd
View file @ d928d757
......@@ -214,7 +214,6 @@ architecture rtl of fmc_tdc_core is
signal acm_cyc, acm_stb, acm_we, acm_ack : std_logic;
signal acm_dat_r, acm_dat_w : std_logic_vector(g_WIDTH-1 downto 0);
signal acam_ef1, acam_ef2 : std_logic;
signal acam_intflag_f_edge_p : std_logic;
signal acam_tstamp1, acam_tstamp2 : std_logic_vector(g_WIDTH-1 downto 0);
signal acam_tstamp1_ok_p, acam_tstamp2_ok_p : std_logic;
-- control unit
......@@ -222,7 +221,6 @@ architecture rtl of fmc_tdc_core is
signal read_acam_config, read_acam_status, read_ififo1 : std_logic;
signal read_ififo2, read_start01, reset_acam, load_utc : std_logic;
signal roll_over_incr_recent : std_logic;
signal deactivate_chan : std_logic_vector(4 downto 0);
signal clk_period : std_logic_vector(g_WIDTH-1 downto 0);
signal starting_utc, acam_inputs_en : std_logic_vector(g_WIDTH-1 downto 0);
signal acam_ififo1, acam_ififo2, acam_start01 : std_logic_vector(g_WIDTH-1 downto 0);
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ d928d757
......@@ -240,23 +240,14 @@ architecture rtl of fmc_tdc_mezzanine is
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- resets
signal general_rst_n, rst_ref_0_n : std_logic;
-- Wishbone buse(s) from crossbar master port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE addresses
signal tdc_core_wb_adr : std_logic_vector(31 downto 0);
signal tdc_mem_wb_adr : std_logic_vector(31 downto 0);
-- 1-wire
signal mezz_owr_en, mezz_owr_i : std_logic_vector(0 downto 0);
-- I2C
signal sys_scl_in, sys_scl_out : std_logic;
signal sys_scl_oe_n, sys_sda_in : std_logic;
signal sys_scl_out : std_logic;
signal sys_scl_oe_n : std_logic;
signal sys_sda_out, sys_sda_oe_n : std_logic;
-- IRQ
signal irq_tstamp : std_logic;
signal reg_to_wr, reg_from_wr : std_logic_vector(31 downto 0);
signal wrabbit_utc_p : std_logic;
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ d928d757
......@@ -224,9 +224,6 @@ architecture rtl of fmc_tdc_wrapper is
signal pll_sclk, pll_sdi, pll_dac_sync : std_logic;
signal fmc_eic_irq : std_logic;
signal fmc_eic_irq_synch : std_logic_vector(1 downto 0);
signal tdc_scl_out, tdc_scl_oen, tdc_sda_out, tdc_sda_oen : std_logic;
signal timestamp : t_tdc_timestamp_array(4 downto 0);
......
hdl/top/spec/wr_spec_tdc.vhd
View file @ d928d757
......@@ -288,16 +288,6 @@ end wr_spec_tdc;
--=================================================================================================
architecture rtl of wr_spec_tdc is
function f_bool2int (x : boolean) return integer is
begin
if(x) then
return 1;
else
return 0;
end if;
end f_bool2int;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
......@@ -344,8 +334,7 @@ architecture rtl of wr_spec_tdc is
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- WRPC TM interface and status
signal tm_link_up, tm_time_valid : std_logic;
signal tm_dac_wr_p : std_logic;
......@@ -358,7 +347,6 @@ architecture rtl of wr_spec_tdc is
-- Interrupts and status
signal ddr_wr_fifo_empty : std_logic; -- not used
signal fmc0_irq : std_logic;
signal irq_vector : std_logic_vector(0 downto 0);
signal gn4124_access : std_logic;
......@@ -367,20 +355,6 @@ architecture rtl of wr_spec_tdc is
signal tdc_sda_oen, tdc_sda_in : std_logic;
-- aux
signal tdc0_soft_rst_n : std_logic;
signal ddr3_tdc_adr : std_logic_vector(31 downto 0);
signal powerup_rst_cnt : unsigned(7 downto 0) := "00000000";
signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
signal tdc_dma_out : t_wishbone_master_out;
signal tdc_dma_in : t_wishbone_master_in;
-- Wishbone buses from FMC ADC cores to DDR controller
signal fmc0_wb_ddr_in : t_wishbone_master_in;
signal fmc0_wb_ddr_out : t_wishbone_master_out;
......@@ -389,21 +363,8 @@ architecture rtl of wr_spec_tdc is
signal sim_ts_valid, sim_ts_ready : std_logic;
signal sim_ts : t_tdc_timestamp;
signal ddr3_status : std_logic_vector(31 downto 0);
function f_to_string(x : boolean) return string is
begin
if x then
return "TRUE";
else
return "FALSE";
end if;
end f_to_string;
signal dma_reg_adr : std_logic_vector(31 downto 0);
signal dma_wb_adr : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......
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