reg_ctrl.vhd: reformating

d5e18468 · Tristan Gingold · Federico Vaga · b65271bf · d5e18468
Commit d5e18468 authored Mar 23, 2021 by Tristan Gingold Committed by Federico Vaga Jul 25, 2022
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reg_ctrl.vhd hdl/rtl/reg_ctrl.vhd +11 -12

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--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
@@ -149,17 +149,17 @@ end reg_ctrl;
 --=================================================================================================
 architecture rtl of reg_ctrl is

-  signal acam_config                                  : config_vector;
-  signal reg_adr, reg_adr_pipe0                       : std_logic_vector(7 downto 0);
-  signal starting_utc, acam_inputs_en                 : std_logic_vector(g_width-1 downto 0);
-  signal ctrl_reg, local_pps_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
-  signal irq_time_threshold                           : std_logic_vector(g_width-1 downto 0);
-  signal clear_ctrl_reg, send_dac_word_p              : std_logic;
-  signal dac_word                                     : std_logic_vector(23 downto 0);
-  signal pulse_extender_en                            : std_logic;
-  signal pulse_extender_c                             : std_logic_vector(2 downto 0);
-  signal dat_out, wrabbit_ctrl_reg                    : std_logic_vector(g_span-1 downto 0);
-  signal ack_out_pipe0, ack_out_pipe1                 : std_logic;
+  signal acam_config                     : config_vector;
+  signal reg_adr, reg_adr_pipe0          : std_logic_vector(7 downto 0);
+  signal starting_utc, acam_inputs_en    : std_logic_vector(g_width-1 downto 0);
+  signal ctrl_reg, irq_tstamp_threshold  : std_logic_vector(g_width-1 downto 0);
+  signal irq_time_threshold              : std_logic_vector(g_width-1 downto 0);
+  signal clear_ctrl_reg, send_dac_word_p : std_logic;
+  signal dac_word                        : std_logic_vector(23 downto 0);
+  signal pulse_extender_en               : std_logic;
+  signal pulse_extender_c                : std_logic_vector(2 downto 0);
+  signal wrabbit_ctrl_reg                : std_logic_vector(g_span-1 downto 0);
+  signal ack_out_pipe0, ack_out_pipe1    : std_logic;


  signal dat_out_comb0, dat_out_comb1 : std_logic_vector(g_span-1 downto 0);
@@ -169,7 +169,6 @@ architecture rtl of reg_ctrl is
  signal dat_out_pipe2, dat_out_pipe3 : std_logic_vector(g_span-1 downto 0);

  signal cyc_in_progress : std_logic;
-  signal cyc2_in_progress : std_logic;

  signal wb_in     : t_wishbone_slave_in;
  signal wb_out    : t_wishbone_slave_out;