Commit a7c64ce2 authored by egousiou's avatar egousiou

little debug on sdb wr_spec_tdc

git-svn-id: http://svn.ohwr.org/fmc-tdc@181 85dfdc96-de2c-444c-878d-45b388be74a9
parent 58de2f4a
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Mon Jun 23 19:15:49 2014
PCBE13136:: Wed Jun 25 17:54:53 2014
par -w -intstyle ise -ol high -xe c -mt off wr_spec_tdc_map.ncd wr_spec_tdc.ncd
wr_spec_tdc.pcf
......@@ -17,12 +17,6 @@ INFO:Par:338 -
design even if the time specs can not be met. If you are looking for the best possible design speed available from a
long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
speed improvements have shrunk to the point that the time specs are not expected to be met.
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
......@@ -178,17 +172,17 @@ Phase 5 : 0 unrouted; (Setup:445, Hold:63078, Component Switching Limit:0)
Phase 6 : 0 unrouted; (Setup:445, Hold:63078, Component Switching Limit:0) REAL time: 2 mins 24 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:63078, Component Switching Limit:0) REAL time: 3 mins 27 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:63078, Component Switching Limit:0) REAL time: 3 mins 26 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:63078, Component Switching Limit:0) REAL time: 3 mins 27 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:63078, Component Switching Limit:0) REAL time: 3 mins 26 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:63078, Component Switching Limit:0) REAL time: 3 mins 27 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:63078, Component Switching Limit:0) REAL time: 3 mins 26 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 28 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 27 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 33 secs
Total REAL time to Router completion: 3 mins 33 secs
Total CPU time to Router completion: 3 mins 45 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 32 secs
Total REAL time to Router completion: 3 mins 32 secs
Total CPU time to Router completion: 3 mins 44 secs
Partition Implementation Status
-------------------------------
......@@ -477,8 +471,8 @@ All signals are completely routed.
WARNING:Par:283 - There are 16 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 3 mins 39 secs
Total CPU time to PAR completion: 3 mins 50 secs
Total REAL time to PAR completion: 3 mins 38 secs
Total CPU time to PAR completion: 3 mins 49 secs
Peak Memory Usage: 462 MB
......
......@@ -4873,7 +4873,7 @@ Design statistics:
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Mon Jun 23 19:20:03 2014
Analysis completed Wed Jun 25 17:59:05 2014
--------------------------------------------------------------------------------
Trace Settings:
......
......@@ -11,14 +11,8 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 19:09:15 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapped Date : Wed Jun 25 17:48:14 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
......@@ -26,34 +20,34 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 40 secs
Total REAL time at the beginning of Placer: 44 secs
Total CPU time at the beginning of Placer: 38 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:89307510) REAL time: 43 secs
Phase 1.1 Initial Placement Analysis (Checksum:89307510) REAL time: 49 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:89307510) REAL time: 45 secs
Phase 2.7 Design Feasibility Check (Checksum:89307510) REAL time: 50 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:476872d8) REAL time: 45 secs
Phase 3.31 Local Placement Optimization (Checksum:476872d8) REAL time: 50 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:87ab2a92) REAL time: 1 mins 32 secs
(Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 32 secs
Phase 5.36 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:87ab2a92) REAL time: 1 mins 32 secs
Phase 6.30 Global Clock Region Assignment (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 32 secs
Phase 7.3 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 33 secs
Phase 8.5 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 9.8 Global Placement
.....................
......@@ -61,22 +55,22 @@ Phase 9.8 Global Placement
............................................................................................................................................................................................
..........................................................................................................................................................................................
........................................................................
Phase 9.8 Global Placement (Checksum:e5911db4) REAL time: 5 mins 15 secs
Phase 9.8 Global Placement (Checksum:e5911db4) REAL time: 5 mins 20 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:e5911db4) REAL time: 5 mins 16 secs
Phase 10.5 Local Placement Optimization (Checksum:e5911db4) REAL time: 5 mins 21 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:675f2f74) REAL time: 6 mins 1 secs
Phase 11.18 Placement Optimization (Checksum:675f2f74) REAL time: 6 mins 6 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:675f2f74) REAL time: 6 mins 1 secs
Phase 12.5 Local Placement Optimization (Checksum:675f2f74) REAL time: 6 mins 6 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:f1209e85) REAL time: 6 mins 2 secs
Phase 13.34 Placement Validation (Checksum:f1209e85) REAL time: 6 mins 7 secs
Total REAL time to Placer completion: 6 mins 21 secs
Total CPU time to Placer completion: 6 mins 18 secs
Total REAL time to Placer completion: 6 mins 25 secs
Total CPU time to Placer completion: 6 mins 17 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -221,8 +215,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 32 secs
Total CPU time to MAP completion: 6 mins 29 secs
Total REAL time to MAP completion: 6 mins 37 secs
Total CPU time to MAP completion: 6 mins 28 secs
Mapping completed.
See MAP report file "wr_spec_tdc_map.mrp" for details.
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 19:09:15 2014
Mapped Date : Wed Jun 25 17:48:14 2014
Design Summary
--------------
......@@ -111,8 +111,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 32 secs
Total CPU time to MAP completion: 6 mins 29 secs
Total REAL time to MAP completion: 6 mins 37 secs
Total CPU time to MAP completion: 6 mins 28 secs
Table of Contents
-----------------
......@@ -135,9 +135,6 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_441_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
......@@ -182,7 +179,6 @@ WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
Section 3 - Informational
-------------------------
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:LIT:243 - Logical network tdc_in_fpga_2_i has no load.
INFO:LIT:395 - The above info message is repeated 144 more times for the
following (max. 5 shown):
......
......@@ -302,7 +302,7 @@ architecture rtl of wr_spec_tdc is
constant c_MASTER_GENNUM : integer := 0;
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
(0 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
......
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