white rabbit svec folders update

git-svn-id: http://svn.ohwr.org/fmc-tdc@165 85dfdc96-de2c-444c-878d-45b388be74a9

white rabbit svec folders update
git-svn-id: http://svn.ohwr.org/fmc-tdc@165 85dfdc96-de2c-444c-878d-45b388be74a9
a730429a · egousiou · b9e8e280 · a730429a · a730429a · a730429a
Commit a730429a authored Jun 03, 2014 by egousiou
11 changed files
--- a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.bin
+++ b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.bin
--- a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.twr
+++ b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.twr
--- a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.xise
+++ b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc.xise
--- a/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc_map.mrp
+++ b/hdl/wrabbit_tdc/hdl/syn/svec/svec_top_fmc_tdc_map.mrp
--- a/hdl/wrabbit_tdc/hdl/syn/svec/wrc.ram
+++ b/hdl/wrabbit_tdc/hdl/syn/svec/wrc.ram
--- a/hdl/wrabbit_tdc/hdl/top/svec/sdb_meta_pkg.vhd
+++ b/hdl/wrabbit_tdc/hdl/top/svec/sdb_meta_pkg.vhd
+--_________________________________________________________________________________________________
+--                                                                                                |
+--                                           |TDC core|                                           |
+--                                                                                                |
+--                                         CERN,BE/CO-HT                                          |
+--________________________________________________________________________________________________|
+
+---------------------------------------------------------------------------------------------------
+--                                                                                                |
+--                                         sdb_meta_pkg                                           |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+-- File         sdb_meta_pkg.vhd                                                                  |
+--                                                                                                |
+-- Description  Sdb meta-information for the FMC TDC design for SPEC.                             |
+--                                                                                                |
+-- Authors      Matthieu Cattin (matthieu.cattin@cern.ch)                                         |
+--              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
+-- Date         04/2013                                                                           |
+-- Version      v1                                                                                |
+--                                                                                                |
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
+--                              ------------------------------------                              |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
+-- version 2.1 of the License, or (at your option) any later version.                             |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
+-- See the GNU Lesser General Public License for more details.                                    |
+-- You should have received a copy of the GNU Lesser General Public License along with this       |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
+---------------------------------------------------------------------------------------------------
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+
+package sdb_meta_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Meta-information sdb records
+  ------------------------------------------------------------------------------
+
+  -- Top module repository url
+  constant c_SDB_REPO_URL : t_sdb_repo_url := (
+    -- url (string, 63 char)
+    repo_url => "http://svn.ohwr.org/fmc-tdc/hdl/spec/                          ");
+
+  -- Synthesis informations
+  constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
+    -- Top module name (string, 16 char)
+    syn_module_name  => "spec_top_fmc_tdc",
+    -- Commit ID (hex string, 128-bit = 32 char)
+    -- git log -1 --format="%H" | cut -c1-320
+    syn_commit_id    => x"00000000",
+    -- Synthesis tool name (string, 8 char)
+    syn_tool_name    => "ISE     ",
+    -- Synthesis tool version (bcd encoded, 32-bit)
+    syn_tool_version => x"00000134",
+    -- Synthesis date (bcd encoded, 32-bit)
+    syn_date         => x"20140121",
+    -- Synthesised by (string, 15 char)
+    syn_username     => "egousiou       ");
+
+  -- Integration record
+  constant c_SDB_INTEGRATION : t_sdb_integration := (
+    product     => (
+      vendor_id => x"000000000000CE42",  -- CERN
+      device_id => x"593b56e5",          -- echo "spec_fmc-tdc-1ns5cha" | md5sum | cut -c1-8
+      version   => x"00050000",          -- bcd encoded, [31:16] = major, [15:0] = minor
+      date      => x"20140121",          -- yyyymmdd
+      name      => "svec_top_fmc_tdc   "));
+
+
+end sdb_meta_pkg;
+
+
+package body sdb_meta_pkg is
+end sdb_meta_pkg;
\ No newline at end of file
--- a/hdl/wrabbit_tdc/hdl/top/svec/svec_tdc.ucf
+++ b/hdl/wrabbit_tdc/hdl/top/svec/svec_tdc.ucf
--- a/hdl/wrabbit_tdc/hdl/top/svec/svec_top_fmc_tdc.vhd
+++ b/hdl/wrabbit_tdc/hdl/top/svec/svec_top_fmc_tdc.vhd
--- a/hdl/wrabbit_tdc/hdl/top/svec/synthesis_descriptor.vhd
+++ b/hdl/wrabbit_tdc/hdl/top/svec/synthesis_descriptor.vhd
+-------------------------------------------------------------------------------
+-- Title      : TDC FMC SVEC (Simple VME FMC Carrier) SDB descriptor
+-- Project    : TDC FMC (fmc-tdc-1ns-5cha)
+-------------------------------------------------------------------------------
+-- File       : synthesis_descriptor.vhd
+-- Author     : Evangelia Gousiou
+-- Company    : CERN
+-- Created    : 2013-04-16
+-- Last update: 2013-04-16
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
+-- Contains synthesis & source repository information.
+-- Warning: this file is modified whenever a synthesis is executed.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use work.wishbone_pkg.all;
+
+package synthesis_descriptor is
+  
+constant c_sdb_synthesis_info : t_sdb_synthesis :=
+  (
+    syn_module_name => "tdc-svec        ",
+    syn_commit_id => "00000000000000000000000000000000",
+    syn_tool_name => "ISE     ",
+    syn_tool_version => x"00000134",
+    syn_date => x"00000000",
+    syn_username => "egousiou       ");
+
+constant c_sdb_repo_url : t_sdb_repo_url :=
+  (
+    repo_url => "http://svn.ohwr.org/fmc-tdc                                    " 
+  );
+
+end package synthesis_descriptor;
\ No newline at end of file
--- a/hdl/wrabbit_tdc/hdl/top/svec/tdc_core_pkg.vhd
+++ b/hdl/wrabbit_tdc/hdl/top/svec/tdc_core_pkg.vhd
--- a/hdl/wrabbit_tdc/hdl/top/svec/xvme64x_core.vhd
+++ b/hdl/wrabbit_tdc/hdl/top/svec/xvme64x_core.vhd
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use WORK.wishbone_pkg.all;
+use work.vme64x_pack.all;
+
+entity xvme64x_core is
+  
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    VME_AS_n_i      : in  std_logic;
+    VME_RST_n_i     : in  std_logic;
+    VME_WRITE_n_i   : in  std_logic;
+    VME_AM_i        : in  std_logic_vector(5 downto 0);
+    VME_DS_n_i      : in  std_logic_vector(1 downto 0);
+    VME_GA_i        : in  std_logic_vector(5 downto 0);
+    VME_BERR_o      : out std_logic;
+    VME_DTACK_n_o   : out std_logic;
+    VME_RETRY_n_o   : out std_logic;
+    VME_RETRY_OE_o  : out std_logic;
+    VME_LWORD_n_b_i : in  std_logic;
+    VME_LWORD_n_b_o : out std_logic;
+    VME_ADDR_b_i    : in  std_logic_vector(31 downto 1);
+    VME_ADDR_b_o    : out std_logic_vector(31 downto 1);
+    VME_DATA_b_i    : in  std_logic_vector(31 downto 0);
+    VME_DATA_b_o    : out std_logic_vector(31 downto 0);
+    VME_IRQ_n_o     : out std_logic_vector(6 downto 0);
+    VME_IACKIN_n_i  : in  std_logic;
+    VME_IACK_n_i    : in  std_logic;
+    VME_IACKOUT_n_o : out std_logic;
+    VME_DTACK_OE_o  : out std_logic;
+    VME_DATA_DIR_o  : out std_logic;
+    VME_DATA_OE_N_o : out std_logic;
+    VME_ADDR_DIR_o  : out std_logic;
+    VME_ADDR_OE_N_o : out std_logic;
+
+    master_o : out t_wishbone_master_out;
+    master_i : in  t_wishbone_master_in;
+
+    irq_i     : in  std_logic;
+    irq_ack_o : out std_logic
+
+    );
+
+end xvme64x_core;
+
+architecture wrapper of xvme64x_core is
+
+  component VME64xCore_Top
+    generic (
+      g_wb_data_width : integer := 32;
+      g_wb_addr_width : integer := 64;
+      g_CRAM_SIZE     : integer := 1024);
+    port (
+      clk_i           : in  std_logic;
+      rst_n_i         : in  std_logic;
+      VME_AS_n_i      : in  std_logic;
+      VME_RST_n_i     : in  std_logic;
+      VME_WRITE_n_i   : in  std_logic;
+      VME_AM_i        : in  std_logic_vector(5 downto 0);
+      VME_DS_n_i      : in  std_logic_vector(1 downto 0);
+      VME_GA_i        : in  std_logic_vector(5 downto 0);
+      VME_BERR_o      : out std_logic;
+      VME_DTACK_n_o   : out std_logic;
+      VME_RETRY_n_o   : out std_logic;
+      VME_LWORD_n_i   : in  std_logic;
+      VME_LWORD_n_o   : out std_logic;
+      VME_ADDR_i      : in  std_logic_vector(31 downto 1);
+      VME_ADDR_o      : out std_logic_vector(31 downto 1);
+      VME_DATA_i      : in  std_logic_vector(31 downto 0);
+      VME_DATA_o      : out std_logic_vector(31 downto 0);
+      VME_IRQ_o       : out std_logic_vector(6 downto 0);
+      VME_IACKIN_n_i  : in  std_logic;
+      VME_IACK_n_i    : in  std_logic;
+      VME_IACKOUT_n_o : out std_logic;
+      VME_DTACK_OE_o  : out std_logic;
+      VME_DATA_DIR_o  : out std_logic;
+      VME_DATA_OE_N_o : out std_logic;
+      VME_ADDR_DIR_o  : out std_logic;
+      VME_ADDR_OE_N_o : out std_logic;
+      VME_RETRY_OE_o  : out std_logic;
+      DAT_i           : in  std_logic_vector(g_wb_data_width - 1 downto 0);
+      DAT_o           : out std_logic_vector(g_wb_data_width - 1 downto 0);
+      ADR_o           : out std_logic_vector(g_wb_addr_width - 1 downto 0);
+      CYC_o           : out std_logic;
+      ERR_i           : in  std_logic;
+      RTY_i           : in  std_logic;
+      SEL_o           : out std_logic_vector(f_div8(g_wb_addr_width) - 1 downto 0);
+      STB_o           : out std_logic;
+      ACK_i           : in  std_logic;
+      WE_o            : out std_logic;
+      STALL_i         : in  std_logic;
+      INT_ack_o       : out std_logic;
+      IRQ_i           : in  std_logic;
+      debug           : out std_logic_vector(7 downto 0));
+  end component;
+
+  signal rst_in, rst_out : std_logic;
+  signal dat_out, dat_in : std_logic_vector(31 downto 0);
+  signal adr_out         : std_logic_vector(63 downto 0);
+  
+begin  -- wrapper
+
+  U_Wrapped_VME : VME64xCore_Top
+    port map (
+      clk_i           => clk_i,
+      rst_n_i         => rst_n_i,
+      VME_AS_n_i      => VME_AS_n_i,
+      VME_RST_n_i     => VME_RST_n_i,
+      VME_WRITE_n_i   => VME_WRITE_n_i,
+      VME_AM_i        => VME_AM_i,
+      VME_DS_n_i      => VME_DS_n_i,
+      VME_GA_i        => VME_GA_i,
+      VME_BERR_o      => VME_BERR_o,
+      VME_DTACK_n_o   => VME_DTACK_n_o,
+      VME_RETRY_n_o   => VME_RETRY_n_o,
+      VME_RETRY_OE_o  => VME_RETRY_OE_o,
+      VME_LWORD_n_i   => VME_LWORD_n_b_i,
+      VME_LWORD_n_o   => VME_LWORD_n_b_o,
+      VME_ADDR_i      => VME_ADDR_b_i,
+      VME_ADDR_o      => VME_ADDR_b_o,
+      VME_DATA_i      => VME_DATA_b_i,
+      VME_DATA_o      => VME_DATA_b_o,
+      VME_IRQ_o       => VME_IRQ_n_o,
+      VME_IACKIN_n_i  => VME_IACKIN_n_i,
+      VME_IACK_n_i    => VME_IACK_n_i,
+      VME_IACKOUT_n_o => VME_IACKOUT_n_o,
+      VME_DTACK_OE_o  => VME_DTACK_OE_o,
+      VME_DATA_DIR_o  => VME_DATA_DIR_o,
+      VME_DATA_OE_N_o => VME_DATA_OE_N_o,
+      VME_ADDR_DIR_o  => VME_ADDR_DIR_o,
+      VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
+
+      DAT_i     => dat_in,
+      DAT_o     => dat_out,
+      ADR_o     => adr_out,
+      CYC_o     => master_o.cyc,
+      ERR_i     => master_i.err,
+      RTY_i     => master_i.rty,
+      SEL_o     => open,
+      STB_o     => master_o.stb,
+      ACK_i     => master_i.ack,
+      WE_o      => master_o.we,
+      STALL_i   => master_i.stall,
+      IRQ_i     => irq_i,
+      INT_ack_o => irq_ack_o
+      );
+
+  master_o.dat <= dat_out(31 downto 0);
+  master_o.sel <= (others => '1');
+  master_o.adr <= adr_out(29 downto 0) & "00";   -- word address to byte address
+  dat_in       <= master_i.dat;
+
+--  VME_IRQ_n_o <= (others => '0');
+  
+  
+  
+end wrapper;