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FMC TDC 1ns 5cha
Commit 9f5320cf authored by Federico Vaga's avatar Federico Vaga
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sw:drv: include tdc_eic.h header because wbgen2 is buggy 

wbgen2 does not generate the correct header file, wrong offset.
Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent b8da52f0
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Showing with 175 additions and 6 deletions
software/kernel/.gitignore
View file @ 9f5320cf
hw/tdc_eic.h
hw/tdc_dma_eic.h hw/tdc_dma_eic.h
hw/tdc_onewire_regs.h hw/tdc_onewire_regs.h
hw/tdc_buffer_control_regs.h hw/tdc_buffer_control_regs.h
......
software/kernel/Makefile
View file @ 9f5320cf
...@@ -55,10 +55,7 @@ GIT_VERSION = $(shell git describe --always --dirty --long --tags) ...@@ -55,10 +55,7 @@ GIT_VERSION = $(shell git describe --always --dirty --long --tags)
all: modules all: modules
hw_headers: tdc_eic.h tdc_dma_eic.h tdc_onewire_regs.h tdc_buffer_control_regs.h timestamp_fifo_regs.h channel_regs.h hw_headers: tdc_dma_eic.h tdc_onewire_regs.h tdc_buffer_control_regs.h timestamp_fifo_regs.h channel_regs.h
tdc_eic.h: $(TDC_HDL)/rtl/wbgen/tdc_eic.wb
$(WBGEN2) -s defines -C hw/$@ $<
tdc_dma_eic.h: $(TDC_HDL)/rtl/wbgen/dma_eic.wb tdc_dma_eic.h: $(TDC_HDL)/rtl/wbgen/dma_eic.wb
$(WBGEN2) -s defines -C hw/$@ $< $(WBGEN2) -s defines -C hw/$@ $<
...@@ -90,7 +87,7 @@ install modules_install: modules ...@@ -90,7 +87,7 @@ install modules_install: modules
clean: clean:
rm -rf *.o *~ .*.cmd *.ko *.mod.c .tmp_versions Module.symvers \ rm -rf *.o *~ .*.cmd *.ko *.mod.c .tmp_versions Module.symvers \
Module.markers modules.order Module.markers modules.order
rm -f hw/tdc_eic.h hw/tdc_dma_eic.h hw/tdc_onewire_regs.h rm -f hw/tdc_dma_eic.h hw/tdc_onewire_regs.h
rm -f hw/tdc_buffer_control_regs.h hw/timestamp_fifo_regs.h rm -f hw/tdc_buffer_control_regs.h hw/timestamp_fifo_regs.h
rm -f hw/channel_regs.h rm -f hw/channel_regs.h
......
software/kernel/hw/tdc_eic.h 0 → 100644
View file @ 9f5320cf
/*
Register definitions for slave core: TDC EIC
* File : hw/tdc_eic.h
* Author : auto-generated by wbgen2 from /afs/cern.ch/work/f/fvaga/projects/fmc-tdc/software/kernel/../..//hdl/rtl/wbgen/tdc_eic.wb
* Created : Tue Nov 17 11:44:54 2020
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /afs/cern.ch/work/f/fvaga/projects/fmc-tdc/software/kernel/../..//hdl/rtl/wbgen/tdc_eic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TDC_EIC_WB
#define __WBGEN2_REGDEFS_TDC_EIC_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: FMC TDC timestamps interrupt (FIFO1) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO2) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO2 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO3) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO3 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO4) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO4 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO5) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO5 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA1) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA1 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA2) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA3) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA3 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA4) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA4 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA5) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA5 WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: FMC TDC timestamps interrupt (FIFO1) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO2) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO2 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO3) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO3 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO4) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO4 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO5) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO5 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA1) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA1 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA2) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA3) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA3 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA4) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA4 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA5) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA5 WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: FMC TDC timestamps interrupt (FIFO1) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO2) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO2 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO3) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO3 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO4) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO4 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO5) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO5 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA1) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA1 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA2) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA3) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA3 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA4) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA4 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA5) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA5 WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: FMC TDC timestamps interrupt (FIFO1) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO2) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO2 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO3) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO3 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO4) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO4 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO5) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO5 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA1) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA1 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA2) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA3) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA3 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA4) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA4 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA5) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA5 WBGEN2_GEN_MASK(9, 1)
/* [0x20]: REG Interrupt disable register */
#define TDC_EIC_REG_EIC_IDR 0x00000000
/* [0x24]: REG Interrupt enable register */
#define TDC_EIC_REG_EIC_IER 0x00000004
/* [0x28]: REG Interrupt mask register */
#define TDC_EIC_REG_EIC_IMR 0x00000008
/* [0x2c]: REG Interrupt status register */
#define TDC_EIC_REG_EIC_ISR 0x0000000c
#endif
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