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FMC TDC 1ns 5cha
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FMC TDC 1ns 5cha
Commits
9b1880f9
Commit
9b1880f9
authored
Mar 24, 2021
by
Tristan Gingold
Committed by
Federico Vaga
Jul 25, 2022
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rtl: minor style and comments.
parent
23be8ac6
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3 changed files
with
3 additions
and
10 deletions
+3
-10
fmc_tdc_core.vhd
hdl/rtl/fmc_tdc_core.vhd
+1
-2
reg_ctrl.vhd
hdl/rtl/reg_ctrl.vhd
+1
-8
wrabbit_sync.vhd
hdl/rtl/wrabbit_sync.vhd
+1
-0
No files found.
hdl/rtl/fmc_tdc_core.vhd
View file @
9b1880f9
...
...
@@ -198,8 +198,7 @@ entity fmc_tdc_core is
irq_threshold_o
:
out
std_logic_vector
(
9
downto
0
);
irq_timeout_o
:
out
std_logic_vector
(
9
downto
0
);
fmc_id_i
:
in
std_logic
);
fmc_id_i
:
in
std_logic
);
end
fmc_tdc_core
;
...
...
hdl/rtl/reg_ctrl.vhd
View file @
9b1880f9
...
...
@@ -94,7 +94,7 @@ entity reg_ctrl is
local_utc_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
-- local utc time
-- Signals not used so far
core_status_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
-- TDC core status word
currently unused
core_status_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
-- TDC core status word
-- White Rabbit status
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
--
...
...
@@ -173,15 +173,8 @@ architecture rtl of reg_ctrl is
signal
wb_in
:
t_wishbone_slave_in
;
signal
wb_out
:
t_wishbone_slave_out
;
--=================================================================================================
-- architecture begin
--=================================================================================================
signal
cc_rst_n
:
std_logic
;
signal
cc_rst_n_or_sys
:
std_logic
;
begin
wb_out
.
stall
<=
'0'
;
...
...
hdl/rtl/wrabbit_sync.vhd
View file @
9b1880f9
...
...
@@ -176,6 +176,7 @@ begin
else
wrabbit_state_changed
<=
'0'
;
end
if
;
when
wrabbit_WAIT_READY
=>
wrabbit_clk_aux_lock_en
<=
'0'
;
...
...
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