Commit 92b7f5e7 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

top/svec: single, WR-only top level

parent 3ee4e288
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Release 13.4 Map O.87xd (nt)
Xilinx Map Application Log File for Design 'svec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o svec_tdc_map.ncd svec_tdc.ngd svec_tdc.pcf
Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 18:14:34 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 32 secs
Total CPU time at the beginning of Placer: 31 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:8f55c916) REAL time: 39 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:8f55c916) REAL time: 40 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:8f55c916) REAL time: 40 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:a1530eec) REAL time: 54 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:a1530eec) REAL time: 54 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:a1530eec) REAL time: 54 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:a1530eec) REAL time: 55 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a1530eec) REAL time: 55 secs
Phase 9.8 Global Placement
....................................................
.........................................................................................................................................................................................................
......................................................................................................................................................................................
....................................................................
Phase 9.8 Global Placement (Checksum:da2f71c0) REAL time: 1 mins 56 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:da2f71c0) REAL time: 1 mins 56 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:f94a054e) REAL time: 2 mins 33 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:f94a054e) REAL time: 2 mins 33 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:3b63104b) REAL time: 2 mins 34 secs
Total REAL time to Placer completion: 3 mins 23 secs
Total CPU time to Placer completion: 3 mins 22 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_76_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_76_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 3
Slice Logic Utilization:
Number of Slice Registers: 7,035 out of 184,304 3%
Number used as Flip Flops: 6,985
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 46
Number of Slice LUTs: 9,194 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909
Number using O5 output only: 351
Number using O5 and O6: 2,766
Number used as ROM: 0
Number used as Memory: 35 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 35
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 26
Number used exclusively as route-thrus: 133
Number with same-slice register load: 58
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,585 out of 23,038 15%
Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,689
Number with an unused Flip Flop: 4,235 out of 10,689 39%
Number with an unused LUT: 1,495 out of 10,689 13%
Number of fully used LUT-FF pairs: 4,959 out of 10,689 46%
Number of unique control sets: 264
Number of slice register sites lost
to control set restrictions: 486 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 253 out of 540 46%
Number of LOCed IOBs: 253 out of 253 100%
IOB Flip Flops: 201
Specific Feature Utilization:
Number of RAMB16BWERs: 14 out of 268 5%
Number of RAMB8BWERs: 7 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 138 out of 586 23%
Number used as ILOGIC2s: 138
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 63 out of 586 10%
Number used as OLOGIC2s: 63
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 6 16%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.00
Peak Memory Usage: 528 MB
Total REAL time to MAP completion: 3 mins 32 secs
Total CPU time to MAP completion: 3 mins 30 secs
Mapping completed.
See MAP report file "svec_tdc_map.mrp" for details.
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......@@ -2,13 +2,13 @@ files = ["synthesis_descriptor.vhd",
"wr_svec_tdc.ucf",
"wr_svec_tdc.vhd"];
fetchto = "../../../ip_cores"
fetchto = "../../ip_cores"
modules = {
"local" : [ "../../../rtl/",
"../../../ip_cores/vme64x-core",
"../../../ip_cores/general-cores",
"../../../ip_cores/wr-cores"
"local" : [ "../../rtl/",
"../../ip_cores/vme64x-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"
]
}
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......@@ -376,16 +376,16 @@ architecture rtl of wr_svec_tdc is
constant c_SLAVE_WRCORE : integer := 4; -- White Rabbit PTP core
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_FMC_TDC1_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_FMC_TDC2_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_FMC_TDC1_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_FMC_TDC2_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(0 => f_sdb_embed_device (c_SVEC_INFO_SDB_DEVICE, x"00020000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"),
2 => f_sdb_embed_bridge (c_FMC_TDC1_SDB_BRIDGE, x"00040000"),
3 => f_sdb_embed_bridge (c_FMC_TDC2_SDB_BRIDGE, x"00060000"),
4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
(0 => f_sdb_embed_device (c_SVEC_INFO_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00002000"),
2 => f_sdb_embed_bridge (c_FMC_TDC1_SDB_BRIDGE, x"00010000"),
3 => f_sdb_embed_bridge (c_FMC_TDC2_SDB_BRIDGE, x"00020000"),
4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00040000"),
5 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
6 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
......@@ -393,8 +393,8 @@ architecture rtl of wr_svec_tdc is
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00052000",
1 => x"00072000");
(0 => x"00013000",
1 => x"00023000");
---------------------------------------------------------------------------------------------------
-- Signals --
......@@ -498,9 +498,6 @@ architecture rtl of wr_svec_tdc is
signal led_state : std_logic_vector(15 downto 0);
signal tdc1_ef, tdc2_ef, led_tdc1_ef : std_logic;
signal led_tdc2_ef, led_vme_access : std_logic;
signal led_clk_62m5_divider : unsigned(22 downto 0);
signal led_clk_62m5_aux : std_logic_vector(7 downto 0);
signal led_clk_62m5 : std_logic;
signal wrabbit_led_red, wrabbit_led_green : std_logic;
--=================================================================================================
......@@ -524,7 +521,7 @@ begin
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50, -- 20 MHz x 50 = 1 GHz
CLKFBOUT_MULT => 8, -- 125 MHz x 8 = 1 GHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
......@@ -535,7 +532,7 @@ begin
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_sys_fb,
......@@ -548,7 +545,7 @@ begin
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_sys_fb,
CLKIN => clk_20m_vcxo_buf);
CLKIN => clk_125m_pllref);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_sys_buf : BUFG
port map
......@@ -999,10 +996,87 @@ begin
tdc1_scl_in <= tdc1_scl_b;
tdc1_sda_in <= tdc1_sda_b;
cmp_tdc_mezzanine_2: fmc_tdc_wrapper
generic map (
g_simulation => g_simulation,
g_with_direct_readout => false )
port map (
clk_sys_i => clk_62m5_sys,
rst_sys_n_i => rst_n_sys,
rst_n_a_i => tdc2_soft_rst_n,
pll_sclk_o => tdc2_pll_sclk_o,
pll_sdi_o => tdc2_pll_sdi_o,
pll_cs_o => tdc2_pll_cs_n_o,
pll_dac_sync_o => tdc2_pll_dac_sync_n_o,
pll_sdo_i => tdc2_pll_sdo_i,
pll_status_i => tdc2_pll_status_i,
tdc_clk_125m_p_i => tdc2_125m_clk_p_i,
tdc_clk_125m_n_i => tdc2_125m_clk_n_i,
acam_refclk_p_i => tdc2_acam_refclk_p_i,
acam_refclk_n_i => tdc2_acam_refclk_n_i,
start_from_fpga_o => tdc2_start_from_fpga_o,
err_flag_i => tdc2_err_flag_i,
int_flag_i => tdc2_int_flag_i,
start_dis_o => tdc2_start_dis_o,
stop_dis_o => tdc2_stop_dis_o,
data_bus_io => tdc2_data_bus_io,
address_o => tdc2_address_o,
cs_n_o => tdc2_cs_n_o,
oe_n_o => tdc2_oe_n_o,
rd_n_o => tdc2_rd_n_o,
wr_n_o => tdc2_wr_n_o,
ef1_i => tdc2_ef1_i,
ef2_i => tdc2_ef2_i,
enable_inputs_o => tdc2_enable_inputs_o,
term_en_1_o => tdc2_term_en_1_o,
term_en_2_o => tdc2_term_en_2_o,
term_en_3_o => tdc2_term_en_3_o,
term_en_4_o => tdc2_term_en_4_o,
term_en_5_o => tdc2_term_en_5_o,
tdc_led_status_o => tdc2_led_status_o,
tdc_led_trig1_o => tdc2_led_trig1_o,
tdc_led_trig2_o => tdc2_led_trig2_o,
tdc_led_trig3_o => tdc2_led_trig3_o,
tdc_led_trig4_o => tdc2_led_trig4_o,
tdc_led_trig5_o => tdc2_led_trig5_o,
tdc_in_fpga_1_i => tdc2_in_fpga_1_i,
tdc_in_fpga_2_i => tdc2_in_fpga_2_i,
tdc_in_fpga_3_i => tdc2_in_fpga_3_i,
tdc_in_fpga_4_i => tdc2_in_fpga_4_i,
tdc_in_fpga_5_i => tdc2_in_fpga_5_i,
mezz_scl_i => tdc2_scl_in,
mezz_sda_i => tdc2_sda_in,
mezz_scl_o => tdc2_scl_oen,
mezz_sda_o => tdc2_sda_oen,
mezz_one_wire_b => tdc2_onewire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_utc,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(1),
tm_clk_aux_locked_i => tm_clk_aux_locked(1),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr_p(1),
slave_i => cnx_master_out(c_SLAVE_TDC1),
slave_o => cnx_master_in(c_SLAVE_TDC1),
irq_o => tdc2_irq,
clk_125m_tdc_o => tdc2_125m_clk);
tdc2_scl_b <= '0' when (tdc2_scl_oen = '0') else 'Z';
tdc2_sda_b <= '0' when (tdc2_sda_oen = '0') else 'Z';
tdc2_scl_in <= tdc2_scl_b;
tdc2_sda_in <= tdc2_sda_b;
---------------------------------------------------------------------------------------------------
-- VECTOR INTERRUPTS CONTROLLER --
---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
cmp_irq_vic : xwb_vic
generic map
......
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