hdl: eliminate WB int, bring all submodules up-to-date

8a82e727 · Dimitris Lampridis · b10c63a4 · f19220ff · 0545c25b · 5ffe9f53
Commit 8a82e727 authored Jul 20, 2018 by Dimitris Lampridis
11 changed files
--- a/etherbone-core @ f19220ff
+++ b/etherbone-core @ f19220ff
-Subproject commit 8489445985ff2afe6c72712014a92a271869f20a
+Subproject commit f19220ffa3c5e526f66ebbded5e0e1e789e7255d
--- a/general-cores @ 0545c25b
+++ b/general-cores @ 0545c25b
-Subproject commit 5205d9754b1e0887df5914a47f8aa745e4f3c2fe
+Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
--- a/gn4124-core @ 5ffe9f53
+++ b/gn4124-core @ 5ffe9f53
-Subproject commit 9b9625bb4270114266cd357f199d649f3d799f04
+Subproject commit 5ffe9f5344e22262d1badeef21b8426d20948368
--- a/vme64x-core @ 633d3174
+++ b/vme64x-core @ 633d3174
-Subproject commit fa34d06e35ca0bfad8eac24aa51713e81639da64
+Subproject commit 633d31749b104d4ca04c569cf3e30c5a6c9902b5
--- a/wr-cores @ c466a66b
+++ b/wr-cores @ c466a66b
-Subproject commit 69cc4cc3132530c836cd57ce1b282e8377fe7a07
+Subproject commit c466a66b4d17173d3ee5e18af26a2d263a760aa0
--- a/hdl/rtl/data_engine.vhd
+++ b/hdl/rtl/data_engine.vhd
@@ -76,6 +76,7 @@ use IEEE.NUMERIC_STD.all;    -- conversion functions
 -- Specific library
 library work;
 use work.tdc_core_pkg.all;   -- definitions of types, constants, entities
+use work.gencores_pkg.all;


 --=================================================================================================

--- a/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/rtl/fmc_tdc_mezzanine.vhd
@@ -534,7 +534,6 @@ begin
  -- Unused wishbone signals
  cnx_master_in(c_WB_SLAVE_TDC_EIC).err <= '0';
  cnx_master_in(c_WB_SLAVE_TDC_EIC).rty <= '0';
-  cnx_master_in(c_WB_SLAVE_TDC_EIC).int <= '0';


 ---------------------------------------------------------------------------------------------------

--- a/hdl/rtl/tdc_core_pkg.vhd
+++ b/hdl/rtl/tdc_core_pkg.vhd
@@ -937,29 +937,8 @@ package tdc_core_pkg is
      clk_125m_tdc_o       : out   std_logic);
  end component fmc_tdc_wrapper;

-  function f_pick(cond:boolean; if_true: std_logic_vector; if_false: std_logic_vector) return std_logic_vector;
-  
-  
-end tdc_core_pkg;
--=================================================================================================
--                                        package body
--=================================================================================================
-package body tdc_core_pkg is
-
-  function f_pick(cond:boolean; if_true: std_logic_vector; if_false: std_logic_vector) return std_logic_vector is
-    begin
-      if(cond) then
-        return if_true;
-        else
-          return if_false;
-          end if;
-      end f_pick;
-  
 end tdc_core_pkg;
--=================================================================================================
--                                         package end
--=================================================================================================
+
 ---------------------------------------------------------------------------------------------------
 --                                      E N D   O F   F I L E
 ---------------------------------------------------------------------------------------------------
-
--- a/hdl/top/spec/wr_spec_tdc.vhd
+++ b/hdl/top/spec/wr_spec_tdc.vhd
@@ -525,7 +525,6 @@ begin
     csr_stall_i     => cnx_slave_out(c_MASTER_GENNUM).stall,
     csr_err_i       => cnx_slave_out(c_MASTER_GENNUM).err,
     csr_rty_i       => cnx_slave_out(c_MASTER_GENNUM).rty,
-     csr_int_i       => cnx_slave_out(c_MASTER_GENNUM).int,
     -- DMA: not used
     dma_clk_i       => clk_sys_62m5,
     dma_ack_i       => '1',
@@ -533,7 +532,6 @@ begin
     dma_stall_i     => '0',
     dma_err_i       => '0',
     dma_rty_i       => '0',
-     dma_int_i       => '0',
     dma_reg_clk_i   => clk_sys_62m5,
     dma_reg_adr_i   => (others => '0'),
     dma_reg_dat_i   => (others => '0'),
@@ -676,7 +674,6 @@ begin
  -- Unused wishbone signals
  cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
  cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
-  cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- Tristates for TDC mezzanine EEPROM

--- a/hdl/top/svec/wr_svec_tdc.ucf
+++ b/hdl/top/svec/wr_svec_tdc.ucf
@@ -115,8 +115,8 @@ NET "vme_iack_n_i" LOC = N1;
 NET "vme_ga_i[5]" LOC = M6;
 NET "vme_dtack_oe_o" LOC = T1;
 NET "vme_dtack_n_o" LOC = R5;
-NET "vme_ds_n_i[1]" LOC = Y7;
-NET "vme_ds_n_i[0]" LOC = Y6;
+NET "vme_ds_n_i[1]" LOC = Y6;
+NET "vme_ds_n_i[0]" LOC = Y7;
 NET "vme_data_oe_n_o" LOC = P1;
 NET "vme_data_dir_o" LOC = P2;
 NET "vme_berr_o" LOC = R3;

--- a/hdl/top/svec/wr_svec_tdc.vhd
+++ b/hdl/top/svec/wr_svec_tdc.vhd
@@ -615,7 +615,8 @@ begin
     vme_o.addr_dir   => vme_addr_dir_int,
     vme_o.addr_oe_n  => vme_addr_oe_n_o,
     wb_o             => cnx_slave_in(c_MASTER_VME),
-     wb_i             => vme_wb_in);
+     wb_i             => vme_wb_in,
+     int_i            => irq_to_vmecore); 
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  vme_berr_o <= not vme_berr_n;
  vme_irq_o  <= not vme_irq_n;
@@ -626,7 +627,6 @@ begin
  vme_wb_in.rty      <= cnx_slave_out(c_MASTER_VME).rty;
  vme_wb_in.stall    <= cnx_slave_out(c_MASTER_VME).stall;
  vme_wb_in.dat      <= cnx_slave_out(c_MASTER_VME).dat;
-  vme_wb_in.int      <= irq_to_vmecore;

  -- VME tri-state bufferes
  vme_data_b         <= vme_data_b_out    when vme_data_dir_int = '1' else (others => 'Z');
@@ -857,7 +857,6 @@ begin
  -- Unused wishbone signals
  cnx_master_in(c_SLAVE_SVEC_INFO).err   <= '0';
  cnx_master_in(c_SLAVE_SVEC_INFO).rty   <= '0';
-  cnx_master_in(c_SLAVE_SVEC_INFO).int   <= '0';


 ---------------------------------------------------------------------------------------------------