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FMC TDC 1ns 5cha
Commit 7f103f41 authored by egousiou's avatar egousiou
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small change on TDC LEDs behavior (to include termination enable) 

+code commenting

git-svn-id: http://svn.ohwr.org/fmc-tdc@176 85dfdc96-de2c-444c-878d-45b388be74a9
parent 2aeccb02
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Showing with 10411 additions and 4366 deletions
hdl/rtl/clks_rsts_manager.vhd
View file @ 7f103f41
......@@ -110,7 +110,7 @@ entity clks_rsts_manager is
send_dac_word_p_i : in std_logic; -- pulse upon PCIe/VME request for a DAC reconfiguration
dac_word_i : in std_logic_vector(23 downto 0); -- DAC Vout = Vref (dac_word/65536)
-- Signals from the white rabbit unit for the reconfiguration of the DAC
-- Signals from the White Rabbit unit for the reconfiguration of the DAC
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
......
hdl/rtl/data_engine.vhd
View file @ 7f103f41
......@@ -43,7 +43,10 @@
-- Last changes |
-- 06/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 04/2014 v1 EG added state RD_START01 |
-- 04/2014 v1 EG added states for reading the RD_START01 (currently though the start01 |
-- is not essential absolute timestamp calculations). added wait state |
-- before starting receiving timestamps, to ensure that the start pulse has|
-- been sent and the ACAM IRflag has toggled once |
-- |
---------------------------------------------------------------------------------------------------
......@@ -145,7 +148,8 @@ end data_engine;
architecture rtl of data_engine is
type engine_state_ty is (ACTIVE, INACTIVE, GET_STAMP1, GET_STAMP2, WR_CONFIG, RDBK_CONFIG,
RD_STATUS, RD_IFIFO1, RD_IFIFO2, RD_START01, WR_RESET, WAIT_FOR_START01, WAIT_START_FROM_FPGA, WAIT_UTC);
RD_STATUS, RD_IFIFO1, RD_IFIFO2, RD_START01, WR_RESET,
WAIT_FOR_START01, WAIT_START_FROM_FPGA, WAIT_UTC);
signal engine_st, nxt_engine_st : engine_state_ty;
signal acam_cyc, acam_stb, acam_we : std_logic;
......@@ -247,7 +251,7 @@ begin
-- ACTIVE, GET_STAMP1, GET_STAMP2: intensive acquisition of timestamps from ACAM.
-- ACAM can receive and tag pulses with an overall rate up to 31.25 MHz;
-- therefore locally, running with a 125 MHz clk, in order to be able to receive timestamps
-- as fast as they arrive, it is needed to use up to 4 clk cycles to retreive each of them.
-- as fast as they arrive, it is needed to use up to 4 clk cycles to retrieve each of them.
-- Timestamps are received as soon as the ef1, ef2 flags are at zero (indicating that the
-- iFIFOs are not empty!). In order to avoid metastabilities locally, the ef signals are
-- synchronized using a set of two registers.
......@@ -268,7 +272,7 @@ begin
-- = 16 ns after an rdn falling edge the ef_synch1 should be stable.
--
-- Using the ef_synch1 signal instead of the ef_synch2 makes it possible to realise
-- timestamps' aquisitions from ACAM in just 4 clk cycles.
-- timestamps' acquisitions from ACAM in just 4 clk cycles.
-- clk --|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
-- ef ------|_______________________________________________________|--------------
-- ef_meta -----------|_____________________________________________________|-----------
......@@ -304,7 +308,7 @@ begin
when WAIT_FOR_START01 => -- wait for some time until the acam Start01 is available
when WAIT_FOR_START01 => -- wait for some time until the ACAM Start01 is available
-----------------------------------------------
acam_cyc <= '0';
acam_stb <= '0';
......@@ -321,7 +325,7 @@ begin
when RD_START01 => -- read now the acam Start01
when RD_START01 => -- read now the ACAM Start01
-----------------------------------------------
acam_cyc <= '1';
acam_stb <= '1';
......@@ -337,8 +341,8 @@ begin
end if;
when WAIT_UTC => -- wait until the next utc comes; now the offsets of the start_retrig_ctrl unit are defined
-- the acam is disabled during this period
when WAIT_UTC => -- wait until the next UTC comes; now the offsets of the start_retrig_ctrl unit are defined
-- the ACAM is disabled during this period
-----------------------------------------------
acam_cyc <= '0';
acam_stb <= '0';
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 7f103f41
......@@ -410,6 +410,7 @@ begin
---------------------------------------------------------------------------------------------------
-- WHITE RABBIT STUFF --
-- only synthesized if g_with_wrabbit_core is TRUE --
---------------------------------------------------------------------------------------------------
cmp_wrabbit_synch: wrabbit_sync
generic map
......
hdl/rtl/leds_manager.vhd
View file @ 7f103f41
......@@ -18,15 +18,35 @@
-- | | |
-- | O O | 1, 2 |
-- | O O | 3, 4 |
-- | O O | 5, 6 |
-- | O O | 5, STA |
-- |______| |
-- |
-- TDC LED 1 orange: division of the 125 MHz clock; one hz pulses |
-- TDC LED 2 orange: Channel 1 termination enable |
-- TDC LED 3 orange: Channel 2 termination enable |
-- TDC LED 4 orange: Channel 3 termination enable |
-- TDC LED 5 orange: Channel 4 termination enable |
-- TDC LED 6 orange: Channel 5 termination enable |
-- TDC LED 1 orange :blink upon timestamp registration for Channel 1; |
-- if the input termination for Channel 1 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 1 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED 2 orange: blink upon timestamp registration for Channel 2; |
-- if the input termination for Channel 2 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 2 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED 3 orange: blink upon timestamp registration for Channel 2; |
-- if the input termination for Channel 3 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 3 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED 4 orange: blink upon timestamp registration for Channel 4; |
-- if the input termination for Channel 4 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 4 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED 5 orange: blink upon timestamp registration for Channel 5; |
-- if the input termination for Channel 5 is ON, there is a |
-- blinking of the LED when the timestamp is written in the buffer|
-- if the input termination for Channel 5 is OFF,the LED is always|
-- ON and it turns OFF when the timestamp is written in the buffer|
-- TDC LED STA orange:division of the 125 MHz clock; one hz pulses |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Date 05/2012 |
......@@ -88,8 +108,8 @@ entity leds_manager is
-- activation comes through dedicated reg c_ACAM_INPUTS_EN_ADR
-- Signal for debugging
acam_channel_i : in std_logic_vector(5 downto 0); -- for debugging, currently not used
tstamp_wr_p_i : in std_logic;
acam_channel_i : in std_logic_vector(5 downto 0); -- identification of the channel for which a timestamp has arrived
tstamp_wr_p_i : in std_logic; -- pulse upon the writing of the timestamp in the circular buffer
-- OUTPUTS
......@@ -159,11 +179,31 @@ begin
led_1to5_outputs: process (clk_i)
begin
if rising_edge (clk_i) then
tdc_led_trig1_o <= blink_led1; --acam_inputs_en_i(0) and blink_led1;
tdc_led_trig2_o <= blink_led2; --acam_inputs_en_i(1) and blink_led2;
tdc_led_trig3_o <= blink_led3; --acam_inputs_en_i(2) and blink_led3;
tdc_led_trig4_o <= blink_led4; --acam_inputs_en_i(3) and blink_led4;
tdc_led_trig5_o <= blink_led5; --acam_inputs_en_i(4) and blink_led5;
if acam_inputs_en_i(0) = '1' then
tdc_led_trig1_o <= blink_led1;
else
tdc_led_trig1_o <= not blink_led1;
end if;
if acam_inputs_en_i(1) = '1' then
tdc_led_trig2_o <= blink_led2;
else
tdc_led_trig2_o <= not blink_led2;
end if;
if acam_inputs_en_i(2) = '1' then
tdc_led_trig3_o <= blink_led3;
else
tdc_led_trig3_o <= not blink_led3;
end if;
if acam_inputs_en_i(3) = '1' then
tdc_led_trig4_o <= blink_led4;
else
tdc_led_trig4_o <= not blink_led4;
end if;
if acam_inputs_en_i(4) = '1' then
tdc_led_trig5_o <= blink_led5;
else
tdc_led_trig5_o <= not blink_led5;
end if;
end if;
end process;
......
hdl/syn/spec/no_wrabbit/spec_tdc.par
View file @ 7f103f41
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hdl/syn/spec/no_wrabbit/spec_tdc.twr
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hdl/syn/spec/no_wrabbit/spec_tdc_map.map
View file @ 7f103f41
......@@ -10,7 +10,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 19:36:47 2014
Mapped Date : Wed Jun 18 10:48:16 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
......@@ -25,60 +25,56 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 21 secs
Total REAL time at the beginning of Placer: 16 secs
Total CPU time at the beginning of Placer: 16 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:2600903f) REAL time: 23 secs
Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 18 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 134 IOs, 133 are locked
and 1 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:2600903f) REAL time: 24 secs
Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 19 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:2600903f) REAL time: 24 secs
Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 19 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:ec6e8cf2) REAL time: 56 secs
(Checksum:46e77852) REAL time: 49 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:ec6e8cf2) REAL time: 56 secs
Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 49 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:ec6e8cf2) REAL time: 56 secs
Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 49 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:1cc69456) REAL time: 57 secs
Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 49 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:1cc69456) REAL time: 57 secs
Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 50 secs
Phase 9.8 Global Placement
.........................
.......................................................
..............................................................
.............................
......................................................................................................................
....................................
...........................
Phase 9.8 Global Placement (Checksum:a68d4d0b) REAL time: 1 mins 35 secs
Phase 9.8 Global Placement (Checksum:986ae115) REAL time: 1 mins 18 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:a68d4d0b) REAL time: 1 mins 35 secs
Phase 10.5 Local Placement Optimization (Checksum:986ae115) REAL time: 1 mins 18 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:53438eda) REAL time: 1 mins 54 secs
Phase 11.18 Placement Optimization (Checksum:49eeddee) REAL time: 1 mins 33 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:53438eda) REAL time: 1 mins 54 secs
Phase 12.5 Local Placement Optimization (Checksum:49eeddee) REAL time: 1 mins 33 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:101dbd96) REAL time: 1 mins 55 secs
Phase 13.34 Placement Validation (Checksum:8fcb33fb) REAL time: 1 mins 33 secs
Total REAL time to Placer completion: 2 mins 10 secs
Total CPU time to Placer completion: 1 mins 45 secs
Total REAL time to Placer completion: 1 mins 40 secs
Total CPU time to Placer completion: 1 mins 40 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -98,7 +94,7 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,877 out of 27,288 14%
Number of Slice LUTs: 3,871 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
......@@ -111,18 +107,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 94
Number with same-slice register load: 61
Number with same-slice carry load: 33
Number used exclusively as route-thrus: 88
Number with same-slice register load: 54
Number with same-slice carry load: 34
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,513 out of 6,822 22%
Number of occupied Slices: 1,514 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,843
Number with an unused Flip Flop: 1,551 out of 4,843 32%
Number with an unused LUT: 966 out of 4,843 19%
Number of fully used LUT-FF pairs: 2,326 out of 4,843 48%
Number of LUT Flip Flop pairs used: 4,830
Number with an unused Flip Flop: 1,533 out of 4,830 31%
Number with an unused LUT: 959 out of 4,830 19%
Number of fully used LUT-FF pairs: 2,338 out of 4,830 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
......@@ -135,7 +131,7 @@ Slice Logic Distribution:
IO Utilization:
Number of bonded IOBs: 134 out of 296 45%
Number of LOCed IOBs: 133 out of 134 99%
Number of LOCed IOBs: 134 out of 134 100%
IOB Flip Flops: 55
Specific Feature Utilization:
......@@ -178,9 +174,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 354 MB
Total REAL time to MAP completion: 2 mins 21 secs
Total CPU time to MAP completion: 1 mins 49 secs
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 1 mins 45 secs
Total CPU time to MAP completion: 1 mins 44 secs
Mapping completed.
See MAP report file "spec_tdc_map.mrp" for details.
hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp 0 → 100644
View file @ 7f103f41
This diff is collapsed.
hdl/syn/spec/with_wrabbit/wr_spec_tdc.par
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This diff is collapsed.
hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr
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This diff is collapsed.
hdl/syn/spec/with_wrabbit/wr_spec_tdc.xise
View file @ 7f103f41
......@@ -1041,7 +1041,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../../top/spec/with_wrabbit/wr_spec_tdc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="326"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map
View file @ 7f103f41
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 19:54:15 2014
Mapped Date : Wed Jun 18 11:23:56 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
......@@ -26,57 +26,57 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 45 secs
Total CPU time at the beginning of Placer: 41 secs
Total REAL time at the beginning of Placer: 42 secs
Total CPU time at the beginning of Placer: 39 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:7ac4c860) REAL time: 49 secs
Phase 1.1 Initial Placement Analysis (Checksum:1353f92f) REAL time: 46 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:7ac4c860) REAL time: 51 secs
Phase 2.7 Design Feasibility Check (Checksum:1353f92f) REAL time: 47 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:403893f8) REAL time: 51 secs
Phase 3.31 Local Placement Optimization (Checksum:e55e413f) REAL time: 47 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:bb368ef0) REAL time: 1 mins 43 secs
(Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:bb368ef0) REAL time: 1 mins 43 secs
Phase 5.36 Local Placement Optimization (Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:bb368ef0) REAL time: 1 mins 43 secs
Phase 6.30 Global Clock Region Assignment (Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:bb368ef0) REAL time: 1 mins 43 secs
Phase 7.3 Local Placement Optimization (Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:bb368ef0) REAL time: 1 mins 44 secs
Phase 8.5 Local Placement Optimization (Checksum:31ab954b) REAL time: 1 mins 36 secs
Phase 9.8 Global Placement
......................
..........................................................................................
.............................................................................................................................................................................
........................................................................................................................................................
......................................................................
Phase 9.8 Global Placement (Checksum:12a29ddc) REAL time: 5 mins 35 secs
........................
.....................................................
............................................................................................................................................................................
..................................................................................................................................................................................
.................................................................................
Phase 9.8 Global Placement (Checksum:3d13c910) REAL time: 5 mins 19 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:12a29ddc) REAL time: 5 mins 36 secs
Phase 10.5 Local Placement Optimization (Checksum:3d13c910) REAL time: 5 mins 20 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:befb4ab8) REAL time: 6 mins 22 secs
Phase 11.18 Placement Optimization (Checksum:a2ead40e) REAL time: 6 mins 1 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:befb4ab8) REAL time: 6 mins 22 secs
Phase 12.5 Local Placement Optimization (Checksum:a2ead40e) REAL time: 6 mins 1 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:a3dc479f) REAL time: 6 mins 23 secs
Phase 13.34 Placement Validation (Checksum:6637292) REAL time: 6 mins 2 secs
Total REAL time to Placer completion: 6 mins 42 secs
Total CPU time to Placer completion: 6 mins 32 secs
Total REAL time to Placer completion: 6 mins 21 secs
Total CPU time to Placer completion: 6 mins 14 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -85,19 +85,19 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
......@@ -105,7 +105,7 @@ WARNING:PhysDesignRules:367 - The signal
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......@@ -133,10 +133,10 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,697 out of 27,288 39%
Number of Slice LUTs: 10,661 out of 27,288 39%
Number used as logic: 10,390 out of 27,288 38%
Number using O6 output only: 7,384
Number using O5 output only: 775
Number using O6 output only: 7,383
Number using O5 output only: 776
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
......@@ -149,18 +149,18 @@ Slice Logic Utilization:
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 240
Number with same-slice register load: 164
Number with same-slice carry load: 76
Number used exclusively as route-thrus: 204
Number with same-slice register load: 133
Number with same-slice carry load: 71
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,977 out of 6,822 58%
Number of occupied Slices: 4,024 out of 6,822 58%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,389
Number with an unused Flip Flop: 4,852 out of 12,389 39%
Number with an unused LUT: 1,692 out of 12,389 13%
Number of fully used LUT-FF pairs: 5,845 out of 12,389 47%
Number of LUT Flip Flop pairs used: 12,505
Number with an unused Flip Flop: 4,934 out of 12,505 39%
Number with an unused LUT: 1,844 out of 12,505 14%
Number of fully used LUT-FF pairs: 5,727 out of 12,505 45%
Number of unique control sets: 372
Number of slice register sites lost
to control set restrictions: 990 out of 54,576 1%
......@@ -220,9 +220,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 480 MB
Total REAL time to MAP completion: 6 mins 54 secs
Total CPU time to MAP completion: 6 mins 44 secs
Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 33 secs
Total CPU time to MAP completion: 6 mins 26 secs
Mapping completed.
See MAP report file "wr_spec_tdc_map.mrp" for details.
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp 0 → 100644
View file @ 7f103f41
This diff is collapsed.
hdl/syn/svec/no_wrabbit/svec_tdc.par
View file @ 7f103f41
This diff is collapsed.
hdl/syn/svec/no_wrabbit/svec_tdc.twr
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This diff is collapsed.
hdl/syn/svec/no_wrabbit/svec_tdc.xise
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......@@ -1045,7 +1045,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../../top/svec/no_wrabbit/svec_tdc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="316"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
hdl/syn/svec/no_wrabbit/svec_tdc_map.map
View file @ 7f103f41
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 20:06:12 2014
Mapped Date : Wed Jun 18 12:27:04 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
......@@ -25,56 +25,56 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 32 secs
Total CPU time at the beginning of Placer: 31 secs
Total REAL time at the beginning of Placer: 33 secs
Total CPU time at the beginning of Placer: 32 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:be5d5549) REAL time: 39 secs
Phase 1.1 Initial Placement Analysis (Checksum:a7de1977) REAL time: 39 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:be5d5549) REAL time: 41 secs
Phase 2.7 Design Feasibility Check (Checksum:a7de1977) REAL time: 41 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:be5d5549) REAL time: 41 secs
Phase 3.31 Local Placement Optimization (Checksum:a7de1977) REAL time: 41 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:daa240) REAL time: 54 secs
(Checksum:2b539d14) REAL time: 55 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:daa240) REAL time: 54 secs
Phase 5.36 Local Placement Optimization (Checksum:2b539d14) REAL time: 55 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:daa240) REAL time: 54 secs
Phase 6.30 Global Clock Region Assignment (Checksum:2b539d14) REAL time: 55 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:daa240) REAL time: 55 secs
Phase 7.3 Local Placement Optimization (Checksum:2b539d14) REAL time: 55 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:daa240) REAL time: 55 secs
Phase 8.5 Local Placement Optimization (Checksum:2b539d14) REAL time: 56 secs
Phase 9.8 Global Placement
...................................
................................................................................................................................................................................................................
..................................................................................................................................................................................
.................................................
Phase 9.8 Global Placement (Checksum:76fab4b7) REAL time: 1 mins 57 secs
.........................................
...............................................................................................................................................................................................................
.........................................................................................................................................................................................
.......................................................................
Phase 9.8 Global Placement (Checksum:4c7cc37c) REAL time: 2 mins
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:76fab4b7) REAL time: 1 mins 57 secs
Phase 10.5 Local Placement Optimization (Checksum:4c7cc37c) REAL time: 2 mins
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:a0540d59) REAL time: 2 mins 45 secs
Phase 11.18 Placement Optimization (Checksum:4ab5face) REAL time: 2 mins 54 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:a0540d59) REAL time: 2 mins 45 secs
Phase 12.5 Local Placement Optimization (Checksum:4ab5face) REAL time: 2 mins 54 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:fbe1fef2) REAL time: 2 mins 46 secs
Phase 13.34 Placement Validation (Checksum:ed98fec0) REAL time: 2 mins 55 secs
Total REAL time to Placer completion: 3 mins 31 secs
Total CPU time to Placer completion: 3 mins 28 secs
Total REAL time to Placer completion: 3 mins 41 secs
Total CPU time to Placer completion: 3 mins 39 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -102,11 +102,11 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 46
Number of Slice LUTs: 9,215 out of 92,152 9%
Number used as logic: 9,025 out of 92,152 9%
Number using O6 output only: 5,907
Number of Slice LUTs: 9,203 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909
Number using O5 output only: 351
Number using O5 and O6: 2,767
Number using O5 and O6: 2,766
Number used as ROM: 0
Number used as Memory: 35 out of 21,680 1%
Number used as Dual Port RAM: 0
......@@ -115,18 +115,18 @@ Slice Logic Utilization:
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 26
Number used exclusively as route-thrus: 155
Number with same-slice register load: 88
Number with same-slice carry load: 67
Number used exclusively as route-thrus: 142
Number with same-slice register load: 67
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,268 out of 23,038 14%
Number of occupied Slices: 3,359 out of 23,038 14%
Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,508
Number with an unused Flip Flop: 4,082 out of 10,508 38%
Number with an unused LUT: 1,293 out of 10,508 12%
Number of fully used LUT-FF pairs: 5,133 out of 10,508 48%
Number of LUT Flip Flop pairs used: 10,598
Number with an unused Flip Flop: 4,155 out of 10,598 39%
Number with an unused LUT: 1,395 out of 10,598 13%
Number of fully used LUT-FF pairs: 5,048 out of 10,598 47%
Number of unique control sets: 264
Number of slice register sites lost
to control set restrictions: 486 out of 184,304 1%
......@@ -177,9 +177,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 4.00
Peak Memory Usage: 534 MB
Total REAL time to MAP completion: 3 mins 40 secs
Total CPU time to MAP completion: 3 mins 37 secs
Peak Memory Usage: 529 MB
Total REAL time to MAP completion: 3 mins 50 secs
Total CPU time to MAP completion: 3 mins 47 secs
Mapping completed.
See MAP report file "svec_tdc_map.mrp" for details.
hdl/syn/svec/no_wrabbit/svec_tdc_map.mrp
View file @ 7f103f41
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jun 17 20:06:12 2014
Mapped Date : Wed Jun 18 12:27:04 2014
Design Summary
--------------
......@@ -22,11 +22,11 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 46
Number of Slice LUTs: 9,215 out of 92,152 9%
Number used as logic: 9,025 out of 92,152 9%
Number using O6 output only: 5,907
Number of Slice LUTs: 9,203 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909
Number using O5 output only: 351
Number using O5 and O6: 2,767
Number using O5 and O6: 2,766
Number used as ROM: 0
Number used as Memory: 35 out of 21,680 1%
Number used as Dual Port RAM: 0
......@@ -35,18 +35,18 @@ Slice Logic Utilization:
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 26
Number used exclusively as route-thrus: 155
Number with same-slice register load: 88
Number with same-slice carry load: 67
Number used exclusively as route-thrus: 142
Number with same-slice register load: 67
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,268 out of 23,038 14%
Number of occupied Slices: 3,359 out of 23,038 14%
Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,508
Number with an unused Flip Flop: 4,082 out of 10,508 38%
Number with an unused LUT: 1,293 out of 10,508 12%
Number of fully used LUT-FF pairs: 5,133 out of 10,508 48%
Number of LUT Flip Flop pairs used: 10,598
Number with an unused Flip Flop: 4,155 out of 10,598 39%
Number with an unused LUT: 1,395 out of 10,598 13%
Number of fully used LUT-FF pairs: 5,048 out of 10,598 47%
Number of unique control sets: 264
Number of slice register sites lost
to control set restrictions: 486 out of 184,304 1%
......@@ -97,9 +97,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 4.00
Peak Memory Usage: 534 MB
Total REAL time to MAP completion: 3 mins 40 secs
Total CPU time to MAP completion: 3 mins 37 secs
Peak Memory Usage: 529 MB
Total REAL time to MAP completion: 3 mins 50 secs
Total CPU time to MAP completion: 3 mins 47 secs
Table of Contents
-----------------
......
hdl/syn/svec/with_wrabbit/wr_svec_tdc.par
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hdl/syn/svec/with_wrabbit/wr_svec_tdc.twr
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This diff is collapsed.
hdl/syn/svec/with_wrabbit/wr_svec_tdc.xise
View file @ 7f103f41
......@@ -1046,7 +1046,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../../top/svec/with_wrabbit/wr_svec_tdc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="316"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
hdl/top/spec/no_wrabbit/spec_tdc.ucf
View file @ 7f103f41
......@@ -330,8 +330,8 @@ NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#NET "spec_aux5_o" IOSTANDARD = "LVCMOS18";
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = "LVCMOS25";
#NET "led_red_o" LOC = D5;
#NET "led_red_o" IOSTANDARD = "LVCMOS25";
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# False Path
......
hdl/top/spec/no_wrabbit/spec_tdc.vhd
View file @ 7f103f41
......@@ -585,12 +585,13 @@ begin
(g_width => 5000000)
port map
(clk_i => clk_125m,
rst_n_i => not(rst_125m),
rst_n_i => rst_125m_n,
pulse_i => irq_to_gn4124,
extended_o => led_red);
-- -- -- -- -- -- --
led_red_o <= led_red;
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
---------------------------------------------------------------------------------------------------
......
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