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FMC TDC 1ns 5cha
Commits
6ea12fc9
Commit
6ea12fc9
authored
Mar 24, 2021
by
Tristan Gingold
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direct_readout: add a presence status for the fmc
parent
0f3ea17e
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6 changed files
with
68 additions
and
10 deletions
+68
-10
fmc_tdc_direct_readout.vhd
hdl/rtl/fmc_tdc_direct_readout.vhd
+2
-0
fmc_tdc_direct_readout_slave.vhd
hdl/rtl/fmc_tdc_direct_readout_slave.vhd
+43
-5
fmc_tdc_direct_readout_slave_pkg.vhd
hdl/rtl/fmc_tdc_direct_readout_slave_pkg.vhd
+8
-5
fmc_tdc_wrapper.vhd
hdl/rtl/fmc_tdc_wrapper.vhd
+2
-0
build_wb.sh
hdl/rtl/wbgen/build_wb.sh
+2
-0
fmc_tdc_direct_readout_slave.wb
hdl/rtl/wbgen/fmc_tdc_direct_readout_slave.wb
+11
-0
No files found.
hdl/rtl/fmc_tdc_direct_readout.vhd
View file @
6ea12fc9
...
...
@@ -12,6 +12,7 @@ entity fmc_tdc_direct_readout is
port
(
clk_sys_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
fmc_present_n_i
:
in
std_logic
;
timestamp_i
:
in
t_tdc_timestamp_array
(
4
downto
0
);
timestamp_valid_i
:
in
std_logic_vector
(
4
downto
0
);
...
...
@@ -66,6 +67,7 @@ begin
regs_in
.
fifo_bins_i
<=
"000000"
&
timestamp_i
(
channel_select
)
.
frac
;
regs_in
.
fifo_wr_req_i
<=
f_to_std_logic
(
fifo_wr
(
channel_select
)
=
'1'
and
regs_out
.
fifo_wr_full_o
=
'0'
);
regs_in
.
status_i
<=
not
fmc_present_n_i
;
U_WB_Slave
:
entity
work
.
fmc_tdc_direct_readout_wb_slave
port
map
(
...
...
hdl/rtl/fmc_tdc_direct_readout_slave.vhd
View file @
6ea12fc9
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC Direct Readout WB Slave
---------------------------------------------------------------------------------------
-- File : fmc_tdc_direct_readout_slave.vhd
-- File :
../
fmc_tdc_direct_readout_slave.vhd
-- Author : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb
-- Created :
Thu Sep 26 16:03:31 2019
-- Created :
Wed Mar 24 09:22:15 2021
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb
...
...
@@ -137,6 +137,43 @@ begin
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
regs_i
.
status_i
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
if
(
dr_fifo_rdreq_int_d0
=
'0'
)
then
...
...
@@ -146,13 +183,13 @@ begin
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
if
;
when
"
011
"
=>
when
"
100
"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
dr_fifo_out_int
(
63
downto
32
);
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10
0
"
=>
when
"10
1
"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
17
downto
0
)
<=
dr_fifo_out_int
(
81
downto
64
);
...
...
@@ -169,7 +206,7 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1
01
"
=>
when
"1
10
"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
16
)
<=
dr_fifo_full_int
;
...
...
@@ -244,6 +281,7 @@ begin
regs_o
.
chan_enable_o
<=
dr_chan_enable_int
;
-- Dead time (8ns ticks)
regs_o
.
dead_time_o
<=
dr_dead_time_int
;
-- FMC present
-- extra code for reg/fifo/mem: FIFO 'Readout FIFO' data output register 0
process
(
clk_sys_i
,
rst_n_i
)
begin
...
...
hdl/rtl/fmc_tdc_direct_readout_slave_pkg.vhd
View file @
6ea12fc9
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC Direct Readout WB Slave
---------------------------------------------------------------------------------------
-- File : fmc_tdc_direct_readout_slave_pkg.vhd
-- Author : auto-generated by wbgen2 from
wbgen/
fmc_tdc_direct_readout_slave.wb
-- Created :
Thu Sep 26 16:03:31 2019
-- File :
../
fmc_tdc_direct_readout_slave_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb
-- Created :
Wed Mar 24 09:22:15 2021
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
wbgen/
fmc_tdc_direct_readout_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
...
...
@@ -27,6 +27,7 @@ package dr_wbgen2_pkg is
fifo_bins_i
:
std_logic_vector
(
17
downto
0
);
fifo_edge_i
:
std_logic
;
fifo_channel_i
:
std_logic_vector
(
3
downto
0
);
status_i
:
std_logic
;
end
record
;
constant
c_dr_in_registers_init_value
:
t_dr_in_registers
:
=
(
...
...
@@ -35,7 +36,8 @@ package dr_wbgen2_pkg is
fifo_cycles_i
=>
(
others
=>
'0'
),
fifo_bins_i
=>
(
others
=>
'0'
),
fifo_edge_i
=>
'0'
,
fifo_channel_i
=>
(
others
=>
'0'
)
fifo_channel_i
=>
(
others
=>
'0'
),
status_i
=>
'0'
);
-- Output registers (WB slave -> user design)
...
...
@@ -90,6 +92,7 @@ tmp.fifo_cycles_i := f_x_to_zero(left.fifo_cycles_i) or f_x_to_zero(right.fifo_c
tmp
.
fifo_bins_i
:
=
f_x_to_zero
(
left
.
fifo_bins_i
)
or
f_x_to_zero
(
right
.
fifo_bins_i
);
tmp
.
fifo_edge_i
:
=
f_x_to_zero
(
left
.
fifo_edge_i
)
or
f_x_to_zero
(
right
.
fifo_edge_i
);
tmp
.
fifo_channel_i
:
=
f_x_to_zero
(
left
.
fifo_channel_i
)
or
f_x_to_zero
(
right
.
fifo_channel_i
);
tmp
.
status_i
:
=
f_x_to_zero
(
left
.
status_i
)
or
f_x_to_zero
(
right
.
status_i
);
return
tmp
;
end
function
;
end
package
body
;
hdl/rtl/fmc_tdc_wrapper.vhd
View file @
6ea12fc9
...
...
@@ -116,6 +116,7 @@ entity fmc_tdc_wrapper is
rst_n_a_i
:
in
std_logic
;
fmc_id_i
:
in
std_logic
;
fmc_present_n_i
:
in
std_logic
;
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
pll_sclk_o
:
out
std_logic
;
-- SPI clock
...
...
@@ -282,6 +283,7 @@ begin
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_sys_n_i
=>
rst_sys_n_i
,
fmc_present_n_i
=>
fmc_present_n_i
,
timestamp_i
=>
timestamp
,
timestamp_valid_i
=>
timestamp_valid
,
direct_slave_i
=>
cnx_master_out
(
c_slave_direct
),
...
...
hdl/rtl/wbgen/build_wb.sh
View file @
6ea12fc9
...
...
@@ -6,3 +6,5 @@ wbgen2 -V tdc_onewire_wb.vhd -H record_full -p tdc_onewire_wbgen2_pkg.vhd -K tim
#don't do this, latest wbgen is buggy
#wbgen2 -V tdc_eic.vhd -s defines -C tdc_eic.h -D wbgen/tdc_eic.html wbgen/tdc_eic.wb
# wbgen2 --hstyle=record -V ../fmc_tdc_direct_readout_slave.vhd -p ../fmc_tdc_direct_readout_slave_pkg.vhd -s defines -C fmctdc-direct.h fmc_tdc_direct_readout_slave.wb
hdl/rtl/wbgen/fmc_tdc_direct_readout_slave.wb
View file @
6ea12fc9
...
...
@@ -71,4 +71,15 @@ peripheral
access_dev = READ_ONLY;
};
};
reg {
name = "Status Register";
prefix = "STATUS";
field {
name = "FMC present";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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