Commit 69b62c38 authored by egousiou's avatar egousiou

-added reg for the deactivation of tstamps storage from a particular channel,…

-added reg for the deactivation of tstamps storage from a particular channel, while in acquisition mode
-this version has chipscope

git-svn-id: http://svn.ohwr.org/fmc-tdc@162 85dfdc96-de2c-444c-878d-45b388be74a9
parent 3fdf1bc3
......@@ -43,7 +43,7 @@
-- Last changes |
-- 06/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 14/2014 v1 EG added state RD_START01 |
-- 14/2014 v1 EG added state RD_START01 |
-- |
---------------------------------------------------------------------------------------------------
......@@ -384,7 +384,10 @@ begin
acam_we <= '0';
-----------------------------------------------
if acam_ack_i ='1' then
if deactivate_acq_p_i = '1' then
nxt_engine_st <= INACTIVE;
elsif acam_ack_i ='1' then
if acam_ef2_i = '0' then
nxt_engine_st <= GET_STAMP2;
......@@ -408,7 +411,10 @@ begin
acam_we <= '0';
-----------------------------------------------
if acam_ack_i ='1' then -- idem.
if deactivate_acq_p_i = '1' then
nxt_engine_st <= INACTIVE;
elsif acam_ack_i ='1' then
if acam_ef1_i ='0' then
nxt_engine_st <= GET_STAMP1;
......
......@@ -90,7 +90,8 @@ entity data_formatting is
-- Signals from the reg_ctrl unit
dacapo_c_rst_p_i : in std_logic; -- instruction from GN4124/VME to clear dacapo flag
deactivate_chan_i : in std_logic_vector(4 downto 0); -- instruction from GN4124/VME to stop registering tstamps from a specific channel
-- Signals from the one_hz_gen unit
utc_i : in std_logic_vector(31 downto 0); -- local UTC time
......@@ -153,7 +154,7 @@ architecture rtl of data_formatting is
signal tstamp_on_first_retrig_case2 : std_logic;
signal un_previous_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_previous_retrig_nb_offset : unsigned(31 downto 0);
signal un_previous_roll_over_nb, un_previous_roll_over_nb2, un_previous_roll_over_nb3 : unsigned(31 downto 0);
signal un_previous_roll_over_nb : unsigned(31 downto 0);
signal un_current_retrig_nb_offset, un_current_roll_over_nb : unsigned(31 downto 0);
signal un_current_retrig_from_roll_over : unsigned(31 downto 0);
signal un_acam_fine_time :unsigned(31 downto 0);
......@@ -193,10 +194,45 @@ begin
tstamp_wr_cyc <= '0';
tstamp_wr_we <= '0';
elsif acam_tstamp1_ok_p_i ='1' or acam_tstamp2_ok_p_i ='1' then
tstamp_wr_stb <= '1';
tstamp_wr_cyc <= '1';
tstamp_wr_we <= '1';
elsif acam_tstamp1_ok_p_i = '1' then
if deactivate_chan_i = "00000" then
tstamp_wr_stb <= '1';
tstamp_wr_cyc <= '1';
tstamp_wr_we <= '1';
else
if deactivate_chan_i = "00001" and acam_tstamp1_i(27 downto 26) = "00" then
tstamp_wr_stb <= '0';
tstamp_wr_cyc <= '0';
tstamp_wr_we <= '0';
elsif deactivate_chan_i = "00010" and acam_tstamp1_i(27 downto 26) = "01" then
tstamp_wr_stb <= '0';
tstamp_wr_cyc <= '0';
tstamp_wr_we <= '0';
elsif deactivate_chan_i = "00100" and acam_tstamp1_i(27 downto 26) = "10" then
tstamp_wr_stb <= '0';
tstamp_wr_cyc <= '0';
tstamp_wr_we <= '0';
elsif deactivate_chan_i = "01000" and acam_tstamp1_i(27 downto 26) = "11" then
tstamp_wr_stb <= '0';
tstamp_wr_cyc <= '0';
tstamp_wr_we <= '0';
else
tstamp_wr_stb <= '1';
tstamp_wr_cyc <= '1';
tstamp_wr_we <= '1';
end if;
end if;
elsif acam_tstamp2_ok_p_i = '1' then
if deactivate_chan_i = "10000" then
tstamp_wr_stb <= '0';
tstamp_wr_cyc <= '0';
tstamp_wr_we <= '0';
else
tstamp_wr_stb <= '1';
tstamp_wr_cyc <= '1';
tstamp_wr_we <= '1';
end if;
elsif tstamp_wr_wb_ack_i = '1' then
tstamp_wr_stb <= '0';
......@@ -321,8 +357,6 @@ begin
un_previous_retrig_nb_offset <= (others => '0');
un_previous_roll_over_nb <= (others => '0');
previous_utc <= (others => '0');
un_previous_roll_over_nb2 <= unsigned(roll_over_nb_i);
un_previous_roll_over_nb3 <= un_previous_roll_over_nb2;
elsif utc_p_i = '1' then
un_previous_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
un_previous_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
......@@ -444,8 +478,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- metadata: information about the timestamp
metadata <= std_logic_vector(acam_start_nb(7 downto 0)) & -- std_logic_vector(un_previous_retrig_nb_offset(7 downto 0)) & -- for debugging (24 MSbits)
std_logic_vector(un_retrig_from_roll_over(4 downto 0)) & --acam_fifo_ef & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
std_logic_vector(un_retrig_nb_offset(7 downto 0)) & std_logic_vector(un_clk_i_cycles_offset(5 downto 0)) &
coarse_zero &--acam_fifo_ef & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
std_logic_vector(un_retrig_nb_offset(7 downto 0)) & std_logic_vector(roll_over_nb_i(9 downto 0)) &
acam_slope & roll_over_incr_recent_i & acam_channel; -- 5 LSbits-----------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......
......@@ -249,6 +249,7 @@ architecture rtl of fmc_tdc_core is
signal read_acam_config, read_acam_status, read_ififo1 : std_logic;
signal read_ififo2, read_start01, reset_acam, load_utc : std_logic;
signal clear_dacapo_counter, roll_over_incr_recent : std_logic;
signal deactivate_chan : std_logic_vector(4 downto 0);
signal pulse_delay, window_delay, clk_period : std_logic_vector(g_width-1 downto 0);
signal starting_utc, acam_inputs_en : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1, acam_ififo2, acam_start01 : std_logic_vector(g_width-1 downto 0);
......@@ -275,27 +276,27 @@ architecture rtl of fmc_tdc_core is
signal acam_tstamp_channel : std_logic_vector(2 downto 0);
-- Chipscope
--component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
-- CLK : in std_logic;
-- TRIG0 : in std_logic_vector(31 downto 0);
-- TRIG1 : in std_logic_vector(31 downto 0);
-- TRIG2 : in std_logic_vector(31 downto 0);
-- TRIG3 : in std_logic_vector(31 downto 0));
--end component;
--component chipscope_icon
-- port (
-- CONTROL0 : inout std_logic_vector (35 downto 0));
--end component;
--signal CONTROL : std_logic_vector(35 downto 0);
--signal CLK : std_logic;
--signal TRIG0 : std_logic_vector(31 downto 0);
--signal TRIG1 : std_logic_vector(31 downto 0);
--signal TRIG2 : std_logic_vector(31 downto 0);
--signal TRIG3 : std_logic_vector(31 downto 0);
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
......@@ -330,6 +331,7 @@ begin
acam_rst_p_o => reset_acam,
load_utc_p_o => load_utc,
dacapo_c_rst_p_o => clear_dacapo_counter,
deactivate_chan_o => deactivate_chan,
acam_config_rdbk_i => acam_config_rdbk,
acam_ififo1_i => acam_ififo1,
acam_ififo2_i => acam_ififo2,
......@@ -524,6 +526,7 @@ begin
acam_tstamp2_i => acam_tstamp2,
acam_tstamp2_ok_p_i => acam_tstamp2_ok_p,
dacapo_c_rst_p_i => clear_dacapo_counter,
deactivate_chan_i => deactivate_chan,
roll_over_incr_recent_i => roll_over_incr_recent,
clk_i_cycles_offset_i => clk_i_cycles_offset,
roll_over_nb_i => roll_over_nb,
......@@ -614,35 +617,35 @@ begin
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_125m_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
-- chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_125m_i,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL);
-- TRIG0(0) <= utc_p;
-- TRIG0(1) <= ef1_i;
-- TRIG0(2) <= int_flag_i;
-- TRIG0(3) <= acam_intflag_f_edge_p;
-- TRIG0(16 downto 4) <= roll_over_nb(12 downto 0);
-- TRIG0(17) <= start_from_fpga;
-- TRIG0(25 downto 18) <= retrig_nb_offset(7 downto 0);
-- TRIG0(31 downto 26) <= clk_i_cycles_offset(5 downto 0);
-- TRIG1(30 downto 0) <= acam_tstamp1(30 downto 0);
-- TRIG1(31) <= acam_tstamp1_ok_p;
-- TRIG2(31 downto 0) <= utc(31 downto 0);
TRIG0(0) <= utc_p;
TRIG0(1) <= ef1_i;
TRIG0(2) <= int_flag_i;
TRIG0(3) <= acam_intflag_f_edge_p;
TRIG0(16 downto 4) <= roll_over_nb(12 downto 0);
TRIG0(17) <= start_from_fpga;
TRIG0(25 downto 18) <= retrig_nb_offset(7 downto 0);
TRIG0(31 downto 26) <= clk_i_cycles_offset(5 downto 0);
TRIG1(30 downto 0) <= acam_tstamp1(30 downto 0);
TRIG1(31) <= acam_tstamp1_ok_p;
TRIG2(31 downto 0) <= utc(31 downto 0);
-- TRIG3(0) <= tdc_in_fpga_1_i;
-- TRIG3(31 downto 1) <= current_retrig_nb(30 downto 0);
TRIG3(0) <= tdc_in_fpga_1_i;
TRIG3(31 downto 1) <= current_retrig_nb(30 downto 0);
end rtl;
----------------------------------------------------------------------------------------------------
......
......@@ -240,6 +240,9 @@ architecture rtl of fmc_tdc_mezzanine is
-- Wishbone buse(s) to crossbar slave port(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
-- Wishbone bus from additional registers
signal xreg_slave_out : t_wishbone_slave_out;
signal xreg_slave_in : t_wishbone_slave_in;
-- WISHBONE addresses
signal tdc_core_wb_adr : std_logic_vector(31 downto 0);
signal tdc_mem_wb_adr : std_logic_vector(31 downto 0);
......@@ -275,6 +278,31 @@ begin
-- 0x13000 -> TDC mezzanine board EEPROM I2C
-- 0x14000 -> TDC core timestamps retreival
-- Additional register to help timing
cmp_xwb_reg : xwb_register_link
port map
(clk_sys_i => clk_ref_0_i,
rst_n_i => rst_ref_0_n,
slave_i => xreg_slave_in,
slave_o => xreg_slave_out,
master_i => cnx_slave_out(c_WB_MASTER),
master_o => cnx_slave_in(c_WB_MASTER));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
wb_tdc_csr_dat_o <= xreg_slave_out.dat;
wb_tdc_csr_ack_o <= xreg_slave_out.ack;
wb_tdc_csr_stall_o <= xreg_slave_out.stall;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Connect crossbar slave port to entity port
xreg_slave_in.adr <= wb_tdc_csr_adr_i;
xreg_slave_in.dat <= wb_tdc_csr_dat_i;
xreg_slave_in.sel <= wb_tdc_csr_sel_i;
xreg_slave_in.stb <= wb_tdc_csr_stb_i;
xreg_slave_in.we <= wb_tdc_csr_we_i;
xreg_slave_in.cyc <= wb_tdc_csr_cyc_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
......@@ -291,21 +319,7 @@ begin
master_i => cnx_master_in,
master_o => cnx_master_out);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
wb_tdc_csr_dat_o <= cnx_slave_out(c_WB_MASTER).dat;
wb_tdc_csr_ack_o <= cnx_slave_out(c_WB_MASTER).ack;
wb_tdc_csr_stall_o <= cnx_slave_out(c_WB_MASTER).stall;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Connect crossbar slave port to entity port
cnx_slave_in(c_WB_MASTER).adr <= wb_tdc_csr_adr_i;
cnx_slave_in(c_WB_MASTER).dat <= wb_tdc_csr_dat_i;
cnx_slave_in(c_WB_MASTER).sel <= wb_tdc_csr_sel_i;
cnx_slave_in(c_WB_MASTER).stb <= wb_tdc_csr_stb_i;
cnx_slave_in(c_WB_MASTER).we <= wb_tdc_csr_we_i;
cnx_slave_in(c_WB_MASTER).cyc <= wb_tdc_csr_cyc_i;
---------------------------------------------------------------------------------------------------
-- TDC CORE --
---------------------------------------------------------------------------------------------------
......@@ -506,28 +520,32 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board EEPROM I2C --
---------------------------------------------------------------------------------------------------
cmp_I2C_master : xwb_i2c_master
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map
(clk_sys_i => clk_ref_0_i,
rst_n_i => rst_ref_0_n,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
desc_o => open,
scl_pad_i => i2c_scl_i,
scl_pad_o => sys_scl_out,
scl_padoen_o => sys_scl_oe_n,
sda_pad_i => i2c_sda_i,
sda_pad_o => sys_sda_out,
sda_padoen_o => sys_sda_oe_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
i2c_sda_oen_o <= sys_sda_oe_n;
i2c_sda_o <= sys_sda_out;
i2c_scl_oen_o <= sys_scl_oe_n;
i2c_scl_o <= sys_scl_out;
-- cmp_I2C_master : xwb_i2c_master
-- generic map
-- (g_interface_mode => PIPELINED,
-- g_address_granularity => BYTE)
-- port map
-- (clk_sys_i => clk_ref_0_i,
-- rst_n_i => rst_ref_0_n,
-- slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
-- slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
-- desc_o => open,
-- scl_pad_i => i2c_scl_i,
-- scl_pad_o => sys_scl_out,
-- scl_padoen_o => sys_scl_oe_n,
-- sda_pad_i => i2c_sda_i,
-- sda_pad_o => sys_sda_out,
-- sda_padoen_o => sys_sda_oe_n);
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- i2c_sda_oen_o <= sys_sda_oe_n;
-- i2c_sda_o <= sys_sda_out;
-- i2c_scl_oen_o <= sys_scl_oe_n;
-- i2c_scl_o <= sys_scl_out;
i2c_sda_oen_o <= '0';
i2c_sda_o <= '0';
i2c_scl_oen_o <= '0';
i2c_scl_o <= '0';
end rtl;
......
......@@ -136,8 +136,9 @@ entity reg_ctrl is
-- Signal to the data_formatting unit
dacapo_c_rst_p_o : out std_logic; -- clears the dacapo counter
deactivate_chan_o : out std_logic_vector(4 downto 0); -- stops registering timestamps from a specific channel
-- Signals to the clks_resets_manager ubit
-- Signals to the clks_resets_manager unit
send_dac_word_p_o : out std_logic; -- initiates the reconfiguration of the DAC
dac_word_o : out std_logic_vector(23 downto 0);
......@@ -174,7 +175,7 @@ architecture rtl of reg_ctrl is
signal dac_word : std_logic_vector(23 downto 0);
signal pulse_extender_en : std_logic;
signal pulse_extender_c : std_logic_vector(2 downto 0);
signal dat_out, wrabbit_ctrl_reg : std_logic_vector(g_span-1 downto 0);
signal dat_out, wrabbit_ctrl_reg, deactivate_chan : std_logic_vector(g_span-1 downto 0);
signal tdc_config_wb_ack_o_pipe0 : std_logic;
......@@ -347,6 +348,10 @@ begin
if reg_adr = c_WRABBIT_CTRL_ADR then
wrabbit_ctrl_reg <= tdc_config_wb_dat_i;
end if;
if reg_adr = c_DEACT_CHAN_ADR then
deactivate_chan <= tdc_config_wb_dat_i;
end if;
end if;
end if;
......@@ -360,6 +365,7 @@ begin
irq_time_threshold_o <= irq_time_threshold;
dac_word_o <= dac_word;
wrabbit_ctrl_reg_o <= wrabbit_ctrl_reg;
deactivate_chan_o <= deactivate_chan(4 downto 0);
---------------------------------------------------------------------------------------------------
-- Reception of TDC core Control Register --
......@@ -486,7 +492,8 @@ begin
core_status_i when c_CORE_STATUS_ADR,
-- White Rabbit regs
wrabbit_status_reg_i when c_WRABBIT_STATUS_ADR,
wrabbit_ctrl_reg when c_WRABBIT_CTRL_ADR,
wrabbit_ctrl_reg when c_WRABBIT_CTRL_ADR,
deactivate_chan when c_DEACT_CHAN_ADR,
-- others
x"C0FFEEEE" when others;
......
......@@ -700,8 +700,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for Carrier EEPROM
mezz_sys_scl_b <= tdc_scl_out when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
mezz_sys_sda_b <= tdc_sda_out when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
mezz_sys_scl_b <= '0' when (wrc_scl_out = '0') else 'Z';--tdc_scl_out when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
mezz_sys_sda_b <= '0' when (wrc_sda_out = '0') else 'Z';--tdc_sda_out when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
wrc_scl_in <= mezz_sys_scl_b;
wrc_sda_in <= mezz_sys_sda_b;
tdc_scl_in <= mezz_sys_scl_b;
......@@ -891,7 +891,7 @@ begin
wrabbit_time_valid_i => tm_time_valid,
wrabbit_cycles_i => tm_cycles,
wrabbit_utc_i => tm_utc(31 downto 0),
wrabbit_utc_p_o => open,
wrabbit_utc_p_o => open, -- for debug
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
......
......@@ -269,7 +269,7 @@ package tdc_core_pkg is
constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 0x51094 of GN4124 BAR 0
constant c_DAC_WORD_ADR : std_logic_vector(7 downto 0) := x"26"; -- address 0x51098 of GN4124 BAR 0
-- constant c_RESERVED1 : std_logic_vector(7 downto 0) := x"27"; -- address 0x5109C of GN4124 BAR 0
constant c_DEACT_CHAN_ADR : std_logic_vector(7 downto 0) := x"27"; -- address 0x5109C of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of TDC core Status registers to be written by the different core units
......@@ -677,6 +677,7 @@ package tdc_core_pkg is
tdc_config_wb_dat_o : out std_logic_vector(g_width-1 downto 0);
activate_acq_p_o : out std_logic;
deactivate_acq_p_o : out std_logic;
deactivate_chan_o : out std_logic_vector(4 downto 0);
acam_wr_config_p_o : out std_logic;
acam_rdbk_config_p_o : out std_logic;
acam_rdbk_status_p_o : out std_logic;
......@@ -734,6 +735,7 @@ package tdc_core_pkg is
acam_tstamp2_ok_p_i : in std_logic;
clk_i : in std_logic;
dacapo_c_rst_p_i : in std_logic;
deactivate_chan_i : in std_logic_vector(4 downto 0);
rst_i : in std_logic;
roll_over_incr_recent_i : in std_logic;
clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
......
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