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FMC TDC 1ns 5cha
Commit 62e81cfe authored by egousiou's avatar egousiou
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corrected bug in case where utp_p and acam_intflag_p arrive at the same time 

git-svn-id: http://svn.ohwr.org/fmc-tdc@163 85dfdc96-de2c-444c-878d-45b388be74a9
parent 69b62c38
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hdl/wr_spec_tdc/hdl/rtl/Copy of clks_rsts_manager.vhd deleted 100644 → 0
View file @ 69b62c38
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hdl/wr_spec_tdc/hdl/rtl/data_formatting.vhd
View file @ 62e81cfe
......@@ -387,7 +387,7 @@ begin
un_acam_start_nb <= unsigned(acam_start_nb_32);
un_current_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
un_current_roll_over_nb <= unsigned(roll_over_nb_i);
un_current_retrig_from_roll_over <= shift_left(un_current_roll_over_nb-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192
un_current_retrig_from_roll_over <= shift_left(un_current_roll_over_nb-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 and un_current_roll_over_nb > 0
else shift_left(un_current_roll_over_nb, 8);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -426,8 +426,10 @@ begin
coarse_zero <= '0';
else
-- ACAM tstamp arrived on the same retgigger after a new second
if (un_acam_start_nb+un_current_retrig_from_roll_over = un_current_retrig_nb_offset) or
if (un_acam_start_nb+un_current_retrig_from_roll_over = un_current_retrig_nb_offset) or
(un_acam_start_nb = un_current_retrig_nb_offset-1 and un_acam_fine_time > 6318 and (un_current_retrig_from_roll_over = 0) ) then
--if (un_acam_start_nb = un_current_retrig_nb_offset) or
-- (un_acam_start_nb = un_current_retrig_nb_offset-1 and un_acam_fine_time > 6318) then
coarse_zero <= '1';
un_clk_i_cycles_offset <= un_previous_clk_i_cycles_offset;
un_retrig_nb_offset <= un_previous_retrig_nb_offset;
......@@ -479,7 +481,7 @@ begin
-- metadata: information about the timestamp
metadata <= std_logic_vector(acam_start_nb(7 downto 0)) & -- std_logic_vector(un_previous_retrig_nb_offset(7 downto 0)) & -- for debugging (24 MSbits)
coarse_zero &--acam_fifo_ef & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
std_logic_vector(un_retrig_nb_offset(7 downto 0)) & std_logic_vector(roll_over_nb_i(9 downto 0)) &
std_logic_vector(un_retrig_nb_offset(7 downto 0)) & std_logic_vector(roll_over_nb_i(2 downto 0)) & std_logic_vector(un_clk_i_cycles_offset(6 downto 0)) &
acam_slope & roll_over_incr_recent_i & acam_channel; -- 5 LSbits-----------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......
hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_core.vhd
View file @ 62e81cfe
......@@ -617,35 +617,34 @@ begin
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_125m_i,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL);
TRIG0(0) <= utc_p;
TRIG0(1) <= ef1_i;
TRIG0(2) <= int_flag_i;
TRIG0(3) <= acam_intflag_f_edge_p;
TRIG0(16 downto 4) <= roll_over_nb(12 downto 0);
TRIG0(17) <= start_from_fpga;
TRIG0(25 downto 18) <= retrig_nb_offset(7 downto 0);
TRIG0(31 downto 26) <= clk_i_cycles_offset(5 downto 0);
TRIG1(30 downto 0) <= acam_tstamp1(30 downto 0);
TRIG1(31) <= acam_tstamp1_ok_p;
TRIG2(31 downto 0) <= utc(31 downto 0);
TRIG3(0) <= tdc_in_fpga_1_i;
TRIG3(31 downto 1) <= current_retrig_nb(30 downto 0);
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_125m_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--
-- chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
--
-- TRIG0(0) <= utc_p;
-- TRIG0(1) <= ef1_i;
-- TRIG0(2) <= acam_intflag_f_edge_p;
-- TRIG0(15 downto 3) <= roll_over_nb(12 downto 0);
-- TRIG0(16) <= start_from_fpga;
-- TRIG0(24 downto 17) <= retrig_nb_offset(7 downto 0);
-- TRIG0(31 downto 25) <= clk_i_cycles_offset(6 downto 0);
--
-- TRIG1(30 downto 0) <= acam_tstamp1(30 downto 0);
-- TRIG1(31) <= acam_tstamp1_ok_p;
--
-- TRIG2(31 downto 0) <= utc(31 downto 0);
--
-- TRIG3(0) <= tdc_in_fpga_1_i;
-- TRIG3(31 downto 1) <= current_retrig_nb(30 downto 0);
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 62e81cfe
......@@ -520,32 +520,32 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board EEPROM I2C --
---------------------------------------------------------------------------------------------------
-- cmp_I2C_master : xwb_i2c_master
-- generic map
-- (g_interface_mode => PIPELINED,
-- g_address_granularity => BYTE)
-- port map
-- (clk_sys_i => clk_ref_0_i,
-- rst_n_i => rst_ref_0_n,
-- slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
-- slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
-- desc_o => open,
-- scl_pad_i => i2c_scl_i,
-- scl_pad_o => sys_scl_out,
-- scl_padoen_o => sys_scl_oe_n,
-- sda_pad_i => i2c_sda_i,
-- sda_pad_o => sys_sda_out,
-- sda_padoen_o => sys_sda_oe_n);
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- i2c_sda_oen_o <= sys_sda_oe_n;
-- i2c_sda_o <= sys_sda_out;
-- i2c_scl_oen_o <= sys_scl_oe_n;
-- i2c_scl_o <= sys_scl_out;
i2c_sda_oen_o <= '0';
i2c_sda_o <= '0';
i2c_scl_oen_o <= '0';
i2c_scl_o <= '0';
cmp_I2C_master : xwb_i2c_master
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map
(clk_sys_i => clk_ref_0_i,
rst_n_i => rst_ref_0_n,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
desc_o => open,
scl_pad_i => i2c_scl_i,
scl_pad_o => sys_scl_out,
scl_padoen_o => sys_scl_oe_n,
sda_pad_i => i2c_sda_i,
sda_pad_o => sys_sda_out,
sda_padoen_o => sys_sda_oe_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
i2c_sda_oen_o <= sys_sda_oe_n;
i2c_sda_o <= sys_sda_out;
i2c_scl_oen_o <= sys_scl_oe_n;
i2c_scl_o <= sys_scl_out;
-- i2c_sda_oen_o <= '0';
-- i2c_sda_o <= '0';
-- i2c_scl_oen_o <= '0';
-- i2c_scl_o <= '0';
end rtl;
......
hdl/wr_spec_tdc/hdl/rtl/start_retrig_ctrl.vhd
View file @ 62e81cfe
......@@ -4,7 +4,6 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- start_retrig_ctrl |
......@@ -115,7 +114,6 @@
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
......@@ -145,7 +143,6 @@ entity start_retrig_ctrl is
acam_intflag_f_edge_p_i : in std_logic;
-- Signal from the one_hz_generator unit
utc_p_i : in std_logic;
-- OUTPUTS
-- Signals to the data_formatting unit
current_retrig_nb_o : out std_logic_vector(g_width-1 downto 0);
......@@ -153,13 +150,13 @@ entity start_retrig_ctrl is
clk_i_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
roll_over_nb_o : out std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
end start_retrig_ctrl;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of start_retrig_ctrl is
signal clk_i_cycles_offset : std_logic_vector(g_width-1 downto 0);
......@@ -167,7 +164,7 @@ architecture rtl of start_retrig_ctrl is
signal current_retrig_nb : std_logic_vector(g_width-1 downto 0);
signal retrig_nb_offset : std_logic_vector(g_width-1 downto 0);
signal retrig_p : std_logic;
signal roll_over_c : std_logic_vector(g_width-1 downto 0);
signal roll_over_c : unsigned(g_width-1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -180,7 +177,6 @@ begin
-- IrFlag_f_edge_p : ______________________________________|-|________________________________________|-|________
-- retrig_p : |-|__|-|__ ... __|-|__|-|__ ... __|-|__|-|__|-|__ ...__|-|__|-|__|-|___ ...__|-|__|-|__|-|___
-- current_retrig_nb: 0 1 127 128 255 0 1 127 128 129 255 0 1
-- utc_p_i : _____________________|-|_______________________________________________________________
-- roll_over_c : 0 1 2
-- retrig_nb_offset : 127
......@@ -211,7 +207,6 @@ begin
-- Finally, note that the the current_cycles counter is a decreasing counter giving the amount of
-- clk_i cycles between the resing edge of the one_hz_pulse_i and the next retrigger.
-- Note that in this project we are only interested in time differences between
-- _______________________________________ _________________________________________ ____________________
-- utc_p_i | _|-|_ || | |
-- ACAM Stop pulse | || | | _|-|_
......@@ -224,15 +219,15 @@ begin
-- |-----------------------------------------------------------|
-- (3)
-- |--------|
-- (1): ((retrig_nb_offset + 1) * retrig_period) - (clk_i_cycles_offset)
-- (2): (roll_over_c * 256 * retrig_period) - (the amount that (1) represents)
-- (3): from ACAM tstamps: (Start# * retrig_period) + (Fine time: Hit)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- These two counters keep a track of the current internal start retrigger
-- of the ACAM in parallel with the ACAM itself. Counting up to c_ACAM_RETRIG_PERIOD = 64
retrig_period_counter: free_counter -- retrigger periods
generic map
(width => g_width)
......@@ -259,20 +254,33 @@ begin
counter_o => current_retrig_nb);
-------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- This counter keeps track of the number of overflows of the ACAM counter within one second
roll_over_counter: incr_counter
generic map
(width => g_width)
port map
(clk_i => clk_i,
rst_i => utc_p_i,
counter_top_i => x"FFFFFFFF",
counter_incr_en_i => acam_intflag_f_edge_p_i,
counter_is_full_o => open,
counter_o => roll_over_c);
-- roll_over_counter: incr_counter
-- generic map
-- (width => g_width)
-- port map
-- (clk_i => clk_i,
-- rst_i => roll_over_c_rst,
-- counter_top_i => x"FFFFFFFF",
-- counter_incr_en_i => acam_intflag_f_edge_p_i,
-- counter_is_full_o => open,
-- counter_o => roll_over_c);
roll_over_counter: process (clk_i)
begin
if rising_edge (clk_i) then
if utc_p_i = '1' and acam_intflag_f_edge_p_i = '0' then
roll_over_c <= x"00000000";
elsif utc_p_i = '1' and acam_intflag_f_edge_p_i = '1' then
roll_over_c <= x"00000001";
elsif acam_intflag_f_edge_p_i = '1' then
roll_over_c <= roll_over_c + "1";
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- When a new second starts, all values are captured and stored as offsets.
-- when a timestamp arrives, these offsets will be subtracted in order
......@@ -288,22 +296,21 @@ begin
clk_i_cycles_offset <= current_cycles;
retrig_nb_offset <= current_retrig_nb;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- outputs
roll_over_incr_recent_o <= '1' when unsigned(current_retrig_nb) < 64 else '0';
clk_i_cycles_offset_o <= clk_i_cycles_offset;
retrig_nb_offset_o <= retrig_nb_offset;
roll_over_nb_o <= roll_over_c;
roll_over_nb_o <= std_logic_vector(roll_over_c);
current_retrig_nb_o <= current_retrig_nb; ----------------
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/wr_spec_tdc/hdl/top/spec/spec_top_fmc_tdc.vhd
View file @ 62e81cfe
......@@ -700,8 +700,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for Carrier EEPROM
mezz_sys_scl_b <= '0' when (wrc_scl_out = '0') else 'Z';--tdc_scl_out when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
mezz_sys_sda_b <= '0' when (wrc_sda_out = '0') else 'Z';--tdc_sda_out when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
mezz_sys_scl_b <= tdc_scl_out when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
mezz_sys_sda_b <= tdc_sda_out when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
wrc_scl_in <= mezz_sys_scl_b;
wrc_sda_in <= mezz_sys_sda_b;
tdc_scl_in <= mezz_sys_scl_b;
......
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