Skip to content

F
FMC TDC 1ns 5cha
Commit 56bf994b authored by egousiou's avatar egousiou
Browse files
Options

- removed DMA from SPEC design 

- changed SPEC synthesis to ISE (was Synplify)
- general cleanup

git-svn-id: http://svn.ohwr.org/fmc-tdc@152 85dfdc96-de2c-444c-878d-45b388be74a9
parent ccfbe404
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 3374 additions and 116033 deletions
hdl/ip_cores/gnum_core/xilinx_cores/coregen.cgp
View file @ 56bf994b
# Date: Thu Feb 3 16:41:04 2011
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: f66dfaab
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET package = fgg484
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
hdl/ip_cores/gnum_core/xilinx_cores/fifo_32x512.gise
View file @ 56bf994b
......@@ -29,6 +29,27 @@
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8777296749647723518" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2104667735123416897" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1627810207069309888" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/ip_cores/gnum_core/xilinx_cores/fifo_64x512.gise
View file @ 56bf994b
......@@ -29,6 +29,27 @@
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5972887507274424632" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6973896807994015797" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5324370023856713354" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/ip_cores/mem_core/blk_mem_circ_buff_v6_4.gise
View file @ 56bf994b
......@@ -26,6 +26,27 @@
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7640980108902946276" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4819290180276573634" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6718039799359289506" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xise
View file @ 56bf994b
......@@ -14,19 +14,7 @@
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="blk_mem_circ_buff_v6_4.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="blk_mem_circ_buff_v6_4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
</files>
<files/>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
......
hdl/ip_cores/mem_core/blk_mem_gen_v6_1.gise
View file @ 56bf994b
......@@ -22,10 +22,30 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="blk_mem_gen_v6_1.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_1.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="165936098113533828" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7071533197450788902" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="8814703242142704070" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/ip_cores/mem_core/blk_mem_gen_v6_1.xise
View file @ 56bf994b
This diff is collapsed.
hdl/ip_cores/mem_core/blk_mem_gen_v6_2.gise
View file @ 56bf994b
......@@ -22,10 +22,30 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="blk_mem_gen_v6_2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_2.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4883055629214282022" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="851143268618168456" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4914921300466099352" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/ip_cores/mem_core/blk_mem_gen_v6_2.xise
View file @ 56bf994b
This diff is collapsed.
hdl/ip_cores/mem_core/blk_mem_gen_v6_3.gise
View file @ 56bf994b
......@@ -22,10 +22,30 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="blk_mem_gen_v6_3.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_3.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8846568913394521400" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5369246660214451990" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1390819957" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-197801769365351158" xil_pn:start_ts="1390819957">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/ip_cores/mem_core/blk_mem_gen_v6_3.xise
View file @ 56bf994b
This diff is collapsed.
hdl/ip_cores/mem_core/coregen.cgp
View file @ 56bf994b
SET busformat = BusFormatParenNotRipped
SET designentry = VHDL
SET device = xc6slx150t
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Synplicity
SET package = fgg900
SET package = fgg484
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
hdl/rtl/data_formatting.vhd
View file @ 56bf994b
......@@ -114,6 +114,7 @@ entity data_formatting is
-- Signal to the irq_generator unit
tstamp_wr_p_o : out std_logic; -- pulse upon storage of a new tstamp
acam_channel_o : out std_logic_vector(2 downto 0); --
-- Signal to the reg_ctrl unit
wr_index_o : out std_logic_vector(31 downto 0)); -- index of last byte written
......@@ -457,6 +458,8 @@ begin
tstamp_wr_wb_cyc_o <= tstamp_wr_cyc;
tstamp_wr_wb_stb_o <= tstamp_wr_stb;
tstamp_wr_wb_we_o <= tstamp_wr_we;
acam_channel_o <= acam_channel;
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_core.vhd
View file @ 56bf994b
......@@ -257,8 +257,9 @@ architecture rtl of fmc_tdc_core is
signal circ_buff_class_data_wr, circ_buff_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
-- LEDs
signal fordebug : std_logic_vector(5 downto 0);
-- signal tdc_in_fpga_1, tdc_in_fpga_2, tdc_in_fpga_3 : std_logic_vector(1 downto 0);
-- signal tdc_in_fpga_4, tdc_in_fpga_5 : std_logic_vector(1 downto 0);
signal tdc_in_fpga_1, tdc_in_fpga_2, tdc_in_fpga_3 : std_logic_vector(1 downto 0);
signal tdc_in_fpga_4, tdc_in_fpga_5 : std_logic_vector(1 downto 0);
signal acam_channel : std_logic_vector(2 downto 0);
--=================================================================================================
......@@ -483,6 +484,7 @@ begin
one_hz_p_i => one_hz_p,
local_utc_i => local_utc,
tstamp_wr_p_o => tstamp_wr_p,
acam_channel_o => acam_channel,
wr_index_o => wr_index);
......@@ -544,6 +546,7 @@ begin
one_hz_p_i => one_hz_p,
acam_inputs_en_i => acam_inputs_en,
fordebug_i => fordebug,
tstamp_wr_p_i => tstamp_wr_p,
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
......@@ -570,7 +573,8 @@ begin
-- end if;
-- end process;
-- fordebug <= '0' & tdc_in_fpga_5(1) & tdc_in_fpga_4(1) & tdc_in_fpga_3(1) & tdc_in_fpga_2(1) & tdc_in_fpga_1(1);
fordebug <= "000000";
--fordebug <= "000000";
fordebug <= "000" & acam_channel;
---------------------------------------------------------------------------------------------------
-- ACAM start_dis/ stop_dis, not used --
......
hdl/rtl/leds_manager.vhd
View file @ 56bf994b
......@@ -90,6 +90,7 @@ entity leds_manager is
-- Signal for debugging
fordebug_i : in std_logic_vector(5 downto 0); -- for debugging, currently not used
tstamp_wr_p_i : in std_logic;
-- OUTPUTS
......@@ -109,10 +110,13 @@ end leds_manager;
--=================================================================================================
architecture rtl of leds_manager is
signal tdc_led_blink_done : std_logic;
signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
-- signal rst_n, blink_led1, blink_led2 : std_logic;
-- signal blink_led3, blink_led4, blink_led5 : std_logic;
signal tdc_led_blink_done : std_logic;
signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
signal rst_n, blink_led1, blink_led2 : std_logic;
signal ch1, ch2, ch3, ch4, ch5 : std_logic;
signal blink_led3, blink_led4, blink_led5 : std_logic;
signal tstamp_wr_p, blink_led : std_logic;
signal acam_channel : std_logic_vector(5 downto 0);
begin
......@@ -151,7 +155,7 @@ begin
-- TDC FRONT PANEL LEDs 2-6 --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- rst_n <= not(rst_i);
rst_n <= not(rst_i);
-- cmp_extend_ch1_pulse: gc_extend_pulse
-- generic map
......@@ -159,57 +163,160 @@ begin
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(0),
-- pulse_i => acam_channel_i(0),
-- extended_o => blink_led1);
-- -- -- -- -- --
-- -- -- --
-- cmp_extend_ch2_pulse: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(1),
-- pulse_i => acam_channel_i(1),
-- extended_o => blink_led2);
-- -- -- -- -- --
-- -- -- --
-- cmp_extend_ch3_pulse: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(2),
-- pulse_i => acam_channel_i(2),
-- extended_o => blink_led3);
-- -- -- -- -- --
-- -- -- --
-- cmp_extend_ch4_pulse: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(3),
-- pulse_i => acam_channel_i(3),
-- extended_o => blink_led4);
-- -- -- -- -- --
-- -- -- --
-- cmp_extend_ch5_pulse: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- pulse_i => fordebug_i(4),
-- pulse_i => acam_channel_i(4),
-- extended_o => blink_led5);
-- -- -- -- -- --
led_1to5_outputs: process (clk_i)
begin
if rising_edge (clk_i) then
tdc_led_trig1_o <= acam_inputs_en_i(0) and acam_inputs_en_i(7);-- and blink_led1;
tdc_led_trig2_o <= acam_inputs_en_i(1) and acam_inputs_en_i(7);-- and blink_led2;
tdc_led_trig3_o <= acam_inputs_en_i(2) and acam_inputs_en_i(7);-- and blink_led3;
tdc_led_trig4_o <= acam_inputs_en_i(3) and acam_inputs_en_i(7);-- and blink_led4;
tdc_led_trig5_o <= acam_inputs_en_i(4) and acam_inputs_en_i(7);-- and blink_led5;
tdc_led_trig1_o <= acam_inputs_en_i(0) and blink_led1;
tdc_led_trig2_o <= acam_inputs_en_i(1) and blink_led2;
tdc_led_trig3_o <= acam_inputs_en_i(2) and blink_led3;
tdc_led_trig4_o <= acam_inputs_en_i(3) and blink_led4;
tdc_led_trig5_o <= acam_inputs_en_i(4) and blink_led5;
end if;
end process;
input_pulse_synchronizer: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
acam_channel <= (others => '0');
tstamp_wr_p <= '0';
ch1 <= '0';
ch2 <= '0';
ch3 <= '0';
ch4 <= '0';
ch5 <= '0';
else
acam_channel <= fordebug_i;
tstamp_wr_p <= tstamp_wr_p_i;
if tstamp_wr_p = '1' and acam_inputs_en_i(7) = '1' then
if acam_channel(2 downto 0) = "000" then
ch1 <= '1';
ch2 <= '0';
ch3 <= '0';
ch4 <= '0';
ch5 <= '0';
elsif acam_channel(2 downto 0) = "001" then
ch1 <= '0';
ch2 <= '1';
ch3 <= '0';
ch4 <= '0';
ch5 <= '0';
elsif acam_channel(2 downto 0) = "010" then
ch1 <= '0';
ch2 <= '0';
ch3 <= '1';
ch4 <= '0';
ch5 <= '0';
elsif acam_channel(2 downto 0) = "011" then
ch1 <= '0';
ch2 <= '0';
ch3 <= '0';
ch4 <= '1';
ch5 <= '0';
else
ch1 <= '0';
ch2 <= '0';
ch3 <= '0';
ch4 <= '0';
ch5 <= '1';
end if;
else
ch1 <= '0';
ch2 <= '0';
ch3 <= '0';
ch4 <= '0';
ch5 <= '0';
end if;
end if;
end if;
end process;
cmp_extend_ch1_pulse: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_i,
rst_n_i => rst_n,
pulse_i => ch1,
extended_o => blink_led1);
cmp_extend_ch2_pulse: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_i,
rst_n_i => rst_n,
pulse_i => ch2,
extended_o => blink_led2);
cmp_extend_ch3_pulse: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_i,
rst_n_i => rst_n,
pulse_i => ch3,
extended_o => blink_led3);
cmp_extend_ch4_pulse: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_i,
rst_n_i => rst_n,
pulse_i => ch4,
extended_o => blink_led4);
cmp_extend_ch5_pulse: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_i,
rst_n_i => rst_n,
pulse_i => ch5,
extended_o => blink_led5);
end rtl;
......
hdl/syn/spec/blk_mem_circ_buff_v6_4.ngc deleted 100644 → 0
View file @ ccfbe404
This diff is collapsed.
hdl/syn/spec/fifo_32x512.ngc deleted 100644 → 0
View file @ ccfbe404
This diff is collapsed.
hdl/syn/spec/fifo_64x512.ngc deleted 100644 → 0
View file @ ccfbe404
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/spec_top_fmc_tdc.twr 0 → 100644
View file @ 56bf994b
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/spec_top_fmc_tdc.xise 0 → 100644
View file @ 56bf994b
This diff is collapsed.
hdl/syn/spec/spec_top_fmc_tdc_map.map 0 → 100644
View file @ 56bf994b
Release 13.4 Map O.87xd (nt)
Xilinx Map Application Log File for Design 'spec_top_fmc_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o spec_top_fmc_tdc_map.ncd spec_top_fmc_tdc.ngd
spec_top_fmc_tdc.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Jan 30 19:45:48 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 16 secs
Total CPU time at the beginning of Placer: 16 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:86187307) REAL time: 19 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:86187307) REAL time: 19 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:86187307) REAL time: 19 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:41b25089) REAL time: 49 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:41b25089) REAL time: 49 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:41b25089) REAL time: 49 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:41b25089) REAL time: 49 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:41b25089) REAL time: 49 secs
Phase 9.8 Global Placement
.............................
.....................................................................................................................................................................................
......................................................................................................................................................................................
........................................................
Phase 9.8 Global Placement (Checksum:f7363124) REAL time: 1 mins 23 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:f7363124) REAL time: 1 mins 23 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:deb7504) REAL time: 1 mins 46 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:deb7504) REAL time: 1 mins 46 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:364223ed) REAL time: 1 mins 47 secs
Total REAL time to Placer completion: 1 mins 54 secs
Total CPU time to Placer completion: 1 mins 53 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 3,663 out of 54,576 6%
Number used as Flip Flops: 3,640
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,904 out of 27,288 14%
Number used as logic: 3,763 out of 27,288 13%
Number using O6 output only: 2,168
Number using O5 output only: 299
Number using O5 and O6: 1,296
Number used as ROM: 0
Number used as Memory: 1 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 1
Number using O6 output only: 1
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 140
Number with same-slice register load: 101
Number with same-slice carry load: 39
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,665 out of 6,822 24%
Nummber of MUXCYs used: 1,448 out of 13,644 10%
Number of LUT Flip Flop pairs used: 4,968
Number with an unused Flip Flop: 1,681 out of 4,968 33%
Number with an unused LUT: 1,064 out of 4,968 21%
Number of fully used LUT-FF pairs: 2,223 out of 4,968 44%
Number of unique control sets: 157
Number of slice register sites lost
to control set restrictions: 511 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 132 out of 296 44%
Number of LOCed IOBs: 132 out of 132 100%
IOB Flip Flops: 57
Specific Feature Utilization:
Number of RAMB16BWERs: 11 out of 116 9%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 59 out of 376 15%
Number used as ILOGIC2s: 39
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 38 out of 376 10%
Number used as OLOGIC2s: 18
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 352 MB
Total REAL time to MAP completion: 1 mins 59 secs
Total CPU time to MAP completion: 1 mins 57 secs
Mapping completed.
See MAP report file "spec_top_fmc_tdc_map.mrp" for details.
hdl/syn/spec/syn_tdc.edf deleted 100644 → 0
View file @ ccfbe404
This diff is collapsed.
hdl/syn/spec/syn_tdc.ncf deleted 100644 → 0
View file @ ccfbe404
#
# Constraints generated by Synplify Premier maprc, Build 943R
# Product Version "F-2012.03"
#
# Location Constraints
NET "rst_n_a_i" LOC="N20" ;
NET "p2l_clk_p_i" LOC="M20" ;
NET "p2l_clk_n_i" LOC="M19" ;
NET "p2l_data_i(0)" LOC="K20" ;
NET "p2l_data_i(1)" LOC="H22" ;
NET "p2l_data_i(2)" LOC="H21" ;
NET "p2l_data_i(3)" LOC="L17" ;
NET "p2l_data_i(4)" LOC="K17" ;
NET "p2l_data_i(5)" LOC="G22" ;
NET "p2l_data_i(6)" LOC="G20" ;
NET "p2l_data_i(7)" LOC="K18" ;
NET "p2l_data_i(8)" LOC="K19" ;
NET "p2l_data_i(9)" LOC="H20" ;
NET "p2l_data_i(10)" LOC="J19" ;
NET "p2l_data_i(11)" LOC="E22" ;
NET "p2l_data_i(12)" LOC="E20" ;
NET "p2l_data_i(13)" LOC="F22" ;
NET "p2l_data_i(14)" LOC="F21" ;
NET "p2l_data_i(15)" LOC="H19" ;
NET "p2l_dframe_i" LOC="J22" ;
NET "p2l_valid_i" LOC="L19" ;
NET "p2l_rdy_o" LOC="J16" ;
NET "p_wr_req_i(0)" LOC="M22" ;
NET "p_wr_req_i(1)" LOC="M21" ;
NET "p_wr_rdy_o(0)" LOC="L15" ;
NET "p_wr_rdy_o(1)" LOC="K16" ;
NET "rx_error_o" LOC="J17" ;
NET "vc_rdy_i(0)" LOC="B21" ;
NET "vc_rdy_i(1)" LOC="B22" ;
NET "l2p_clk_p_o" LOC="K21" ;
NET "l2p_clk_n_o" LOC="K22" ;
NET "l2p_data_o(0)" LOC="P16" ;
NET "l2p_data_o(1)" LOC="P21" ;
NET "l2p_data_o(2)" LOC="P18" ;
NET "l2p_data_o(3)" LOC="T20" ;
NET "l2p_data_o(4)" LOC="V21" ;
NET "l2p_data_o(5)" LOC="V19" ;
NET "l2p_data_o(6)" LOC="W22" ;
NET "l2p_data_o(7)" LOC="Y22" ;
NET "l2p_data_o(8)" LOC="P22" ;
NET "l2p_data_o(9)" LOC="R22" ;
NET "l2p_data_o(10)" LOC="T21" ;
NET "l2p_data_o(11)" LOC="T19" ;
NET "l2p_data_o(12)" LOC="V22" ;
NET "l2p_data_o(13)" LOC="V20" ;
NET "l2p_data_o(14)" LOC="W20" ;
NET "l2p_data_o(15)" LOC="Y21" ;
NET "l2p_dframe_o" LOC="U22" ;
NET "l2p_valid_o" LOC="T18" ;
NET "l2p_edb_o" LOC="U20" ;
NET "l2p_rdy_i" LOC="U19" ;
NET "l_wr_rdy_i(0)" LOC="R20" ;
NET "l_wr_rdy_i(1)" LOC="T22" ;
NET "p_rd_d_rdy_i(0)" LOC="N16" ;
NET "p_rd_d_rdy_i(1)" LOC="P19" ;
NET "tx_error_i" LOC="M17" ;
NET "irq_p_o" LOC="U16" ;
NET "pll_sclk_o" LOC="AA16" ;
NET "pll_sdi_o" LOC="AA18" ;
NET "pll_cs_o" LOC="Y17" ;
NET "pll_dac_sync_o" LOC="AB16" ;
NET "pll_sdo_i" LOC="AB18" ;
NET "pll_status_i" LOC="Y18" ;
NET "tdc_clk_p_i" LOC="L20" ;
NET "tdc_clk_n_i" LOC="L22" ;
NET "acam_refclk_p_i" LOC="E16" ;
NET "acam_refclk_n_i" LOC="F16" ;
NET "start_from_fpga_o" LOC="W17" ;
NET "err_flag_i" LOC="V11" ;
NET "int_flag_i" LOC="W11" ;
NET "start_dis_o" LOC="T15" ;
NET "stop_dis_o" LOC="U15" ;
NET "data_bus_io(0)" LOC="W6" ;
NET "data_bus_io(1)" LOC="Y6" ;
NET "data_bus_io(2)" LOC="V7" ;
NET "data_bus_io(3)" LOC="W8" ;
NET "data_bus_io(4)" LOC="T8" ;
NET "data_bus_io(5)" LOC="AA12" ;
NET "data_bus_io(6)" LOC="U8" ;
NET "data_bus_io(7)" LOC="AB12" ;
NET "data_bus_io(8)" LOC="Y5" ;
NET "data_bus_io(9)" LOC="AB5" ;
NET "data_bus_io(10)" LOC="R9" ;
NET "data_bus_io(11)" LOC="R8" ;
NET "data_bus_io(12)" LOC="AA6" ;
NET "data_bus_io(13)" LOC="AB6" ;
NET "data_bus_io(14)" LOC="U9" ;
NET "data_bus_io(15)" LOC="V9" ;
NET "data_bus_io(16)" LOC="Y7" ;
NET "data_bus_io(17)" LOC="AB7" ;
NET "data_bus_io(18)" LOC="AA8" ;
NET "data_bus_io(19)" LOC="AB8" ;
NET "data_bus_io(20)" LOC="T10" ;
NET "data_bus_io(21)" LOC="U10" ;
NET "data_bus_io(22)" LOC="W10" ;
NET "data_bus_io(23)" LOC="Y10" ;
NET "data_bus_io(24)" LOC="Y9" ;
NET "data_bus_io(25)" LOC="AB9" ;
NET "data_bus_io(26)" LOC="AA4" ;
NET "data_bus_io(27)" LOC="AB4" ;
NET "address_o(0)" LOC="T12" ;
NET "address_o(1)" LOC="U12" ;
NET "address_o(2)" LOC="Y15" ;
NET "address_o(3)" LOC="AB15" ;
NET "cs_n_o" LOC="AB17" ;
NET "oe_n_o" LOC="V13" ;
NET "rd_n_o" LOC="AB13" ;
NET "wr_n_o" LOC="Y13" ;
NET "ef1_i" LOC="W12" ;
NET "ef2_i" LOC="Y12" ;
NET "enable_inputs_o" LOC="C19" ;
NET "term_en_1_o" LOC="Y11" ;
NET "term_en_2_o" LOC="AB11" ;
NET "term_en_3_o" LOC="R11" ;
NET "term_en_4_o" LOC="T11" ;
NET "term_en_5_o" LOC="R13" ;
NET "tdc_led_status_o" LOC="T14" ;
NET "tdc_led_trig1_o" LOC="W18" ;
NET "tdc_led_trig2_o" LOC="B20" ;
NET "tdc_led_trig3_o" LOC="A20" ;
NET "tdc_led_trig4_o" LOC="D17" ;
NET "tdc_led_trig5_o" LOC="C18" ;
NET "mezz_sys_scl_b" LOC="F7" ;
NET "mezz_sys_sda_b" LOC="F8" ;
NET "mezz_one_wire_b" LOC="A19" ;
NET "spec_clk_i" LOC="H12" ;
NET "carrier_one_wire_b" LOC="D4" ;
NET "pcb_ver_i(0)" LOC="P5" ;
NET "pcb_ver_i(1)" LOC="P4" ;
NET "pcb_ver_i(2)" LOC="AA2" ;
NET "pcb_ver_i(3)" LOC="AA1" ;
NET "prsnt_m2c_n_i" LOC="AB14" ;
NET "spec_led_green_o" LOC="E5" ;
NET "spec_led_red_o" LOC="D5" ;
NET "spec_aux0_i" LOC="C22" ;
NET "spec_aux1_i" LOC="D21" ;
NET "spec_aux2_o" LOC="G19" ;
NET "spec_aux3_o" LOC="F20" ;
NET "spec_aux4_o" LOC="F18" ;
NET "spec_aux5_o" LOC="C20" ;
# End of generated constraints
hdl/syn/spec/synplicity.ucf deleted 100644 → 0
View file @ ccfbe404
#
# Constraints generated by Synplify Premier maprc, Build 943R
# Product Version "F-2012.03"
#
# Period Constraints
#Begin clock constraints
# 1003 : define_clock {p:acam_refclk_p_i} -name {acam_refclk31_25} -freq {31.25} -clockgroup {default_clkgroup30__3}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "acam_refclk_p_i" TNM_NET = "acam_refclk_p_i";
TIMESPEC "TS_acam_refclk_p_i" = PERIOD "acam_refclk_p_i" 32.000 ns HIGH 50.00%;
# 1246 : define_clock {n:cmp_GN4124.cmp_clk_in.buf_P_clk} -name {serdes_1_to_n_clk_pll_s2_diff_work_spec_top_fmc_tdc_rtl_6layer0|buf_P_clk_inferred_clock} -ref_rise {0.000000} -ref_fall {2.500000} -uncertainty {0.000000} -period {5.000000} -clockgroup {Inferred_clkgroup_0} -rise {0.000000} -fall {2.500000}
NET "cmp_GN4124.cmp_clk_in.buf_P_clk" TNM_NET = "cmp_GN4124_cmp_clk_in_buf_P_clk";
TIMESPEC "TS_cmp_GN4124_cmp_clk_in_buf_P_clk" = PERIOD "cmp_GN4124_cmp_clk_in_buf_P_clk" 5.000 ns HIGH 50.00%;
# 1002 : define_clock {p:spec_clk_i} -name {spec_clk20} -freq {20} -clockgroup {default_clkgroup29__2}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "spec_clk_i" TNM_NET = "spec_clk_i";
TIMESPEC "TS_spec_clk_i" = PERIOD "spec_clk_i" 50.000 ns HIGH 50.00%;
# 1001 : define_clock {p:tdc_clk_p_i} -name {tdc_clk125p} -freq {125} -clockgroup {default_clkgroup28__1}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_clk_p_i" TNM_NET = "tdc_clk_p_i";
TIMESPEC "TS_tdc_clk_p_i" = PERIOD "tdc_clk_p_i" 8.000 ns HIGH 50.00%;
#End clock constraints
# 1018 : define_false_path -to {p:tdc_led_status_o}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_status_o" TNM = "to_1018_0";
TIMESPEC "TS_1018_0" = TO "to_1018_0" TIG;
# 1019 : define_false_path -to {p:tdc_led_trig1_o}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig1_o" TNM = "to_1019_0";
TIMESPEC "TS_1019_0" = TO "to_1019_0" TIG;
# 1020 : define_false_path -to {p:tdc_led_trig2_o}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig2_o" TNM = "to_1020_0";
TIMESPEC "TS_1020_0" = TO "to_1020_0" TIG;
# 1021 : define_false_path -to {p:tdc_led_trig3_o}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig3_o" TNM = "to_1021_0";
TIMESPEC "TS_1021_0" = TO "to_1021_0" TIG;
# 1022 : define_false_path -to {p:tdc_led_trig4_o}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig4_o" TNM = "to_1022_0";
TIMESPEC "TS_1022_0" = TO "to_1022_0" TIG;
# 1023 : define_false_path -to {p:tdc_led_trig5_o}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig5_o" TNM = "to_1023_0";
TIMESPEC "TS_1023_0" = TO "to_1023_0" TIG;
# 1024 : define_false_path -from {p:rst_n_a_i}
# c:\fmc-tdc-master\check\hdl\syn\spec\tdc_syn_constraints.sdc
NET "rst_n_a_i" TNM = "from_1024_0";
TIMESPEC "TS_1024_0" = FROM "from_1024_0" TIG;
# Unused constraints (intentionally commented out)
# define_multicycle_path -from { p:data_bus_io[27:0] } { 3 }
# define_multicycle_path -to { p:data_bus_io[27:0] } { 3 }
# define_multicycle_path -to { p:address_o[3:0] } { 3 }
# define_false_path -from { p:spec_aux0_i }
# define_false_path -from { p:spec_aux1_i }
# define_false_path -to { p:spec_aux2_o }
# define_false_path -to { p:spec_aux3_o }
# define_false_path -to { p:spec_aux4_o }
# define_false_path -to { p:spec_aux5_o }
# define_false_path -to { p:spec_led_green_o }
# define_false_path -to { p:spec_led_red_o }
# define_false_path -from { i:gnum_interface_block.rst_reg }
# Location Constraints
PIN "svec_clk_ibuf_cb.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "cmp_GN4124.cmp_clk_in.bufg_135.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "cmp_tdc_clks_rsts_mgment.tdc_clk125_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
# End of generated constraints
hdl/syn/spec/tdc_par_script.tcl deleted 100644 → 0
View file @ ccfbe404
ngdbuild -uc synplicity.ucf syn_tdc.edf
map -detail -w -timing -ol high syn_tdc.ngd
par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
#bitgen -w par_tdc.ncd tdc
bitgen -w -g Binary:Yes par_tdc.ncd tdc
ngdbuild -uc synplicity.ucf syn_tdc.edf;map -detail -w -timing -ol high syn_tdc.ngd;par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf;trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report;bitgen -w -g Binary:Yes par_tdc.ncd tdc
hdl/syn/spec/tdc_syn.prj deleted 100644 → 0
View file @ ccfbe404
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn.prj
#-- Written on Fri Jul 4 10:00:00 2011
#project files
#add_file -include "../../ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
#add_file -include "../../ip_cores/mem_core/blk_mem_circ_buff_v6_4.ndf"
add_file -vhdl -lib work "../../ip_cores/gnum_core/gn4124_core_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../../ip_cores/genrams/genram_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wishbone_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/common/gencores_pkg.vhd"
add_file -vhdl -lib work "../../top/spec/sdb_meta_pkg.vhd"
add_file -vhdl -lib work "../../top/spec/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/common/gc_extend_pulse.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/xilinx_cores/generic_async_fifo_wrapper.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/l2p_ser.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/p2l_des.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/pulse_sync_rtl.vhd"
add_file -vhdl -lib work "../../ip_cores/gnum_core/gn4124_core.vhd"
add_file -vhdl -lib work "../../ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_crossbar/sdb_rom.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_crossbar/xwb_crossbar.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/i2c_master_top.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/wb_i2c_master.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
add_file -verilog -lib work "../../ip_cores/wishbone/wb_onewire_master/sockit_owm.v"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_onewire_master/wb_onewire_master.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_dpssram.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_eic.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_fifo_async.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wbgen2/wbgen2_pkg.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/vic_prio_enc.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/wb_slave_vic.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/wb_vic.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/xwb_vic.vhd"
add_file -vhdl -lib work "../../rtl/carrier_info.vhd"
add_file -vhdl -lib work "../../rtl/fmc_tdc_core.vhd"
add_file -vhdl -lib work "../../rtl/tdc_eic.vhd"
add_file -vhdl -lib work "../../rtl/fmc_tdc_mezzanine.vhd"
add_file -vhdl -lib work "../../rtl/free_counter.vhd"
add_file -vhdl -lib work "../../rtl/incr_counter.vhd"
add_file -vhdl -lib work "../../rtl/decr_counter.vhd"
add_file -vhdl -lib work "../../rtl/clks_rsts_manager.vhd"
add_file -vhdl -lib work "../../rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../../rtl/start_retrig_ctrl.vhd"
add_file -vhdl -lib work "../../rtl/data_formatting.vhd"
add_file -vhdl -lib work "../../rtl/data_engine.vhd"
add_file -vhdl -lib work "../../rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../../rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../../rtl/circular_buffer.vhd"
add_file -vhdl -lib work "../../rtl/irq_generator.vhd"
add_file -vhdl -lib work "../../rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../../rtl/leds_manager.vhd"
add_file -vhdl -lib work "../../top/spec/dma_eic.vhd"
add_file -vhdl -lib work "../../top/spec/spec_top_fmc_tdc.vhd"
add_file -constraint -lib work "./tdc_syn_constraints.sdc"
#implementation attributes (Verilog)
set_option -vlog_std v2001
set_option -project_relative_includes 1
#implementation: "syn"
impl -add syn -type fpga
impl -active "syn"
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
set_option -synthesis_onoff_pragma 0
set_option -resolve_mixed_driver 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
set_option -no_sequential_opt 0
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "spec_top_fmc_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -num_critical_paths 5
# Xilinx options
set_option -run_prop_extract 1
set_option -maxfan 500
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -enable_prepacking 1
set_option -enhance_optimization 1
# NFilter (Netlist restructure)
set_option -enable_nfilter 1
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
#project -result_file "./test_tdc_pll/syn_tdc.edf"
#project -result_file "./test_tdc_acam/syn_tdc.edf"
#project -run -fg synthesis
#project -run -fg timing
\ No newline at end of file
hdl/syn/spec/tdc_syn_constraints.sdc deleted 100644 → 0
View file @ ccfbe404
This diff is collapsed.
hdl/syn/spec/timing_report.twr deleted 100644 → 0
View file @ ccfbe404
This diff is collapsed.
hdl/syn/svec/svec-tdc-fmc.gise
View file @ 56bf994b
......@@ -107,7 +107,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="top_tdc.lso"/>
......@@ -129,6 +131,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="top_tdc.bld"/>
......@@ -138,6 +141,7 @@
<transform xil_pn:end_ts="1385649562" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1385649353">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="top_tdc.pcf"/>
<outfile xil_pn:name="top_tdc_map.map"/>
......@@ -152,6 +156,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="top_tdc.ncd"/>
<outfile xil_pn:name="top_tdc.pad"/>
......@@ -166,6 +171,7 @@
<transform xil_pn:end_ts="1385649768" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1385649703">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="top_tdc.bgn"/>
<outfile xil_pn:name="top_tdc.bin"/>
......@@ -178,6 +184,7 @@
<transform xil_pn:end_ts="1385649703" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1385649681">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="top_tdc.twr"/>
<outfile xil_pn:name="top_tdc.twx"/>
......
hdl/syn/svec/top_tdc_summary.html
View file @ 56bf994b
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>top_tdc Project Status (11/28/2013 - 15:42:49)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>top_tdc Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>svec-tdc-fmc.xise</TD>
......@@ -19,13 +19,12 @@
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx150t-3fgg900</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/*.xmsgs?&DataKey=Warning'>3325 Warnings (3303 new)</A></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
......@@ -470,7 +469,7 @@ System Settings</A>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:35:36 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Warning'>3314 Warnings (3303 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/xst.xmsgs?&DataKey=Info'>131 Infos (131 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:35:53 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:35:53 2013</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:39:22 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/map.xmsgs?&DataKey=Info'>279 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\top_tdc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Nov 28 15:41:21 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Warning'>6 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/ohwr-fmc-tdc/hdl/syn/svec\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
......@@ -485,5 +484,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 11/28/2013 - 15:42:49</center>
<br><center><b>Date Generated:</b> 01/27/2014 - 11:38:41</center>
</BODY></HTML>
\ No newline at end of file
hdl/top/spec/sdb_meta_pkg.vhd
View file @ 56bf994b
......@@ -60,9 +60,9 @@ package sdb_meta_pkg is
-- git log -1 --format="%H" | cut -c1-320
syn_commit_id => x"00000000",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "SynpliDP",
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00201203",
syn_tool_version => x"00000134",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20140121",
-- Synthesised by (string, 15 char)
......
hdl/top/spec/spec_top_fmc_tdc.vhd
View file @ 56bf994b
......@@ -167,8 +167,8 @@ entity spec_top_fmc_tdc is
pll_dac_sync_o : out std_logic; -- DAC chip select
pll_sdo_i : in std_logic; -- not used for the moment
pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
tdc_clk_p_i : in std_logic; -- 125 MHz differential clock: system clock
tdc_clk_n_i : in std_logic; -- 125 MHz differential clock: system clock
tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
......@@ -224,15 +224,15 @@ entity spec_top_fmc_tdc is
carrier_one_wire_b : inout std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic; -- Mezzanine presence (active low)
spec_led_green_o : out std_logic; -- Green LED on SPEC front pannel, PLL status
spec_led_red_o : out std_logic; -- Red LED on SPEC front pannel
spec_aux0_i : in std_logic; -- Button on SPEC board
spec_aux1_i : in std_logic; -- Button on SPEC board
spec_aux2_o : out std_logic; -- Red LED on spec board
spec_aux3_o : out std_logic; -- Red LED on spec board
spec_aux4_o : out std_logic; -- Red LED on spec board
spec_aux5_o : out std_logic); -- Red LED on spec board
prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
-- spec_led_green_o : out std_logic; -- Green LED on SPEC front pannel, PLL status
-- spec_led_red_o : out std_logic; -- Red LED on SPEC front pannel
-- spec_aux0_i : in std_logic; -- Button on SPEC board
-- spec_aux1_i : in std_logic; -- Button on SPEC board
-- spec_aux2_o : out std_logic; -- Red LED on spec board
-- spec_aux3_o : out std_logic; -- Red LED on spec board
-- spec_aux4_o : out std_logic; -- Red LED on spec board
-- spec_aux5_o : out std_logic); -- Red LED on spec board
end spec_top_fmc_tdc;
......@@ -276,7 +276,7 @@ architecture rtl of spec_top_fmc_tdc is
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
(0 => x"00040000");
(0 => x"00052000");
---------------------------------------------------------------------------------------------------
......@@ -326,8 +326,8 @@ begin
(clk_20m_vcxo_i => clk_20m_vcxo_buf,
acam_refclk_p_i => acam_refclk_p_i,
acam_refclk_n_i => acam_refclk_n_i,
tdc_125m_clk_p_i => tdc_clk_p_i,
tdc_125m_clk_n_i => tdc_clk_n_i,
tdc_125m_clk_p_i => tdc_clk_125m_p_i,
tdc_125m_clk_n_i => tdc_clk_125m_n_i,
rst_n_i => rst_n_a_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
......@@ -378,7 +378,7 @@ begin
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
cmp_GN4124: gn4124_core
cmp_gn4124_core: gn4124_core
port map
(rst_n_a_i => rst_n_a_i,
status_o => gn4124_status,
......@@ -515,9 +515,6 @@ begin
-- TDC board 1-wire UniqueID&Thermometer interface
one_wire_b => mezz_one_wire_b);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert byte address into word address
tdc_core_wb_adr <= "00" & cnx_master_out(c_WB_SLAVE_TDC).adr(31 downto 2);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TDC).err <= '0';
......
hdl/top/spec/tdc_core_pkg.vhd
View file @ 56bf994b
......@@ -679,6 +679,7 @@ package tdc_core_pkg is
tstamp_wr_wb_stb_o : out std_logic;
tstamp_wr_wb_we_o : out std_logic;
tstamp_wr_p_o : out std_logic;
acam_channel_o : out std_logic_vector(2 downto 0);
wr_index_o : out std_logic_vector(31 downto 0));
----------------------------------------------------------------------
end component;
......@@ -836,6 +837,7 @@ package tdc_core_pkg is
one_hz_p_i : in std_logic;
acam_inputs_en_i : in std_logic_vector(g_width-1 downto 0);
fordebug_i : in std_logic_vector(5 downto 0);
tstamp_wr_p_i : in std_logic;
----------------------------------------------------------------------
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
......
hdl/top/spec/top_tdc.vhd deleted 100644 → 0
View file @ ccfbe404
This diff is collapsed.
hdl/top/svec/sdb_meta_pkg.vhd
View file @ 56bf994b
This diff is collapsed.
hdl/top/svec/tdc_core_pkg.vhd
View file @ 56bf994b
This diff is collapsed.
hdl/top/svec/top_tdc.vhd
View file @ 56bf994b
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment