Commit 3b3d9c9b authored by Federico Vaga's avatar Federico Vaga

remove white-spaces

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 35c65db0
......@@ -61,7 +61,7 @@ entity acam_timecontrol_interface is
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- reset
-- upc_p from the WRabbit or the local generator
-- upc_p from the WRabbit or the local generator
utc_p_i : in std_logic;
-- Signals from the data_engine unit
......@@ -80,7 +80,7 @@ entity acam_timecontrol_interface is
stop_dis_o : out std_logic);
end entity;
--=================================================================================================
architecture rtl of acam_timecontrol_interface is
......@@ -94,7 +94,7 @@ begin
---------------------------------------------------------------------------------------------------
-- IntFlag and ERRflag Input Synchronizers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
rst_n <= not(rst_i);
......
......@@ -59,11 +59,11 @@ signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
......@@ -88,46 +88,46 @@ begin
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
when "000" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.delta1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
when "001" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.delta2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
when "010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.delta3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
when "011" =>
if (slave_i.we = '1') then
ch_reg_offset1_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= ch_reg_offset1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
when "100" =>
if (slave_i.we = '1') then
ch_reg_offset2_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= ch_reg_offset2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
when "101" =>
if (slave_i.we = '1') then
ch_reg_offset3_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= ch_reg_offset3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110" =>
when "110" =>
if (slave_i.we = '1') then
ch_reg_csr_delta_read_int <= wrdata_reg(1);
ch_reg_csr_rst_seq_int <= wrdata_reg(2);
......@@ -175,8 +175,8 @@ begin
end if;
end if;
end process;
-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Delta Timestamp Word 1 (TAI cycles, signed)
......@@ -192,7 +192,7 @@ begin
-- Read Delta Timestamp
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ch_reg_csr_delta_read_dly0 <= '0';
regs_o.csr_delta_read_o <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -200,12 +200,12 @@ begin
regs_o.csr_delta_read_o <= ch_reg_csr_delta_read_int and (not ch_reg_csr_delta_read_dly0);
end if;
end process;
-- Reset Sequence Counter
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ch_reg_csr_rst_seq_dly0 <= '0';
regs_o.csr_rst_seq_o <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -213,8 +213,8 @@ begin
regs_o.csr_rst_seq_o <= ch_reg_csr_rst_seq_int and (not ch_reg_csr_rst_seq_dly0);
end if;
end process;
-- Delta Timestamp Reference Channel
regs_o.csr_delta_ref_o <= ch_reg_csr_delta_ref_int;
-- Raw readout mode
......
......@@ -20,26 +20,26 @@ use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package ch_reg_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_ch_reg_in_registers is record
delta1_i : std_logic_vector(31 downto 0);
delta2_i : std_logic_vector(31 downto 0);
delta3_i : std_logic_vector(31 downto 0);
csr_delta_ready_i : std_logic;
end record;
constant c_ch_reg_in_registers_init_value: t_ch_reg_in_registers := (
delta1_i => (others => '0'),
delta2_i => (others => '0'),
delta3_i => (others => '0'),
csr_delta_ready_i => '0'
);
-- Output registers (WB slave -> user design)
type t_ch_reg_out_registers is record
offset1_o : std_logic_vector(31 downto 0);
offset2_o : std_logic_vector(31 downto 0);
......@@ -49,7 +49,7 @@ package ch_reg_wbgen2_pkg is
csr_delta_ref_o : std_logic_vector(2 downto 0);
csr_raw_mode_o : std_logic;
end record;
constant c_ch_reg_out_registers_init_value: t_ch_reg_out_registers := (
offset1_o => (others => '0'),
offset2_o => (others => '0'),
......@@ -59,11 +59,11 @@ package ch_reg_wbgen2_pkg is
csr_delta_ref_o => (others => '0'),
csr_raw_mode_o => '0'
);
function "or" (left, right: t_ch_reg_in_registers) return t_ch_reg_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component channel_regs is
port (
rst_n_i : in std_logic;
......@@ -75,7 +75,7 @@ package ch_reg_wbgen2_pkg is
regs_o : out t_ch_reg_out_registers
);
end component;
end package;
package body ch_reg_wbgen2_pkg is
......@@ -87,7 +87,7 @@ package body ch_reg_wbgen2_pkg is
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
......@@ -96,11 +96,11 @@ package body ch_reg_wbgen2_pkg is
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_ch_reg_in_registers) return t_ch_reg_in_registers is
variable tmp: t_ch_reg_in_registers;
begin
......
This diff is collapsed.
......@@ -82,11 +82,11 @@ entity data_engine is
rst_i : in std_logic; -- global reset
-- Signals from the reg_ctrl unit: communication with GN4124/VME for registers configuration
activate_acq_p_i : in std_logic; -- activates tstamps aquisition
activate_acq_p_i : in std_logic; -- activates tstamps aquisition
deactivate_acq_p_i : in std_logic; -- for configuration readings/ writings
acam_wr_config_p_i : in std_logic; -- enables writing acam_config_i values to ACAM regs 0-7, 11, 12, 14
acam_wr_config_p_i : in std_logic; -- enables writing acam_config_i values to ACAM regs 0-7, 11, 12, 14
acam_rst_p_i : in std_logic; -- enables writing reset_word to ACAM reg 4
acam_rdbk_config_p_i : in std_logic; -- enables reading of ACAM regs 0-7, 11, 12, 14
acam_rdbk_config_p_i : in std_logic; -- enables reading of ACAM regs 0-7, 11, 12, 14
acam_rdbk_status_p_i : in std_logic; -- enables reading of ACAM reg 12
acam_rdbk_ififo1_p_i : in std_logic; -- enables reading of ACAM reg 8
acam_rdbk_ififo2_p_i : in std_logic; -- enables reading of ACAM reg 9
......@@ -105,10 +105,10 @@ entity data_engine is
-- includes ef1 & ef2 & 0 & 0 & 28 bits ACAM data_bus_io
start_from_fpga_i : in std_logic;
-- OUTPUTS
state_active_p_o : out std_logic;
-- Signals to the acam_databus_interface unit: communication with ACAM for configuration or tstamps retreival
acam_adr_o : out std_logic_vector(7 downto 0); -- address of reg/ FIFO to write/ read
acam_cyc_o : out std_logic; -- WISHBONE cycle
......@@ -182,7 +182,7 @@ begin
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process
data_engine_fsm_comb: process (engine_st, activate_acq_p_i, deactivate_acq_p_i, acam_ef1_i, acam_adr,
......@@ -197,7 +197,7 @@ begin
-- from the INACTIVE state modifications/readings of the ACAM configuration can be initiated;
-- all interactions here refer to transfers between the ACAM and locally this core.
-- All the interactions between the GN4124/VME interface and this core take place at the
-- the reg_ctrl unit.
-- the reg_ctrl unit.
when INACTIVE =>
-----------------------------------------------
acam_cyc <= '0';
......@@ -206,7 +206,7 @@ begin
time_c_en <= '0';
time_c_rst <= '1';
-----------------------------------------------
if activate_acq_p_i = '1' then -- activation of timestamps acquisition
nxt_engine_st <= WAIT_START_FROM_FPGA;
......@@ -250,7 +250,7 @@ begin
-- |_____ef____|______| |____ef_meta____| |_____ef_synched
-- ACAM | | |DFF1| |DFF2|
-- | | |\ | |\ |
-- | | |/___| |/___|
-- | | |/___| |/___|
-- _______| |___________________________________________________
--
-- In the beginning the output of the second synchronizer flip-flop (ef_synch2) is used,
......@@ -260,7 +260,7 @@ begin
-- random any more and depend on the rdn signal generated locally by the
-- acam_databus_interface unit. Following ACAM documentation (pg 7, Figure 2) 2 clk cycles
-- = 16 ns after an rdn falling edge the ef_synch1 should be stable.
--
--
-- Using the ef_synch1 signal instead of the ef_synch2 makes it possible to realise
-- timestamps' acquisitions from ACAM in just 4 clk cycles.
-- clk --|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
......@@ -270,7 +270,7 @@ begin
-- stb _______________________|-----------------------------------------------|_____
-- adr _______________________| iFIFO adr set
-- rdn -----------------------------|_________________|-----|_______________________
-- data valid ^ ^
-- data valid ^ ^
-- ack _________________________________________|-----|_________________|-----|_____
-- data retrieval ^ ^
-- ef check ^
......@@ -329,8 +329,8 @@ begin
else
nxt_engine_st <= RD_START01;
end if;
when WAIT_UTC => -- wait until the next UTC comes; now the offsets of the start_retrig_ctrl unit are defined
-- the ACAM is disabled during this period
-----------------------------------------------
......@@ -345,7 +345,7 @@ begin
nxt_engine_st <= ACTIVE;
else
nxt_engine_st <= WAIT_UTC;
end if;
end if;
when ACTIVE =>
......@@ -462,7 +462,7 @@ begin
acam_stb <= '1';
acam_we <= '0';
time_c_en <= '0';
time_c_rst <= '0';
time_c_rst <= '0';
-----------------------------------------------
if acam_ack_i ='1' then
......@@ -472,7 +472,7 @@ begin
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when RD_IFIFO1 =>
-----------------------------------------------
acam_cyc <= '1';
......@@ -600,7 +600,7 @@ begin
if rising_edge (clk_i) then
if rst_i = '1' or acam_wr_config_p_i = '1' or acam_rdbk_config_p_i = '1' then
config_adr_c <= unsigned (c_ACAM_REG0_ADR);
elsif acam_ack_i ='1' then
if config_adr_c = unsigned (c_ACAM_REG14_ADR) then
config_adr_c <= unsigned (c_ACAM_REG14_ADR);
......@@ -679,7 +679,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
acam_config_reg4 <= acam_config_i(4);
reset_word <= acam_config_reg4(31 downto 24) & "01" & acam_config_reg4(21 downto 0);
-- reg 4 bit 22: MasterReset :'1' = general reset excluding config regs
-- reg 4 bit 22: MasterReset :'1' = general reset excluding config regs
-- reg 4 bit 23: PartialReset: would initiate a general reset excluding
-- config regs&FIFOs, but this option is not used
......
This diff is collapsed.
......@@ -90,7 +90,7 @@ architecture rtl of decr_counter is
-- architecture begin
--=================================================================================================
begin
decr_counting: process (clk_i)
begin
if rising_edge (clk_i) then
......
......@@ -69,11 +69,11 @@ begin
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
......@@ -95,7 +95,7 @@ begin
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
when "00" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
......@@ -133,7 +133,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
when "01" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
......@@ -171,7 +171,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
when "10" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= eic_imr_int(1 downto 0);
......@@ -207,7 +207,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
when "11" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
......@@ -253,8 +253,8 @@ begin
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Interrupt disable register
......@@ -315,7 +315,7 @@ begin
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_dma_done_i;
irq_inputs_vector_int(1) <= irq_dma_error_i;
rwaddr_reg <= wb_adr_i;
......
......@@ -144,7 +144,7 @@ entity fmc_tdc_core is
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
clk_tdc_i : in std_logic; -- 125 MHz reference from the PLL
clk_tdc_i : in std_logic; -- 125 MHz reference from the PLL
rst_tdc_n_i : in std_logic; -- global reset, synched to clk_tdc_i
acam_refclk_r_edge_p_i : in std_logic; -- rising edge on 31.25MHz ACAM reference clock
......@@ -260,7 +260,7 @@ architecture rtl of fmc_tdc_core is
signal gen_fake_ts_channel : std_logic_vector(2 downto 0);
signal gen_fake_ts_period : std_logic_vector(27 downto 0);
signal int_flag_delay : std_logic_vector(15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -542,7 +542,7 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC LEDs --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
TDCboard_leds : entity work.leds_manager
generic map (
g_WIDTH => 32,
......@@ -558,7 +558,7 @@ begin
---------------------------------------------------------------------------------------------------
-- ACAM start_dis, not used --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
start_dis_o <= '0';
U_Sync_ChannelEnable : entity work.gc_sync_register
......
......@@ -68,11 +68,11 @@ signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
......@@ -91,7 +91,7 @@ begin
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
when "000" =>
if (wb_we_i = '1') then
dr_chan_enable_int <= wrdata_reg(4 downto 0);
end if;
......@@ -125,7 +125,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
when "001" =>
if (wb_we_i = '1') then
dr_dead_time_int <= wrdata_reg(23 downto 0);
end if;
......@@ -140,7 +140,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
when "010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.status_i;
......@@ -177,7 +177,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
when "011" =>
if (wb_we_i = '1') then
end if;
if (dr_fifo_rdreq_int_d0 = '0') then
......@@ -187,13 +187,13 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "100" =>
when "100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= dr_fifo_out_int(63 downto 32);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
when "101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(17 downto 0) <= dr_fifo_out_int(81 downto 64);
......@@ -210,7 +210,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110" =>
when "110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dr_fifo_full_int;
......@@ -249,8 +249,8 @@ begin
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Readout FIFO
......@@ -280,7 +280,7 @@ begin
wr_data_i => dr_fifo_in_int,
rd_data_o => dr_fifo_out_int
);
-- Channel enable
regs_o.chan_enable_o <= dr_chan_enable_int;
-- Dead time (8ns ticks)
......@@ -289,14 +289,14 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Readout FIFO' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
dr_fifo_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dr_fifo_rdreq_int_d0 <= dr_fifo_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Readout FIFO' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Readout FIFO' data output register 2
rwaddr_reg <= wb_adr_i;
......
......@@ -20,10 +20,10 @@ use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package dr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_dr_in_registers is record
fifo_wr_req_i : std_logic;
fifo_seconds_i : std_logic_vector(31 downto 0);
......@@ -33,7 +33,7 @@ package dr_wbgen2_pkg is
fifo_channel_i : std_logic_vector(3 downto 0);
status_i : std_logic;
end record;
constant c_dr_in_registers_init_value: t_dr_in_registers := (
fifo_wr_req_i => '0',
fifo_seconds_i => (others => '0'),
......@@ -43,9 +43,9 @@ package dr_wbgen2_pkg is
fifo_channel_i => (others => '0'),
status_i => '0'
);
-- Output registers (WB slave -> user design)
type t_dr_out_registers is record
fifo_wr_full_o : std_logic;
fifo_wr_empty_o : std_logic;
......@@ -53,7 +53,7 @@ package dr_wbgen2_pkg is
chan_enable_o : std_logic_vector(4 downto 0);
dead_time_o : std_logic_vector(23 downto 0);
end record;
constant c_dr_out_registers_init_value: t_dr_out_registers := (
fifo_wr_full_o => '0',
fifo_wr_empty_o => '0',
......@@ -83,8 +83,8 @@ if(x(i) = '1') then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_dr_in_registers) return t_dr_in_registers is
......
......@@ -141,7 +141,7 @@ entity fmc_tdc_mezzanine is
wr_n_o : out std_logic;
ef1_i : in std_logic;
ef2_i : in std_logic;
-- Channels termination
-- Channels termination
enable_inputs_o : out std_logic;
term_en_1_o : out std_logic;
term_en_2_o : out std_logic;
......@@ -163,7 +163,7 @@ entity fmc_tdc_mezzanine is
wrabbit_dac_wr_p_i : in std_logic;
-- WISHBONE interface with the GN4124/VME_core (clk_sys)
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
......
......@@ -86,7 +86,7 @@ architecture rtl of free_counter is
-- architecture begin
--=================================================================================================
begin
decr_counting: process (clk_i)
begin
if rising_edge (clk_i) then
......
......@@ -86,7 +86,7 @@ architecture rtl of incr_counter is
-- architecture begin
--=================================================================================================
begin
incr_counting: process (clk_i)
begin
if rising_edge (clk_i) then
......
This diff is collapsed.
......@@ -61,8 +61,8 @@ entity local_pps_gen is
-- INPUTS
-- Signals from the clk_rst_manager unit
(clk_i : in std_logic;
rst_i : in std_logic;
acam_refclk_r_edge_p_i : in std_logic;
rst_i : in std_logic;
acam_refclk_r_edge_p_i : in std_logic;
clk_period_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods for 1s
-- Signals from the reg_ctrl unit
......@@ -76,7 +76,7 @@ entity local_pps_gen is
local_utc_o : out std_logic_vector(g_width-1 downto 0); -- tstamp current second
-- Signal to start_retrig_ctrl unit
local_utc_p_o : out std_logic); -- pulse upon new second
local_utc_p_o : out std_logic); -- pulse upon new second
end local_pps_gen;
......@@ -120,7 +120,7 @@ begin
counter_o => open);
-------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_periods_counter_en_trigger: process (clk_i)
begin
if rising_edge (clk_i) then
......@@ -142,7 +142,7 @@ begin
-- utc_counter: generation of a 1 clk-long pulse every second
utc_counter: process (clk_i)
begin
begin
if rising_edge (clk_i) then
if rst_i ='1' then
local_utc <= (others => '0');
......@@ -164,7 +164,7 @@ begin
-- Delays --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
pulse_delayer_counter: decr_counter -- delays the one_hz_p_pre pulse for total_delay clk_i ticks
pulse_delayer_counter: decr_counter -- delays the one_hz_p_pre pulse for total_delay clk_i ticks
generic map
(width => g_width)
port map
......
......@@ -101,7 +101,7 @@ entity reg_ctrl is
core_status_i : in std_logic_vector(g_width-1 downto 0); -- TDC core status word
-- White Rabbit status
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); --
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); --
-- OUTPUTS
......@@ -111,10 +111,10 @@ entity reg_ctrl is
-- Signals to the data_engine unit: TDC core functionality
activate_acq_p_o : out std_logic; -- activates tstamps acquisition from ACAM
deactivate_acq_p_o : out std_logic; -- activates ACAM configuration readings/ writings
acam_wr_config_p_o : out std_logic; -- enables writing to ACAM regs 0-7, 11, 12, 14
acam_rdbk_config_p_o : out std_logic; -- enables reading of ACAM regs 0-7, 11, 12, 14
acam_wr_config_p_o : out std_logic; -- enables writing to ACAM regs 0-7, 11, 12, 14
acam_rdbk_config_p_o : out std_logic; -- enables reading of ACAM regs 0-7, 11, 12, 14
acam_rst_p_o : out std_logic; -- enables writing the c_RESET_WORD to ACAM reg 4
acam_rdbk_status_p_o : out std_logic; -- enables reading of ACAM reg 12
acam_rdbk_status_p_o : out std_logic; -- enables reading of ACAM reg 12
acam_rdbk_ififo1_p_o : out std_logic; -- enables reading of ACAM reg 8
acam_rdbk_ififo2_p_o : out std_logic; -- enables reading of ACAM reg 9
acam_rdbk_start01_p_o : out std_logic; -- enables reading of ACAM reg 10
......@@ -123,7 +123,7 @@ entity reg_ctrl is
gen_fake_ts_period_o : out std_logic_vector(27 downto 0);
gen_fake_ts_channel_o : out std_logic_vector(2 downto 0);
-- Signals to the clks_resets_manager unit
send_dac_word_p_o : out std_logic; -- initiates the reconfiguration of the DAC
dac_word_o : out std_logic_vector(23 downto 0);
......@@ -140,7 +140,7 @@ entity reg_ctrl is
acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0); -- enables all five input channels
-- White Rabbit control
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0); --
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0); --
int_flag_delay_o : out std_logic_vector(15 downto 0)
);
......@@ -196,7 +196,7 @@ begin
cmp_clks_crossing : xwb_clock_crossing
port map
(slave_clk_i => clk_sys_i, -- Slave control port: VME interface at 62.5 MHz
(slave_clk_i => clk_sys_i, -- Slave control port: VME interface at 62.5 MHz
slave_rst_n_i => cc_rst_n_or_sys, -- reset the slave port also when resetting the TDC
slave_i => slave_i,
slave_o => slave_o,
......@@ -309,7 +309,7 @@ begin
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
acam_config_o <= acam_config;
......@@ -339,10 +339,10 @@ begin
gen_fake_ts_enable_o <= '0';
int_flag_delay_o <= (others => '0');
elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then
if reg_adr = c_STARTING_UTC_ADR then
starting_utc <= wb_in.dat;
end if;
......@@ -372,7 +372,7 @@ begin
gen_fake_ts_channel_o <= wb_in.dat(30 downto 28);
gen_fake_ts_period_o <= wb_in.dat(27 downto 0);
end if;
if reg_adr = c_TEST1_ADR then
int_flag_delay_o <= wb_in.dat(15 downto 0);
end if;
......@@ -390,12 +390,12 @@ begin
---------------------------------------------------------------------------------------------------
-- Reception of TDC core Control Register --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TDCcore_ctrl_reg_reception: reception from the GN4124/VME interface of the control register that
-- defines the action to be taken by the TDC core.
-- Note that only one bit of the register should be written at a time. The process receives
-- the register, defines the action to be taken and after 1 clk cycle clears the register.
-- the register, defines the action to be taken and after 1 clk cycle clears the register.
TDCcore_ctrl_reg_reception : process (clk_tdc_i)
begin
......@@ -417,7 +417,7 @@ begin
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
activate_acq_p_o <= ctrl_reg(0);
deactivate_acq_p_o <= ctrl_reg(1);
acam_wr_config_p_o <= ctrl_reg(2);
......@@ -431,7 +431,7 @@ begin
send_dac_word_p <= ctrl_reg(11); -- not used
-- ctrl_reg bits 12 to 31 not used for the moment!
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
-- Pulse_stretcher: Increases the width of the send_dac_word_p pulse so that it can be sampled
-- by the 20 MHz clock of the clks_rsts_manager that is communicating with the DAC.
......@@ -445,17 +445,17 @@ begin
counter_incr_en_i => pulse_extender_en,
counter_is_full_o => open,
counter_o => pulse_extender_c);
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
pulse_extender_en <= '1' when pulse_extender_c < "111" else '0';
send_dac_word_p_o <= pulse_extender_en;
---------------------------------------------------------------------------------------------------
-- HOST Reading of ACAM and TDC core registers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- TDCcore_ctrl_reg_reception: Delivery to the GN4124/VME interface of all the readable registers,
-- including those of the ACAM and the TDC core.
-- Note: pipelining of the address for timing/slack reasons
-- Note: pipelining of the address for timing/slack reasons
WISHBONEreads : process (clk_tdc_i)
begin
......
......@@ -47,7 +47,7 @@ package reg_ctrl_pkg is
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM configuration readback registers, to be written by the ACAM
-- Addresses of ACAM configuration readback registers, to be written by the ACAM
-- corresponds to host address:
constant c_ACAM_REG0_RDBK_ADR : std_logic_vector(7 downto 0) := x"10"; -- [core base] + 0x40
constant c_ACAM_REG1_RDBK_ADR : std_logic_vector(7 downto 0) := x"11"; -- [core base] + 0x44
......
......@@ -173,7 +173,7 @@ architecture rtl of start_retrig_ctrl is
-- architecture begin
--=================================================================================================
begin
-- retrigger # : 0 1 127 128 255 256 257 383 384 385 511 512 513
-- retriggers : _|____|____...____|____|____...____|____|____|____...___|____|____|____...____|____|____|___
-- IrFlag : __________________|---------------------|____________________|---------------------|________
......@@ -183,7 +183,7 @@ begin
-- utc_p_i : _____________________|-|_______________________________________________________________
-- roll_over_c : 0 1 2
-- retrig_nb_offset : 127
-- clk_i_cycles_offs: |..| (counts clk_i cycles from the pulse to the end of this retrigger)
-- clk_i_cycles_offs: |..| (counts clk_i cycles from the pulse to the end of this retrigger)
--
-- At the moment that a new second arrives through the utc_p_i, we:
-- o keep note of the current_retrig_nb, 127 in this case (stored in retrig_nb_offset)
......@@ -208,13 +208,13 @@ begin
-- utc_p_i and the Stop pulse respectively, we would have to subtract 1, but since counting
-- starts from zero, we don't.
-- Finally, note that the the current_cycles counter is a decreasing counter giving the amount of
-- clk_i cycles between the resing edge of the one_hz_pulse_i and the next retrigger.
-- Note that in this project we are only interested in time differences between
-- clk_i cycles between the resing edge of the one_hz_pulse_i and the next retrigger.
-- Note that in this project we are only interested in time differences between
-- _______________________________________ _________________________________________ ____________________
-- utc_p_i | _|-|_ || | |
-- ACAM Stop pulse | || | | _|-|_
-- | || | ... |
-- roll_over_c | 0 ||1 | |n-1
-- | || | ... |
-- roll_over_c | 0 ||1 | |n-1
-- |_______________________________________||_________________________________________| |____________________
-- (1)
-- |----------------------------|
......@@ -288,7 +288,7 @@ begin
roll_over_c <= x"00000000";
-- the following case covers the rare possibility when utc_p_i and acam_intflag_f_edge_p_i
-- arrive on the exact same moment
-- arrive on the exact same moment
elsif utc_p_i = '1' and retrig_cnt = (c_full_retrig_period - 1) then
roll_over_c <= x"00000001";
elsif retrig_cnt = (c_full_retrig_period - 1) then
......@@ -315,7 +315,7 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- outputs
roll_over_incr_recent_o <= '1' when unsigned(current_retrig_nb) < 64 else '0';
clk_i_cycles_offset_o <= clk_i_cycles_offset;
......
......@@ -55,11 +55,11 @@ signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
......@@ -104,7 +104,7 @@ begin
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
when "000" =>
if (slave_i.we = '1') then
tdc_buf_csr_enable_int <= wrdata_reg(0);
tdc_buf_csr_irq_timeout_int <= wrdata_reg(10 downto 1);
......@@ -129,20 +129,20 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
when "001" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_cur_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_cur_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
when "010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_cur_count_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
when "011" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_cur_size_size_load_o <= '1';
regs_o.tdc_buf_cur_size_valid_load_o <= '1';
......@@ -152,14 +152,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
when "100" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_next_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_next_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
when "101" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_next_size_size_load_o <= '1';
regs_o.tdc_buf_next_size_valid_load_o <= '1';
......@@ -191,7 +191,7 @@ regs_o.tdc_buf_csr_burst_size_o <= tdc_buf_csr_burst_size_int;
-- Switch buffers
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
tdc_buf_csr_switch_buffers_dly0 <= '0';
regs_o.tdc_buf_csr_switch_buffers_o <= '0';
elsif rising_edge(clk_sys_i) then
......
......@@ -20,10 +20,10 @@ use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package TDC_BUF_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_TDC_BUF_in_registers is record
tdc_buf_csr_done_i : std_logic;
tdc_buf_csr_overflow_i : std_logic;
......@@ -35,7 +35,7 @@ package TDC_BUF_wbgen2_pkg is
tdc_buf_next_size_size_i : std_logic_vector(29 downto 0);
tdc_buf_next_size_valid_i : std_logic;
end record;
constant c_TDC_BUF_in_registers_init_value: t_TDC_BUF_in_registers := (
tdc_buf_csr_done_i => '0',
tdc_buf_csr_overflow_i => '0',
......@@ -47,9 +47,9 @@ package TDC_BUF_wbgen2_pkg is
tdc_buf_next_size_size_i => (others => '0'),
tdc_buf_next_size_valid_i => '0'
);
-- Output registers (WB slave -> user design)
type t_TDC_BUF_out_registers is record
tdc_buf_csr_enable_o : std_logic;
tdc_buf_csr_irq_timeout_o : std_logic_vector(9 downto 0);
......@@ -72,7 +72,7 @@ package TDC_BUF_wbgen2_pkg is
tdc_buf_next_size_valid_o : std_logic;
tdc_buf_next_size_valid_load_o : std_logic;
end record;
constant c_TDC_BUF_out_registers_init_value: t_TDC_BUF_out_registers := (
tdc_buf_csr_enable_o => '0',
tdc_buf_csr_irq_timeout_o => (others => '0'),
......@@ -132,8 +132,8 @@ begin
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
end if;
end loop;
return tmp;
end function;
......
This diff is collapsed.
......@@ -55,11 +55,11 @@ signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
......@@ -104,7 +104,7 @@ begin
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
when "000" =>
if (slave_i.we = '1') then
tdma_csr_enable_int <= wrdata_reg(0);
tdma_csr_irq_timeout_int <= wrdata_reg(10 downto 1);
......@@ -129,20 +129,20 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
when "001" =>
if (slave_i.we = '1') then
regs_o.tdma_cur_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_cur_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
when "010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_cur_count_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
when "011" =>
if (slave_i.we = '1') then
regs_o.tdma_cur_size_size_load_o <= '1';
regs_o.tdma_cur_size_valid_load_o <= '1';
......@@ -152,14 +152,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
when "100" =>
if (slave_i.we = '1') then
regs_o.tdma_next_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_next_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
when "101" =>
if (slave_i.we = '1') then
regs_o.tdma_next_size_size_load_o <= '1';
regs_o.tdma_next_size_valid_load_o <= '1';
......@@ -191,7 +191,7 @@ regs_o.tdma_csr_burst_size_o <= tdma_csr_burst_size_int;
-- Switch buffers
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
tdma_csr_switch_buffers_dly0 <= '0';
regs_o.tdma_csr_switch_buffers_o <= '0';
elsif rising_edge(clk_sys_i) then
......
......@@ -20,10 +20,10 @@ use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package TDMA_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_TDMA_in_registers is record
tdma_csr_done_i : std_logic;
tdma_csr_overflow_i : std_logic;
......@@ -35,7 +35,7 @@ package TDMA_wbgen2_pkg is
tdma_next_size_size_i : std_logic_vector(29 downto 0);
tdma_next_size_valid_i : std_logic;
end record;
constant c_TDMA_in_registers_init_value: t_TDMA_in_registers := (
tdma_csr_done_i => '0',
tdma_csr_overflow_i => '0',
......@@ -47,9 +47,9 @@ package TDMA_wbgen2_pkg is
tdma_next_size_size_i => (others => '0'),
tdma_next_size_valid_i => '0'
);
-- Output registers (WB slave -> user design)
type t_TDMA_out_registers is record
tdma_csr_enable_o : std_logic;
tdma_csr_irq_timeout_o : std_logic_vector(9 downto 0);
......@@ -72,7 +72,7 @@ package TDMA_wbgen2_pkg is
tdma_next_size_valid_o : std_logic;
tdma_next_size_valid_load_o : std_logic;
end record;
constant c_TDMA_out_registers_init_value: t_TDMA_out_registers := (
tdma_csr_enable_o => '0',
tdma_csr_irq_timeout_o => (others => '0'),
......@@ -132,8 +132,8 @@ begin
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
end if;
end loop;
return tmp;
end function;
......
......@@ -23,7 +23,7 @@ entity tdc_dma_engine is
enable_i : in std_logic_vector(4 downto 0);
raw_mode_i : in std_logic_vector(4 downto 0);
ts_i : in t_tdc_timestamp_array(4 downto 0);
ts_valid_i : in std_logic_vector(4 downto 0);
ts_ready_o : out std_logic_vector(4 downto 0);
......@@ -70,8 +70,8 @@ architecture rtl of tdc_dma_engine is
return g_CLOCK_FREQ * c_TIMER_PERIOD_MS / 1000 - 1;
end if;
end f_pick_timer_divider;
constant c_TIMER_DIVIDER_VALUE : integer := f_pick_timer_divider;
signal irq_tick_div : unsigned(15 downto 0);
......
......@@ -74,11 +74,11 @@ signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
......@@ -100,7 +100,7 @@ begin
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
when "0000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
......@@ -138,7 +138,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
when "0001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
......@@ -176,7 +176,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
when "0010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(9 downto 0) <= eic_imr_int(9 downto 0);
......@@ -204,7 +204,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
when "0011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
......@@ -242,8 +242,8 @@ begin
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Interrupt disable register
......@@ -304,7 +304,7 @@ begin
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_tdc_fifo1_i;
irq_inputs_vector_int(1) <= irq_tdc_fifo2_i;
irq_inputs_vector_int(2) <= irq_tdc_fifo3_i;
......
......@@ -50,11 +50,11 @@ signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
......@@ -73,7 +73,7 @@ begin
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
when "00" =>
if (slave_i.we = '1') then
regs_o.tdc_ow_csr_valid_load_o <= '1';
end if;
......@@ -111,7 +111,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
when "01" =>
if (slave_i.we = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.tdc_ow_temp_i;
......@@ -133,13 +133,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
when "10" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_ow_id_h_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
when "11" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_ow_id_l_i;
......
......@@ -20,31 +20,31 @@ use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package TDC_OW_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_TDC_OW_in_registers is record
tdc_ow_csr_valid_i : std_logic;
tdc_ow_temp_i : std_logic_vector(15 downto 0);
tdc_ow_id_h_i : std_logic_vector(31 downto 0);
tdc_ow_id_l_i : std_logic_vector(31 downto 0);
end record;
constant c_TDC_OW_in_registers_init_value: t_TDC_OW_in_registers := (
tdc_ow_csr_valid_i => '0',
tdc_ow_temp_i => (others => '0'),
tdc_ow_id_h_i => (others => '0'),
tdc_ow_id_l_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_TDC_OW_out_registers is record
tdc_ow_csr_valid_o : std_logic;
tdc_ow_csr_valid_load_o : std_logic;
end record;
constant c_TDC_OW_out_registers_init_value: t_TDC_OW_out_registers := (
tdc_ow_csr_valid_o => '0',
tdc_ow_csr_valid_load_o => '0'
......@@ -86,8 +86,8 @@ begin
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
end if;
end loop;
return tmp;
end function;
......
......@@ -26,20 +26,20 @@
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
......
......@@ -24,20 +24,20 @@
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
......@@ -60,7 +60,7 @@ entity tdc_ts_sub is
a_i : in t_tdc_timestamp;
b_i : in t_tdc_timestamp;
valid_o : out std_logic;
q_o : out t_tdc_timestamp
);
......@@ -86,7 +86,7 @@ architecture rtl of tdc_ts_sub is
signal ovf_frac : std_logic;
signal ovf_coarse : std_logic;
signal unf_coarse : std_logic_vector(1 downto 0);
begin -- rtl
-- Pipeline stage 0: just subtract the two timestamps field by field
......@@ -115,7 +115,7 @@ begin -- rtl
p_stage1 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pipe(1) <= '0';
else
......
......@@ -336,7 +336,7 @@ begin
end if;
end if;
end process;
ts_valid_p_o <= ts_valid_postseq;
end generate gen_channels;
......
......@@ -69,11 +69,11 @@ signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
......@@ -101,46 +101,46 @@ begin
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
when "0000" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.delta1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
when "0001" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.delta2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
when "0010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.delta3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
when "0011" =>
if (slave_i.we = '1') then
tsf_offset1_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= tsf_offset1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
when "0100" =>
if (slave_i.we = '1') then
tsf_offset2_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= tsf_offset2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
when "0101" =>
if (slave_i.we = '1') then
tsf_offset3_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= tsf_offset3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
when "0110" =>
if (slave_i.we = '1') then
tsf_csr_delta_read_int <= wrdata_reg(1);
tsf_csr_rst_seq_int <= wrdata_reg(2);
......@@ -179,7 +179,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0111" =>
when "0111" =>
if (slave_i.we = '1') then
end if;
if (tsf_fifo_rdreq_int_d0 = '0') then
......@@ -189,25 +189,25 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "1000" =>
when "1000" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(63 downto 32);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
when "1001" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(95 downto 64);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
when "1010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(127 downto 96);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
when "1011" =>
if (slave_i.we = '1') then
if (wrdata_reg(18) = '1') then
tsf_fifo_clear_bus_int <= '1';
......@@ -295,7 +295,7 @@ regs_o.offset3_o <= tsf_offset3_int;
-- Read Delta Timestamp
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
tsf_csr_delta_read_dly0 <= '0';
regs_o.csr_delta_read_o <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -308,7 +308,7 @@ end process;
-- Reset Sequence Counter
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
tsf_csr_rst_seq_dly0 <= '0';
regs_o.csr_rst_seq_o <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -325,7 +325,7 @@ regs_o.csr_raw_mode_o <= tsf_csr_raw_mode_int;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
if (rst_n_i = '0') then
tsf_fifo_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
tsf_fifo_rdreq_int_d0 <= tsf_fifo_rdreq_int;
......
......@@ -21,10 +21,10 @@ use work.wbgen2_pkg.all;
use work.wishbone_pkg.all;
package tsf_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_tsf_in_registers is record
fifo_wr_req_i : std_logic;
fifo_ts0_i : std_logic_vector(31 downto 0);
......@@ -36,7 +36,7 @@ package tsf_wbgen2_pkg is
delta3_i : std_logic_vector(31 downto 0);
csr_delta_ready_i : std_logic;
end record;
constant c_tsf_in_registers_init_value: t_tsf_in_registers := (
fifo_wr_req_i => '0',
fifo_ts0_i => (others => '0'),
......@@ -48,9 +48,9 @@ package tsf_wbgen2_pkg is
delta3_i => (others => '0'),
csr_delta_ready_i => '0'
);
-- Output registers (WB slave -> user design)
type t_tsf_out_registers is record
fifo_wr_full_o : std_logic;
fifo_wr_empty_o : std_logic;
......@@ -63,7 +63,7 @@ package tsf_wbgen2_pkg is
csr_delta_ref_o : std_logic_vector(2 downto 0);
csr_raw_mode_o : std_logic;
end record;
constant c_tsf_out_registers_init_value: t_tsf_out_registers := (
fifo_wr_full_o => '0',
fifo_wr_empty_o => '0',
......@@ -113,8 +113,8 @@ begin
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
end if;
end loop;
return tmp;
end function;
......
......@@ -10,7 +10,7 @@ use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity wbgen2_eic_nomask is
generic (
g_num_interrupts : natural := 1;
......@@ -52,11 +52,11 @@ entity wbgen2_eic_nomask is
clk_i : in std_logic;
-- raw interrupt inputs
irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);
-- interrupt acknowledge signal, used for level-active interrupts to
-- indicate that the interrupt has been handled
irq_ack_o: out std_logic_vector(g_num_interrupts-1 downto 0);
irq_ack_o: out std_logic_vector(g_num_interrupts-1 downto 0);
-- interrupt mask regsiter (slv/bus read-only)
reg_imr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
......@@ -99,7 +99,7 @@ architecture syn of wbgen2_eic_nomask is
signal irq_i_d0 : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_i_d1 : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_i_d2 : std_logic_vector(g_num_interrupts-1 downto 0);
begin -- syn
irq_mode(0) <= g_irq00_mode;
......@@ -144,11 +144,11 @@ begin -- syn
irq_i_d1 <= (others => '0');
irq_pending <= (others => '0');
irq_mask <= (others => '0');
elsif rising_edge(clk_i) then
for i in 0 to g_num_interrupts-1 loop
irq_i_d0(i) <= irq_i(i);
irq_i_d1(i) <= irq_i_d0(i);
irq_i_d2(i) <= irq_i_d1(i);
......@@ -159,9 +159,9 @@ begin -- syn
irq_i_d0(i) <= '0';
irq_i_d1(i) <= '0';
irq_i_d2(i) <= '0';
else
case irq_mode(i) is
when c_IRQ_MODE_LEVEL_0 => irq_pending(i) <= not irq_i_d2(i);
when c_IRQ_MODE_LEVEL_1 => irq_pending(i) <= irq_i_d2(i);
......@@ -202,7 +202,7 @@ begin -- syn
else
wb_irq_o <= '1';
end if;
end if;
end process;
......
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