integration of svec and spec design with and without White Rabbit in the folders structure

git-svn-id: http://svn.ohwr.org/fmc-tdc@172 85dfdc96-de2c-444c-878d-45b388be74a9

integration of svec and spec design with and without White Rabbit in the folders structure
git-svn-id: http://svn.ohwr.org/fmc-tdc@172 85dfdc96-de2c-444c-878d-45b388be74a9
17f2c6e2 · egousiou · 10b74dcd · 17f2c6e2 · 17f2c6e2 · 17f2c6e2
Commit 17f2c6e2 authored Jun 17, 2014 by egousiou
61 changed files
--- a/hdl/rtl/acam_timecontrol_interface.vhd
+++ b/hdl/rtl/acam_timecontrol_interface.vhd
--- a/hdl/rtl/circular_buffer.vhd
+++ b/hdl/rtl/circular_buffer.vhd
@@ -129,7 +129,7 @@ entity circular_buffer is
     tstamp_wr_dat_o   : out std_logic_vector(127 downto 0);   -- not used

     -- Signals to the GN4124/VME core unit (WISHBONE pipelined): timestamps reading
-     tdc_mem_wb_ack_o     : out std_logic;                     -- timestamp reading WISHBONE pepelined acknowledge
+     tdc_mem_wb_ack_o     : out std_logic;                     -- timestamp reading WISHBONE pipelined acknowledge
     tdc_mem_wb_dat_o     : out std_logic_vector(31 downto 0); -- 32 bit words
     tdc_mem_wb_stall_o   : out std_logic);                    -- timestamp reading WISHBONE pipelined stall


--- a/hdl/rtl/clks_rsts_manager.vhd
+++ b/hdl/rtl/clks_rsts_manager.vhd
--- a/hdl/rtl/data_engine.vhd
+++ b/hdl/rtl/data_engine.vhd
--- a/hdl/rtl/data_formatting.vhd
+++ b/hdl/rtl/data_formatting.vhd
--- a/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/rtl/fmc_tdc_core.vhd
--- a/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/rtl/fmc_tdc_mezzanine.vhd
--- a/hdl/rtl/irq_generator.vhd
+++ b/hdl/rtl/irq_generator.vhd
@@ -12,16 +12,16 @@
 ---------------------------------------------------------------------------------------------------
 -- File         irq_generator.vhd                                                                 |
 --                                                                                                |
-- Description  Interrupts generator: the unit generates three interrups:                         |
+-- Description  Interrupts generator: the unit generates three interrupts:                        |
 --                                                                                                |
 --                o irq_tstamp_p_o is a 1-clk_i-long pulse generated when the amount of           |
 --                  timestamps written in the circular_buffer, since the last interrupt or since  |
--                  the startup of the aquisition, exceeds the GN4124/VME settable threshold      |
+--                  the startup of the acquisition, exceeds the GN4124/VME settable threshold     |
 --                  irq_tstamp_threshold.                                                         |
 --                                                                                                |
 --                o irq_time_p_o is a 1-clk_i-long pulse generated when some timestamps have been |
 --                  written in the circular_buffer (>=1 timestamp) and the amount of time passed  |
--                  since the last interrupt or since the aquisition startup, exceeds the         |
+--                  since the last interrupt or since the acquisition startup, exceeds the        |
 --                  GN4124/VME settable threshold irq_time_threshold. The threshold is in ms.     |
 --                                                                                                |
 --                o irq_acam_err_p_o is a 1-clk_i-long pulse generated when the ACAM Hit FIFOS are|
@@ -91,8 +91,8 @@ entity irq_generator is
                                                                        -- the ERRflag is configured to follow the full flags of the
                                                                        -- Hit FIFOs; this would translate to data loss
     -- Signal from the reg_ctrl unit 
-     activate_acq_p_i        : in std_logic;                            -- activates tstamps aquisition from ACAM
-     deactivate_acq_p_i      : in std_logic;                            -- deactivates tstamps aquisition
+     activate_acq_p_i        : in std_logic;                            -- activates tstamps acquisition from ACAM
+     deactivate_acq_p_i      : in std_logic;                            -- deactivates tstamps acquisition

     -- Signals from the data_formatting unit
     tstamp_wr_p_i           : in std_logic;                            -- pulse upon storage of a new timestamp
@@ -241,7 +241,7 @@ begin
 -- last reset. The counter counts up to 255.
  tstamps_counter: incr_counter
    generic map
-      (width             => 9)--(c_CIRCULAR_BUFF_SIZE'length)) -- 9 digits, counting up to 255
+      (width             => 9) -- 9 digits, counting up to 255
    port map
      (clk_i             => clk_i,
       rst_i             => tstamps_c_rst,  

--- a/hdl/rtl/leds_manager.vhd
+++ b/hdl/rtl/leds_manager.vhd
@@ -66,7 +66,6 @@ use work.tdc_core_pkg.all;   -- definitions of types, constants, entities
 use work.gencores_pkg.all;


-
 --=================================================================================================
 --                            Entity declaration for leds_manager
 --=================================================================================================
@@ -82,14 +81,14 @@ entity leds_manager is
     rst_i             : in std_logic;                            -- core internal reset, synched with 125 MHz clk

     -- Signal from the one_hz_generator unit
-     one_hz_p_i        : in std_logic;
+     utc_p_i           : in std_logic;

     -- Signal from the reg_ctrl unit
     acam_inputs_en_i  : in std_logic_vector(g_width-1 downto 0); -- enable for the ACAM channels;
                                                                  -- activation comes through dedicated reg c_ACAM_INPUTS_EN_ADR

     -- Signal for debugging
-     fordebug_i        : in std_logic_vector(5 downto 0);         -- for debugging, currently not used
+     acam_channel_i        : in std_logic_vector(5 downto 0);         -- for debugging, currently not used
     tstamp_wr_p_i     : in std_logic;


@@ -129,7 +128,7 @@ begin
  port map
    (clk_i             => clk_i,
     rst_i             => rst_i,
-     counter_load_i    => one_hz_p_i,
+     counter_load_i    => utc_p_i,
     counter_top_i     => visible_blink_length,
     counter_is_zero_o => tdc_led_blink_done,
     counter_o         => open);
@@ -140,7 +139,7 @@ begin
    if rising_edge (clk_i) then
      if rst_i ='1' then
        tdc_led_status_o <= '0';
-      elsif one_hz_p_i ='1' then
+      elsif utc_p_i ='1' then
        tdc_led_status_o <= '1';
      elsif tdc_led_blink_done = '1' then
        tdc_led_status_o <= '0';
@@ -157,65 +156,19 @@ begin
 ---------------------------------------------------------------------------------------------------
  rst_n <= not(rst_i);

-  -- cmp_extend_ch1_pulse: gc_extend_pulse
-  -- generic map
-    -- (g_width    => 5000000)
-  -- port map
-    -- (clk_i      => clk_i,
-     -- rst_n_i    => rst_n,
-     -- pulse_i    => acam_channel_i(0),
-     -- extended_o => blink_led1);
-     --  --  --  -- 
-  -- cmp_extend_ch2_pulse: gc_extend_pulse
-  -- generic map
-    -- (g_width    => 5000000)
-  -- port map
-    -- (clk_i      => clk_i,
-     -- rst_n_i    => rst_n,
-     -- pulse_i    => acam_channel_i(1),
-     -- extended_o => blink_led2);
-     --  --  --  -- 
-  -- cmp_extend_ch3_pulse: gc_extend_pulse
-  -- generic map
-    -- (g_width    => 5000000)
-  -- port map
-    -- (clk_i      => clk_i,
-     -- rst_n_i    => rst_n,
-     -- pulse_i    => acam_channel_i(2),
-     -- extended_o => blink_led3);
-     --  --  --  -- 
-  -- cmp_extend_ch4_pulse: gc_extend_pulse
-  -- generic map
-    -- (g_width    => 5000000)
-  -- port map
-    -- (clk_i      => clk_i,
-     -- rst_n_i    => rst_n,
-     -- pulse_i    => acam_channel_i(3),
-     -- extended_o => blink_led4);
-     --  --  --  -- 
-  -- cmp_extend_ch5_pulse: gc_extend_pulse
-  -- generic map
-    -- (g_width    => 5000000)
-  -- port map
-    -- (clk_i      => clk_i,
-     -- rst_n_i    => rst_n,
-     -- pulse_i    => acam_channel_i(4),
-     -- extended_o => blink_led5);
-   --  --  --  --  --  -- 
-
  led_1to5_outputs: process (clk_i)
  begin
    if rising_edge (clk_i) then
-      tdc_led_trig1_o  <= acam_inputs_en_i(0) and blink_led1;
-      tdc_led_trig2_o  <= acam_inputs_en_i(1) and blink_led2;
-      tdc_led_trig3_o  <= acam_inputs_en_i(2) and blink_led3;
-      tdc_led_trig4_o  <= acam_inputs_en_i(3) and blink_led4;
-      tdc_led_trig5_o  <= acam_inputs_en_i(4) and blink_led5;
+      tdc_led_trig1_o  <= blink_led1; --acam_inputs_en_i(0) and blink_led1;
+      tdc_led_trig2_o  <= blink_led2; --acam_inputs_en_i(1) and blink_led2;
+      tdc_led_trig3_o  <= blink_led3; --acam_inputs_en_i(2) and blink_led3;
+      tdc_led_trig4_o  <= blink_led4; --acam_inputs_en_i(3) and blink_led4;
+      tdc_led_trig5_o  <= blink_led5; --acam_inputs_en_i(4) and blink_led5;
    end if;
  end process;


-  input_pulse_synchronizer: process (clk_i)
+  pulse_generator: process (clk_i)
  begin
    if rising_edge (clk_i) then
      if rst_i = '1' then
@@ -227,7 +180,7 @@ begin
        ch4          <= '0';
        ch5          <= '0';
      else
-        acam_channel <= fordebug_i;
+        acam_channel <= acam_channel_i;
        tstamp_wr_p  <= tstamp_wr_p_i;
        if tstamp_wr_p = '1' and acam_inputs_en_i(7) = '1' then
          if acam_channel(2 downto 0)    = "000" then

--- a/hdl/rtl/one_hz_gen.vhd
+++ b/hdl/rtl/one_hz_gen.vhd
@@ -7,14 +7,16 @@

 ---------------------------------------------------------------------------------------------------
 --                                                                                                |
--                                          one_hz_gen                                            |
+--                                        local_pps_gen                                           |
 --                                                                                                |
 ---------------------------------------------------------------------------------------------------
-- File         one_hz_gen.vhd                                                                    |
+-- File         local_pps_gen.vhd                                                                 |
 --                                                                                                |
 -- Description  Generates one pulse every second synchronously with the ACAM reference clock.     |
 --              The phase with the reference clock can be adjusted (eva: think that is not needed)|
 --              It also keeps track of the UTC time based on the local clock.                     |
+--              If there is no White Rabbit synchronization, this unit is the source of UTC timing|
+--              in the design.
 --                                                                                                |
 --                                                                                                |
 -- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
@@ -58,10 +60,10 @@ use work.tdc_core_pkg.all;   -- definitions of types, constants, entities


 --=================================================================================================
--                            Entity declaration for one_hz_gen
+--                            Entity declaration for local_pps_gen
 --=================================================================================================

-entity one_hz_gen is
+entity local_pps_gen is
  generic
    (g_width                : integer := 32);
  port
@@ -83,14 +85,14 @@ entity one_hz_gen is
     local_utc_o            : out std_logic_vector(g_width-1 downto 0); -- tstamp current second

     -- Signal to start_retrig_ctrl unit
-     one_hz_p_o             : out std_logic);                           -- pulse upon new second 
+     local_utc_p_o          : out std_logic);                           -- pulse upon new second 

-end one_hz_gen;
+end local_pps_gen;

 --=================================================================================================
 --                                    architecture declaration
 --=================================================================================================
-architecture rtl of one_hz_gen is
+architecture rtl of local_pps_gen is

  constant constant_delay         : unsigned(g_width-1 downto 0) := x"00000004";
  signal local_utc                : unsigned(g_width-1 downto 0);
@@ -186,7 +188,7 @@ begin

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  total_delay       <= std_logic_vector(unsigned(pulse_delay_i)+constant_delay);
-  one_hz_p_o        <= one_hz_p_post;
+  local_utc_p_o     <= one_hz_p_post;


 end architecture rtl;

--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
--- a/hdl/rtl/start_retrig_ctrl.vhd
+++ b/hdl/rtl/start_retrig_ctrl.vhd
--- a/hdl/rtl/wrabbit_sync.vhd
+++ b/hdl/rtl/wrabbit_sync.vhd
--- a/hdl/syn/spec/no_wrabbit/spec_tdc.par
+++ b/hdl/syn/spec/no_wrabbit/spec_tdc.par
--- a/hdl/syn/spec/spec_top_fmc_tdc.twr
+++ b/hdl/syn/spec/spec_top_fmc_tdc.twr
--- a/hdl/syn/spec/spec_top_fmc_tdc.xise
+++ b/hdl/syn/spec/spec_top_fmc_tdc.xise
--- a/hdl/syn/spec/spec_top_fmc_tdc_map.map
+++ b/hdl/syn/spec/spec_top_fmc_tdc_map.map
--- a/hdl/syn/spec/no_wrabbit/wrc.ram
+++ b/hdl/syn/spec/no_wrabbit/wrc.ram
--- a/hdl/syn/spec/with_wrabbit/wr_spec_tdc.par
+++ b/hdl/syn/spec/with_wrabbit/wr_spec_tdc.par
--- a/hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr
+++ b/hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr
--- a/hdl/syn/spec/with_wrabbit/wr_spec_tdc.xise
+++ b/hdl/syn/spec/with_wrabbit/wr_spec_tdc.xise
--- a/hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map
+++ b/hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map
--- a/hdl/syn/spec/with_wrabbit/wrc.ram
+++ b/hdl/syn/spec/with_wrabbit/wrc.ram
--- a/hdl/syn/svec/no_wrabbit/svec_tdc.par
+++ b/hdl/syn/svec/no_wrabbit/svec_tdc.par
--- a/hdl/syn/svec/no_wrabbit/svec_tdc.twr
+++ b/hdl/syn/svec/no_wrabbit/svec_tdc.twr
--- a/hdl/syn/svec/svec_top_fmc_tdc.xise
+++ b/hdl/syn/svec/svec_top_fmc_tdc.xise
--- a/hdl/syn/svec/no_wrabbit/svec_tdc_map.map
+++ b/hdl/syn/svec/no_wrabbit/svec_tdc_map.map
--- a/hdl/syn/svec/no_wrabbit/svec_tdc_map.mrp
+++ b/hdl/syn/svec/no_wrabbit/svec_tdc_map.mrp
--- a/hdl/syn/svec/no_wrabbit/wrc.ram
+++ b/hdl/syn/svec/no_wrabbit/wrc.ram
--- a/hdl/syn/svec/svec_top_fmc_tdc.twr
+++ b/hdl/syn/svec/svec_top_fmc_tdc.twr
--- a/hdl/syn/svec/svec_top_fmc_tdc_map.mrp
+++ b/hdl/syn/svec/svec_top_fmc_tdc_map.mrp
--- a/hdl/syn/svec/with_wrabbit/wr_svec_tdc.par
+++ b/hdl/syn/svec/with_wrabbit/wr_svec_tdc.par
--- a/hdl/syn/svec/with_wrabbit/wr_svec_tdc.twr
+++ b/hdl/syn/svec/with_wrabbit/wr_svec_tdc.twr
--- a/hdl/syn/svec/with_wrabbit/wr_svec_tdc.xise
+++ b/hdl/syn/svec/with_wrabbit/wr_svec_tdc.xise
--- a/hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.map
+++ b/hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.map
--- a/hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.mrp
+++ b/hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.mrp
--- a/hdl/syn/svec/with_wrabbit/wrc.ram
+++ b/hdl/syn/svec/with_wrabbit/wrc.ram
--- a/hdl/top/spec/no_wrabbit/spec_reset_gen.vhd
+++ b/hdl/top/spec/no_wrabbit/spec_reset_gen.vhd
--- a/hdl/syn/spec/spec_top_fmc_tdc.ucf
+++ b/hdl/syn/spec/spec_top_fmc_tdc.ucf
--- a/hdl/top/spec/spec_top_fmc_tdc.vhd
+++ b/hdl/top/spec/spec_top_fmc_tdc.vhd
--- a/hdl/top/spec/no_wrabbit/synthesis_descriptor.vhd
+++ b/hdl/top/spec/no_wrabbit/synthesis_descriptor.vhd
--- a/hdl/top/spec/tdc_core_pkg.vhd
+++ b/hdl/top/spec/tdc_core_pkg.vhd
--- a/hdl/top/spec/sdb_meta_pkg.vhd
+++ b/hdl/top/spec/sdb_meta_pkg.vhd
--- a/hdl/top/spec/with_wrabbit/spec_reset_gen.vhd
+++ b/hdl/top/spec/with_wrabbit/spec_reset_gen.vhd
--- a/hdl/top/spec/with_wrabbit/synthesis_descriptor.vhd
+++ b/hdl/top/spec/with_wrabbit/synthesis_descriptor.vhd
--- a/hdl/top/spec/with_wrabbit/tdc_core_pkg.vhd
+++ b/hdl/top/spec/with_wrabbit/tdc_core_pkg.vhd
--- a/hdl/top/spec/with_wrabbit/wr_spec_tdc.ucf
+++ b/hdl/top/spec/with_wrabbit/wr_spec_tdc.ucf
--- a/hdl/top/spec/with_wrabbit/wr_spec_tdc.vhd
+++ b/hdl/top/spec/with_wrabbit/wr_spec_tdc.vhd
--- a/hdl/syn/svec/svec_tdc.ucf
+++ b/hdl/syn/svec/svec_tdc.ucf
--- a/hdl/top/svec/svec_top_fmc_tdc.vhd
+++ b/hdl/top/svec/svec_top_fmc_tdc.vhd
--- a/hdl/top/svec/no_wrabbit/synthesis_descriptor.vhd
+++ b/hdl/top/svec/no_wrabbit/synthesis_descriptor.vhd
--- a/hdl/top/svec/tdc_core_pkg.vhd
+++ b/hdl/top/svec/tdc_core_pkg.vhd
--- a/hdl/top/svec/xvme64x_core.vhd
+++ b/hdl/top/svec/xvme64x_core.vhd
--- a/hdl/top/svec/sdb_meta_pkg.vhd
+++ b/hdl/top/svec/sdb_meta_pkg.vhd
--- a/hdl/top/svec/wb_irq_controller/irq_controller.vhd
+++ b/hdl/top/svec/wb_irq_controller/irq_controller.vhd
--- a/hdl/top/svec/wb_irq_controller/irq_controller.wb
+++ b/hdl/top/svec/wb_irq_controller/irq_controller.wb
-peripheral {
-    name = "Interrupt controller";
-    description = "FMC TDC interrrupt controller.";
-    hdl_entity = "irq_controller";
-    prefix = "irq_ctrl";
-
-
-    irq {
-            name = "FMC TDC timestamps interrupt";
-            description = "FMC TDC timestamp interrupt (rising edge sensitive).";
-            prefix = "tdc_tstamps";
-            trigger = EDGE_RISING;
-        };
-
-    irq {
-            name = "FMC TDC time interrupt";
-            description = "FMC TDC time interrupt (rising edge sensitive).";
-            prefix = "tdc_time";
-            trigger = EDGE_RISING;
-        };
-
-    irq {
-            name = "FMC TDC acam error interrupt";
-            description = "FMC slot 1 acam error interrupt (rising edge sensitive).";
-            prefix = "tdc_acam_err";
-            trigger = EDGE_RISING;
-        };
-
-};
--- a/hdl/top/svec/with_wrabbit/synthesis_descriptor.vhd
+++ b/hdl/top/svec/with_wrabbit/synthesis_descriptor.vhd
--- a/hdl/top/svec/with_wrabbit/tdc_core_pkg.vhd
+++ b/hdl/top/svec/with_wrabbit/tdc_core_pkg.vhd
--- a/hdl/top/svec/with_wrabbit/wr_svec_tdc.ucf
+++ b/hdl/top/svec/with_wrabbit/wr_svec_tdc.ucf
--- a/hdl/top/svec/with_wrabbit/wr_svec_tdc.vhd
+++ b/hdl/top/svec/with_wrabbit/wr_svec_tdc.vhd
--- a/hdl/top/svec/with_wrabbit/xvme64x_core.vhd
+++ b/hdl/top/svec/with_wrabbit/xvme64x_core.vhd