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FMC TDC 1ns 5cha
Commit 099aebec authored by Federico Vaga's avatar Federico Vaga
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Merge remote-tracking branch 'origin/develop' into develop

parents 5699e1e0 6ea12fc9
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hdl/rtl/fmc_tdc_core.vhd
View file @ 099aebec
...@@ -122,22 +122,21 @@ use work.genram_pkg.all; ...@@ -122,22 +122,21 @@ use work.genram_pkg.all;
-- Entity declaration for fmc_tdc_core -- Entity declaration for fmc_tdc_core
--================================================================================================= --=================================================================================================
entity fmc_tdc_core is entity fmc_tdc_core is
generic generic (
(g_SPAN : integer := 32; -- address span in bus interfaces g_SPAN : integer := 32; -- address span in bus interfaces
g_WIDTH : integer := 32; -- data width in bus interfaces g_WIDTH : integer := 32; -- data width in bus interfaces
g_SIMULATION : boolean := FALSE; g_SIMULATION : boolean := FALSE;
-- Enable filtering based on pulse width. This will have the following effects: -- Enable filtering based on pulse width. This will have the following effects:
-- * Suppress theforwarding of negative slope timestamps. -- * Suppress theforwarding of negative slope timestamps.
-- * Delay the forwarding of timestamps until after the falling edge timestamp. -- * Delay the forwarding of timestamps until after the falling edge timestamp.
-- Once enabled, all pulses wider than 1 second or narrower than -- Once enabled, all pulses wider than 1 second or narrower than
-- g_pulse_width_filter_min will be dropped. -- g_pulse_width_filter_min will be dropped.
g_PULSE_WIDTH_FILTER : boolean := true; g_PULSE_WIDTH_FILTER : boolean := true;
-- In 8ns ticks. -- In 8ns ticks.
g_PULSE_WIDTH_FILTER_MIN : natural := 12; g_PULSE_WIDTH_FILTER_MIN : natural := 12;
g_USE_DMA_READOUT : boolean := FALSE; g_USE_DMA_READOUT : boolean := FALSE;
g_USE_FIFO_READOUT : boolean := FALSE); g_USE_FIFO_READOUT : boolean := FALSE);
port port (
(
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic; rst_sys_n_i : in std_logic;
...@@ -173,7 +172,7 @@ entity fmc_tdc_core is ...@@ -173,7 +172,7 @@ entity fmc_tdc_core is
tdc_led_stat_o : out std_logic; -- amber led on front pannel, division of clk_tdc_i tdc_led_stat_o : out std_logic; -- amber led on front pannel, division of clk_tdc_i
tdc_led_trig_o : out std_logic_vector(4 downto 0); -- one amber led on front pannel per Ch tdc_led_trig_o : out std_logic_vector(4 downto 0); -- one amber led on front pannel per Ch
-- White Rabbit control and status registers -- White Rabbit control and status registers
wrabbit_status_reg_i : in std_logic_vector(g_WIDTH-1 downto 0); wrabbit_status_reg_i : in std_logic_vector(g_WIDTH-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_WIDTH-1 downto 0); wrabbit_ctrl_reg_o : out std_logic_vector(g_WIDTH-1 downto 0);
-- White Rabbit timing -- White Rabbit timing
...@@ -199,8 +198,7 @@ entity fmc_tdc_core is ...@@ -199,8 +198,7 @@ entity fmc_tdc_core is
irq_threshold_o : out std_logic_vector(9 downto 0); irq_threshold_o : out std_logic_vector(9 downto 0);
irq_timeout_o : out std_logic_vector(9 downto 0); irq_timeout_o : out std_logic_vector(9 downto 0);
fmc_id_i : in std_logic fmc_id_i : in std_logic);
);
end fmc_tdc_core; end fmc_tdc_core;
...@@ -285,7 +283,6 @@ begin ...@@ -285,7 +283,6 @@ begin
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i, rst_sys_n_i => rst_sys_n_i,
slave_i => cfg_slave_i, slave_i => cfg_slave_i,
slave_o => cfg_slave_o, slave_o => cfg_slave_o,
...@@ -329,8 +326,6 @@ begin ...@@ -329,8 +326,6 @@ begin
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
wrabbit_ctrl_reg_o <= wrabbit_ctrl_reg; wrabbit_ctrl_reg_o <= wrabbit_ctrl_reg;
...@@ -362,25 +357,25 @@ begin ...@@ -362,25 +357,25 @@ begin
-- LOCAL ONE HZ GENERATOR -- -- LOCAL ONE HZ GENERATOR --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
local_one_second_block : entity work.local_pps_gen local_one_second_block : entity work.local_pps_gen
generic map generic map (
(g_WIDTH => g_WIDTH) g_WIDTH => g_WIDTH)
port map port map (
(acam_refclk_r_edge_p_i => acam_refclk_r_edge_p_i, acam_refclk_r_edge_p_i => acam_refclk_r_edge_p_i,
clk_i => clk_tdc_i, clk_i => clk_tdc_i,
clk_period_i => clk_period, clk_period_i => clk_period,
load_utc_p_i => load_utc, load_utc_p_i => load_utc,
rst_i => rst_tdc, rst_i => rst_tdc,
starting_utc_i => starting_utc, starting_utc_i => starting_utc,
local_utc_o => local_utc, local_utc_o => local_utc,
local_utc_p_o => local_utc_p); local_utc_p_o => local_utc_p);
clk_period <= work.tdc_core_pkg.f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD); clk_period <= work.tdc_core_pkg.f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- ACAM TIMECONTROL INTERFACE -- -- ACAM TIMECONTROL INTERFACE --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
acam_timing_block : entity work.acam_timecontrol_interface acam_timing_block : entity work.acam_timecontrol_interface
port map port map (
(
start_from_fpga_o => start_from_fpga, start_from_fpga_o => start_from_fpga,
stop_dis_o => stop_dis_o, stop_dis_o => stop_dis_o,
utc_p_i => utc_p, utc_p_i => utc_p,
...@@ -442,7 +437,7 @@ begin ...@@ -442,7 +437,7 @@ begin
-- DATA ENGINE -- -- DATA ENGINE --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
data_engine_block : entity work.data_engine data_engine_block : entity work.data_engine
generic map( generic map (
g_simulation => g_simulation) g_simulation => g_simulation)
port map port map
(acam_ack_i => acm_ack, (acam_ack_i => acm_ack,
...@@ -545,17 +540,17 @@ begin ...@@ -545,17 +540,17 @@ begin
-- TDC LEDs -- -- TDC LEDs --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
TDCboard_leds : entity work.leds_manager TDCboard_leds : entity work.leds_manager
generic map generic map (
(g_WIDTH => 32, g_WIDTH => 32,
g_simulation => g_simulation) g_simulation => g_simulation)
port map port map (
(clk_i => clk_tdc_i, clk_i => clk_tdc_i,
rst_i => rst_tdc, rst_i => rst_tdc,
utc_p_i => utc_p, utc_p_i => utc_p,
tstamp_valid_p_i => final_timestamp_valid, tstamp_valid_p_i => final_timestamp_valid,
term_en_i => term_enable_tdc, term_en_i => term_enable_tdc,
tdc_led_stat_o => tdc_led_stat_o, tdc_led_stat_o => tdc_led_stat_o,
tdc_led_trig_o => tdc_led_trig_o); tdc_led_trig_o => tdc_led_trig_o);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- ACAM start_dis, not used -- -- ACAM start_dis, not used --
...@@ -571,7 +566,7 @@ begin ...@@ -571,7 +566,7 @@ begin
d_i => channel_enable_tdc, d_i => channel_enable_tdc,
q_o => channel_enable_sys); q_o => channel_enable_sys);
term_enable_tdc <= acam_inputs_en(4 downto 0); term_enable_tdc <= acam_inputs_en(4 downto 0);
channel_enable_tdc <= acam_inputs_en(20 downto 16); channel_enable_tdc <= acam_inputs_en(20 downto 16);
channel_enable_o <= channel_enable_sys; channel_enable_o <= channel_enable_sys;
......
hdl/rtl/fmc_tdc_direct_readout.vhd
View file @ 099aebec
...@@ -9,18 +9,16 @@ use work.wishbone_pkg.all; ...@@ -9,18 +9,16 @@ use work.wishbone_pkg.all;
use work.dr_wbgen2_pkg.all; use work.dr_wbgen2_pkg.all;
entity fmc_tdc_direct_readout is entity fmc_tdc_direct_readout is
port port (
( clk_sys_i : in std_logic;
clk_sys_i : in std_logic; rst_sys_n_i : in std_logic;
rst_sys_n_i : in std_logic; fmc_present_n_i : in std_logic;
timestamp_i : in t_tdc_timestamp_array(4 downto 0); timestamp_i : in t_tdc_timestamp_array(4 downto 0);
timestamp_valid_i : in std_logic_vector(4 downto 0); timestamp_valid_i : in std_logic_vector(4 downto 0);
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out
);
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out);
end entity; end entity;
...@@ -69,6 +67,7 @@ begin ...@@ -69,6 +67,7 @@ begin
regs_in.fifo_bins_i <= "000000" & timestamp_i(channel_select).frac; regs_in.fifo_bins_i <= "000000" & timestamp_i(channel_select).frac;
regs_in.fifo_wr_req_i <= f_to_std_logic(fifo_wr(channel_select) = '1' and regs_in.fifo_wr_req_i <= f_to_std_logic(fifo_wr(channel_select) = '1' and
regs_out.fifo_wr_full_o = '0'); regs_out.fifo_wr_full_o = '0');
regs_in.status_i <= not fmc_present_n_i;
U_WB_Slave : entity work.fmc_tdc_direct_readout_wb_slave U_WB_Slave : entity work.fmc_tdc_direct_readout_wb_slave
port map ( port map (
......
hdl/rtl/fmc_tdc_direct_readout_slave.vhd
View file @ 099aebec
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC Direct Readout WB Slave -- Title : Wishbone slave core for TDC Direct Readout WB Slave
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fmc_tdc_direct_readout_slave.vhd -- File : ../fmc_tdc_direct_readout_slave.vhd
-- Author : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb -- Author : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb
-- Created : Thu Sep 26 16:03:31 2019 -- Created : Wed Mar 24 09:22:15 2021
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb
...@@ -137,6 +137,43 @@ begin ...@@ -137,6 +137,43 @@ begin
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "010" => when "010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.status_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
if (dr_fifo_rdreq_int_d0 = '0') then if (dr_fifo_rdreq_int_d0 = '0') then
...@@ -146,13 +183,13 @@ begin ...@@ -146,13 +183,13 @@ begin
ack_in_progress <= '1'; ack_in_progress <= '1';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
end if; end if;
when "011" => when "100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(31 downto 0) <= dr_fifo_out_int(63 downto 32); rddata_reg(31 downto 0) <= dr_fifo_out_int(63 downto 32);
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "100" => when "101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(17 downto 0) <= dr_fifo_out_int(81 downto 64); rddata_reg(17 downto 0) <= dr_fifo_out_int(81 downto 64);
...@@ -169,7 +206,7 @@ begin ...@@ -169,7 +206,7 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "101" => when "110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(16) <= dr_fifo_full_int; rddata_reg(16) <= dr_fifo_full_int;
...@@ -244,6 +281,7 @@ begin ...@@ -244,6 +281,7 @@ begin
regs_o.chan_enable_o <= dr_chan_enable_int; regs_o.chan_enable_o <= dr_chan_enable_int;
-- Dead time (8ns ticks) -- Dead time (8ns ticks)
regs_o.dead_time_o <= dr_dead_time_int; regs_o.dead_time_o <= dr_dead_time_int;
-- FMC present
-- extra code for reg/fifo/mem: FIFO 'Readout FIFO' data output register 0 -- extra code for reg/fifo/mem: FIFO 'Readout FIFO' data output register 0
process (clk_sys_i, rst_n_i) process (clk_sys_i, rst_n_i)
begin begin
......
hdl/rtl/fmc_tdc_direct_readout_slave_pkg.vhd
View file @ 099aebec
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC Direct Readout WB Slave -- Title : Wishbone slave core for TDC Direct Readout WB Slave
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fmc_tdc_direct_readout_slave_pkg.vhd -- File : ../fmc_tdc_direct_readout_slave_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/fmc_tdc_direct_readout_slave.wb -- Author : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb
-- Created : Thu Sep 26 16:03:31 2019 -- Created : Wed Mar 24 09:22:15 2021
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/fmc_tdc_direct_readout_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -27,6 +27,7 @@ package dr_wbgen2_pkg is ...@@ -27,6 +27,7 @@ package dr_wbgen2_pkg is
fifo_bins_i : std_logic_vector(17 downto 0); fifo_bins_i : std_logic_vector(17 downto 0);
fifo_edge_i : std_logic; fifo_edge_i : std_logic;
fifo_channel_i : std_logic_vector(3 downto 0); fifo_channel_i : std_logic_vector(3 downto 0);
status_i : std_logic;
end record; end record;
constant c_dr_in_registers_init_value: t_dr_in_registers := ( constant c_dr_in_registers_init_value: t_dr_in_registers := (
...@@ -35,7 +36,8 @@ package dr_wbgen2_pkg is ...@@ -35,7 +36,8 @@ package dr_wbgen2_pkg is
fifo_cycles_i => (others => '0'), fifo_cycles_i => (others => '0'),
fifo_bins_i => (others => '0'), fifo_bins_i => (others => '0'),
fifo_edge_i => '0', fifo_edge_i => '0',
fifo_channel_i => (others => '0') fifo_channel_i => (others => '0'),
status_i => '0'
); );
-- Output registers (WB slave -> user design) -- Output registers (WB slave -> user design)
...@@ -90,6 +92,7 @@ tmp.fifo_cycles_i := f_x_to_zero(left.fifo_cycles_i) or f_x_to_zero(right.fifo_c ...@@ -90,6 +92,7 @@ tmp.fifo_cycles_i := f_x_to_zero(left.fifo_cycles_i) or f_x_to_zero(right.fifo_c
tmp.fifo_bins_i := f_x_to_zero(left.fifo_bins_i) or f_x_to_zero(right.fifo_bins_i); tmp.fifo_bins_i := f_x_to_zero(left.fifo_bins_i) or f_x_to_zero(right.fifo_bins_i);
tmp.fifo_edge_i := f_x_to_zero(left.fifo_edge_i) or f_x_to_zero(right.fifo_edge_i); tmp.fifo_edge_i := f_x_to_zero(left.fifo_edge_i) or f_x_to_zero(right.fifo_edge_i);
tmp.fifo_channel_i := f_x_to_zero(left.fifo_channel_i) or f_x_to_zero(right.fifo_channel_i); tmp.fifo_channel_i := f_x_to_zero(left.fifo_channel_i) or f_x_to_zero(right.fifo_channel_i);
tmp.status_i := f_x_to_zero(left.status_i) or f_x_to_zero(right.status_i);
return tmp; return tmp;
end function; end function;
end package body; end package body;
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 099aebec
...@@ -184,9 +184,7 @@ entity fmc_tdc_mezzanine is ...@@ -184,9 +184,7 @@ entity fmc_tdc_mezzanine is
sim_timestamp_i : in t_tdc_timestamp := c_dummy_timestamp; sim_timestamp_i : in t_tdc_timestamp := c_dummy_timestamp;
sim_timestamp_valid_i : in std_logic := '0'; sim_timestamp_valid_i : in std_logic := '0';
sim_timestamp_ready_o : out std_logic sim_timestamp_ready_o : out std_logic);
);
end fmc_tdc_mezzanine; end fmc_tdc_mezzanine;
...@@ -567,30 +565,30 @@ begin ...@@ -567,30 +565,30 @@ begin
gen_enable_eic : if g_USE_FIFO_READOUT or g_USE_DMA_READOUT generate gen_enable_eic : if g_USE_FIFO_READOUT or g_USE_DMA_READOUT generate
cmp_tdc_eic : entity work.tdc_eic cmp_tdc_eic : entity work.tdc_eic
port map port map (
(clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i, rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(5 downto 2), wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(5 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).dat, wb_dat_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).dat, wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).cyc, wb_cyc_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).sel, wb_sel_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).stb, wb_stb_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).we, wb_we_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack, wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall, wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall,
wb_int_o => wb_irq_o, wb_int_o => wb_irq_o,
irq_tdc_fifo1_i => irq_fifo(0), irq_tdc_fifo1_i => irq_fifo(0),
irq_tdc_fifo2_i => irq_fifo(1), irq_tdc_fifo2_i => irq_fifo(1),
irq_tdc_fifo3_i => irq_fifo(2), irq_tdc_fifo3_i => irq_fifo(2),
irq_tdc_fifo4_i => irq_fifo(3), irq_tdc_fifo4_i => irq_fifo(3),
irq_tdc_fifo5_i => irq_fifo(4), irq_tdc_fifo5_i => irq_fifo(4),
irq_tdc_dma1_i => irq_dma(0), irq_tdc_dma1_i => irq_dma(0),
irq_tdc_dma2_i => irq_dma(1), irq_tdc_dma2_i => irq_dma(1),
irq_tdc_dma3_i => irq_dma(2), irq_tdc_dma3_i => irq_dma(2),
irq_tdc_dma4_i => irq_dma(3), irq_tdc_dma4_i => irq_dma(3),
irq_tdc_dma5_i => irq_dma(4) irq_tdc_dma5_i => irq_dma(4)
); );
end generate gen_enable_eic; end generate gen_enable_eic;
gen_disable_eic : if not g_USE_FIFO_READOUT and not g_USE_DMA_READOUT generate gen_disable_eic : if not g_USE_FIFO_READOUT and not g_USE_DMA_READOUT generate
...@@ -659,8 +657,6 @@ begin ...@@ -659,8 +657,6 @@ begin
timestamp_o <= timestamp; timestamp_o <= timestamp;
timestamp_valid_o <= timestamp_valid; timestamp_valid_o <= timestamp_valid;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture ends -- architecture ends
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ 099aebec
...@@ -116,6 +116,7 @@ entity fmc_tdc_wrapper is ...@@ -116,6 +116,7 @@ entity fmc_tdc_wrapper is
rst_n_a_i : in std_logic; rst_n_a_i : in std_logic;
fmc_id_i : in std_logic; fmc_id_i : in std_logic;
fmc_present_n_i : in std_logic;
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine -- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
pll_sclk_o : out std_logic; -- SPI clock pll_sclk_o : out std_logic; -- SPI clock
...@@ -282,6 +283,7 @@ begin ...@@ -282,6 +283,7 @@ begin
port map ( port map (
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i, rst_sys_n_i => rst_sys_n_i,
fmc_present_n_i => fmc_present_n_i,
timestamp_i => timestamp, timestamp_i => timestamp,
timestamp_valid_i => timestamp_valid, timestamp_valid_i => timestamp_valid,
direct_slave_i => cnx_master_out(c_slave_direct), direct_slave_i => cnx_master_out(c_slave_direct),
...@@ -356,98 +358,94 @@ begin ...@@ -356,98 +358,94 @@ begin
-- TDC BOARD -- -- TDC BOARD --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
cmp_tdc_mezz : entity work.fmc_tdc_mezzanine cmp_tdc_mezz : entity work.fmc_tdc_mezzanine
generic map generic map (
(g_span => 32, g_span => 32,
g_width => 32, g_width => 32,
g_simulation => g_simulation, g_simulation => g_simulation,
g_pulse_width_filter => g_pulse_width_filter, g_pulse_width_filter => g_pulse_width_filter,
g_pulse_width_filter_min => g_pulse_width_filter_min, g_pulse_width_filter_min => g_pulse_width_filter_min,
g_use_fifo_readout => g_use_fifo_readout, g_use_fifo_readout => g_use_fifo_readout,
g_use_dma_readout => g_use_dma_readout, g_use_dma_readout => g_use_dma_readout,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim) g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
port map port map (
-- 62M5 clk and reset -- 62M5 clk and reset
(clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i, rst_sys_n_i => rst_sys_n_i,
-- 125M clk and reset -- 125M clk and reset
clk_tdc_i => clk_125m_mezz, clk_tdc_i => clk_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n, rst_tdc_n_i => rst_125m_mezz_n,
-- FMC slot identification -- FMC slot identification
fmc_id_i => fmc_id_i, fmc_id_i => fmc_id_i,
-- Wishbone -- Wishbone
slave_i => cnx_master_out(c_slave_regs), slave_i => cnx_master_out(c_slave_regs),
slave_o => cnx_master_in(c_slave_regs), slave_o => cnx_master_in(c_slave_regs),
dma_wb_i => dma_wb_i, dma_wb_i => dma_wb_i,
dma_wb_o => dma_wb_o, dma_wb_o => dma_wb_o,
-- Interrupt line from EIC -- Interrupt line from EIC
wb_irq_o => irq_o, wb_irq_o => irq_o,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit -- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p, acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
send_dac_word_p_o => send_dac_word_p, send_dac_word_p_o => send_dac_word_p,
dac_word_o => dac_word, dac_word_o => dac_word,
-- ACAM interface -- ACAM interface
start_from_fpga_o => start_from_fpga_o, start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i, err_flag_i => err_flag_i,
int_flag_i => int_flag_i, int_flag_i => int_flag_i,
start_dis_o => start_dis_o, start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o, stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io, data_bus_io => data_bus_io,
address_o => address_o, address_o => address_o,
cs_n_o => cs_n_o, cs_n_o => cs_n_o,
oe_n_o => oe_n_o, oe_n_o => oe_n_o,
rd_n_o => rd_n_o, rd_n_o => rd_n_o,
wr_n_o => wr_n_o, wr_n_o => wr_n_o,
ef1_i => ef1_i, ef1_i => ef1_i,
ef2_i => ef2_i, ef2_i => ef2_i,
-- Input channels enable -- Input channels enable
enable_inputs_o => enable_inputs_o, enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o, term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o, term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o, term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o, term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o, term_en_5_o => term_en_5_o,
-- LEDs on TDC mezzanine -- LEDs on TDC mezzanine
tdc_led_stat_o => tdc_led_stat_o, tdc_led_stat_o => tdc_led_stat_o,
tdc_led_trig_o => tdc_led_trig_o, tdc_led_trig_o => tdc_led_trig_o,
-- WISHBONE interface with the GN4124 core -- WISHBONE interface with the GN4124 core
-- White Rabbit -- White Rabbit
wrabbit_link_up_i => tm_link_up_i, wrabbit_link_up_i => tm_link_up_i,
wrabbit_time_valid_i => tm_time_valid_i, wrabbit_time_valid_i => tm_time_valid_i,
wrabbit_cycles_i => tm_cycles_i, wrabbit_cycles_i => tm_cycles_i,
wrabbit_utc_i => tm_tai_i(31 downto 0), wrabbit_utc_i => tm_tai_i(31 downto 0),
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en_o, wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en_o,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked_i, wrabbit_clk_aux_locked_i => tm_clk_aux_locked_i,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
wrabbit_dac_value_i => tm_dac_value_i, wrabbit_dac_value_i => tm_dac_value_i,
wrabbit_dac_wr_p_i => tm_dac_wr_i, wrabbit_dac_wr_p_i => tm_dac_wr_i,
-- EEPROM I2C on TDC mezzanine -- EEPROM I2C on TDC mezzanine
i2c_scl_oen_o => tdc_scl_oen, i2c_scl_oen_o => tdc_scl_oen,
i2c_scl_i => mezz_scl_i, i2c_scl_i => mezz_scl_i,
i2c_sda_oen_o => tdc_sda_oen, i2c_sda_oen_o => tdc_sda_oen,
i2c_sda_i => mezz_sda_i, i2c_sda_i => mezz_sda_i,
i2c_scl_o => tdc_scl_out, i2c_scl_o => tdc_scl_out,
i2c_sda_o => tdc_sda_out, i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine -- 1-Wire on TDC mezzanine
onewire_b => mezz_one_wire_b, onewire_b => mezz_one_wire_b,
timestamp_o => timestamp, timestamp_o => timestamp,
timestamp_valid_o => timestamp_valid, timestamp_valid_o => timestamp_valid,
sim_timestamp_ready_o => sim_timestamp_ready_o, sim_timestamp_ready_o => sim_timestamp_ready_o,
sim_timestamp_valid_i => sim_timestamp_valid_i, sim_timestamp_valid_i => sim_timestamp_valid_i,
sim_timestamp_i => sim_timestamp_i); sim_timestamp_i => sim_timestamp_i);
mezz_scl_o <= '0' when tdc_scl_out = '0' and tdc_scl_oen = '0' else '1'; mezz_scl_o <= '0' when tdc_scl_out = '0' and tdc_scl_oen = '0' else '1';
mezz_sda_o <= '0' when tdc_sda_out = '0' and tdc_sda_oen = '0' else '1'; mezz_sda_o <= '0' when tdc_sda_out = '0' and tdc_sda_oen = '0' else '1';
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture ends -- architecture ends
......
hdl/rtl/reg_ctrl.vhd
View file @ 099aebec
...@@ -94,7 +94,7 @@ entity reg_ctrl is ...@@ -94,7 +94,7 @@ entity reg_ctrl is
local_utc_i : in std_logic_vector(g_width-1 downto 0); -- local utc time local_utc_i : in std_logic_vector(g_width-1 downto 0); -- local utc time
-- Signals not used so far -- Signals not used so far
core_status_i : in std_logic_vector(g_width-1 downto 0); -- TDC core status word currently unused core_status_i : in std_logic_vector(g_width-1 downto 0); -- TDC core status word
-- White Rabbit status -- White Rabbit status
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); -- wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); --
...@@ -149,17 +149,17 @@ end reg_ctrl; ...@@ -149,17 +149,17 @@ end reg_ctrl;
--================================================================================================= --=================================================================================================
architecture rtl of reg_ctrl is architecture rtl of reg_ctrl is
signal acam_config : config_vector; signal acam_config : config_vector;
signal reg_adr, reg_adr_pipe0 : std_logic_vector(7 downto 0); signal reg_adr, reg_adr_pipe0 : std_logic_vector(7 downto 0);
signal starting_utc, acam_inputs_en : std_logic_vector(g_width-1 downto 0); signal starting_utc, acam_inputs_en : std_logic_vector(g_width-1 downto 0);
signal ctrl_reg, local_pps_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0); signal ctrl_reg, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
signal irq_time_threshold : std_logic_vector(g_width-1 downto 0); signal irq_time_threshold : std_logic_vector(g_width-1 downto 0);
signal clear_ctrl_reg, send_dac_word_p : std_logic; signal clear_ctrl_reg, send_dac_word_p : std_logic;
signal dac_word : std_logic_vector(23 downto 0); signal dac_word : std_logic_vector(23 downto 0);
signal pulse_extender_en : std_logic; signal pulse_extender_en : std_logic;
signal pulse_extender_c : std_logic_vector(2 downto 0); signal pulse_extender_c : std_logic_vector(2 downto 0);
signal dat_out, wrabbit_ctrl_reg : std_logic_vector(g_span-1 downto 0); signal wrabbit_ctrl_reg : std_logic_vector(g_span-1 downto 0);
signal ack_out_pipe0, ack_out_pipe1 : std_logic; signal ack_out_pipe0, ack_out_pipe1 : std_logic;
signal dat_out_comb0, dat_out_comb1 : std_logic_vector(g_span-1 downto 0); signal dat_out_comb0, dat_out_comb1 : std_logic_vector(g_span-1 downto 0);
...@@ -169,20 +169,12 @@ architecture rtl of reg_ctrl is ...@@ -169,20 +169,12 @@ architecture rtl of reg_ctrl is
signal dat_out_pipe2, dat_out_pipe3 : std_logic_vector(g_span-1 downto 0); signal dat_out_pipe2, dat_out_pipe3 : std_logic_vector(g_span-1 downto 0);
signal cyc_in_progress : std_logic; signal cyc_in_progress : std_logic;
signal cyc2_in_progress : std_logic;
signal wb_in : t_wishbone_slave_in; signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out; signal wb_out : t_wishbone_slave_out;
--=================================================================================================
-- architecture begin
--=================================================================================================
signal cc_rst_n : std_logic; signal cc_rst_n : std_logic;
signal cc_rst_n_or_sys : std_logic; signal cc_rst_n_or_sys : std_logic;
begin begin
wb_out.stall <= '0'; wb_out.stall <= '0';
......
hdl/rtl/wbgen/build_wb.sh
View file @ 099aebec
...@@ -6,3 +6,5 @@ wbgen2 -V tdc_onewire_wb.vhd -H record_full -p tdc_onewire_wbgen2_pkg.vhd -K tim ...@@ -6,3 +6,5 @@ wbgen2 -V tdc_onewire_wb.vhd -H record_full -p tdc_onewire_wbgen2_pkg.vhd -K tim
#don't do this, latest wbgen is buggy #don't do this, latest wbgen is buggy
#wbgen2 -V tdc_eic.vhd -s defines -C tdc_eic.h -D wbgen/tdc_eic.html wbgen/tdc_eic.wb #wbgen2 -V tdc_eic.vhd -s defines -C tdc_eic.h -D wbgen/tdc_eic.html wbgen/tdc_eic.wb
# wbgen2 --hstyle=record -V ../fmc_tdc_direct_readout_slave.vhd -p ../fmc_tdc_direct_readout_slave_pkg.vhd -s defines -C fmctdc-direct.h fmc_tdc_direct_readout_slave.wb
hdl/rtl/wbgen/fmc_tdc_direct_readout_slave.wb
View file @ 099aebec
...@@ -71,4 +71,15 @@ peripheral ...@@ -71,4 +71,15 @@ peripheral
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
}; };
reg {
name = "Status Register";
prefix = "STATUS";
field {
name = "FMC present";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
}; };
hdl/rtl/wbgen/reg_ctrl_wb.wb deleted 100644 → 0
View file @ 5699e1e0
This diff is collapsed.
hdl/rtl/wrabbit_sync.vhd
View file @ 099aebec
...@@ -176,6 +176,7 @@ begin ...@@ -176,6 +176,7 @@ begin
else else
wrabbit_state_changed <= '0'; wrabbit_state_changed <= '0';
end if; end if;
when wrabbit_WAIT_READY => when wrabbit_WAIT_READY =>
wrabbit_clk_aux_lock_en <= '0'; wrabbit_clk_aux_lock_en <= '0';
......
hdl/syn/svec/Manifest.py
View file @ 099aebec
...@@ -12,7 +12,11 @@ syn_project = "wr_svec_tdc.xise" ...@@ -12,7 +12,11 @@ syn_project = "wr_svec_tdc.xise"
syn_tool = "ise" syn_tool = "ise"
#top_module = "wr_svec_tdc" #top_module = "wr_svec_tdc"
files = ["buildinfo_pkg.vhd", "sourceid_wr_svec_tdc_pkg.vhd"] files = ["buildinfo_pkg.vhd",
"sourceid_wr_svec_tdc_pkg.vhd",
"svec-tdc0.ucf",
"svec-tdc1.ucf",
"wr_svec_tdc.ucf",]
modules = { "local" : [ "../../top/svec" ] } modules = { "local" : [ "../../top/svec" ] }
......
hdl/syn/svec/svec-tdc1.ucf 0 → 100644
View file @ 099aebec
#----------------------------------------
# FMC1
#----------------------------------------
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 1
NET "fmc1_tdc_acam_refclk_p_i" LOC = AF16;
NET "fmc1_tdc_acam_refclk_p_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_acam_refclk_n_i" LOC = AG16;
NET "fmc1_tdc_acam_refclk_n_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_clk_125m_p_i" LOC = AH16;
NET "fmc1_tdc_clk_125m_p_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_clk_125m_n_i" LOC = AK16;
NET "fmc1_tdc_clk_125m_n_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_led_trig1_o" LOC = Y20;
NET "fmc1_tdc_led_trig1_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig2_o" LOC = W19;
NET "fmc1_tdc_led_trig2_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig3_o" LOC = Y19;
NET "fmc1_tdc_led_trig3_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_1_o" LOC = AJ17;
NET "fmc1_tdc_term_en_1_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_2_o" LOC = AK17;
NET "fmc1_tdc_term_en_2_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_ef1_i" LOC = AB14;
NET "fmc1_tdc_ef1_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_ef2_i" LOC = AC14;
NET "fmc1_tdc_ef2_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_3_o" LOC = AE19;
NET "fmc1_tdc_term_en_3_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_4_o" LOC = AF19;
NET "fmc1_tdc_term_en_4_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_5_o" LOC = AE24;
NET "fmc1_tdc_term_en_5_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_status_o" LOC = AF24;
NET "fmc1_tdc_led_status_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig4_o" LOC = Y21;
NET "fmc1_tdc_led_trig4_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig5_o" LOC = AA21;
NET "fmc1_tdc_led_trig5_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sclk_o" LOC = AF25;
NET "fmc1_tdc_pll_sclk_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_dac_sync_o" LOC = AG25;
NET "fmc1_tdc_pll_dac_sync_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_cs_n_o" LOC = AC19;
NET "fmc1_tdc_pll_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_cs_n_o" LOC = AD19;
NET "fmc1_tdc_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_err_flag_i" LOC = Y17;
NET "fmc1_tdc_err_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_int_flag_i" LOC = AA17;
NET "fmc1_tdc_int_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_start_dis_o" LOC = AB17;
NET "fmc1_tdc_start_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_stop_dis_o" LOC = AD17;
NET "fmc1_tdc_stop_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sdo_i" LOC = AC20;
NET "fmc1_tdc_pll_sdo_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_status_i" LOC = AD24;
NET "fmc1_tdc_pll_status_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sdi_o" LOC = AB20;
NET "fmc1_tdc_pll_sdi_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_start_from_fpga_o" LOC = AC24;
NET "fmc1_tdc_start_from_fpga_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[27]" LOC = AA15;
NET "fmc1_tdc_data_bus_io[27]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[26]" LOC = Y15;
NET "fmc1_tdc_data_bus_io[26]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[25]" LOC = AD15;
NET "fmc1_tdc_data_bus_io[25]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[24]" LOC = AC15;
NET "fmc1_tdc_data_bus_io[24]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[23]" LOC = AB16;
NET "fmc1_tdc_data_bus_io[23]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[22]" LOC = Y16;
NET "fmc1_tdc_data_bus_io[22]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[21]" LOC = AF15;
NET "fmc1_tdc_data_bus_io[21]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[20]" LOC = AE15;
NET "fmc1_tdc_data_bus_io[20]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[19]" LOC = AA14;
NET "fmc1_tdc_data_bus_io[19]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[18]" LOC = Y14;
NET "fmc1_tdc_data_bus_io[18]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[17]" LOC = Y13;
NET "fmc1_tdc_data_bus_io[17]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[16]" LOC = W14;
NET "fmc1_tdc_data_bus_io[16]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[15]" LOC = AE12;
NET "fmc1_tdc_data_bus_io[15]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[14]" LOC = AD12;
NET "fmc1_tdc_data_bus_io[14]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[13]" LOC = AF11;
NET "fmc1_tdc_data_bus_io[13]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[12]" LOC = AE11;
NET "fmc1_tdc_data_bus_io[12]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[11]" LOC = AC12;
NET "fmc1_tdc_data_bus_io[11]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[10]" LOC = AB12;
NET "fmc1_tdc_data_bus_io[10]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[9]" LOC = AE10;
NET "fmc1_tdc_data_bus_io[9]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[8]" LOC = AD10;
NET "fmc1_tdc_data_bus_io[8]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[7]" LOC = AH8;
NET "fmc1_tdc_data_bus_io[7]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[6]" LOC = AK15;
NET "fmc1_tdc_data_bus_io[6]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[5]" LOC = AG8;
NET "fmc1_tdc_data_bus_io[5]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[4]" LOC = AJ15;
NET "fmc1_tdc_data_bus_io[4]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[3]" LOC = AF13;
NET "fmc1_tdc_data_bus_io[3]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[2]" LOC = AE13;
NET "fmc1_tdc_data_bus_io[2]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[1]" LOC = AD11;
NET "fmc1_tdc_data_bus_io[1]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[0]" LOC = AC11;
NET "fmc1_tdc_data_bus_io[0]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[3]" LOC = AF23;
NET "fmc1_tdc_address_o[3]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[2]" LOC = AE23;
NET "fmc1_tdc_address_o[2]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[1]" LOC = AF21;
NET "fmc1_tdc_address_o[1]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[0]" LOC = AE21;
NET "fmc1_tdc_address_o[0]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_oe_n_o" LOC = AD22;
NET "fmc1_tdc_oe_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_rd_n_o" LOC = AD16;
NET "fmc1_tdc_rd_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_wr_n_o" LOC = AC16;
NET "fmc1_tdc_wr_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_enable_inputs_o" LOC = AA19;
NET "fmc1_tdc_enable_inputs_o" IOSTANDARD = LVCMOS25;
NET "fmc1_onewire_b" LOC = AB19;
NET "fmc1_onewire_b" IOSTANDARD = LVCMOS25;
hdl/syn/svec/wr_svec_tdc.ucf 0 → 100644
View file @ 099aebec
#----------------------------------------
# Clock stuff
#----------------------------------------
NET "fp_gpio3_b" TNM_NET = fp_gpio3;
TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
# 125MHz TDC PLL clock
NET "fmc0_tdc_clk_125m" TNM_NET = "fmc0_tdc_clk_125m";
NET "fmc1_tdc_clk_125m" TNM_NET = "fmc1_tdc_clk_125m";
NET "fmc0_tdc_clk_125m_n_i" TNM_NET = "fmc0_tdc_clk_125m_n_i";
TIMESPEC TS_fmc0_tdc_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_clk_125m_n_i" 8 ns HIGH 50 %;
NET "fmc0_tdc_clk_125m_p_i" TNM_NET = "fmc0_tdc_clk_125m_p_i";
TIMESPEC TS_fmc0_tdc_clk_125m_p_i = PERIOD "fmc0_tdc_clk_125m_p_i" 8 ns HIGH 50 %;
NET "fmc1_tdc_clk_125m_p_i" TNM_NET = "fmc1_tdc_clk_125m_p_i";
TIMESPEC TS_fmc1_tdc_tdc_125m_clk_p_i = PERIOD "fmc1_tdc_clk_125m_p_i" 8 ns HIGH 50 %;
NET "fmc1_tdc_clk_125m_n_i" TNM_NET = "fmc1_tdc_clk_125m_n_i";
TIMESPEC TS_fmc1_tdc_tdc_125m_clk_n_i = PERIOD "fmc1_tdc_clk_125m_n_i" 8 ns HIGH 50 %;
# TS_IGNORE
TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "fmc0_tdc_clk_125m" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "fmc0_tdc_clk_125m" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_sys_62m5" TO "fmc1_tdc_clk_125m" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "fmc1_tdc_clk_125m" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_20m_vcxo_i" TO "clk_sys_62m5" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_sys_62m5" TO "clk_20m_vcxo_i" 200ns DATAPATHONLY;
#TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50 %;
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2017/12/06
#NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
#TIMESPEC TS_cmp_xwrc_board_svec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PlanAhead Generated miscellaneous constraints
NET "fmc0_tdc_address_o[3]" SLEW = FAST;
NET "fmc0_tdc_address_o[2]" SLEW = FAST;
NET "fmc0_tdc_address_o[1]" SLEW = FAST;
NET "fmc0_tdc_address_o[0]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[27]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[26]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[25]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[24]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[23]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[22]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[21]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[20]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[19]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[18]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[17]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[16]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[15]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[14]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[13]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[12]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[11]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[10]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[9]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[8]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[7]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[6]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[5]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[4]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[3]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[2]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[1]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[0]" SLEW = FAST;
NET "fmc1_tdc_address_o[3]" SLEW = FAST;
NET "fmc1_tdc_address_o[2]" SLEW = FAST;
NET "fmc1_tdc_address_o[1]" SLEW = FAST;
NET "fmc1_tdc_address_o[0]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[27]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[26]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[25]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[24]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[23]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[22]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[21]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[20]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[19]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[18]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[17]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[16]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[15]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[14]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[13]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[12]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[11]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[10]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[9]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[8]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[7]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[6]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[5]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[4]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[3]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[2]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[1]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[0]" SLEW = FAST;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
#TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#----------------------------------------
# IOB exceptions
#----------------------------------------
INST "cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_fmc_onewire/*" IOB = FALSE;
INST "cmp_tdc_mezzanine_2/cmp_tdc_mezz/cmp_fmc_onewire/*" IOB = FALSE;
hdl/top/svec/Manifest.py
View file @ 099aebec
files = ["wr_svec_tdc.ucf", files = ["wr_svec_tdc.vhd"];
"wr_svec_tdc.vhd"];
fetchto = "../../ip_cores" fetchto = "../../ip_cores"
modules = { modules = {
"local" : [ "local" : [
"../../rtl/", "../../rtl/",
"../../ip_cores/general-cores", "../../ip_cores/general-cores",
"../../ip_cores/vme64x-core", "../../ip_cores/vme64x-core",
"../../ip_cores/wr-cores", "../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/svec", "../../ip_cores/wr-cores/board/svec",
"../../ip_cores/svec", "../../ip_cores/svec",
"../../ip_cores/ddr3-sp6-core" "../../ip_cores/ddr3-sp6-core"
] ]
} }
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