description = "ACAM chip timestamp acquisition enable for all inputs, active high";
type = BIT;
align = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "C000FFEE break";
description = "constant with value C000FFEE";
prefix = "C000FFEE_break";
align = 0x23;
field {
name = "C000FFEE_break";
description = "constant with value C000FFEE";
type = CONSTANT;
size =32;
value = 0xC000FFEE;
};
};
reg {
name = "irq tstamp threshold";
description = "an interrupt is issued if the number of accumulated timestamps since the last irq exceeds this threshold, in any of the FIFOs";
prefix = "irq_tstamp_thresh";
field {
name = "irq_tstamp_thresh";
type = SLV;
size =8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "irq time threshold";
description = "an interrupt is issued if this amount of ms has passed after the last irq and at least a timestamp has been registered, in any of the FIFOs";
prefix = "irq_time_thresh";
field {
name = "irq_time_thresh";
type = SLV;
size =32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DAC word";
description = "!currently not used! TDC DAC configuration word; typical set value 1V65: 0x0000A8F5;\
to load the configuration the LOAD_DAC_P bit of the CTRL reg should be enabled";
#TIMESPEC TS_cmp_xwrc_board_svec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
#TIMESPEC TS_cmp_xwrc_board_svec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;